5 * In contrary to the Amiga and Atari platforms, the Mac hardware seems to
6 * exclusively use the autovector interrupts (the 'generic level0-level7'
7 * interrupts with exception vectors 0x19-0x1f). The following interrupt levels
10 * - slot 0: one second interrupt (CA2)
11 * - slot 1: VBlank (CA1)
12 * - slot 2: ADB data ready (SR full)
13 * - slot 3: ADB data (CB2)
14 * - slot 4: ADB clock (CB1)
17 * - slot 7: status of IRQ; signals 'any enabled int.'
20 * - slot 0: SCSI DRQ (CA2)
21 * - slot 1: NUBUS IRQ (CA1) need to read port A to find which
22 * - slot 2: /EXP IRQ (only on IIci)
23 * - slot 3: SCSI IRQ (CB2)
24 * - slot 4: ASC IRQ (CB1)
25 * - slot 5: timer 2 (not on IIci)
26 * - slot 6: timer 1 (not on IIci)
27 * - slot 7: status of IRQ; signals 'any enabled int.'
29 * 2 - OSS (IIfx only?)
30 * - slot 0: SCSI interrupt
31 * - slot 1: Sound interrupt
33 * Levels 3-6 vary by machine type. For VIA or RBV Macintoshes:
37 * 4 - SCC (slot number determined by reading RR3 on the SSC itself)
38 * - slot 1: SCC channel A
39 * - slot 2: SCC channel B
42 * [serial errors or special conditions seem to raise level 6
43 * interrupts on some models (LC4xx?)]
47 * For OSS Macintoshes (IIfx only at this point):
58 * - slot 1: SCC channel A
59 * - slot 2: SCC channel B
65 * For PSC Macintoshes (660AV, 840AV):
71 * - slot 1: SCC channel A interrupt
72 * - slot 2: SCC channel B interrupt
79 * Finally we have good 'ole level 7, the non-maskable interrupt:
81 * 7 - NMI (programmer's switch on the back of some Macs)
82 * Also RAM parity error on models which support it (IIc, IIfx?)
84 * The current interrupt logic looks something like this:
86 * - We install dispatchers for the autovector interrupts (1-7). These
87 * dispatchers are responsible for querying the hardware (the
88 * VIA/RBV/OSS/PSC chips) to determine the actual interrupt source. Using
89 * this information a machspec interrupt number is generated by placing the
90 * index of the interrupt hardware into the low three bits and the original
91 * autovector interrupt number in the upper 5 bits. The handlers for the
92 * resulting machspec interrupt are then called.
94 * - Nubus is a special case because its interrupts are hidden behind two
95 * layers of hardware. Nubus interrupts come in as index 1 on VIA #2,
96 * which translates to IRQ number 17. In this spot we install _another_
97 * dispatcher. This dispatcher finds the interrupting slot number (9-F) and
98 * then forms a new machspec interrupt number as above with the slot number
99 * minus 9 in the low three bits and the pseudo-level 7 in the upper five
100 * bits. The handlers for this new machspec interrupt number are then
101 * called. This puts Nubus interrupts into the range 56-62.
103 * - The Baboon interrupts (used on some PowerBooks) are an even more special
104 * case. They're hidden behind the Nubus slot $C interrupt thus adding a
105 * third layer of indirection. Why oh why did the Apple engineers do that?
107 * - We support "fast" and "slow" handlers, just like the Amiga port. The
108 * fast handlers are called first and with all interrupts disabled. They
109 * are expected to execute quickly (hence the name). The slow handlers are
110 * called last with interrupts enabled and the interrupt level restored.
111 * They must therefore be reentrant.
117 #include <linux/module.h>
118 #include <linux/types.h>
119 #include <linux/kernel.h>
120 #include <linux/sched.h>
121 #include <linux/kernel_stat.h>
122 #include <linux/interrupt.h> /* for intr_count */
123 #include <linux/delay.h>
124 #include <linux/seq_file.h>
126 #include <asm/system.h>
128 #include <asm/traps.h>
129 #include <asm/bootinfo.h>
130 #include <asm/macintosh.h>
131 #include <asm/mac_via.h>
132 #include <asm/mac_psc.h>
133 #include <asm/hwtest.h>
134 #include <asm/errno.h>
135 #include <asm/macints.h>
136 #include <asm/irq_regs.h>
137 #include <asm/mac_oss.h>
139 #define DEBUG_SPURIOUS
142 /* SCC interrupt mask */
150 extern void via_register_interrupts(void);
151 extern void via_irq_enable(int);
152 extern void via_irq_disable(int);
153 extern void via_irq_clear(int);
154 extern int via_irq_pending(int);
160 extern void oss_register_interrupts(void);
161 extern void oss_irq_enable(int);
162 extern void oss_irq_disable(int);
163 extern void oss_irq_clear(int);
164 extern int oss_irq_pending(int);
170 extern void psc_register_interrupts(void);
171 extern void psc_irq_enable(int);
172 extern void psc_irq_disable(int);
173 extern void psc_irq_clear(int);
174 extern int psc_irq_pending(int);
180 extern void iop_register_interrupts(void);
186 extern int baboon_present
;
188 extern void baboon_register_interrupts(void);
189 extern void baboon_irq_enable(int);
190 extern void baboon_irq_disable(int);
191 extern void baboon_irq_clear(int);
194 * SCC interrupt routines
197 static void scc_irq_enable(unsigned int);
198 static void scc_irq_disable(unsigned int);
201 * console_loglevel determines NMI handler function
204 irqreturn_t
mac_nmi_handler(int, void *);
205 irqreturn_t
mac_debug_handler(int, void *);
207 /* #define DEBUG_MACINTS */
209 void mac_enable_irq(unsigned int irq
);
210 void mac_disable_irq(unsigned int irq
);
212 static struct irq_controller mac_irq_controller
= {
214 .lock
= __SPIN_LOCK_UNLOCKED(mac_irq_controller
.lock
),
215 .enable
= mac_enable_irq
,
216 .disable
= mac_disable_irq
,
219 void __init
mac_init_IRQ(void)
222 printk("mac_init_IRQ(): Setting things up...\n");
226 m68k_setup_irq_controller(&mac_irq_controller
, IRQ_USER
,
227 NUM_MAC_SOURCES
- IRQ_USER
);
228 /* Make sure the SONIC interrupt is cleared or things get ugly */
230 printk("Killing onboard sonic... ");
231 /* This address should hopefully be mapped already */
232 if (hwreg_present((void*)(0x50f0a000))) {
233 *(long *)(0x50f0a014) = 0x7fffL
;
234 *(long *)(0x50f0a010) = 0L;
237 #endif /* SHUTUP_SONIC */
240 * Now register the handlers for the master IRQ handlers
241 * at levels 1-7. Most of the work is done elsewhere.
245 oss_register_interrupts();
247 via_register_interrupts();
249 psc_register_interrupts();
251 baboon_register_interrupts();
252 iop_register_interrupts();
253 request_irq(IRQ_AUTO_7
, mac_nmi_handler
, 0, "NMI",
256 printk("mac_init_IRQ(): Done!\n");
261 * mac_enable_irq - enable an interrupt source
262 * mac_disable_irq - disable an interrupt source
263 * mac_clear_irq - clears a pending interrupt
264 * mac_pending_irq - Returns the pending status of an IRQ (nonzero = pending)
266 * These routines are just dispatchers to the VIA/OSS/PSC routines.
269 void mac_enable_irq(unsigned int irq
)
271 int irq_src
= IRQ_SRC(irq
);
290 else if (oss_present
)
292 else if (irq_src
== 4)
297 baboon_irq_enable(irq
);
302 void mac_disable_irq(unsigned int irq
)
304 int irq_src
= IRQ_SRC(irq
);
308 via_irq_disable(irq
);
313 oss_irq_disable(irq
);
315 via_irq_disable(irq
);
322 psc_irq_disable(irq
);
323 else if (oss_present
)
324 oss_irq_disable(irq
);
325 else if (irq_src
== 4)
326 scc_irq_disable(irq
);
330 baboon_irq_disable(irq
);
335 void mac_clear_irq(unsigned int irq
)
337 switch(IRQ_SRC(irq
)) {
354 else if (oss_present
)
359 baboon_irq_clear(irq
);
364 int mac_irq_pending(unsigned int irq
)
366 switch(IRQ_SRC(irq
)) {
368 return via_irq_pending(irq
);
372 return oss_irq_pending(irq
);
374 return via_irq_pending(irq
);
380 return psc_irq_pending(irq
);
381 else if (oss_present
)
382 return oss_irq_pending(irq
);
386 EXPORT_SYMBOL(mac_irq_pending
);
388 static int num_debug
[8];
390 irqreturn_t
mac_debug_handler(int irq
, void *dev_id
)
392 if (num_debug
[irq
] < 10) {
393 printk("DEBUG: Unexpected IRQ %d\n", irq
);
400 static volatile int nmi_hold
;
402 irqreturn_t
mac_nmi_handler(int irq
, void *dev_id
)
406 * generate debug output on NMI switch if 'debug' kernel option given
407 * (only works with Penguin!)
411 for (i
=0; i
<100; i
++)
416 printk("... pausing, press NMI to resume ...");
424 while (nmi_hold
== 1)
427 if (console_loglevel
>= 8) {
429 struct pt_regs
*fp
= get_irq_regs();
431 printk("PC: %08lx\nSR: %04x SP: %p\n", fp
->pc
, fp
->sr
, fp
);
432 printk("d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n",
433 fp
->d0
, fp
->d1
, fp
->d2
, fp
->d3
);
434 printk("d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n",
435 fp
->d4
, fp
->d5
, fp
->a0
, fp
->a1
);
437 if (STACK_MAGIC
!= *(unsigned long *)current
->kernel_stack_page
)
438 printk("Corrupted stack page\n");
439 printk("Process %s (pid: %d, stackpage=%08lx)\n",
440 current
->comm
, current
->pid
, current
->kernel_stack_page
);
442 dump_stack((struct frame
*)fp
);
444 /* printk("NMI "); */
452 * Simple routines for masking and unmasking
453 * SCC interrupts in cases where this can't be
454 * done in hardware (only the PSC can do that.)
457 static void scc_irq_enable(unsigned int irq
)
459 int irq_idx
= IRQ_IDX(irq
);
461 scc_mask
|= (1 << irq_idx
);
464 static void scc_irq_disable(unsigned int irq
)
466 int irq_idx
= IRQ_IDX(irq
);
468 scc_mask
&= ~(1 << irq_idx
);
472 * SCC master interrupt handler. We have to do a bit of magic here
473 * to figure out what channel gave us the interrupt; putting this
474 * here is cleaner than hacking it into drivers/char/macserial.c.
477 void mac_scc_dispatch(int irq
, void *dev_id
)
479 volatile unsigned char *scc
= (unsigned char *) mac_bi_data
.sccbase
+ 2;
483 /* Read RR3 from the chip. Always do this on channel A */
484 /* This must be an atomic operation so disable irqs. */
486 local_irq_save(flags
);
489 local_irq_restore(flags
);
491 /* Now dispatch. Bits 0-2 are for channel B and */
492 /* bits 3-5 are for channel A. We can safely */
493 /* ignore the remaining bits here. */
495 /* Note that we're ignoring scc_mask for now. */
496 /* If we actually mask the ints then we tend to */
497 /* get hammered by very persistent SCC irqs, */
498 /* and since they're autovector interrupts they */
499 /* pretty much kill the system. */
502 m68k_handle_int(IRQ_SCCA
);
504 m68k_handle_int(IRQ_SCCB
);