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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/m68k/mm/memory.c
2 * linux/arch/m68k/mm/memory.c
4 * Copyright (C) 1995 Hamish Macdonald
7 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/string.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/pagemap.h>
14 #include <linux/gfp.h>
16 #include <asm/setup.h>
17 #include <asm/segment.h>
19 #include <asm/pgalloc.h>
20 #include <asm/traps.h>
21 #include <asm/machdep.h>
24 /* ++andreas: {get,free}_pointer_table rewritten to use unused fields from
25 struct page instead of separately kmalloced struct. Stolen from
26 arch/sparc/mm/srmmu.c ... */
28 typedef struct list_head ptable_desc
;
29 static LIST_HEAD(ptable_list
);
31 #define PD_PTABLE(page) ((ptable_desc *)&(virt_to_page(page)->lru))
32 #define PD_PAGE(ptable) (list_entry(ptable, struct page, lru))
33 #define PD_MARKBITS(dp) (*(unsigned char *)&PD_PAGE(dp)->index)
35 #define PTABLE_SIZE (PTRS_PER_PMD * sizeof(pmd_t))
37 void __init
init_pointer_table(unsigned long ptable
)
40 unsigned long page
= ptable
& PAGE_MASK
;
41 unsigned char mask
= 1 << ((ptable
- page
)/PTABLE_SIZE
);
44 if (!(PD_MARKBITS(dp
) & mask
)) {
45 PD_MARKBITS(dp
) = 0xff;
46 list_add(dp
, &ptable_list
);
49 PD_MARKBITS(dp
) &= ~mask
;
50 pr_debug("init_pointer_table: %lx, %x\n", ptable
, PD_MARKBITS(dp
));
52 /* unreserve the page so it's possible to free that page */
53 PD_PAGE(dp
)->flags
&= ~(1 << PG_reserved
);
54 init_page_count(PD_PAGE(dp
));
59 pmd_t
*get_pointer_table (void)
61 ptable_desc
*dp
= ptable_list
.next
;
62 unsigned char mask
= PD_MARKBITS (dp
);
67 * For a pointer table for a user process address space, a
68 * table is taken from a page allocated for the purpose. Each
69 * page can hold 8 pointer tables. The page is remapped in
70 * virtual address space to be noncacheable.
76 if (!(page
= (void *)get_zeroed_page(GFP_KERNEL
)))
79 flush_tlb_kernel_page(page
);
82 new = PD_PTABLE(page
);
83 PD_MARKBITS(new) = 0xfe;
84 list_add_tail(new, dp
);
89 for (tmp
= 1, off
= 0; (mask
& tmp
) == 0; tmp
<<= 1, off
+= PTABLE_SIZE
)
91 PD_MARKBITS(dp
) = mask
& ~tmp
;
92 if (!PD_MARKBITS(dp
)) {
93 /* move to end of list */
94 list_move_tail(dp
, &ptable_list
);
96 return (pmd_t
*) (page_address(PD_PAGE(dp
)) + off
);
99 int free_pointer_table (pmd_t
*ptable
)
102 unsigned long page
= (unsigned long)ptable
& PAGE_MASK
;
103 unsigned char mask
= 1 << (((unsigned long)ptable
- page
)/PTABLE_SIZE
);
105 dp
= PD_PTABLE(page
);
106 if (PD_MARKBITS (dp
) & mask
)
107 panic ("table already free!");
109 PD_MARKBITS (dp
) |= mask
;
111 if (PD_MARKBITS(dp
) == 0xff) {
112 /* all tables in page are free, free page */
114 cache_page((void *)page
);
117 } else if (ptable_list
.next
!= dp
) {
119 * move this descriptor to the front of the list, since
120 * it has one or more free tables.
122 list_move(dp
, &ptable_list
);
127 /* invalidate page in both caches */
128 static inline void clear040(unsigned long paddr
)
133 "cinvp %%bc,(%0)\n\t"
138 /* invalidate page in i-cache */
139 static inline void cleari040(unsigned long paddr
)
144 "cinvp %%ic,(%0)\n\t"
149 /* push page in both caches */
150 /* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
151 static inline void push040(unsigned long paddr
)
156 "cpushp %%bc,(%0)\n\t"
161 /* push and invalidate page in both caches, must disable ints
162 * to avoid invalidating valid data */
163 static inline void pushcl040(unsigned long paddr
)
167 local_irq_save(flags
);
171 local_irq_restore(flags
);
175 * 040: Hit every page containing an address in the range paddr..paddr+len-1.
176 * (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
177 * Hit every page until there is a page or less to go. Hit the next page,
178 * and the one after that if the range hits it.
180 /* ++roman: A little bit more care is required here: The CINVP instruction
181 * invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
182 * and the end of the region must be treated differently if they are not
183 * exactly at the beginning or end of a page boundary. Else, maybe too much
184 * data becomes invalidated and thus lost forever. CPUSHP does what we need:
185 * it invalidates the page after pushing dirty data to memory. (Thanks to Jes
186 * for discovering the problem!)
188 /* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
189 * the DPI bit in the CACR; would it cause problems with temporarily changing
190 * this?). So we have to push first and then additionally to invalidate.
195 * cache_clear() semantics: Clear any cache entries for the area in question,
196 * without writing back dirty entries first. This is useful if the data will
197 * be overwritten anyway, e.g. by DMA to memory. The range is defined by a
198 * _physical_ address.
201 void cache_clear (unsigned long paddr
, int len
)
203 if (CPU_IS_COLDFIRE
) {
204 clear_cf_bcache(0, DCACHE_MAX_ADDR
);
205 } else if (CPU_IS_040_OR_060
) {
209 * We need special treatment for the first page, in case it
210 * is not page-aligned. Page align the addresses to work
211 * around bug I17 in the 68060.
213 if ((tmp
= -paddr
& (PAGE_SIZE
- 1))) {
214 pushcl040(paddr
& PAGE_MASK
);
215 if ((len
-= tmp
) <= 0)
221 while ((len
-= tmp
) >= 0) {
226 /* a page boundary gets crossed at the end */
229 else /* 68030 or 68020 */
230 asm volatile ("movec %/cacr,%/d0\n\t"
233 : : "i" (FLUSH_I_AND_D
)
235 #ifdef CONFIG_M68K_L2_CACHE
240 EXPORT_SYMBOL(cache_clear
);
244 * cache_push() semantics: Write back any dirty cache data in the given area,
245 * and invalidate the range in the instruction cache. It needs not (but may)
246 * invalidate those entries also in the data cache. The range is defined by a
247 * _physical_ address.
250 void cache_push (unsigned long paddr
, int len
)
252 if (CPU_IS_COLDFIRE
) {
253 flush_cf_bcache(0, DCACHE_MAX_ADDR
);
254 } else if (CPU_IS_040_OR_060
) {
258 * on 68040 or 68060, push cache lines for pages in the range;
259 * on the '040 this also invalidates the pushed lines, but not on
262 len
+= paddr
& (PAGE_SIZE
- 1);
265 * Work around bug I17 in the 68060 affecting some instruction
266 * lines not being invalidated properly.
273 } while ((len
-= tmp
) > 0);
276 * 68030/68020 have no writeback cache. On the other hand,
277 * cache_push is actually a superset of cache_clear (the lines
278 * get written back and invalidated), so we should make sure
279 * to perform the corresponding actions. After all, this is getting
280 * called in places where we've just loaded code, or whatever, so
281 * flushing the icache is appropriate; flushing the dcache shouldn't
284 else /* 68030 or 68020 */
285 asm volatile ("movec %/cacr,%/d0\n\t"
290 #ifdef CONFIG_M68K_L2_CACHE
295 EXPORT_SYMBOL(cache_push
);