4 compatible = "brcm,bcm7425";
10 mips-hpt-frequency = <163125000>;
13 compatible = "brcm,bmips5000";
19 compatible = "brcm,bmips5000";
29 cpu_intc: interrupt-controller {
31 compatible = "mti,cpu-interrupt-controller";
34 #interrupt-cells = <1>;
39 compatible = "fixed-clock";
41 clock-frequency = <81000000>;
45 compatible = "fixed-clock";
47 clock-frequency = <27000000>;
55 compatible = "simple-bus";
56 ranges = <0 0x10000000 0x01000000>;
58 periph_intc: interrupt-controller@41a400 {
59 compatible = "brcm,bcm7038-l1-intc";
60 reg = <0x41a400 0x30>, <0x41a600 0x30>;
63 #interrupt-cells = <1>;
65 interrupt-parent = <&cpu_intc>;
66 interrupts = <2>, <3>;
69 sun_l2_intc: interrupt-controller@403000 {
70 compatible = "brcm,l2-intc";
71 reg = <0x403000 0x30>;
73 #interrupt-cells = <1>;
74 interrupt-parent = <&periph_intc>;
79 compatible = "brcm,bcm7400-gisb-arb";
80 reg = <0x400000 0xdc>;
82 interrupt-parent = <&sun_l2_intc>;
83 interrupts = <0>, <2>;
84 brcm,gisb-arb-master-mask = <0x177b>;
85 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
92 upg_irq0_intc: interrupt-controller@406780 {
93 compatible = "brcm,bcm7120-l2-intc";
96 brcm,int-map-mask = <0x44>, <0x7000000>;
97 brcm,int-fwd-mask = <0x70000>;
100 #interrupt-cells = <1>;
102 interrupt-parent = <&periph_intc>;
103 interrupts = <55>, <53>;
104 interrupt-names = "upg_main", "upg_bsc";
107 upg_aon_irq0_intc: interrupt-controller@409480 {
108 compatible = "brcm,bcm7120-l2-intc";
109 reg = <0x409480 0x8>;
111 brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
112 brcm,int-fwd-mask = <0>;
115 interrupt-controller;
116 #interrupt-cells = <1>;
118 interrupt-parent = <&periph_intc>;
119 interrupts = <56>, <54>, <59>;
120 interrupt-names = "upg_main_aon", "upg_bsc_aon",
124 sun_top_ctrl: syscon@404000 {
125 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
126 reg = <0x404000 0x51c>;
131 compatible = "brcm,brcmstb-reboot";
132 syscon = <&sun_top_ctrl 0x304 0x308>;
135 uart0: serial@406b00 {
136 compatible = "ns16550a";
137 reg = <0x406b00 0x20>;
138 reg-io-width = <0x4>;
140 interrupt-parent = <&periph_intc>;
142 clocks = <&uart_clk>;
146 uart1: serial@406b40 {
147 compatible = "ns16550a";
148 reg = <0x406b40 0x20>;
149 reg-io-width = <0x4>;
151 interrupt-parent = <&periph_intc>;
153 clocks = <&uart_clk>;
157 uart2: serial@406b80 {
158 compatible = "ns16550a";
159 reg = <0x406b80 0x20>;
160 reg-io-width = <0x4>;
162 interrupt-parent = <&periph_intc>;
164 clocks = <&uart_clk>;
169 clock-frequency = <390000>;
170 compatible = "brcm,brcmstb-i2c";
171 interrupt-parent = <&upg_aon_irq0_intc>;
172 reg = <0x409180 0x58>;
174 interrupt-names = "upg_bsca";
179 clock-frequency = <390000>;
180 compatible = "brcm,brcmstb-i2c";
181 interrupt-parent = <&upg_aon_irq0_intc>;
182 reg = <0x409400 0x58>;
184 interrupt-names = "upg_bscb";
189 clock-frequency = <390000>;
190 compatible = "brcm,brcmstb-i2c";
191 interrupt-parent = <&upg_irq0_intc>;
192 reg = <0x406200 0x58>;
194 interrupt-names = "upg_bscc";
199 clock-frequency = <390000>;
200 compatible = "brcm,brcmstb-i2c";
201 interrupt-parent = <&upg_irq0_intc>;
202 reg = <0x406280 0x58>;
204 interrupt-names = "upg_bscd";
209 clock-frequency = <390000>;
210 compatible = "brcm,brcmstb-i2c";
211 interrupt-parent = <&upg_irq0_intc>;
212 reg = <0x406300 0x58>;
214 interrupt-names = "upg_bsce";
219 compatible = "brcm,bcm7038-pwm";
220 reg = <0x406580 0x28>;
227 compatible = "brcm,bcm7038-pwm";
228 reg = <0x406800 0x28>;
234 aon_pm_l2_intc: interrupt-controller@408440 {
235 compatible = "brcm,l2-intc";
236 reg = <0x408440 0x30>;
237 interrupt-controller;
238 #interrupt-cells = <1>;
239 interrupt-parent = <&periph_intc>;
244 upg_gio: gpio@406700 {
245 compatible = "brcm,brcmstb-gpio";
246 reg = <0x406700 0x80>;
248 #interrupt-cells = <2>;
250 interrupt-controller;
251 interrupt-parent = <&upg_irq0_intc>;
253 brcm,gpio-bank-widths = <32 32 32 21>;
256 upg_gio_aon: gpio@4094c0 {
257 compatible = "brcm,brcmstb-gpio";
258 reg = <0x4094c0 0x40>;
260 #interrupt-cells = <2>;
262 interrupt-controller;
263 interrupt-parent = <&upg_aon_irq0_intc>;
265 interrupts-extended = <&upg_aon_irq0_intc 6>,
268 brcm,gpio-bank-widths = <18 4>;
271 enet0: ethernet@b80000 {
272 phy-mode = "internal";
273 phy-handle = <&phy1>;
274 mac-address = [ 00 10 18 36 23 1a ];
275 compatible = "brcm,genet-v3";
276 #address-cells = <0x1>;
278 reg = <0xb80000 0x11c88>;
279 interrupts = <17>, <18>;
280 interrupt-parent = <&periph_intc>;
284 compatible = "brcm,genet-mdio-v3";
285 #address-cells = <0x1>;
289 phy1: ethernet-phy@1 {
292 compatible = "brcm,40nm-ephy",
293 "ethernet-phy-ieee802.3-c22";
299 compatible = "brcm,bcm7425-ehci", "generic-ehci";
300 reg = <0x480300 0x100>;
302 interrupt-parent = <&periph_intc>;
308 compatible = "brcm,bcm7425-ohci", "generic-ohci";
309 reg = <0x480400 0x100>;
312 interrupt-parent = <&periph_intc>;
318 compatible = "brcm,bcm7425-ehci", "generic-ehci";
319 reg = <0x480500 0x100>;
321 interrupt-parent = <&periph_intc>;
327 compatible = "brcm,bcm7425-ohci", "generic-ohci";
328 reg = <0x480600 0x100>;
331 interrupt-parent = <&periph_intc>;
337 compatible = "brcm,bcm7425-ehci", "generic-ehci";
338 reg = <0x490300 0x100>;
340 interrupt-parent = <&periph_intc>;
346 compatible = "brcm,bcm7425-ohci", "generic-ohci";
347 reg = <0x490400 0x100>;
350 interrupt-parent = <&periph_intc>;
356 compatible = "brcm,bcm7425-ehci", "generic-ehci";
357 reg = <0x490500 0x100>;
359 interrupt-parent = <&periph_intc>;
365 compatible = "brcm,bcm7425-ohci", "generic-ohci";
366 reg = <0x490600 0x100>;
369 interrupt-parent = <&periph_intc>;
374 hif_l2_intc: interrupt-controller@41a000 {
375 compatible = "brcm,l2-intc";
376 reg = <0x41a000 0x30>;
377 interrupt-controller;
378 #interrupt-cells = <1>;
379 interrupt-parent = <&periph_intc>;
384 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
385 #address-cells = <1>;
388 reg = <0x41b800 0x400>;
389 interrupt-parent = <&hif_l2_intc>;
395 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
396 reg-names = "ahci", "top-ctrl";
397 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
398 interrupt-parent = <&periph_intc>;
400 #address-cells = <1>;
415 sata_phy: sata-phy@180100 {
416 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
417 reg = <0x180100 0x0eff>;
419 #address-cells = <1>;
423 sata_phy0: sata-phy@0 {
428 sata_phy1: sata-phy@1 {
434 sdhci0: sdhci@419000 {
435 compatible = "brcm,bcm7425-sdhci";
436 reg = <0x419000 0x100>;
437 interrupt-parent = <&periph_intc>;
444 sdhci1: sdhci@419200 {
445 compatible = "brcm,bcm7425-sdhci";
446 reg = <0x419200 0x100>;
447 interrupt-parent = <&periph_intc>;
454 spi_l2_intc: interrupt-controller@41ad00 {
455 compatible = "brcm,l2-intc";
456 reg = <0x41ad00 0x30>;
457 interrupt-controller;
458 #interrupt-cells = <1>;
459 interrupt-parent = <&periph_intc>;
464 #address-cells = <0x1>;
466 compatible = "brcm,spi-bcm-qspi",
467 "brcm,spi-brcmstb-qspi";
469 reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
470 reg-names = "cs_reg", "hif_mspi", "bspi";
471 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
472 interrupt-parent = <&spi_l2_intc>;
473 interrupt-names = "spi_lr_fullness_reached",
474 "spi_lr_session_aborted",
476 "spi_lr_session_done",
484 #address-cells = <1>;
486 compatible = "brcm,spi-bcm-qspi",
487 "brcm,spi-brcmstb-mspi";
489 reg = <0x409200 0x180>;
492 interrupt-parent = <&upg_aon_irq0_intc>;
493 interrupt-names = "mspi_done";