2 * Format of an instruction in memory.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer
10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2014 Imagination Technologies Ltd.
13 #ifndef _UAPI_ASM_INST_H
14 #define _UAPI_ASM_INST_H
16 #include <asm/bitfield.h>
19 * Major opcodes; before MIPS IV cop1x was called cop3.
22 spec_op
, bcond_op
, j_op
, jal_op
,
23 beq_op
, bne_op
, blez_op
, bgtz_op
,
24 addi_op
, pop10_op
= addi_op
, addiu_op
, slti_op
, sltiu_op
,
25 andi_op
, ori_op
, xori_op
, lui_op
,
26 cop0_op
, cop1_op
, cop2_op
, cop1x_op
,
27 beql_op
, bnel_op
, blezl_op
, bgtzl_op
,
28 daddi_op
, pop30_op
= daddi_op
, daddiu_op
, ldl_op
, ldr_op
,
29 spec2_op
, jalx_op
, mdmx_op
, msa_op
= mdmx_op
, spec3_op
,
30 lb_op
, lh_op
, lwl_op
, lw_op
,
31 lbu_op
, lhu_op
, lwr_op
, lwu_op
,
32 sb_op
, sh_op
, swl_op
, sw_op
,
33 sdl_op
, sdr_op
, swr_op
, cache_op
,
34 ll_op
, lwc1_op
, lwc2_op
, bc6_op
= lwc2_op
, pref_op
,
35 lld_op
, ldc1_op
, ldc2_op
, pop66_op
= ldc2_op
, ld_op
,
36 sc_op
, swc1_op
, swc2_op
, balc6_op
= swc2_op
, major_3b_op
,
37 scd_op
, sdc1_op
, sdc2_op
, pop76_op
= sdc2_op
, sd_op
41 * func field of spec opcode.
44 sll_op
, movc_op
, srl_op
, sra_op
,
45 sllv_op
, pmon_op
, srlv_op
, srav_op
,
46 jr_op
, jalr_op
, movz_op
, movn_op
,
47 syscall_op
, break_op
, spim_op
, sync_op
,
48 mfhi_op
, mthi_op
, mflo_op
, mtlo_op
,
49 dsllv_op
, spec2_unused_op
, dsrlv_op
, dsrav_op
,
50 mult_op
, multu_op
, div_op
, divu_op
,
51 dmult_op
, dmultu_op
, ddiv_op
, ddivu_op
,
52 add_op
, addu_op
, sub_op
, subu_op
,
53 and_op
, or_op
, xor_op
, nor_op
,
54 spec3_unused_op
, spec4_unused_op
, slt_op
, sltu_op
,
55 dadd_op
, daddu_op
, dsub_op
, dsubu_op
,
56 tge_op
, tgeu_op
, tlt_op
, tltu_op
,
57 teq_op
, spec5_unused_op
, tne_op
, spec6_unused_op
,
58 dsll_op
, spec7_unused_op
, dsrl_op
, dsra_op
,
59 dsll32_op
, spec8_unused_op
, dsrl32_op
, dsra32_op
63 * func field of spec2 opcode.
66 madd_op
, maddu_op
, mul_op
, spec2_3_unused_op
,
67 msub_op
, msubu_op
, /* more unused ops */
68 clz_op
= 0x20, clo_op
,
69 dclz_op
= 0x24, dclo_op
,
74 * func field of spec3 opcode.
77 ext_op
, dextm_op
, dextu_op
, dext_op
,
78 ins_op
, dinsm_op
, dinsu_op
, dins_op
,
79 yield_op
= 0x09, lx_op
= 0x0a,
80 lwle_op
= 0x19, lwre_op
= 0x1a,
81 cachee_op
= 0x1b, sbe_op
= 0x1c,
82 she_op
= 0x1d, sce_op
= 0x1e,
83 swe_op
= 0x1f, bshfl_op
= 0x20,
84 swle_op
= 0x21, swre_op
= 0x22,
85 prefe_op
= 0x23, dbshfl_op
= 0x24,
86 cache6_op
= 0x25, sc6_op
= 0x26,
87 scd6_op
= 0x27, lbue_op
= 0x28,
88 lhue_op
= 0x29, lbe_op
= 0x2c,
89 lhe_op
= 0x2d, lle_op
= 0x2e,
90 lwe_op
= 0x2f, pref6_op
= 0x35,
91 ll6_op
= 0x36, lld6_op
= 0x37,
96 * Bits 10-6 minor opcode for r6 spec mult/div encodings
104 multu_multu_op
= 0x0,
119 dmult_dmult_op
= 0x0,
124 dmultu_dmultu_op
= 0x0,
125 dmultu_dmulu_op
= 0x2,
126 dmultu_dmuhu_op
= 0x3,
134 ddivu_ddivu_op
= 0x0,
135 ddivu_ddivu6_op
= 0x2,
136 ddivu_dmodu_op
= 0x3,
140 * rt field of bcond opcodes.
143 bltz_op
, bgez_op
, bltzl_op
, bgezl_op
,
144 spimi_op
, unused_rt_op_0x05
, unused_rt_op_0x06
, unused_rt_op_0x07
,
145 tgei_op
, tgeiu_op
, tlti_op
, tltiu_op
,
146 teqi_op
, unused_0x0d_rt_op
, tnei_op
, unused_0x0f_rt_op
,
147 bltzal_op
, bgezal_op
, bltzall_op
, bgezall_op
,
148 rt_op_0x14
, rt_op_0x15
, rt_op_0x16
, rt_op_0x17
,
149 rt_op_0x18
, rt_op_0x19
, rt_op_0x1a
, rt_op_0x1b
,
150 bposge32_op
, rt_op_0x1d
, rt_op_0x1e
, synci_op
154 * rs field of cop opcodes.
157 mfc_op
= 0x00, dmfc_op
= 0x01,
158 cfc_op
= 0x02, mfhc0_op
= 0x02,
159 mfhc_op
= 0x03, mtc_op
= 0x04,
160 dmtc_op
= 0x05, ctc_op
= 0x06,
161 mthc0_op
= 0x06, mthc_op
= 0x07,
162 bc_op
= 0x08, bc1eqz_op
= 0x09,
163 mfmc0_op
= 0x0b, bc1nez_op
= 0x0d,
164 wrpgpr_op
= 0x0e, cop_op
= 0x10,
169 * rt field of cop.bc_op opcodes
172 bcf_op
, bct_op
, bcfl_op
, bctl_op
176 * func field of cop0 coi opcodes.
179 tlbr_op
= 0x01, tlbwi_op
= 0x02,
180 tlbwr_op
= 0x06, tlbp_op
= 0x08,
181 rfe_op
= 0x10, eret_op
= 0x18,
182 wait_op
= 0x20, hypcall_op
= 0x28
186 * func field of cop0 com opcodes.
189 tlbr1_op
= 0x01, tlbw_op
= 0x02,
190 tlbp1_op
= 0x08, dctr_op
= 0x09,
195 * fmt field of cop1 opcodes.
198 s_fmt
, d_fmt
, e_fmt
, q_fmt
,
203 * func field of cop1 instructions using d, s or w format.
206 fadd_op
= 0x00, fsub_op
= 0x01,
207 fmul_op
= 0x02, fdiv_op
= 0x03,
208 fsqrt_op
= 0x04, fabs_op
= 0x05,
209 fmov_op
= 0x06, fneg_op
= 0x07,
210 froundl_op
= 0x08, ftruncl_op
= 0x09,
211 fceill_op
= 0x0a, ffloorl_op
= 0x0b,
212 fround_op
= 0x0c, ftrunc_op
= 0x0d,
213 fceil_op
= 0x0e, ffloor_op
= 0x0f,
215 fmovc_op
= 0x11, fmovz_op
= 0x12,
216 fmovn_op
= 0x13, fseleqz_op
= 0x14,
217 frecip_op
= 0x15, frsqrt_op
= 0x16,
218 fselnez_op
= 0x17, fmaddf_op
= 0x18,
219 fmsubf_op
= 0x19, frint_op
= 0x1a,
220 fclass_op
= 0x1b, fmin_op
= 0x1c,
221 fmina_op
= 0x1d, fmax_op
= 0x1e,
222 fmaxa_op
= 0x1f, fcvts_op
= 0x20,
223 fcvtd_op
= 0x21, fcvte_op
= 0x22,
224 fcvtw_op
= 0x24, fcvtl_op
= 0x25,
229 * func field of cop1x opcodes (MIPS IV).
232 lwxc1_op
= 0x00, ldxc1_op
= 0x01,
233 swxc1_op
= 0x08, sdxc1_op
= 0x09,
234 pfetch_op
= 0x0f, madd_s_op
= 0x20,
235 madd_d_op
= 0x21, madd_e_op
= 0x22,
236 msub_s_op
= 0x28, msub_d_op
= 0x29,
237 msub_e_op
= 0x2a, nmadd_s_op
= 0x30,
238 nmadd_d_op
= 0x31, nmadd_e_op
= 0x32,
239 nmsub_s_op
= 0x38, nmsub_d_op
= 0x39,
244 * func field for mad opcodes (MIPS IV).
247 madd_fp_op
= 0x08, msub_fp_op
= 0x0a,
248 nmadd_fp_op
= 0x0c, nmsub_fp_op
= 0x0e
252 * func field for page table walker (Loongson-3).
262 * func field for special3 lx opcodes (Cavium Octeon).
307 * func field for MSA MI10 format.
315 * MSA 2 bit format fields.
325 * (microMIPS) Major opcodes.
328 mm_pool32a_op
, mm_pool16a_op
, mm_lbu16_op
, mm_move16_op
,
329 mm_addi32_op
, mm_lbu32_op
, mm_sb32_op
, mm_lb32_op
,
330 mm_pool32b_op
, mm_pool16b_op
, mm_lhu16_op
, mm_andi16_op
,
331 mm_addiu32_op
, mm_lhu32_op
, mm_sh32_op
, mm_lh32_op
,
332 mm_pool32i_op
, mm_pool16c_op
, mm_lwsp16_op
, mm_pool16d_op
,
333 mm_ori32_op
, mm_pool32f_op
, mm_pool32s_op
, mm_reserved2_op
,
334 mm_pool32c_op
, mm_lwgp16_op
, mm_lw16_op
, mm_pool16e_op
,
335 mm_xori32_op
, mm_jals32_op
, mm_addiupc_op
, mm_reserved3_op
,
336 mm_reserved4_op
, mm_pool16f_op
, mm_sb16_op
, mm_beqz16_op
,
337 mm_slti32_op
, mm_beq32_op
, mm_swc132_op
, mm_lwc132_op
,
338 mm_reserved5_op
, mm_reserved6_op
, mm_sh16_op
, mm_bnez16_op
,
339 mm_sltiu32_op
, mm_bne32_op
, mm_sdc132_op
, mm_ldc132_op
,
340 mm_reserved7_op
, mm_reserved8_op
, mm_swsp16_op
, mm_b16_op
,
341 mm_andi32_op
, mm_j32_op
, mm_sd32_op
, mm_ld32_op
,
342 mm_reserved11_op
, mm_reserved12_op
, mm_sw16_op
, mm_li16_op
,
343 mm_jalx32_op
, mm_jal32_op
, mm_sw32_op
, mm_lw32_op
,
347 * (microMIPS) POOL32I minor opcodes.
349 enum mm_32i_minor_op
{
350 mm_bltz_op
, mm_bltzal_op
, mm_bgez_op
, mm_bgezal_op
,
351 mm_blez_op
, mm_bnezc_op
, mm_bgtz_op
, mm_beqzc_op
,
352 mm_tlti_op
, mm_tgei_op
, mm_tltiu_op
, mm_tgeiu_op
,
353 mm_tnei_op
, mm_lui_op
, mm_teqi_op
, mm_reserved13_op
,
354 mm_synci_op
, mm_bltzals_op
, mm_reserved14_op
, mm_bgezals_op
,
355 mm_bc2f_op
, mm_bc2t_op
, mm_reserved15_op
, mm_reserved16_op
,
356 mm_reserved17_op
, mm_reserved18_op
, mm_bposge64_op
, mm_bposge32_op
,
357 mm_bc1f_op
, mm_bc1t_op
, mm_reserved19_op
, mm_reserved20_op
,
358 mm_bc1any2f_op
, mm_bc1any2t_op
, mm_bc1any4f_op
, mm_bc1any4t_op
,
362 * (microMIPS) POOL32A minor opcodes.
364 enum mm_32a_minor_op
{
367 mm_sllv32_op
= 0x010,
369 mm_pool32axf_op
= 0x03c,
372 mm_srlv32_op
= 0x090,
375 mm_addu32_op
= 0x150,
376 mm_subu32_op
= 0x1d0,
387 * (microMIPS) POOL32B functions.
406 * (microMIPS) POOL32C functions.
417 * (microMIPS) POOL32AXF minor opcodes.
419 enum mm_32axf_minor_op
{
423 mm_mfhi32_op
= 0x035,
426 mm_mflo32_op
= 0x075,
427 mm_jalrhb_op
= 0x07c,
429 mm_mthi32_op
= 0x0b5,
431 mm_mtlo32_op
= 0x0f5,
434 mm_jalrshb_op
= 0x17c,
436 mm_syscall_op
= 0x22d,
443 * (microMIPS) POOL32F minor opcodes.
445 enum mm_32f_minor_op
{
467 * (microMIPS) POOL32F secondary minor opcodes.
469 enum mm_32f_10_minor_op
{
479 mm_lwxc1_func
= 0x048,
480 mm_swxc1_func
= 0x088,
481 mm_ldxc1_func
= 0x0c8,
482 mm_sdxc1_func
= 0x108,
486 * (microMIPS) POOL32F secondary minor opcodes.
488 enum mm_32f_40_minor_op
{
494 * (microMIPS) POOL32F secondary minor opcodes.
496 enum mm_32f_60_minor_op
{
504 * (microMIPS) POOL32F secondary minor opcodes.
506 enum mm_32f_70_minor_op
{
512 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
514 enum mm_32f_73_minor_op
{
519 mm_ffloorl_op
= 0x0c,
524 mm_ffloorw_op
= 0x2c,
536 mm_ftruncl_op
= 0x8c,
540 mm_ftruncw_op
= 0xac,
543 mm_froundl_op
= 0xcc,
546 mm_froundw_op
= 0xec,
551 * (microMIPS) POOL32S minor opcodes.
553 enum mm_32s_minor_op
{
554 mm_32s_elm_op
= 0x16,
558 * (microMIPS) POOL16C minor opcodes.
560 enum mm_16c_minor_op
{
566 mm_jalrs16_op
= 0x0f,
567 mm_jraddiusp_op
= 0x18,
571 * (microMIPS) POOL16D minor opcodes.
573 enum mm_16d_minor_op
{
582 MIPS16e_jal_op
= 003,
588 MIPS16e_lwsp_op
= 022,
590 MIPS16e_lbu_op
= 024,
591 MIPS16e_lhu_op
= 025,
592 MIPS16e_lwpc_op
= 026,
593 MIPS16e_lwu_op
= 027,
596 MIPS16e_swsp_op
= 032,
599 MIPS16e_extend_op
= 036,
600 MIPS16e_i64_op
= 037,
603 enum MIPS16e_i64_func
{
611 enum MIPS16e_rr_func
{
615 enum MIPS6e_i8_func
{
616 MIPS16e_swrasp_func
= 02,
620 * (microMIPS) NOP instruction.
622 #define MM_NOP16 0x0c00
625 __BITFIELD_FIELD(unsigned int opcode
: 6, /* Jump format */
626 __BITFIELD_FIELD(unsigned int target
: 26,
630 struct i_format
{ /* signed immediate format */
631 __BITFIELD_FIELD(unsigned int opcode
: 6,
632 __BITFIELD_FIELD(unsigned int rs
: 5,
633 __BITFIELD_FIELD(unsigned int rt
: 5,
634 __BITFIELD_FIELD(signed int simmediate
: 16,
638 struct u_format
{ /* unsigned immediate format */
639 __BITFIELD_FIELD(unsigned int opcode
: 6,
640 __BITFIELD_FIELD(unsigned int rs
: 5,
641 __BITFIELD_FIELD(unsigned int rt
: 5,
642 __BITFIELD_FIELD(unsigned int uimmediate
: 16,
646 struct c_format
{ /* Cache (>= R6000) format */
647 __BITFIELD_FIELD(unsigned int opcode
: 6,
648 __BITFIELD_FIELD(unsigned int rs
: 5,
649 __BITFIELD_FIELD(unsigned int c_op
: 3,
650 __BITFIELD_FIELD(unsigned int cache
: 2,
651 __BITFIELD_FIELD(unsigned int simmediate
: 16,
655 struct r_format
{ /* Register format */
656 __BITFIELD_FIELD(unsigned int opcode
: 6,
657 __BITFIELD_FIELD(unsigned int rs
: 5,
658 __BITFIELD_FIELD(unsigned int rt
: 5,
659 __BITFIELD_FIELD(unsigned int rd
: 5,
660 __BITFIELD_FIELD(unsigned int re
: 5,
661 __BITFIELD_FIELD(unsigned int func
: 6,
665 struct c0r_format
{ /* C0 register format */
666 __BITFIELD_FIELD(unsigned int opcode
: 6,
667 __BITFIELD_FIELD(unsigned int rs
: 5,
668 __BITFIELD_FIELD(unsigned int rt
: 5,
669 __BITFIELD_FIELD(unsigned int rd
: 5,
670 __BITFIELD_FIELD(unsigned int z
: 8,
671 __BITFIELD_FIELD(unsigned int sel
: 3,
675 struct mfmc0_format
{ /* MFMC0 register format */
676 __BITFIELD_FIELD(unsigned int opcode
: 6,
677 __BITFIELD_FIELD(unsigned int rs
: 5,
678 __BITFIELD_FIELD(unsigned int rt
: 5,
679 __BITFIELD_FIELD(unsigned int rd
: 5,
680 __BITFIELD_FIELD(unsigned int re
: 5,
681 __BITFIELD_FIELD(unsigned int sc
: 1,
682 __BITFIELD_FIELD(unsigned int : 2,
683 __BITFIELD_FIELD(unsigned int sel
: 3,
687 struct co_format
{ /* C0 CO format */
688 __BITFIELD_FIELD(unsigned int opcode
: 6,
689 __BITFIELD_FIELD(unsigned int co
: 1,
690 __BITFIELD_FIELD(unsigned int code
: 19,
691 __BITFIELD_FIELD(unsigned int func
: 6,
695 struct p_format
{ /* Performance counter format (R10000) */
696 __BITFIELD_FIELD(unsigned int opcode
: 6,
697 __BITFIELD_FIELD(unsigned int rs
: 5,
698 __BITFIELD_FIELD(unsigned int rt
: 5,
699 __BITFIELD_FIELD(unsigned int rd
: 5,
700 __BITFIELD_FIELD(unsigned int re
: 5,
701 __BITFIELD_FIELD(unsigned int func
: 6,
705 struct f_format
{ /* FPU register format */
706 __BITFIELD_FIELD(unsigned int opcode
: 6,
707 __BITFIELD_FIELD(unsigned int : 1,
708 __BITFIELD_FIELD(unsigned int fmt
: 4,
709 __BITFIELD_FIELD(unsigned int rt
: 5,
710 __BITFIELD_FIELD(unsigned int rd
: 5,
711 __BITFIELD_FIELD(unsigned int re
: 5,
712 __BITFIELD_FIELD(unsigned int func
: 6,
716 struct ma_format
{ /* FPU multiply and add format (MIPS IV) */
717 __BITFIELD_FIELD(unsigned int opcode
: 6,
718 __BITFIELD_FIELD(unsigned int fr
: 5,
719 __BITFIELD_FIELD(unsigned int ft
: 5,
720 __BITFIELD_FIELD(unsigned int fs
: 5,
721 __BITFIELD_FIELD(unsigned int fd
: 5,
722 __BITFIELD_FIELD(unsigned int func
: 4,
723 __BITFIELD_FIELD(unsigned int fmt
: 2,
727 struct b_format
{ /* BREAK and SYSCALL */
728 __BITFIELD_FIELD(unsigned int opcode
: 6,
729 __BITFIELD_FIELD(unsigned int code
: 20,
730 __BITFIELD_FIELD(unsigned int func
: 6,
734 struct ps_format
{ /* MIPS-3D / paired single format */
735 __BITFIELD_FIELD(unsigned int opcode
: 6,
736 __BITFIELD_FIELD(unsigned int rs
: 5,
737 __BITFIELD_FIELD(unsigned int ft
: 5,
738 __BITFIELD_FIELD(unsigned int fs
: 5,
739 __BITFIELD_FIELD(unsigned int fd
: 5,
740 __BITFIELD_FIELD(unsigned int func
: 6,
744 struct v_format
{ /* MDMX vector format */
745 __BITFIELD_FIELD(unsigned int opcode
: 6,
746 __BITFIELD_FIELD(unsigned int sel
: 4,
747 __BITFIELD_FIELD(unsigned int fmt
: 1,
748 __BITFIELD_FIELD(unsigned int vt
: 5,
749 __BITFIELD_FIELD(unsigned int vs
: 5,
750 __BITFIELD_FIELD(unsigned int vd
: 5,
751 __BITFIELD_FIELD(unsigned int func
: 6,
755 struct msa_mi10_format
{ /* MSA MI10 */
756 __BITFIELD_FIELD(unsigned int opcode
: 6,
757 __BITFIELD_FIELD(signed int s10
: 10,
758 __BITFIELD_FIELD(unsigned int rs
: 5,
759 __BITFIELD_FIELD(unsigned int wd
: 5,
760 __BITFIELD_FIELD(unsigned int func
: 4,
761 __BITFIELD_FIELD(unsigned int df
: 2,
765 struct dsp_format
{ /* SPEC3 DSP format instructions */
766 __BITFIELD_FIELD(unsigned int opcode
: 6,
767 __BITFIELD_FIELD(unsigned int base
: 5,
768 __BITFIELD_FIELD(unsigned int index
: 5,
769 __BITFIELD_FIELD(unsigned int rd
: 5,
770 __BITFIELD_FIELD(unsigned int op
: 5,
771 __BITFIELD_FIELD(unsigned int func
: 6,
775 struct spec3_format
{ /* SPEC3 */
776 __BITFIELD_FIELD(unsigned int opcode
:6,
777 __BITFIELD_FIELD(unsigned int rs
:5,
778 __BITFIELD_FIELD(unsigned int rt
:5,
779 __BITFIELD_FIELD(signed int simmediate
:9,
780 __BITFIELD_FIELD(unsigned int func
:7,
785 * microMIPS instruction formats (32-bit length)
788 * Parenthesis denote whether the format is a microMIPS instruction or
789 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
791 struct fb_format
{ /* FPU branch format (MIPS32) */
792 __BITFIELD_FIELD(unsigned int opcode
: 6,
793 __BITFIELD_FIELD(unsigned int bc
: 5,
794 __BITFIELD_FIELD(unsigned int cc
: 3,
795 __BITFIELD_FIELD(unsigned int flag
: 2,
796 __BITFIELD_FIELD(signed int simmediate
: 16,
800 struct fp0_format
{ /* FPU multiply and add format (MIPS32) */
801 __BITFIELD_FIELD(unsigned int opcode
: 6,
802 __BITFIELD_FIELD(unsigned int fmt
: 5,
803 __BITFIELD_FIELD(unsigned int ft
: 5,
804 __BITFIELD_FIELD(unsigned int fs
: 5,
805 __BITFIELD_FIELD(unsigned int fd
: 5,
806 __BITFIELD_FIELD(unsigned int func
: 6,
810 struct mm_fp0_format
{ /* FPU multiply and add format (microMIPS) */
811 __BITFIELD_FIELD(unsigned int opcode
: 6,
812 __BITFIELD_FIELD(unsigned int ft
: 5,
813 __BITFIELD_FIELD(unsigned int fs
: 5,
814 __BITFIELD_FIELD(unsigned int fd
: 5,
815 __BITFIELD_FIELD(unsigned int fmt
: 3,
816 __BITFIELD_FIELD(unsigned int op
: 2,
817 __BITFIELD_FIELD(unsigned int func
: 6,
821 struct fp1_format
{ /* FPU mfc1 and cfc1 format (MIPS32) */
822 __BITFIELD_FIELD(unsigned int opcode
: 6,
823 __BITFIELD_FIELD(unsigned int op
: 5,
824 __BITFIELD_FIELD(unsigned int rt
: 5,
825 __BITFIELD_FIELD(unsigned int fs
: 5,
826 __BITFIELD_FIELD(unsigned int fd
: 5,
827 __BITFIELD_FIELD(unsigned int func
: 6,
831 struct mm_fp1_format
{ /* FPU mfc1 and cfc1 format (microMIPS) */
832 __BITFIELD_FIELD(unsigned int opcode
: 6,
833 __BITFIELD_FIELD(unsigned int rt
: 5,
834 __BITFIELD_FIELD(unsigned int fs
: 5,
835 __BITFIELD_FIELD(unsigned int fmt
: 2,
836 __BITFIELD_FIELD(unsigned int op
: 8,
837 __BITFIELD_FIELD(unsigned int func
: 6,
841 struct mm_fp2_format
{ /* FPU movt and movf format (microMIPS) */
842 __BITFIELD_FIELD(unsigned int opcode
: 6,
843 __BITFIELD_FIELD(unsigned int fd
: 5,
844 __BITFIELD_FIELD(unsigned int fs
: 5,
845 __BITFIELD_FIELD(unsigned int cc
: 3,
846 __BITFIELD_FIELD(unsigned int zero
: 2,
847 __BITFIELD_FIELD(unsigned int fmt
: 2,
848 __BITFIELD_FIELD(unsigned int op
: 3,
849 __BITFIELD_FIELD(unsigned int func
: 6,
853 struct mm_fp3_format
{ /* FPU abs and neg format (microMIPS) */
854 __BITFIELD_FIELD(unsigned int opcode
: 6,
855 __BITFIELD_FIELD(unsigned int rt
: 5,
856 __BITFIELD_FIELD(unsigned int fs
: 5,
857 __BITFIELD_FIELD(unsigned int fmt
: 3,
858 __BITFIELD_FIELD(unsigned int op
: 7,
859 __BITFIELD_FIELD(unsigned int func
: 6,
863 struct mm_fp4_format
{ /* FPU c.cond format (microMIPS) */
864 __BITFIELD_FIELD(unsigned int opcode
: 6,
865 __BITFIELD_FIELD(unsigned int rt
: 5,
866 __BITFIELD_FIELD(unsigned int fs
: 5,
867 __BITFIELD_FIELD(unsigned int cc
: 3,
868 __BITFIELD_FIELD(unsigned int fmt
: 3,
869 __BITFIELD_FIELD(unsigned int cond
: 4,
870 __BITFIELD_FIELD(unsigned int func
: 6,
874 struct mm_fp5_format
{ /* FPU lwxc1 and swxc1 format (microMIPS) */
875 __BITFIELD_FIELD(unsigned int opcode
: 6,
876 __BITFIELD_FIELD(unsigned int index
: 5,
877 __BITFIELD_FIELD(unsigned int base
: 5,
878 __BITFIELD_FIELD(unsigned int fd
: 5,
879 __BITFIELD_FIELD(unsigned int op
: 5,
880 __BITFIELD_FIELD(unsigned int func
: 6,
884 struct fp6_format
{ /* FPU madd and msub format (MIPS IV) */
885 __BITFIELD_FIELD(unsigned int opcode
: 6,
886 __BITFIELD_FIELD(unsigned int fr
: 5,
887 __BITFIELD_FIELD(unsigned int ft
: 5,
888 __BITFIELD_FIELD(unsigned int fs
: 5,
889 __BITFIELD_FIELD(unsigned int fd
: 5,
890 __BITFIELD_FIELD(unsigned int func
: 6,
894 struct mm_fp6_format
{ /* FPU madd and msub format (microMIPS) */
895 __BITFIELD_FIELD(unsigned int opcode
: 6,
896 __BITFIELD_FIELD(unsigned int ft
: 5,
897 __BITFIELD_FIELD(unsigned int fs
: 5,
898 __BITFIELD_FIELD(unsigned int fd
: 5,
899 __BITFIELD_FIELD(unsigned int fr
: 5,
900 __BITFIELD_FIELD(unsigned int func
: 6,
904 struct mm_i_format
{ /* Immediate format (microMIPS) */
905 __BITFIELD_FIELD(unsigned int opcode
: 6,
906 __BITFIELD_FIELD(unsigned int rt
: 5,
907 __BITFIELD_FIELD(unsigned int rs
: 5,
908 __BITFIELD_FIELD(signed int simmediate
: 16,
912 struct mm_m_format
{ /* Multi-word load/store format (microMIPS) */
913 __BITFIELD_FIELD(unsigned int opcode
: 6,
914 __BITFIELD_FIELD(unsigned int rd
: 5,
915 __BITFIELD_FIELD(unsigned int base
: 5,
916 __BITFIELD_FIELD(unsigned int func
: 4,
917 __BITFIELD_FIELD(signed int simmediate
: 12,
921 struct mm_x_format
{ /* Scaled indexed load format (microMIPS) */
922 __BITFIELD_FIELD(unsigned int opcode
: 6,
923 __BITFIELD_FIELD(unsigned int index
: 5,
924 __BITFIELD_FIELD(unsigned int base
: 5,
925 __BITFIELD_FIELD(unsigned int rd
: 5,
926 __BITFIELD_FIELD(unsigned int func
: 11,
930 struct mm_a_format
{ /* ADDIUPC format (microMIPS) */
931 __BITFIELD_FIELD(unsigned int opcode
: 6,
932 __BITFIELD_FIELD(unsigned int rs
: 3,
933 __BITFIELD_FIELD(signed int simmediate
: 23,
938 * microMIPS instruction formats (16-bit length)
940 struct mm_b0_format
{ /* Unconditional branch format (microMIPS) */
941 __BITFIELD_FIELD(unsigned int opcode
: 6,
942 __BITFIELD_FIELD(signed int simmediate
: 10,
943 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
947 struct mm_b1_format
{ /* Conditional branch format (microMIPS) */
948 __BITFIELD_FIELD(unsigned int opcode
: 6,
949 __BITFIELD_FIELD(unsigned int rs
: 3,
950 __BITFIELD_FIELD(signed int simmediate
: 7,
951 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
955 struct mm16_m_format
{ /* Multi-word load/store format */
956 __BITFIELD_FIELD(unsigned int opcode
: 6,
957 __BITFIELD_FIELD(unsigned int func
: 4,
958 __BITFIELD_FIELD(unsigned int rlist
: 2,
959 __BITFIELD_FIELD(unsigned int imm
: 4,
960 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
964 struct mm16_rb_format
{ /* Signed immediate format */
965 __BITFIELD_FIELD(unsigned int opcode
: 6,
966 __BITFIELD_FIELD(unsigned int rt
: 3,
967 __BITFIELD_FIELD(unsigned int base
: 3,
968 __BITFIELD_FIELD(signed int simmediate
: 4,
969 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
973 struct mm16_r3_format
{ /* Load from global pointer format */
974 __BITFIELD_FIELD(unsigned int opcode
: 6,
975 __BITFIELD_FIELD(unsigned int rt
: 3,
976 __BITFIELD_FIELD(signed int simmediate
: 7,
977 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
981 struct mm16_r5_format
{ /* Load/store from stack pointer format */
982 __BITFIELD_FIELD(unsigned int opcode
: 6,
983 __BITFIELD_FIELD(unsigned int rt
: 5,
984 __BITFIELD_FIELD(unsigned int imm
: 5,
985 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
990 * MIPS16e instruction formats (16-bit length)
993 __BITFIELD_FIELD(unsigned int opcode
: 5,
994 __BITFIELD_FIELD(unsigned int rx
: 3,
995 __BITFIELD_FIELD(unsigned int nd
: 1,
996 __BITFIELD_FIELD(unsigned int l
: 1,
997 __BITFIELD_FIELD(unsigned int ra
: 1,
998 __BITFIELD_FIELD(unsigned int func
: 5,
1003 __BITFIELD_FIELD(unsigned int opcode
: 5,
1004 __BITFIELD_FIELD(unsigned int x
: 1,
1005 __BITFIELD_FIELD(unsigned int imm20_16
: 5,
1006 __BITFIELD_FIELD(signed int imm25_21
: 5,
1011 __BITFIELD_FIELD(unsigned int opcode
: 5,
1012 __BITFIELD_FIELD(unsigned int func
: 3,
1013 __BITFIELD_FIELD(unsigned int imm
: 8,
1018 __BITFIELD_FIELD(unsigned int opcode
: 5,
1019 __BITFIELD_FIELD(unsigned int func
: 3,
1020 __BITFIELD_FIELD(unsigned int ry
: 3,
1021 __BITFIELD_FIELD(unsigned int imm
: 5,
1026 __BITFIELD_FIELD(unsigned int opcode
: 5,
1027 __BITFIELD_FIELD(unsigned int rx
: 3,
1028 __BITFIELD_FIELD(unsigned int imm
: 8,
1033 __BITFIELD_FIELD(unsigned int opcode
: 5,
1034 __BITFIELD_FIELD(unsigned int rx
: 3,
1035 __BITFIELD_FIELD(unsigned int ry
: 3,
1036 __BITFIELD_FIELD(unsigned int imm
: 5,
1041 __BITFIELD_FIELD(unsigned int opcode
: 5,
1042 __BITFIELD_FIELD(unsigned int func
: 3,
1043 __BITFIELD_FIELD(unsigned int imm
: 8,
1047 union mips_instruction
{
1049 unsigned short halfword
[2];
1050 unsigned char byte
[4];
1051 struct j_format j_format
;
1052 struct i_format i_format
;
1053 struct u_format u_format
;
1054 struct c_format c_format
;
1055 struct r_format r_format
;
1056 struct c0r_format c0r_format
;
1057 struct mfmc0_format mfmc0_format
;
1058 struct co_format co_format
;
1059 struct p_format p_format
;
1060 struct f_format f_format
;
1061 struct ma_format ma_format
;
1062 struct msa_mi10_format msa_mi10_format
;
1063 struct b_format b_format
;
1064 struct ps_format ps_format
;
1065 struct v_format v_format
;
1066 struct dsp_format dsp_format
;
1067 struct spec3_format spec3_format
;
1068 struct fb_format fb_format
;
1069 struct fp0_format fp0_format
;
1070 struct mm_fp0_format mm_fp0_format
;
1071 struct fp1_format fp1_format
;
1072 struct mm_fp1_format mm_fp1_format
;
1073 struct mm_fp2_format mm_fp2_format
;
1074 struct mm_fp3_format mm_fp3_format
;
1075 struct mm_fp4_format mm_fp4_format
;
1076 struct mm_fp5_format mm_fp5_format
;
1077 struct fp6_format fp6_format
;
1078 struct mm_fp6_format mm_fp6_format
;
1079 struct mm_i_format mm_i_format
;
1080 struct mm_m_format mm_m_format
;
1081 struct mm_x_format mm_x_format
;
1082 struct mm_a_format mm_a_format
;
1083 struct mm_b0_format mm_b0_format
;
1084 struct mm_b1_format mm_b1_format
;
1085 struct mm16_m_format mm16_m_format
;
1086 struct mm16_rb_format mm16_rb_format
;
1087 struct mm16_r3_format mm16_r3_format
;
1088 struct mm16_r5_format mm16_r5_format
;
1091 union mips16e_instruction
{
1092 unsigned int full
: 16;
1094 struct m16e_jal jal
;
1095 struct m16e_i64 i64
;
1096 struct m16e_ri64 ri64
;
1098 struct m16e_rri rri
;
1102 #endif /* _UAPI_ASM_INST_H */