2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/kdebug.h>
16 #include <linux/module.h>
17 #include <linux/uaccess.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sched/signal.h>
21 #include <linux/bootmem.h>
25 #include <asm/cacheflush.h>
26 #include <asm/mmu_context.h>
27 #include <asm/pgalloc.h>
28 #include <asm/pgtable.h>
30 #include <linux/kvm_host.h>
32 #include "interrupt.h"
35 #define CREATE_TRACE_POINTS
39 #define VECTORSPACING 0x100 /* for EI/VI mode */
42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
43 struct kvm_stats_debugfs_item debugfs_entries
[] = {
44 { "wait", VCPU_STAT(wait_exits
), KVM_STAT_VCPU
},
45 { "cache", VCPU_STAT(cache_exits
), KVM_STAT_VCPU
},
46 { "signal", VCPU_STAT(signal_exits
), KVM_STAT_VCPU
},
47 { "interrupt", VCPU_STAT(int_exits
), KVM_STAT_VCPU
},
48 { "cop_unsuable", VCPU_STAT(cop_unusable_exits
), KVM_STAT_VCPU
},
49 { "tlbmod", VCPU_STAT(tlbmod_exits
), KVM_STAT_VCPU
},
50 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits
), KVM_STAT_VCPU
},
51 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits
), KVM_STAT_VCPU
},
52 { "addrerr_st", VCPU_STAT(addrerr_st_exits
), KVM_STAT_VCPU
},
53 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits
), KVM_STAT_VCPU
},
54 { "syscall", VCPU_STAT(syscall_exits
), KVM_STAT_VCPU
},
55 { "resvd_inst", VCPU_STAT(resvd_inst_exits
), KVM_STAT_VCPU
},
56 { "break_inst", VCPU_STAT(break_inst_exits
), KVM_STAT_VCPU
},
57 { "trap_inst", VCPU_STAT(trap_inst_exits
), KVM_STAT_VCPU
},
58 { "msa_fpe", VCPU_STAT(msa_fpe_exits
), KVM_STAT_VCPU
},
59 { "fpe", VCPU_STAT(fpe_exits
), KVM_STAT_VCPU
},
60 { "msa_disabled", VCPU_STAT(msa_disabled_exits
), KVM_STAT_VCPU
},
61 { "flush_dcache", VCPU_STAT(flush_dcache_exits
), KVM_STAT_VCPU
},
62 #ifdef CONFIG_KVM_MIPS_VZ
63 { "vz_gpsi", VCPU_STAT(vz_gpsi_exits
), KVM_STAT_VCPU
},
64 { "vz_gsfc", VCPU_STAT(vz_gsfc_exits
), KVM_STAT_VCPU
},
65 { "vz_hc", VCPU_STAT(vz_hc_exits
), KVM_STAT_VCPU
},
66 { "vz_grr", VCPU_STAT(vz_grr_exits
), KVM_STAT_VCPU
},
67 { "vz_gva", VCPU_STAT(vz_gva_exits
), KVM_STAT_VCPU
},
68 { "vz_ghfc", VCPU_STAT(vz_ghfc_exits
), KVM_STAT_VCPU
},
69 { "vz_gpa", VCPU_STAT(vz_gpa_exits
), KVM_STAT_VCPU
},
70 { "vz_resvd", VCPU_STAT(vz_resvd_exits
), KVM_STAT_VCPU
},
72 { "halt_successful_poll", VCPU_STAT(halt_successful_poll
), KVM_STAT_VCPU
},
73 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll
), KVM_STAT_VCPU
},
74 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid
), KVM_STAT_VCPU
},
75 { "halt_wakeup", VCPU_STAT(halt_wakeup
), KVM_STAT_VCPU
},
79 bool kvm_trace_guest_mode_change
;
81 int kvm_guest_mode_change_trace_reg(void)
83 kvm_trace_guest_mode_change
= 1;
87 void kvm_guest_mode_change_trace_unreg(void)
89 kvm_trace_guest_mode_change
= 0;
93 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
94 * Config7, so we are "runnable" if interrupts are pending
96 int kvm_arch_vcpu_runnable(struct kvm_vcpu
*vcpu
)
98 return !!(vcpu
->arch
.pending_exceptions
);
101 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu
*vcpu
)
106 int kvm_arch_vcpu_should_kick(struct kvm_vcpu
*vcpu
)
111 int kvm_arch_hardware_enable(void)
113 return kvm_mips_callbacks
->hardware_enable();
116 void kvm_arch_hardware_disable(void)
118 kvm_mips_callbacks
->hardware_disable();
121 int kvm_arch_hardware_setup(void)
126 void kvm_arch_check_processor_compat(void *rtn
)
131 int kvm_arch_init_vm(struct kvm
*kvm
, unsigned long type
)
134 #ifdef CONFIG_KVM_MIPS_VZ
141 /* Unsupported KVM type */
145 /* Allocate page table to map GPA -> RPA */
146 kvm
->arch
.gpa_mm
.pgd
= kvm_pgd_alloc();
147 if (!kvm
->arch
.gpa_mm
.pgd
)
153 bool kvm_arch_has_vcpu_debugfs(void)
158 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu
*vcpu
)
163 void kvm_mips_free_vcpus(struct kvm
*kvm
)
166 struct kvm_vcpu
*vcpu
;
168 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
169 kvm_arch_vcpu_free(vcpu
);
172 mutex_lock(&kvm
->lock
);
174 for (i
= 0; i
< atomic_read(&kvm
->online_vcpus
); i
++)
175 kvm
->vcpus
[i
] = NULL
;
177 atomic_set(&kvm
->online_vcpus
, 0);
179 mutex_unlock(&kvm
->lock
);
182 static void kvm_mips_free_gpa_pt(struct kvm
*kvm
)
184 /* It should always be safe to remove after flushing the whole range */
185 WARN_ON(!kvm_mips_flush_gpa_pt(kvm
, 0, ~0));
186 pgd_free(NULL
, kvm
->arch
.gpa_mm
.pgd
);
189 void kvm_arch_destroy_vm(struct kvm
*kvm
)
191 kvm_mips_free_vcpus(kvm
);
192 kvm_mips_free_gpa_pt(kvm
);
195 long kvm_arch_dev_ioctl(struct file
*filp
, unsigned int ioctl
,
201 int kvm_arch_create_memslot(struct kvm
*kvm
, struct kvm_memory_slot
*slot
,
202 unsigned long npages
)
207 void kvm_arch_flush_shadow_all(struct kvm
*kvm
)
209 /* Flush whole GPA */
210 kvm_mips_flush_gpa_pt(kvm
, 0, ~0);
212 /* Let implementation do the rest */
213 kvm_mips_callbacks
->flush_shadow_all(kvm
);
216 void kvm_arch_flush_shadow_memslot(struct kvm
*kvm
,
217 struct kvm_memory_slot
*slot
)
220 * The slot has been made invalid (ready for moving or deletion), so we
221 * need to ensure that it can no longer be accessed by any guest VCPUs.
224 spin_lock(&kvm
->mmu_lock
);
225 /* Flush slot from GPA */
226 kvm_mips_flush_gpa_pt(kvm
, slot
->base_gfn
,
227 slot
->base_gfn
+ slot
->npages
- 1);
228 /* Let implementation do the rest */
229 kvm_mips_callbacks
->flush_shadow_memslot(kvm
, slot
);
230 spin_unlock(&kvm
->mmu_lock
);
233 int kvm_arch_prepare_memory_region(struct kvm
*kvm
,
234 struct kvm_memory_slot
*memslot
,
235 const struct kvm_userspace_memory_region
*mem
,
236 enum kvm_mr_change change
)
241 void kvm_arch_commit_memory_region(struct kvm
*kvm
,
242 const struct kvm_userspace_memory_region
*mem
,
243 const struct kvm_memory_slot
*old
,
244 const struct kvm_memory_slot
*new,
245 enum kvm_mr_change change
)
249 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
250 __func__
, kvm
, mem
->slot
, mem
->guest_phys_addr
,
251 mem
->memory_size
, mem
->userspace_addr
);
254 * If dirty page logging is enabled, write protect all pages in the slot
255 * ready for dirty logging.
257 * There is no need to do this in any of the following cases:
258 * CREATE: No dirty mappings will already exist.
259 * MOVE/DELETE: The old mappings will already have been cleaned up by
260 * kvm_arch_flush_shadow_memslot()
262 if (change
== KVM_MR_FLAGS_ONLY
&&
263 (!(old
->flags
& KVM_MEM_LOG_DIRTY_PAGES
) &&
264 new->flags
& KVM_MEM_LOG_DIRTY_PAGES
)) {
265 spin_lock(&kvm
->mmu_lock
);
266 /* Write protect GPA page table entries */
267 needs_flush
= kvm_mips_mkclean_gpa_pt(kvm
, new->base_gfn
,
268 new->base_gfn
+ new->npages
- 1);
269 /* Let implementation do the rest */
271 kvm_mips_callbacks
->flush_shadow_memslot(kvm
, new);
272 spin_unlock(&kvm
->mmu_lock
);
276 static inline void dump_handler(const char *symbol
, void *start
, void *end
)
280 pr_debug("LEAF(%s)\n", symbol
);
282 pr_debug("\t.set push\n");
283 pr_debug("\t.set noreorder\n");
285 for (p
= start
; p
< (u32
*)end
; ++p
)
286 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p
, p
);
288 pr_debug("\t.set\tpop\n");
290 pr_debug("\tEND(%s)\n", symbol
);
293 struct kvm_vcpu
*kvm_arch_vcpu_create(struct kvm
*kvm
, unsigned int id
)
296 void *gebase
, *p
, *handler
, *refill_start
, *refill_end
;
299 struct kvm_vcpu
*vcpu
= kzalloc(sizeof(struct kvm_vcpu
), GFP_KERNEL
);
306 err
= kvm_vcpu_init(vcpu
, kvm
, id
);
311 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm
, id
, vcpu
);
314 * Allocate space for host mode exception handlers that handle
317 if (cpu_has_veic
|| cpu_has_vint
)
318 size
= 0x200 + VECTORSPACING
* 64;
322 gebase
= kzalloc(ALIGN(size
, PAGE_SIZE
), GFP_KERNEL
);
328 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
329 ALIGN(size
, PAGE_SIZE
), gebase
);
332 * Check new ebase actually fits in CP0_EBase. The lack of a write gate
333 * limits us to the low 512MB of physical address space. If the memory
334 * we allocate is out of range, just give up now.
336 if (!cpu_has_ebase_wg
&& virt_to_phys(gebase
) >= 0x20000000) {
337 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
340 goto out_free_gebase
;
344 vcpu
->arch
.guest_ebase
= gebase
;
346 /* Build guest exception vectors dynamically in unmapped memory */
347 handler
= gebase
+ 0x2000;
349 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
350 refill_start
= gebase
;
351 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ
) && IS_ENABLED(CONFIG_64BIT
))
352 refill_start
+= 0x080;
353 refill_end
= kvm_mips_build_tlb_refill_exception(refill_start
, handler
);
355 /* General Exception Entry point */
356 kvm_mips_build_exception(gebase
+ 0x180, handler
);
358 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
359 for (i
= 0; i
< 8; i
++) {
360 kvm_debug("L1 Vectored handler @ %p\n",
361 gebase
+ 0x200 + (i
* VECTORSPACING
));
362 kvm_mips_build_exception(gebase
+ 0x200 + i
* VECTORSPACING
,
366 /* General exit handler */
368 p
= kvm_mips_build_exit(p
);
370 /* Guest entry routine */
371 vcpu
->arch
.vcpu_run
= p
;
372 p
= kvm_mips_build_vcpu_run(p
);
374 /* Dump the generated code */
375 pr_debug("#include <asm/asm.h>\n");
376 pr_debug("#include <asm/regdef.h>\n");
378 dump_handler("kvm_vcpu_run", vcpu
->arch
.vcpu_run
, p
);
379 dump_handler("kvm_tlb_refill", refill_start
, refill_end
);
380 dump_handler("kvm_gen_exc", gebase
+ 0x180, gebase
+ 0x200);
381 dump_handler("kvm_exit", gebase
+ 0x2000, vcpu
->arch
.vcpu_run
);
383 /* Invalidate the icache for these ranges */
384 flush_icache_range((unsigned long)gebase
,
385 (unsigned long)gebase
+ ALIGN(size
, PAGE_SIZE
));
388 * Allocate comm page for guest kernel, a TLB will be reserved for
389 * mapping GVA @ 0xFFFF8000 to this page
391 vcpu
->arch
.kseg0_commpage
= kzalloc(PAGE_SIZE
<< 1, GFP_KERNEL
);
393 if (!vcpu
->arch
.kseg0_commpage
) {
395 goto out_free_gebase
;
398 kvm_debug("Allocated COMM page @ %p\n", vcpu
->arch
.kseg0_commpage
);
399 kvm_mips_commpage_init(vcpu
);
402 vcpu
->arch
.last_sched_cpu
= -1;
403 vcpu
->arch
.last_exec_cpu
= -1;
411 kvm_vcpu_uninit(vcpu
);
420 void kvm_arch_vcpu_free(struct kvm_vcpu
*vcpu
)
422 hrtimer_cancel(&vcpu
->arch
.comparecount_timer
);
424 kvm_vcpu_uninit(vcpu
);
426 kvm_mips_dump_stats(vcpu
);
428 kvm_mmu_free_memory_caches(vcpu
);
429 kfree(vcpu
->arch
.guest_ebase
);
430 kfree(vcpu
->arch
.kseg0_commpage
);
434 void kvm_arch_vcpu_destroy(struct kvm_vcpu
*vcpu
)
436 kvm_arch_vcpu_free(vcpu
);
439 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu
*vcpu
,
440 struct kvm_guest_debug
*dbg
)
445 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
)
450 if (vcpu
->sigset_active
)
451 sigprocmask(SIG_SETMASK
, &vcpu
->sigset
, &sigsaved
);
453 if (vcpu
->mmio_needed
) {
454 if (!vcpu
->mmio_is_write
)
455 kvm_mips_complete_mmio_load(vcpu
, run
);
456 vcpu
->mmio_needed
= 0;
459 if (run
->immediate_exit
)
465 guest_enter_irqoff();
466 trace_kvm_enter(vcpu
);
469 * Make sure the read of VCPU requests in vcpu_run() callback is not
470 * reordered ahead of the write to vcpu->mode, or we could miss a TLB
471 * flush request while the requester sees the VCPU as outside of guest
472 * mode and not needing an IPI.
474 smp_store_mb(vcpu
->mode
, IN_GUEST_MODE
);
476 r
= kvm_mips_callbacks
->vcpu_run(run
, vcpu
);
483 if (vcpu
->sigset_active
)
484 sigprocmask(SIG_SETMASK
, &sigsaved
, NULL
);
489 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu
*vcpu
,
490 struct kvm_mips_interrupt
*irq
)
492 int intr
= (int)irq
->irq
;
493 struct kvm_vcpu
*dvcpu
= NULL
;
495 if (intr
== 3 || intr
== -3 || intr
== 4 || intr
== -4)
496 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__
, irq
->cpu
,
502 dvcpu
= vcpu
->kvm
->vcpus
[irq
->cpu
];
504 if (intr
== 2 || intr
== 3 || intr
== 4) {
505 kvm_mips_callbacks
->queue_io_int(dvcpu
, irq
);
507 } else if (intr
== -2 || intr
== -3 || intr
== -4) {
508 kvm_mips_callbacks
->dequeue_io_int(dvcpu
, irq
);
510 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__
,
515 dvcpu
->arch
.wait
= 0;
517 if (swq_has_sleeper(&dvcpu
->wq
))
518 swake_up(&dvcpu
->wq
);
523 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu
*vcpu
,
524 struct kvm_mp_state
*mp_state
)
529 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu
*vcpu
,
530 struct kvm_mp_state
*mp_state
)
535 static u64 kvm_mips_get_one_regs
[] = {
569 #ifndef CONFIG_CPU_MIPSR6
576 static u64 kvm_mips_get_one_regs_fpu
[] = {
578 KVM_REG_MIPS_FCR_CSR
,
581 static u64 kvm_mips_get_one_regs_msa
[] = {
583 KVM_REG_MIPS_MSA_CSR
,
586 static unsigned long kvm_mips_num_regs(struct kvm_vcpu
*vcpu
)
590 ret
= ARRAY_SIZE(kvm_mips_get_one_regs
);
591 if (kvm_mips_guest_can_have_fpu(&vcpu
->arch
)) {
592 ret
+= ARRAY_SIZE(kvm_mips_get_one_regs_fpu
) + 48;
594 if (boot_cpu_data
.fpu_id
& MIPS_FPIR_F64
)
597 if (kvm_mips_guest_can_have_msa(&vcpu
->arch
))
598 ret
+= ARRAY_SIZE(kvm_mips_get_one_regs_msa
) + 32;
599 ret
+= kvm_mips_callbacks
->num_regs(vcpu
);
604 static int kvm_mips_copy_reg_indices(struct kvm_vcpu
*vcpu
, u64 __user
*indices
)
609 if (copy_to_user(indices
, kvm_mips_get_one_regs
,
610 sizeof(kvm_mips_get_one_regs
)))
612 indices
+= ARRAY_SIZE(kvm_mips_get_one_regs
);
614 if (kvm_mips_guest_can_have_fpu(&vcpu
->arch
)) {
615 if (copy_to_user(indices
, kvm_mips_get_one_regs_fpu
,
616 sizeof(kvm_mips_get_one_regs_fpu
)))
618 indices
+= ARRAY_SIZE(kvm_mips_get_one_regs_fpu
);
620 for (i
= 0; i
< 32; ++i
) {
621 index
= KVM_REG_MIPS_FPR_32(i
);
622 if (copy_to_user(indices
, &index
, sizeof(index
)))
626 /* skip odd doubles if no F64 */
627 if (i
& 1 && !(boot_cpu_data
.fpu_id
& MIPS_FPIR_F64
))
630 index
= KVM_REG_MIPS_FPR_64(i
);
631 if (copy_to_user(indices
, &index
, sizeof(index
)))
637 if (kvm_mips_guest_can_have_msa(&vcpu
->arch
)) {
638 if (copy_to_user(indices
, kvm_mips_get_one_regs_msa
,
639 sizeof(kvm_mips_get_one_regs_msa
)))
641 indices
+= ARRAY_SIZE(kvm_mips_get_one_regs_msa
);
643 for (i
= 0; i
< 32; ++i
) {
644 index
= KVM_REG_MIPS_VEC_128(i
);
645 if (copy_to_user(indices
, &index
, sizeof(index
)))
651 return kvm_mips_callbacks
->copy_reg_indices(vcpu
, indices
);
654 static int kvm_mips_get_reg(struct kvm_vcpu
*vcpu
,
655 const struct kvm_one_reg
*reg
)
657 struct mips_coproc
*cop0
= vcpu
->arch
.cop0
;
658 struct mips_fpu_struct
*fpu
= &vcpu
->arch
.fpu
;
665 /* General purpose registers */
666 case KVM_REG_MIPS_R0
... KVM_REG_MIPS_R31
:
667 v
= (long)vcpu
->arch
.gprs
[reg
->id
- KVM_REG_MIPS_R0
];
669 #ifndef CONFIG_CPU_MIPSR6
670 case KVM_REG_MIPS_HI
:
671 v
= (long)vcpu
->arch
.hi
;
673 case KVM_REG_MIPS_LO
:
674 v
= (long)vcpu
->arch
.lo
;
677 case KVM_REG_MIPS_PC
:
678 v
= (long)vcpu
->arch
.pc
;
681 /* Floating point registers */
682 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
683 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
685 idx
= reg
->id
- KVM_REG_MIPS_FPR_32(0);
686 /* Odd singles in top of even double when FR=0 */
687 if (kvm_read_c0_guest_status(cop0
) & ST0_FR
)
688 v
= get_fpr32(&fpu
->fpr
[idx
], 0);
690 v
= get_fpr32(&fpu
->fpr
[idx
& ~1], idx
& 1);
692 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
693 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
695 idx
= reg
->id
- KVM_REG_MIPS_FPR_64(0);
696 /* Can't access odd doubles in FR=0 mode */
697 if (idx
& 1 && !(kvm_read_c0_guest_status(cop0
) & ST0_FR
))
699 v
= get_fpr64(&fpu
->fpr
[idx
], 0);
701 case KVM_REG_MIPS_FCR_IR
:
702 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
704 v
= boot_cpu_data
.fpu_id
;
706 case KVM_REG_MIPS_FCR_CSR
:
707 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
712 /* MIPS SIMD Architecture (MSA) registers */
713 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
714 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
716 /* Can't access MSA registers in FR=0 mode */
717 if (!(kvm_read_c0_guest_status(cop0
) & ST0_FR
))
719 idx
= reg
->id
- KVM_REG_MIPS_VEC_128(0);
720 #ifdef CONFIG_CPU_LITTLE_ENDIAN
721 /* least significant byte first */
722 vs
[0] = get_fpr64(&fpu
->fpr
[idx
], 0);
723 vs
[1] = get_fpr64(&fpu
->fpr
[idx
], 1);
725 /* most significant byte first */
726 vs
[0] = get_fpr64(&fpu
->fpr
[idx
], 1);
727 vs
[1] = get_fpr64(&fpu
->fpr
[idx
], 0);
730 case KVM_REG_MIPS_MSA_IR
:
731 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
733 v
= boot_cpu_data
.msa_id
;
735 case KVM_REG_MIPS_MSA_CSR
:
736 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
741 /* registers to be handled specially */
743 ret
= kvm_mips_callbacks
->get_one_reg(vcpu
, reg
, &v
);
748 if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U64
) {
749 u64 __user
*uaddr64
= (u64 __user
*)(long)reg
->addr
;
751 return put_user(v
, uaddr64
);
752 } else if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U32
) {
753 u32 __user
*uaddr32
= (u32 __user
*)(long)reg
->addr
;
756 return put_user(v32
, uaddr32
);
757 } else if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U128
) {
758 void __user
*uaddr
= (void __user
*)(long)reg
->addr
;
760 return copy_to_user(uaddr
, vs
, 16) ? -EFAULT
: 0;
766 static int kvm_mips_set_reg(struct kvm_vcpu
*vcpu
,
767 const struct kvm_one_reg
*reg
)
769 struct mips_coproc
*cop0
= vcpu
->arch
.cop0
;
770 struct mips_fpu_struct
*fpu
= &vcpu
->arch
.fpu
;
775 if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U64
) {
776 u64 __user
*uaddr64
= (u64 __user
*)(long)reg
->addr
;
778 if (get_user(v
, uaddr64
) != 0)
780 } else if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U32
) {
781 u32 __user
*uaddr32
= (u32 __user
*)(long)reg
->addr
;
784 if (get_user(v32
, uaddr32
) != 0)
787 } else if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U128
) {
788 void __user
*uaddr
= (void __user
*)(long)reg
->addr
;
790 return copy_from_user(vs
, uaddr
, 16) ? -EFAULT
: 0;
796 /* General purpose registers */
797 case KVM_REG_MIPS_R0
:
798 /* Silently ignore requests to set $0 */
800 case KVM_REG_MIPS_R1
... KVM_REG_MIPS_R31
:
801 vcpu
->arch
.gprs
[reg
->id
- KVM_REG_MIPS_R0
] = v
;
803 #ifndef CONFIG_CPU_MIPSR6
804 case KVM_REG_MIPS_HI
:
807 case KVM_REG_MIPS_LO
:
811 case KVM_REG_MIPS_PC
:
815 /* Floating point registers */
816 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
817 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
819 idx
= reg
->id
- KVM_REG_MIPS_FPR_32(0);
820 /* Odd singles in top of even double when FR=0 */
821 if (kvm_read_c0_guest_status(cop0
) & ST0_FR
)
822 set_fpr32(&fpu
->fpr
[idx
], 0, v
);
824 set_fpr32(&fpu
->fpr
[idx
& ~1], idx
& 1, v
);
826 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
827 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
829 idx
= reg
->id
- KVM_REG_MIPS_FPR_64(0);
830 /* Can't access odd doubles in FR=0 mode */
831 if (idx
& 1 && !(kvm_read_c0_guest_status(cop0
) & ST0_FR
))
833 set_fpr64(&fpu
->fpr
[idx
], 0, v
);
835 case KVM_REG_MIPS_FCR_IR
:
836 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
840 case KVM_REG_MIPS_FCR_CSR
:
841 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
846 /* MIPS SIMD Architecture (MSA) registers */
847 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
848 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
850 idx
= reg
->id
- KVM_REG_MIPS_VEC_128(0);
851 #ifdef CONFIG_CPU_LITTLE_ENDIAN
852 /* least significant byte first */
853 set_fpr64(&fpu
->fpr
[idx
], 0, vs
[0]);
854 set_fpr64(&fpu
->fpr
[idx
], 1, vs
[1]);
856 /* most significant byte first */
857 set_fpr64(&fpu
->fpr
[idx
], 1, vs
[0]);
858 set_fpr64(&fpu
->fpr
[idx
], 0, vs
[1]);
861 case KVM_REG_MIPS_MSA_IR
:
862 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
866 case KVM_REG_MIPS_MSA_CSR
:
867 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
872 /* registers to be handled specially */
874 return kvm_mips_callbacks
->set_one_reg(vcpu
, reg
, v
);
879 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu
*vcpu
,
880 struct kvm_enable_cap
*cap
)
884 if (!kvm_vm_ioctl_check_extension(vcpu
->kvm
, cap
->cap
))
892 case KVM_CAP_MIPS_FPU
:
893 vcpu
->arch
.fpu_enabled
= true;
895 case KVM_CAP_MIPS_MSA
:
896 vcpu
->arch
.msa_enabled
= true;
906 long kvm_arch_vcpu_ioctl(struct file
*filp
, unsigned int ioctl
,
909 struct kvm_vcpu
*vcpu
= filp
->private_data
;
910 void __user
*argp
= (void __user
*)arg
;
914 case KVM_SET_ONE_REG
:
915 case KVM_GET_ONE_REG
: {
916 struct kvm_one_reg reg
;
918 if (copy_from_user(®
, argp
, sizeof(reg
)))
920 if (ioctl
== KVM_SET_ONE_REG
)
921 return kvm_mips_set_reg(vcpu
, ®
);
923 return kvm_mips_get_reg(vcpu
, ®
);
925 case KVM_GET_REG_LIST
: {
926 struct kvm_reg_list __user
*user_list
= argp
;
927 struct kvm_reg_list reg_list
;
930 if (copy_from_user(®_list
, user_list
, sizeof(reg_list
)))
933 reg_list
.n
= kvm_mips_num_regs(vcpu
);
934 if (copy_to_user(user_list
, ®_list
, sizeof(reg_list
)))
938 return kvm_mips_copy_reg_indices(vcpu
, user_list
->reg
);
942 struct kvm_mips_interrupt irq
;
944 if (copy_from_user(&irq
, argp
, sizeof(irq
)))
946 kvm_debug("[%d] %s: irq: %d\n", vcpu
->vcpu_id
, __func__
,
949 r
= kvm_vcpu_ioctl_interrupt(vcpu
, &irq
);
952 case KVM_ENABLE_CAP
: {
953 struct kvm_enable_cap cap
;
955 if (copy_from_user(&cap
, argp
, sizeof(cap
)))
957 r
= kvm_vcpu_ioctl_enable_cap(vcpu
, &cap
);
967 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
969 * @log: slot id and address to which we copy the log
971 * Steps 1-4 below provide general overview of dirty page logging. See
972 * kvm_get_dirty_log_protect() function description for additional details.
974 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
975 * always flush the TLB (step 4) even if previous step failed and the dirty
976 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
977 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
978 * writes will be marked dirty for next log read.
980 * 1. Take a snapshot of the bit and clear it if needed.
981 * 2. Write protect the corresponding page.
982 * 3. Copy the snapshot to the userspace.
983 * 4. Flush TLB's if needed.
985 int kvm_vm_ioctl_get_dirty_log(struct kvm
*kvm
, struct kvm_dirty_log
*log
)
987 struct kvm_memslots
*slots
;
988 struct kvm_memory_slot
*memslot
;
989 bool is_dirty
= false;
992 mutex_lock(&kvm
->slots_lock
);
994 r
= kvm_get_dirty_log_protect(kvm
, log
, &is_dirty
);
997 slots
= kvm_memslots(kvm
);
998 memslot
= id_to_memslot(slots
, log
->slot
);
1000 /* Let implementation handle TLB/GVA invalidation */
1001 kvm_mips_callbacks
->flush_shadow_memslot(kvm
, memslot
);
1004 mutex_unlock(&kvm
->slots_lock
);
1008 long kvm_arch_vm_ioctl(struct file
*filp
, unsigned int ioctl
, unsigned long arg
)
1020 int kvm_arch_init(void *opaque
)
1022 if (kvm_mips_callbacks
) {
1023 kvm_err("kvm: module already exists\n");
1027 return kvm_mips_emulation_init(&kvm_mips_callbacks
);
1030 void kvm_arch_exit(void)
1032 kvm_mips_callbacks
= NULL
;
1035 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu
*vcpu
,
1036 struct kvm_sregs
*sregs
)
1038 return -ENOIOCTLCMD
;
1041 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu
*vcpu
,
1042 struct kvm_sregs
*sregs
)
1044 return -ENOIOCTLCMD
;
1047 void kvm_arch_vcpu_postcreate(struct kvm_vcpu
*vcpu
)
1051 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu
*vcpu
, struct kvm_fpu
*fpu
)
1053 return -ENOIOCTLCMD
;
1056 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu
*vcpu
, struct kvm_fpu
*fpu
)
1058 return -ENOIOCTLCMD
;
1061 int kvm_arch_vcpu_fault(struct kvm_vcpu
*vcpu
, struct vm_fault
*vmf
)
1063 return VM_FAULT_SIGBUS
;
1066 int kvm_vm_ioctl_check_extension(struct kvm
*kvm
, long ext
)
1071 case KVM_CAP_ONE_REG
:
1072 case KVM_CAP_ENABLE_CAP
:
1073 case KVM_CAP_READONLY_MEM
:
1074 case KVM_CAP_SYNC_MMU
:
1075 case KVM_CAP_IMMEDIATE_EXIT
:
1078 case KVM_CAP_NR_VCPUS
:
1079 r
= num_online_cpus();
1081 case KVM_CAP_MAX_VCPUS
:
1084 case KVM_CAP_MIPS_FPU
:
1085 /* We don't handle systems with inconsistent cpu_has_fpu */
1086 r
= !!raw_cpu_has_fpu
;
1088 case KVM_CAP_MIPS_MSA
:
1090 * We don't support MSA vector partitioning yet:
1091 * 1) It would require explicit support which can't be tested
1092 * yet due to lack of support in current hardware.
1093 * 2) It extends the state that would need to be saved/restored
1094 * by e.g. QEMU for migration.
1096 * When vector partitioning hardware becomes available, support
1097 * could be added by requiring a flag when enabling
1098 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1099 * to save/restore the appropriate extra state.
1101 r
= cpu_has_msa
&& !(boot_cpu_data
.msa_id
& MSA_IR_WRPF
);
1104 r
= kvm_mips_callbacks
->check_extension(kvm
, ext
);
1110 int kvm_cpu_has_pending_timer(struct kvm_vcpu
*vcpu
)
1112 return kvm_mips_pending_timer(vcpu
) ||
1113 kvm_read_c0_guest_cause(vcpu
->arch
.cop0
) & C_TI
;
1116 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu
*vcpu
)
1119 struct mips_coproc
*cop0
;
1124 kvm_debug("VCPU Register Dump:\n");
1125 kvm_debug("\tpc = 0x%08lx\n", vcpu
->arch
.pc
);
1126 kvm_debug("\texceptions: %08lx\n", vcpu
->arch
.pending_exceptions
);
1128 for (i
= 0; i
< 32; i
+= 4) {
1129 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i
,
1131 vcpu
->arch
.gprs
[i
+ 1],
1132 vcpu
->arch
.gprs
[i
+ 2], vcpu
->arch
.gprs
[i
+ 3]);
1134 kvm_debug("\thi: 0x%08lx\n", vcpu
->arch
.hi
);
1135 kvm_debug("\tlo: 0x%08lx\n", vcpu
->arch
.lo
);
1137 cop0
= vcpu
->arch
.cop0
;
1138 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1139 kvm_read_c0_guest_status(cop0
),
1140 kvm_read_c0_guest_cause(cop0
));
1142 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0
));
1147 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu
*vcpu
, struct kvm_regs
*regs
)
1151 for (i
= 1; i
< ARRAY_SIZE(vcpu
->arch
.gprs
); i
++)
1152 vcpu
->arch
.gprs
[i
] = regs
->gpr
[i
];
1153 vcpu
->arch
.gprs
[0] = 0; /* zero is special, and cannot be set. */
1154 vcpu
->arch
.hi
= regs
->hi
;
1155 vcpu
->arch
.lo
= regs
->lo
;
1156 vcpu
->arch
.pc
= regs
->pc
;
1161 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu
*vcpu
, struct kvm_regs
*regs
)
1165 for (i
= 0; i
< ARRAY_SIZE(vcpu
->arch
.gprs
); i
++)
1166 regs
->gpr
[i
] = vcpu
->arch
.gprs
[i
];
1168 regs
->hi
= vcpu
->arch
.hi
;
1169 regs
->lo
= vcpu
->arch
.lo
;
1170 regs
->pc
= vcpu
->arch
.pc
;
1175 static void kvm_mips_comparecount_func(unsigned long data
)
1177 struct kvm_vcpu
*vcpu
= (struct kvm_vcpu
*)data
;
1179 kvm_mips_callbacks
->queue_timer_int(vcpu
);
1181 vcpu
->arch
.wait
= 0;
1182 if (swq_has_sleeper(&vcpu
->wq
))
1183 swake_up(&vcpu
->wq
);
1186 /* low level hrtimer wake routine */
1187 static enum hrtimer_restart
kvm_mips_comparecount_wakeup(struct hrtimer
*timer
)
1189 struct kvm_vcpu
*vcpu
;
1191 vcpu
= container_of(timer
, struct kvm_vcpu
, arch
.comparecount_timer
);
1192 kvm_mips_comparecount_func((unsigned long) vcpu
);
1193 return kvm_mips_count_timeout(vcpu
);
1196 int kvm_arch_vcpu_init(struct kvm_vcpu
*vcpu
)
1200 err
= kvm_mips_callbacks
->vcpu_init(vcpu
);
1204 hrtimer_init(&vcpu
->arch
.comparecount_timer
, CLOCK_MONOTONIC
,
1206 vcpu
->arch
.comparecount_timer
.function
= kvm_mips_comparecount_wakeup
;
1210 void kvm_arch_vcpu_uninit(struct kvm_vcpu
*vcpu
)
1212 kvm_mips_callbacks
->vcpu_uninit(vcpu
);
1215 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu
*vcpu
,
1216 struct kvm_translation
*tr
)
1221 /* Initial guest state */
1222 int kvm_arch_vcpu_setup(struct kvm_vcpu
*vcpu
)
1224 return kvm_mips_callbacks
->vcpu_setup(vcpu
);
1227 static void kvm_mips_set_c0_status(void)
1229 u32 status
= read_c0_status();
1234 write_c0_status(status
);
1239 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1241 int kvm_mips_handle_exit(struct kvm_run
*run
, struct kvm_vcpu
*vcpu
)
1243 u32 cause
= vcpu
->arch
.host_cp0_cause
;
1244 u32 exccode
= (cause
>> CAUSEB_EXCCODE
) & 0x1f;
1245 u32 __user
*opc
= (u32 __user
*) vcpu
->arch
.pc
;
1246 unsigned long badvaddr
= vcpu
->arch
.host_cp0_badvaddr
;
1247 enum emulation_result er
= EMULATE_DONE
;
1249 int ret
= RESUME_GUEST
;
1251 vcpu
->mode
= OUTSIDE_GUEST_MODE
;
1253 /* re-enable HTW before enabling interrupts */
1254 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ
))
1257 /* Set a default exit reason */
1258 run
->exit_reason
= KVM_EXIT_UNKNOWN
;
1259 run
->ready_for_interrupt_injection
= 1;
1262 * Set the appropriate status bits based on host CPU features,
1263 * before we hit the scheduler
1265 kvm_mips_set_c0_status();
1269 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1270 cause
, opc
, run
, vcpu
);
1271 trace_kvm_exit(vcpu
, exccode
);
1273 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ
)) {
1275 * Do a privilege check, if in UM most of these exit conditions
1276 * end up causing an exception to be delivered to the Guest
1279 er
= kvm_mips_check_privilege(cause
, opc
, run
, vcpu
);
1280 if (er
== EMULATE_PRIV_FAIL
) {
1282 } else if (er
== EMULATE_FAIL
) {
1283 run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
1291 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu
->vcpu_id
, opc
);
1293 ++vcpu
->stat
.int_exits
;
1302 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc
);
1304 ++vcpu
->stat
.cop_unusable_exits
;
1305 ret
= kvm_mips_callbacks
->handle_cop_unusable(vcpu
);
1306 /* XXXKYMA: Might need to return to user space */
1307 if (run
->exit_reason
== KVM_EXIT_IRQ_WINDOW_OPEN
)
1312 ++vcpu
->stat
.tlbmod_exits
;
1313 ret
= kvm_mips_callbacks
->handle_tlb_mod(vcpu
);
1317 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1318 cause
, kvm_read_c0_guest_status(vcpu
->arch
.cop0
), opc
,
1321 ++vcpu
->stat
.tlbmiss_st_exits
;
1322 ret
= kvm_mips_callbacks
->handle_tlb_st_miss(vcpu
);
1326 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1327 cause
, opc
, badvaddr
);
1329 ++vcpu
->stat
.tlbmiss_ld_exits
;
1330 ret
= kvm_mips_callbacks
->handle_tlb_ld_miss(vcpu
);
1334 ++vcpu
->stat
.addrerr_st_exits
;
1335 ret
= kvm_mips_callbacks
->handle_addr_err_st(vcpu
);
1339 ++vcpu
->stat
.addrerr_ld_exits
;
1340 ret
= kvm_mips_callbacks
->handle_addr_err_ld(vcpu
);
1344 ++vcpu
->stat
.syscall_exits
;
1345 ret
= kvm_mips_callbacks
->handle_syscall(vcpu
);
1349 ++vcpu
->stat
.resvd_inst_exits
;
1350 ret
= kvm_mips_callbacks
->handle_res_inst(vcpu
);
1354 ++vcpu
->stat
.break_inst_exits
;
1355 ret
= kvm_mips_callbacks
->handle_break(vcpu
);
1359 ++vcpu
->stat
.trap_inst_exits
;
1360 ret
= kvm_mips_callbacks
->handle_trap(vcpu
);
1363 case EXCCODE_MSAFPE
:
1364 ++vcpu
->stat
.msa_fpe_exits
;
1365 ret
= kvm_mips_callbacks
->handle_msa_fpe(vcpu
);
1369 ++vcpu
->stat
.fpe_exits
;
1370 ret
= kvm_mips_callbacks
->handle_fpe(vcpu
);
1373 case EXCCODE_MSADIS
:
1374 ++vcpu
->stat
.msa_disabled_exits
;
1375 ret
= kvm_mips_callbacks
->handle_msa_disabled(vcpu
);
1379 /* defer exit accounting to handler */
1380 ret
= kvm_mips_callbacks
->handle_guest_exit(vcpu
);
1384 if (cause
& CAUSEF_BD
)
1387 kvm_get_badinstr(opc
, vcpu
, &inst
);
1388 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
1389 exccode
, opc
, inst
, badvaddr
,
1390 kvm_read_c0_guest_status(vcpu
->arch
.cop0
));
1391 kvm_arch_vcpu_dump_regs(vcpu
);
1392 run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
1399 local_irq_disable();
1401 if (ret
== RESUME_GUEST
)
1402 kvm_vz_acquire_htimer(vcpu
);
1404 if (er
== EMULATE_DONE
&& !(ret
& RESUME_HOST
))
1405 kvm_mips_deliver_interrupts(vcpu
, cause
);
1407 if (!(ret
& RESUME_HOST
)) {
1408 /* Only check for signals if not already exiting to userspace */
1409 if (signal_pending(current
)) {
1410 run
->exit_reason
= KVM_EXIT_INTR
;
1411 ret
= (-EINTR
<< 2) | RESUME_HOST
;
1412 ++vcpu
->stat
.signal_exits
;
1413 trace_kvm_exit(vcpu
, KVM_TRACE_EXIT_SIGNAL
);
1417 if (ret
== RESUME_GUEST
) {
1418 trace_kvm_reenter(vcpu
);
1421 * Make sure the read of VCPU requests in vcpu_reenter()
1422 * callback is not reordered ahead of the write to vcpu->mode,
1423 * or we could miss a TLB flush request while the requester sees
1424 * the VCPU as outside of guest mode and not needing an IPI.
1426 smp_store_mb(vcpu
->mode
, IN_GUEST_MODE
);
1428 kvm_mips_callbacks
->vcpu_reenter(run
, vcpu
);
1431 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1432 * is live), restore FCR31 / MSACSR.
1434 * This should be before returning to the guest exception
1435 * vector, as it may well cause an [MSA] FP exception if there
1436 * are pending exception bits unmasked. (see
1437 * kvm_mips_csr_die_notifier() for how that is handled).
1439 if (kvm_mips_guest_has_fpu(&vcpu
->arch
) &&
1440 read_c0_status() & ST0_CU1
)
1441 __kvm_restore_fcsr(&vcpu
->arch
);
1443 if (kvm_mips_guest_has_msa(&vcpu
->arch
) &&
1444 read_c0_config5() & MIPS_CONF5_MSAEN
)
1445 __kvm_restore_msacsr(&vcpu
->arch
);
1448 /* Disable HTW before returning to guest or host */
1449 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ
))
1455 /* Enable FPU for guest and restore context */
1456 void kvm_own_fpu(struct kvm_vcpu
*vcpu
)
1458 struct mips_coproc
*cop0
= vcpu
->arch
.cop0
;
1459 unsigned int sr
, cfg5
;
1463 sr
= kvm_read_c0_guest_status(cop0
);
1466 * If MSA state is already live, it is undefined how it interacts with
1467 * FR=0 FPU state, and we don't want to hit reserved instruction
1468 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1469 * play it safe and save it first.
1471 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1472 * get called when guest CU1 is set, however we can't trust the guest
1473 * not to clobber the status register directly via the commpage.
1475 if (cpu_has_msa
&& sr
& ST0_CU1
&& !(sr
& ST0_FR
) &&
1476 vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_MSA
)
1480 * Enable FPU for guest
1481 * We set FR and FRE according to guest context
1483 change_c0_status(ST0_CU1
| ST0_FR
, sr
);
1485 cfg5
= kvm_read_c0_guest_config5(cop0
);
1486 change_c0_config5(MIPS_CONF5_FRE
, cfg5
);
1488 enable_fpu_hazard();
1490 /* If guest FPU state not active, restore it now */
1491 if (!(vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_FPU
)) {
1492 __kvm_restore_fpu(&vcpu
->arch
);
1493 vcpu
->arch
.aux_inuse
|= KVM_MIPS_AUX_FPU
;
1494 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_RESTORE
, KVM_TRACE_AUX_FPU
);
1496 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_ENABLE
, KVM_TRACE_AUX_FPU
);
1502 #ifdef CONFIG_CPU_HAS_MSA
1503 /* Enable MSA for guest and restore context */
1504 void kvm_own_msa(struct kvm_vcpu
*vcpu
)
1506 struct mips_coproc
*cop0
= vcpu
->arch
.cop0
;
1507 unsigned int sr
, cfg5
;
1512 * Enable FPU if enabled in guest, since we're restoring FPU context
1513 * anyway. We set FR and FRE according to guest context.
1515 if (kvm_mips_guest_has_fpu(&vcpu
->arch
)) {
1516 sr
= kvm_read_c0_guest_status(cop0
);
1519 * If FR=0 FPU state is already live, it is undefined how it
1520 * interacts with MSA state, so play it safe and save it first.
1522 if (!(sr
& ST0_FR
) &&
1523 (vcpu
->arch
.aux_inuse
& (KVM_MIPS_AUX_FPU
|
1524 KVM_MIPS_AUX_MSA
)) == KVM_MIPS_AUX_FPU
)
1527 change_c0_status(ST0_CU1
| ST0_FR
, sr
);
1528 if (sr
& ST0_CU1
&& cpu_has_fre
) {
1529 cfg5
= kvm_read_c0_guest_config5(cop0
);
1530 change_c0_config5(MIPS_CONF5_FRE
, cfg5
);
1534 /* Enable MSA for guest */
1535 set_c0_config5(MIPS_CONF5_MSAEN
);
1536 enable_fpu_hazard();
1538 switch (vcpu
->arch
.aux_inuse
& (KVM_MIPS_AUX_FPU
| KVM_MIPS_AUX_MSA
)) {
1539 case KVM_MIPS_AUX_FPU
:
1541 * Guest FPU state already loaded, only restore upper MSA state
1543 __kvm_restore_msa_upper(&vcpu
->arch
);
1544 vcpu
->arch
.aux_inuse
|= KVM_MIPS_AUX_MSA
;
1545 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_RESTORE
, KVM_TRACE_AUX_MSA
);
1548 /* Neither FPU or MSA already active, restore full MSA state */
1549 __kvm_restore_msa(&vcpu
->arch
);
1550 vcpu
->arch
.aux_inuse
|= KVM_MIPS_AUX_MSA
;
1551 if (kvm_mips_guest_has_fpu(&vcpu
->arch
))
1552 vcpu
->arch
.aux_inuse
|= KVM_MIPS_AUX_FPU
;
1553 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_RESTORE
,
1554 KVM_TRACE_AUX_FPU_MSA
);
1557 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_ENABLE
, KVM_TRACE_AUX_MSA
);
1565 /* Drop FPU & MSA without saving it */
1566 void kvm_drop_fpu(struct kvm_vcpu
*vcpu
)
1569 if (cpu_has_msa
&& vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_MSA
) {
1571 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_DISCARD
, KVM_TRACE_AUX_MSA
);
1572 vcpu
->arch
.aux_inuse
&= ~KVM_MIPS_AUX_MSA
;
1574 if (vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_FPU
) {
1575 clear_c0_status(ST0_CU1
| ST0_FR
);
1576 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_DISCARD
, KVM_TRACE_AUX_FPU
);
1577 vcpu
->arch
.aux_inuse
&= ~KVM_MIPS_AUX_FPU
;
1582 /* Save and disable FPU & MSA */
1583 void kvm_lose_fpu(struct kvm_vcpu
*vcpu
)
1586 * With T&E, FPU & MSA get disabled in root context (hardware) when it
1587 * is disabled in guest context (software), but the register state in
1588 * the hardware may still be in use.
1589 * This is why we explicitly re-enable the hardware before saving.
1593 if (cpu_has_msa
&& vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_MSA
) {
1594 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ
)) {
1595 set_c0_config5(MIPS_CONF5_MSAEN
);
1596 enable_fpu_hazard();
1599 __kvm_save_msa(&vcpu
->arch
);
1600 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_SAVE
, KVM_TRACE_AUX_FPU_MSA
);
1602 /* Disable MSA & FPU */
1604 if (vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_FPU
) {
1605 clear_c0_status(ST0_CU1
| ST0_FR
);
1606 disable_fpu_hazard();
1608 vcpu
->arch
.aux_inuse
&= ~(KVM_MIPS_AUX_FPU
| KVM_MIPS_AUX_MSA
);
1609 } else if (vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_FPU
) {
1610 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ
)) {
1611 set_c0_status(ST0_CU1
);
1612 enable_fpu_hazard();
1615 __kvm_save_fpu(&vcpu
->arch
);
1616 vcpu
->arch
.aux_inuse
&= ~KVM_MIPS_AUX_FPU
;
1617 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_SAVE
, KVM_TRACE_AUX_FPU
);
1620 clear_c0_status(ST0_CU1
| ST0_FR
);
1621 disable_fpu_hazard();
1627 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1628 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1629 * exception if cause bits are set in the value being written.
1631 static int kvm_mips_csr_die_notify(struct notifier_block
*self
,
1632 unsigned long cmd
, void *ptr
)
1634 struct die_args
*args
= (struct die_args
*)ptr
;
1635 struct pt_regs
*regs
= args
->regs
;
1638 /* Only interested in FPE and MSAFPE */
1639 if (cmd
!= DIE_FP
&& cmd
!= DIE_MSAFP
)
1642 /* Return immediately if guest context isn't active */
1643 if (!(current
->flags
& PF_VCPU
))
1646 /* Should never get here from user mode */
1647 BUG_ON(user_mode(regs
));
1649 pc
= instruction_pointer(regs
);
1652 /* match 2nd instruction in __kvm_restore_fcsr */
1653 if (pc
!= (unsigned long)&__kvm_restore_fcsr
+ 4)
1657 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1659 pc
< (unsigned long)&__kvm_restore_msacsr
+ 4 ||
1660 pc
> (unsigned long)&__kvm_restore_msacsr
+ 8)
1665 /* Move PC forward a little and continue executing */
1666 instruction_pointer(regs
) += 4;
1671 static struct notifier_block kvm_mips_csr_die_notifier
= {
1672 .notifier_call
= kvm_mips_csr_die_notify
,
1675 static int __init
kvm_mips_init(void)
1679 ret
= kvm_mips_entry_setup();
1683 ret
= kvm_init(NULL
, sizeof(struct kvm_vcpu
), 0, THIS_MODULE
);
1688 register_die_notifier(&kvm_mips_csr_die_notifier
);
1693 static void __exit
kvm_mips_exit(void)
1697 unregister_die_notifier(&kvm_mips_csr_die_notifier
);
1700 module_init(kvm_mips_init
);
1701 module_exit(kvm_mips_exit
);
1703 EXPORT_TRACEPOINT_SYMBOL(kvm_exit
);