2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * Copyright (C) 2010 John Crispin <john@phrozen.org>
7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
10 #include <linux/interrupt.h>
11 #include <linux/ioport.h>
12 #include <linux/sched.h>
13 #include <linux/irqdomain.h>
14 #include <linux/of_platform.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
18 #include <asm/bootinfo.h>
19 #include <asm/irq_cpu.h>
21 #include <lantiq_soc.h>
24 /* register definitions - internal irqs */
25 #define LTQ_ICU_IM0_ISR 0x0000
26 #define LTQ_ICU_IM0_IER 0x0008
27 #define LTQ_ICU_IM0_IOSR 0x0010
28 #define LTQ_ICU_IM0_IRSR 0x0018
29 #define LTQ_ICU_IM0_IMR 0x0020
30 #define LTQ_ICU_IM1_ISR 0x0028
31 #define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
33 /* register definitions - external irqs */
34 #define LTQ_EIU_EXIN_C 0x0000
35 #define LTQ_EIU_EXIN_INIC 0x0004
36 #define LTQ_EIU_EXIN_INC 0x0008
37 #define LTQ_EIU_EXIN_INEN 0x000C
39 /* number of external interrupts */
42 /* the performance counter */
43 #define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
46 * irqs generated by devices attached to the EBU need to be acked in
49 #define LTQ_ICU_EBU_IRQ 22
51 #define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
52 #define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
54 #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
55 #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
57 /* our 2 ipi interrupts for VSMP */
58 #define MIPS_CPU_IPI_RESCHED_IRQ 0
59 #define MIPS_CPU_IPI_CALL_IRQ 1
61 /* we have a cascade of 8 irqs */
62 #define MIPS_CPU_IRQ_CASCADE 8
64 #ifdef CONFIG_MIPS_MT_SMP
68 static int exin_avail
;
69 static u32 ltq_eiu_irq
[MAX_EIU
];
70 static void __iomem
*ltq_icu_membase
[MAX_IM
];
71 static void __iomem
*ltq_eiu_membase
;
72 static struct irq_domain
*ltq_domain
;
73 static int ltq_perfcount_irq
;
75 int ltq_eiu_get_irq(int exin
)
77 if (exin
< exin_avail
)
78 return ltq_eiu_irq
[exin
];
82 void ltq_disable_irq(struct irq_data
*d
)
84 u32 ier
= LTQ_ICU_IM0_IER
;
85 int offset
= d
->hwirq
- MIPS_CPU_IRQ_CASCADE
;
86 int im
= offset
/ INT_NUM_IM_OFFSET
;
88 offset
%= INT_NUM_IM_OFFSET
;
89 ltq_icu_w32(im
, ltq_icu_r32(im
, ier
) & ~BIT(offset
), ier
);
92 void ltq_mask_and_ack_irq(struct irq_data
*d
)
94 u32 ier
= LTQ_ICU_IM0_IER
;
95 u32 isr
= LTQ_ICU_IM0_ISR
;
96 int offset
= d
->hwirq
- MIPS_CPU_IRQ_CASCADE
;
97 int im
= offset
/ INT_NUM_IM_OFFSET
;
99 offset
%= INT_NUM_IM_OFFSET
;
100 ltq_icu_w32(im
, ltq_icu_r32(im
, ier
) & ~BIT(offset
), ier
);
101 ltq_icu_w32(im
, BIT(offset
), isr
);
104 static void ltq_ack_irq(struct irq_data
*d
)
106 u32 isr
= LTQ_ICU_IM0_ISR
;
107 int offset
= d
->hwirq
- MIPS_CPU_IRQ_CASCADE
;
108 int im
= offset
/ INT_NUM_IM_OFFSET
;
110 offset
%= INT_NUM_IM_OFFSET
;
111 ltq_icu_w32(im
, BIT(offset
), isr
);
114 void ltq_enable_irq(struct irq_data
*d
)
116 u32 ier
= LTQ_ICU_IM0_IER
;
117 int offset
= d
->hwirq
- MIPS_CPU_IRQ_CASCADE
;
118 int im
= offset
/ INT_NUM_IM_OFFSET
;
120 offset
%= INT_NUM_IM_OFFSET
;
121 ltq_icu_w32(im
, ltq_icu_r32(im
, ier
) | BIT(offset
), ier
);
124 static int ltq_eiu_settype(struct irq_data
*d
, unsigned int type
)
128 for (i
= 0; i
< exin_avail
; i
++) {
129 if (d
->hwirq
== ltq_eiu_irq
[i
]) {
134 case IRQF_TRIGGER_NONE
:
136 case IRQF_TRIGGER_RISING
:
140 case IRQF_TRIGGER_FALLING
:
144 case IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
:
148 case IRQF_TRIGGER_HIGH
:
151 case IRQF_TRIGGER_LOW
:
155 pr_err("invalid type %d for irq %ld\n",
161 irq_set_handler(d
->hwirq
, handle_edge_irq
);
163 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C
) |
164 (val
<< (i
* 4)), LTQ_EIU_EXIN_C
);
171 static unsigned int ltq_startup_eiu_irq(struct irq_data
*d
)
176 for (i
= 0; i
< exin_avail
; i
++) {
177 if (d
->hwirq
== ltq_eiu_irq
[i
]) {
178 /* by default we are low level triggered */
179 ltq_eiu_settype(d
, IRQF_TRIGGER_LOW
);
180 /* clear all pending */
181 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC
) & ~BIT(i
),
184 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN
) | BIT(i
),
193 static void ltq_shutdown_eiu_irq(struct irq_data
*d
)
198 for (i
= 0; i
< exin_avail
; i
++) {
199 if (d
->hwirq
== ltq_eiu_irq
[i
]) {
201 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN
) & ~BIT(i
),
208 static struct irq_chip ltq_irq_type
= {
210 .irq_enable
= ltq_enable_irq
,
211 .irq_disable
= ltq_disable_irq
,
212 .irq_unmask
= ltq_enable_irq
,
213 .irq_ack
= ltq_ack_irq
,
214 .irq_mask
= ltq_disable_irq
,
215 .irq_mask_ack
= ltq_mask_and_ack_irq
,
218 static struct irq_chip ltq_eiu_type
= {
220 .irq_startup
= ltq_startup_eiu_irq
,
221 .irq_shutdown
= ltq_shutdown_eiu_irq
,
222 .irq_enable
= ltq_enable_irq
,
223 .irq_disable
= ltq_disable_irq
,
224 .irq_unmask
= ltq_enable_irq
,
225 .irq_ack
= ltq_ack_irq
,
226 .irq_mask
= ltq_disable_irq
,
227 .irq_mask_ack
= ltq_mask_and_ack_irq
,
228 .irq_set_type
= ltq_eiu_settype
,
231 static void ltq_hw_irqdispatch(int module
)
235 irq
= ltq_icu_r32(module
, LTQ_ICU_IM0_IOSR
);
240 * silicon bug causes only the msb set to 1 to be valid. all
241 * other bits might be bogus
244 do_IRQ((int)irq
+ MIPS_CPU_IRQ_CASCADE
+ (INT_NUM_IM_OFFSET
* module
));
246 /* if this is a EBU irq, we need to ack it or get a deadlock */
247 if ((irq
== LTQ_ICU_EBU_IRQ
) && (module
== 0) && LTQ_EBU_PCC_ISTAT
)
248 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT
) | 0x10,
252 #define DEFINE_HWx_IRQDISPATCH(x) \
253 static void ltq_hw ## x ## _irqdispatch(void) \
255 ltq_hw_irqdispatch(x); \
257 DEFINE_HWx_IRQDISPATCH(0)
258 DEFINE_HWx_IRQDISPATCH(1)
259 DEFINE_HWx_IRQDISPATCH(2)
260 DEFINE_HWx_IRQDISPATCH(3)
261 DEFINE_HWx_IRQDISPATCH(4)
263 #if MIPS_CPU_TIMER_IRQ == 7
264 static void ltq_hw5_irqdispatch(void)
266 do_IRQ(MIPS_CPU_TIMER_IRQ
);
269 DEFINE_HWx_IRQDISPATCH(5)
272 static void ltq_hw_irq_handler(struct irq_desc
*desc
)
274 ltq_hw_irqdispatch(irq_desc_get_irq(desc
) - 2);
277 asmlinkage
void plat_irq_dispatch(void)
279 unsigned int pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
283 spurious_interrupt();
287 pending
>>= CAUSEB_IP
;
289 irq
= fls(pending
) - 1;
290 do_IRQ(MIPS_CPU_IRQ_BASE
+ irq
);
291 pending
&= ~BIT(irq
);
295 static int icu_map(struct irq_domain
*d
, unsigned int irq
, irq_hw_number_t hw
)
297 struct irq_chip
*chip
= <q_irq_type
;
300 if (hw
< MIPS_CPU_IRQ_CASCADE
)
303 for (i
= 0; i
< exin_avail
; i
++)
304 if (hw
== ltq_eiu_irq
[i
])
305 chip
= <q_eiu_type
;
307 irq_set_chip_and_handler(irq
, chip
, handle_level_irq
);
312 static const struct irq_domain_ops irq_domain_ops
= {
313 .xlate
= irq_domain_xlate_onetwocell
,
317 int __init
icu_of_init(struct device_node
*node
, struct device_node
*parent
)
319 struct device_node
*eiu_node
;
323 for (i
= 0; i
< MAX_IM
; i
++) {
324 if (of_address_to_resource(node
, i
, &res
))
325 panic("Failed to get icu memory range");
327 if (!request_mem_region(res
.start
, resource_size(&res
),
329 pr_err("Failed to request icu memory");
331 ltq_icu_membase
[i
] = ioremap_nocache(res
.start
,
332 resource_size(&res
));
333 if (!ltq_icu_membase
[i
])
334 panic("Failed to remap icu memory");
337 /* turn off all irqs by default */
338 for (i
= 0; i
< MAX_IM
; i
++) {
339 /* make sure all irqs are turned off by default */
340 ltq_icu_w32(i
, 0, LTQ_ICU_IM0_IER
);
341 /* clear all possibly pending interrupts */
342 ltq_icu_w32(i
, ~0, LTQ_ICU_IM0_ISR
);
347 for (i
= 0; i
< MAX_IM
; i
++)
348 irq_set_chained_handler(i
+ 2, ltq_hw_irq_handler
);
351 pr_info("Setting up vectored interrupts\n");
352 set_vi_handler(2, ltq_hw0_irqdispatch
);
353 set_vi_handler(3, ltq_hw1_irqdispatch
);
354 set_vi_handler(4, ltq_hw2_irqdispatch
);
355 set_vi_handler(5, ltq_hw3_irqdispatch
);
356 set_vi_handler(6, ltq_hw4_irqdispatch
);
357 set_vi_handler(7, ltq_hw5_irqdispatch
);
360 ltq_domain
= irq_domain_add_linear(node
,
361 (MAX_IM
* INT_NUM_IM_OFFSET
) + MIPS_CPU_IRQ_CASCADE
,
364 #ifndef CONFIG_MIPS_MT_SMP
365 set_c0_status(IE_IRQ0
| IE_IRQ1
| IE_IRQ2
|
366 IE_IRQ3
| IE_IRQ4
| IE_IRQ5
);
368 set_c0_status(IE_SW0
| IE_SW1
| IE_IRQ0
| IE_IRQ1
|
369 IE_IRQ2
| IE_IRQ3
| IE_IRQ4
| IE_IRQ5
);
372 /* tell oprofile which irq to use */
373 ltq_perfcount_irq
= irq_create_mapping(ltq_domain
, LTQ_PERF_IRQ
);
376 * if the timer irq is not one of the mips irqs we need to
379 if (MIPS_CPU_TIMER_IRQ
!= 7)
380 irq_create_mapping(ltq_domain
, MIPS_CPU_TIMER_IRQ
);
382 /* the external interrupts are optional and xway only */
383 eiu_node
= of_find_compatible_node(NULL
, NULL
, "lantiq,eiu-xway");
384 if (eiu_node
&& !of_address_to_resource(eiu_node
, 0, &res
)) {
385 /* find out how many external irq sources we have */
386 exin_avail
= of_property_count_u32_elems(eiu_node
,
389 if (exin_avail
> MAX_EIU
)
390 exin_avail
= MAX_EIU
;
392 ret
= of_property_read_u32_array(eiu_node
, "lantiq,eiu-irqs",
393 ltq_eiu_irq
, exin_avail
);
395 panic("failed to load external irq resources");
397 if (!request_mem_region(res
.start
, resource_size(&res
),
399 pr_err("Failed to request eiu memory");
401 ltq_eiu_membase
= ioremap_nocache(res
.start
,
402 resource_size(&res
));
403 if (!ltq_eiu_membase
)
404 panic("Failed to remap eiu memory");
410 int get_c0_perfcount_int(void)
412 return ltq_perfcount_irq
;
414 EXPORT_SYMBOL_GPL(get_c0_perfcount_int
);
416 unsigned int get_c0_compare_int(void)
418 return MIPS_CPU_TIMER_IRQ
;
421 static struct of_device_id __initdata of_irq_ids
[] = {
422 { .compatible
= "lantiq,icu", .data
= icu_of_init
},
426 void __init
arch_init_irq(void)
428 of_irq_init(of_irq_ids
);