arch/mips/philips/pnx8550/common/int.c

   1 /*
   2  *
   3  * Copyright (C) 2005 Embedded Alley Solutions, Inc
   4  * Ported to 2.6.
   5  *
   6  * Per Hallsmark, per.hallsmark@mvista.com
   7  * Copyright (C) 2000, 2001 MIPS Technologies, Inc.
   8  * Copyright (C) 2001 Ralf Baechle
   9  *
  10  * Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com
  11  *
  12  *  This program is free software; you can distribute it and/or modify it
  13  *  under the terms of the GNU General Public License (Version 2) as
  14  *  published by the Free Software Foundation.
  15  *
  16  *  This program is distributed in the hope it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  19  *  for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along
  22  *  with this program; if not, write to the Free Software Foundation, Inc.,
  23  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  24  *
  25  */
  26 #include <linux/config.h>
  27 #include <linux/init.h>
  28 #include <linux/irq.h>
  29 #include <linux/sched.h>
  30 #include <linux/slab.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/kernel_stat.h>
  33 #include <linux/random.h>
  34 #include <linux/module.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/gdb-stub.h>
  38 #include <int.h>
  39 #include <uart.h>
  40
  41 extern asmlinkage void cp0_irqdispatch(void);
  42
  43 static DEFINE_SPINLOCK(irq_lock);
  44
  45 /* default prio for interrupts */
  46 /* first one is a no-no so therefore always prio 0 (disabled) */
  47 static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
  48         0, 1, 1, 1, 1, 15, 1, 1, 1, 1,  //   0 -  9
  49         1, 1, 1, 1, 1, 1, 1, 1, 1, 1,   //  10 - 19
  50         1, 1, 1, 1, 1, 1, 1, 1, 1, 1,   //  20 - 29
  51         1, 1, 1, 1, 1, 1, 1, 1, 1, 1,   //  30 - 39
  52         1, 1, 1, 1, 1, 1, 1, 1, 1, 1,   //  40 - 49
  53         1, 1, 1, 1, 1, 1, 1, 1, 2, 1,   //  50 - 59
  54         1, 1, 1, 1, 1, 1, 1, 1, 1, 1,   //  60 - 69
  55         1                       //  70
  56 };
  57
  58 void hw0_irqdispatch(int irq, struct pt_regs *regs)
  59 {
  60         /* find out which interrupt */
  61         irq = PNX8550_GIC_VECTOR_0 >> 3;
  62
  63         if (irq == 0) {
  64                 printk("hw0_irqdispatch: irq 0, spurious interrupt?\n");
  65                 return;
  66         }
  67         do_IRQ(PNX8550_INT_GIC_MIN + irq, regs);
  68 }
  69
  70
  71 void timer_irqdispatch(int irq, struct pt_regs *regs)
  72 {
  73         irq = (0x01c0 & read_c0_config7()) >> 6;
  74
  75         if (irq == 0) {
  76                 printk("timer_irqdispatch: irq 0, spurious interrupt?\n");
  77                 return;
  78         }
  79
  80         if (irq & 0x1) {
  81                 do_IRQ(PNX8550_INT_TIMER1, regs);
  82         }
  83         if (irq & 0x2) {
  84                 do_IRQ(PNX8550_INT_TIMER2, regs);
  85         }
  86         if (irq & 0x4) {
  87                 do_IRQ(PNX8550_INT_TIMER3, regs);
  88         }
  89 }
  90
  91 static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
  92 {
  93         unsigned long status = read_c0_status();
  94
  95         status &= ~((clr_mask & 0xFF) << 8);
  96         status |= (set_mask & 0xFF) << 8;
  97
  98         write_c0_status(status);
  99 }
 100
 101 static inline void mask_gic_int(unsigned int irq_nr)
 102 {
 103         /* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */
 104         PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */
 105 }
 106
 107 static inline void unmask_gic_int(unsigned int irq_nr)
 108 {
 109         /* set prio mask to lower four bits and enable interrupt */
 110         PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr];
 111 }
 112
 113 static inline void mask_irq(unsigned int irq_nr)
 114 {
 115         if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
 116                 modify_cp0_intmask(1 << irq_nr, 0);
 117         } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
 118                 (irq_nr <= PNX8550_INT_GIC_MAX)) {
 119                 mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
 120         } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
 121                 (irq_nr <= PNX8550_INT_TIMER_MAX)) {
 122                 modify_cp0_intmask(1 << 7, 0);
 123         } else {
 124                 printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
 125         }
 126 }
 127
 128 static inline void unmask_irq(unsigned int irq_nr)
 129 {
 130         if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
 131                 modify_cp0_intmask(0, 1 << irq_nr);
 132         } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
 133                 (irq_nr <= PNX8550_INT_GIC_MAX)) {
 134                 unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
 135         } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
 136                 (irq_nr <= PNX8550_INT_TIMER_MAX)) {
 137                 modify_cp0_intmask(0, 1 << 7);
 138         } else {
 139                 printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
 140         }
 141 }
 142
 143 #define pnx8550_disable pnx8550_ack
 144 static void pnx8550_ack(unsigned int irq)
 145 {
 146         unsigned long flags;
 147
 148         spin_lock_irqsave(&irq_lock, flags);
 149         mask_irq(irq);
 150         spin_unlock_irqrestore(&irq_lock, flags);
 151 }
 152
 153 #define pnx8550_enable pnx8550_unmask
 154 static void pnx8550_unmask(unsigned int irq)
 155 {
 156         unsigned long flags;
 157
 158         spin_lock_irqsave(&irq_lock, flags);
 159         unmask_irq(irq);
 160         spin_unlock_irqrestore(&irq_lock, flags);
 161 }
 162
 163 static unsigned int startup_irq(unsigned int irq_nr)
 164 {
 165         pnx8550_unmask(irq_nr);
 166         return 0;
 167 }
 168
 169 static void shutdown_irq(unsigned int irq_nr)
 170 {
 171         pnx8550_ack(irq_nr);
 172         return;
 173 }
 174
 175 int pnx8550_set_gic_priority(int irq, int priority)
 176 {
 177         int gic_irq = irq-PNX8550_INT_GIC_MIN;
 178         int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf;
 179
 180         gic_prio[gic_irq] = priority;
 181         PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]);
 182
 183         return prev_priority;
 184 }
 185
 186 static inline void mask_and_ack_level_irq(unsigned int irq)
 187 {
 188         pnx8550_disable(irq);
 189         return;
 190 }
 191
 192 static void end_irq(unsigned int irq)
 193 {
 194         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
 195                 pnx8550_enable(irq);
 196         }
 197 }
 198
 199 static struct hw_interrupt_type level_irq_type = {
 200         .typename =     "PNX Level IRQ",
 201         .startup =      startup_irq,
 202         .shutdown =     shutdown_irq,
 203         .enable =       pnx8550_enable,
 204         .disable =      pnx8550_disable,
 205         .ack =          mask_and_ack_level_irq,
 206         .end =          end_irq,
 207 };
 208
 209 static struct irqaction gic_action = {
 210         .handler =      no_action,
 211         .flags =        SA_INTERRUPT,
 212         .name =         "GIC",
 213 };
 214
 215 static struct irqaction timer_action = {
 216         .handler =      no_action,
 217         .flags =        SA_INTERRUPT,
 218         .name =         "Timer",
 219 };
 220
 221 void __init arch_init_irq(void)
 222 {
 223         int i;
 224         int configPR;
 225
 226         /* init of cp0 interrupts */
 227         set_except_vector(0, cp0_irqdispatch);
 228
 229         for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
 230                 irq_desc[i].handler = &level_irq_type;
 231                 pnx8550_ack(i); /* mask the irq just in case  */
 232         }
 233
 234         /* init of GIC/IPC interrupts */
 235         /* should be done before cp0 since cp0 init enables the GIC int */
 236         for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) {
 237                 int gic_int_line = i - PNX8550_INT_GIC_MIN;
 238                 if (gic_int_line == 0 )
 239                         continue;       // don't fiddle with int 0
 240                 /*
 241                  * enable change of TARGET, ENABLE and ACTIVE_LOW bits
 242                  * set TARGET        0 to route through hw0 interrupt
 243                  * set ACTIVE_LOW    0 active high  (correct?)
 244                  *
 245                  * We really should setup an interrupt description table
 246                  * to do this nicely.
 247                  * Note, PCI INTA is active low on the bus, but inverted
 248                  * in the GIC, so to us it's active high.
 249                  */
 250 #ifdef CONFIG_PNX8550_V2PCI
 251                 if (gic_int_line == (PNX8550_INT_GPIO0 - PNX8550_INT_GIC_MIN)) {
 252                         /* PCI INT through gpio 8, which is setup in
 253                          * pnx8550_setup.c and routed to GPIO
 254                          * Interrupt Level 0 (GPIO Connection 58).
 255                          * Set it active low. */
 256
 257                         PNX8550_GIC_REQ(gic_int_line) = 0x1E020000;
 258                 } else
 259 #endif
 260                 {
 261                         PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
 262                 }
 263
 264                 /* mask/priority is still 0 so we will not get any
 265                  * interrupts until it is unmasked */
 266
 267                 irq_desc[i].handler = &level_irq_type;
 268         }
 269
 270         /* Priority level 0 */
 271         PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0;
 272
 273         /* Set int vector table address */
 274         PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
 275
 276         irq_desc[MIPS_CPU_GIC_IRQ].handler = &level_irq_type;
 277         setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
 278
 279         /* init of Timer interrupts */
 280         for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) {
 281                 irq_desc[i].handler = &level_irq_type;
 282         }
 283
 284         /* Stop Timer 1-3 */
 285         configPR = read_c0_config7();
 286         configPR |= 0x00000038;
 287         write_c0_config7(configPR);
 288
 289         irq_desc[MIPS_CPU_TIMER_IRQ].handler = &level_irq_type;
 290         setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
 291 }
 292
 293 EXPORT_SYMBOL(pnx8550_set_gic_priority);