2 * linux/arch/mips/txx9/pci.c
4 * Based on linux/arch/mips/txx9/rbtx4927/setup.c,
5 * linux/arch/mips/txx9/rbtx4938/setup.c,
6 * and RBTX49xx patch from CELF patch archive.
8 * Copyright 2001-2005 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
16 #include <linux/delay.h>
17 #include <linux/jiffies.h>
19 #include <asm/txx9/generic.h>
20 #include <asm/txx9/pci.h>
21 #ifdef CONFIG_TOSHIBA_FPCIB0
22 #include <linux/interrupt.h>
23 #include <linux/slab.h>
24 #include <asm/i8259.h>
25 #include <asm/txx9/smsc_fdc37m81x.h>
29 early_read_config_word(struct pci_controller
*hose
,
30 int top_bus
, int bus
, int devfn
, int offset
, u16
*value
)
32 struct pci_dev fake_dev
;
33 struct pci_bus fake_bus
;
35 fake_dev
.bus
= &fake_bus
;
36 fake_dev
.sysdata
= hose
;
37 fake_dev
.devfn
= devfn
;
38 fake_bus
.number
= bus
;
39 fake_bus
.sysdata
= hose
;
40 fake_bus
.ops
= hose
->pci_ops
;
43 /* Fake a parent bus structure. */
44 fake_bus
.parent
= &fake_bus
;
46 fake_bus
.parent
= NULL
;
48 return pci_read_config_word(&fake_dev
, offset
, value
);
51 int __init
txx9_pci66_check(struct pci_controller
*hose
, int top_bus
,
59 /* It seems SLC90E66 needs some time after PCI reset... */
62 printk(KERN_INFO
"PCI: Checking 66MHz capabilities...\n");
64 for (pci_devfn
= 0; pci_devfn
< 0xff; pci_devfn
++) {
65 if (PCI_FUNC(pci_devfn
))
67 if (early_read_config_word(hose
, top_bus
, current_bus
,
68 pci_devfn
, PCI_VENDOR_ID
, &vid
) !=
74 /* check 66MHz capability */
78 early_read_config_word(hose
, top_bus
, current_bus
,
79 pci_devfn
, PCI_STATUS
, &stat
);
80 if (!(stat
& PCI_STATUS_66MHZ
)) {
82 "PCI: %02x:%02x not 66MHz capable.\n",
83 current_bus
, pci_devfn
);
92 static struct resource primary_pci_mem_res
[2] = {
93 { .name
= "PCI MEM" },
94 { .name
= "PCI MMIO" },
96 static struct resource primary_pci_io_res
= { .name
= "PCI IO" };
97 struct pci_controller txx9_primary_pcic
= {
98 .mem_resource
= &primary_pci_mem_res
[0],
99 .io_resource
= &primary_pci_io_res
,
103 int txx9_pci_mem_high __initdata
= 1;
105 int txx9_pci_mem_high __initdata
;
109 * allocate pci_controller and resources.
110 * mem_base, io_base: physical addresss. 0 for auto assignment.
111 * mem_size and io_size means max size on auto assignment.
112 * pcic must be &txx9_primary_pcic or NULL.
114 struct pci_controller
*__init
115 txx9_alloc_pci_controller(struct pci_controller
*pcic
,
116 unsigned long mem_base
, unsigned long mem_size
,
117 unsigned long io_base
, unsigned long io_size
)
120 struct pci_controller c
;
121 struct resource r_mem
[2];
122 struct resource r_io
;
124 int min_size
= 0x10000;
127 new = kzalloc(sizeof(*new), GFP_KERNEL
);
130 new->r_mem
[0].name
= "PCI mem";
131 new->r_mem
[1].name
= "PCI mmio";
132 new->r_io
.name
= "PCI io";
133 new->c
.mem_resource
= new->r_mem
;
134 new->c
.io_resource
= &new->r_io
;
137 BUG_ON(pcic
!= &txx9_primary_pcic
);
138 pcic
->io_resource
->flags
= IORESOURCE_IO
;
141 * for auto assignment, first search a (big) region for PCI
142 * MEM, then search a region for PCI IO.
145 pcic
->mem_resource
[0].start
= mem_base
;
146 pcic
->mem_resource
[0].end
= mem_base
+ mem_size
- 1;
147 if (request_resource(&iomem_resource
, &pcic
->mem_resource
[0]))
150 unsigned long min
= 0, max
= 0x20000000; /* low 512MB */
152 /* default size for auto assignment */
153 if (txx9_pci_mem_high
)
154 mem_size
= 0x20000000; /* mem:512M(max) */
156 mem_size
= 0x08000000; /* mem:128M(max) */
158 if (txx9_pci_mem_high
) {
162 /* search free region for PCI MEM */
163 for (; mem_size
>= min_size
; mem_size
/= 2) {
164 if (allocate_resource(&iomem_resource
,
165 &pcic
->mem_resource
[0],
167 mem_size
, NULL
, NULL
) == 0)
170 if (mem_size
< min_size
)
174 pcic
->mem_resource
[1].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
176 pcic
->mem_resource
[1].start
= io_base
;
177 pcic
->mem_resource
[1].end
= io_base
+ io_size
- 1;
178 if (request_resource(&iomem_resource
, &pcic
->mem_resource
[1]))
179 goto release_and_exit
;
182 /* default size for auto assignment */
183 io_size
= 0x01000000; /* io:16M(max) */
184 /* search free region for PCI IO in low 512MB */
185 for (; io_size
>= min_size
; io_size
/= 2) {
186 if (allocate_resource(&iomem_resource
,
187 &pcic
->mem_resource
[1],
188 io_size
, 0, 0x20000000,
189 io_size
, NULL
, NULL
) == 0)
192 if (io_size
< min_size
)
193 goto release_and_exit
;
194 io_base
= pcic
->mem_resource
[1].start
;
197 pcic
->mem_resource
[0].flags
= IORESOURCE_MEM
;
198 if (pcic
== &txx9_primary_pcic
&&
199 mips_io_port_base
== (unsigned long)-1) {
200 /* map ioport 0 to PCI I/O space address 0 */
201 set_io_port_base(IO_BASE
+ pcic
->mem_resource
[1].start
);
202 pcic
->io_resource
->start
= 0;
203 pcic
->io_offset
= 0; /* busaddr == ioaddr */
204 pcic
->io_map_base
= IO_BASE
+ pcic
->mem_resource
[1].start
;
206 /* physaddr to ioaddr */
207 pcic
->io_resource
->start
=
208 io_base
- (mips_io_port_base
- IO_BASE
);
209 pcic
->io_offset
= io_base
- (mips_io_port_base
- IO_BASE
);
210 pcic
->io_map_base
= mips_io_port_base
;
212 pcic
->io_resource
->end
= pcic
->io_resource
->start
+ io_size
- 1;
214 pcic
->mem_offset
= 0; /* busaddr == physaddr */
216 printk(KERN_INFO
"PCI: IO 0x%08llx-0x%08llx MEM 0x%08llx-0x%08llx\n",
217 (unsigned long long)pcic
->mem_resource
[1].start
,
218 (unsigned long long)pcic
->mem_resource
[1].end
,
219 (unsigned long long)pcic
->mem_resource
[0].start
,
220 (unsigned long long)pcic
->mem_resource
[0].end
);
222 /* register_pci_controller() will request MEM resource */
223 release_resource(&pcic
->mem_resource
[0]);
226 release_resource(&pcic
->mem_resource
[0]);
229 printk(KERN_ERR
"PCI: Failed to allocate resources.\n");
234 txx9_arch_pci_init(void)
236 PCIBIOS_MIN_IO
= 0x8000; /* reseve legacy I/O space */
239 arch_initcall(txx9_arch_pci_init
);
241 /* IRQ/IDSEL mapping */
242 int txx9_pci_option
=
243 #ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
246 TXX9_PCI_OPT_CLK_AUTO
;
248 enum txx9_pci_err_action txx9_pci_err_action
= TXX9_PCI_ERR_REPORT
;
250 #ifdef CONFIG_TOSHIBA_FPCIB0
251 static irqreturn_t
i8259_interrupt(int irq
, void *dev_id
)
255 isairq
= i8259_irq();
256 if (unlikely(isairq
<= I8259A_IRQ_BASE
))
258 generic_handle_irq(isairq
);
263 txx9_i8259_irq_setup(int irq
)
268 err
= request_irq(irq
, &i8259_interrupt
, IRQF_DISABLED
|IRQF_SHARED
,
269 "cascade(i8259)", (void *)(long)irq
);
271 printk(KERN_INFO
"PCI-ISA bridge PIC (irq %d)\n", irq
);
275 static void __init
quirk_slc90e66_bridge(struct pci_dev
*dev
)
277 int irq
; /* PCI/ISA Bridge interrupt */
281 irq
= pcibios_map_irq(dev
, PCI_SLOT(dev
->devfn
), 1); /* INTA */
284 txx9_i8259_irq_setup(irq
);
285 pci_read_config_byte(dev
, 0x64, ®_64
);
286 pci_read_config_dword(dev
, 0xb0, ®_b0
);
287 pci_read_config_byte(dev
, 0xe1, ®_e1
);
288 /* serial irq control */
291 reg_b0
|= 0x00010000;
292 /* ide irq on isa14 */
295 pci_write_config_byte(dev
, 0x64, reg_64
);
296 pci_write_config_dword(dev
, 0xb0, reg_b0
);
297 pci_write_config_byte(dev
, 0xe1, reg_e1
);
299 smsc_fdc37m81x_init(0x3f0);
300 smsc_fdc37m81x_config_beg();
301 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM
,
303 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT
, 1);
304 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2
, 12);
305 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE
,
307 smsc_fdc37m81x_config_end();
310 static void quirk_slc90e66_ide(struct pci_dev
*dev
)
313 int regs
[2] = {0x41, 0x43};
316 /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
317 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, 14);
318 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &dat
);
319 printk(KERN_INFO
"PCI: %s: IRQ %02x", pci_name(dev
), dat
);
320 /* enable SMSC SLC90E66 IDE */
321 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
322 pci_read_config_byte(dev
, regs
[i
], &dat
);
323 pci_write_config_byte(dev
, regs
[i
], dat
| 0x80);
324 pci_read_config_byte(dev
, regs
[i
], &dat
);
325 printk(KERN_CONT
" IDETIM%d %02x", i
, dat
);
327 pci_read_config_byte(dev
, 0x5c, &dat
);
329 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
331 * This line of code is intended to provide the user with a work
332 * around solution to the anomalies cited in SMSC's anomaly sheet
333 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
335 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
338 pci_write_config_byte(dev
, regs
[i
], dat
);
339 pci_read_config_byte(dev
, 0x5c, &dat
);
340 printk(KERN_CONT
" REG5C %02x", dat
);
341 printk(KERN_CONT
"\n");
343 #endif /* CONFIG_TOSHIBA_FPCIB0 */
345 static void tc35815_fixup(struct pci_dev
*dev
)
347 /* This device may have PM registers but not they are not suported. */
349 dev_info(&dev
->dev
, "PM disabled\n");
354 static void final_fixup(struct pci_dev
*dev
)
358 /* Do build-in self test */
359 if (pci_read_config_byte(dev
, PCI_BIST
, &bist
) == PCIBIOS_SUCCESSFUL
&&
360 (bist
& PCI_BIST_CAPABLE
)) {
361 unsigned long timeout
;
362 pci_set_power_state(dev
, PCI_D0
);
363 printk(KERN_INFO
"PCI: %s BIST...", pci_name(dev
));
364 pci_write_config_byte(dev
, PCI_BIST
, PCI_BIST_START
);
365 timeout
= jiffies
+ HZ
* 2; /* timeout after 2 sec */
367 pci_read_config_byte(dev
, PCI_BIST
, &bist
);
368 if (time_after(jiffies
, timeout
))
370 } while (bist
& PCI_BIST_START
);
371 if (bist
& (PCI_BIST_CODE_MASK
| PCI_BIST_START
))
372 printk(KERN_CONT
"failed. (0x%x)\n", bist
);
374 printk(KERN_CONT
"OK.\n");
378 #ifdef CONFIG_TOSHIBA_FPCIB0
379 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
380 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR
, PCI_DEVICE_ID_EFAR_SLC90E66_0
,
381 quirk_slc90e66_bridge
);
382 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR
, PCI_DEVICE_ID_EFAR_SLC90E66_1
,
384 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR
, PCI_DEVICE_ID_EFAR_SLC90E66_1
,
387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2
,
388 PCI_DEVICE_ID_TOSHIBA_TC35815_NWU
, tc35815_fixup
);
389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2
,
390 PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939
, tc35815_fixup
);
391 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, final_fixup
);
392 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID
, PCI_ANY_ID
, final_fixup
);
394 int pcibios_plat_dev_init(struct pci_dev
*dev
)
399 int __init
pcibios_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
401 return txx9_board_vec
->pci_map_irq(dev
, slot
, pin
);
404 char * (*txx9_board_pcibios_setup
)(char *str
) __devinitdata
;
406 char *__devinit
txx9_pcibios_setup(char *str
)
408 if (txx9_board_pcibios_setup
&& !txx9_board_pcibios_setup(str
))
410 if (!strcmp(str
, "picmg")) {
411 /* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
412 (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
413 txx9_pci_option
|= TXX9_PCI_OPT_PICMG
;
415 } else if (!strcmp(str
, "nopicmg")) {
416 /* non-PICMG compliant backplane (TOSHIBA
417 RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
418 txx9_pci_option
&= ~TXX9_PCI_OPT_PICMG
;
420 } else if (!strncmp(str
, "clk=", 4)) {
422 txx9_pci_option
&= ~TXX9_PCI_OPT_CLK_MASK
;
423 if (strcmp(val
, "33") == 0)
424 txx9_pci_option
|= TXX9_PCI_OPT_CLK_33
;
425 else if (strcmp(val
, "66") == 0)
426 txx9_pci_option
|= TXX9_PCI_OPT_CLK_66
;
428 txx9_pci_option
|= TXX9_PCI_OPT_CLK_AUTO
;
430 } else if (!strncmp(str
, "err=", 4)) {
431 if (!strcmp(str
+ 4, "panic"))
432 txx9_pci_err_action
= TXX9_PCI_ERR_PANIC
;
433 else if (!strcmp(str
+ 4, "ignore"))
434 txx9_pci_err_action
= TXX9_PCI_ERR_IGNORE
;