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1 #
2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
4 #
5
6 config OPENRISC
7 def_bool y
8 select OF
9 select OF_EARLY_FLATTREE
10 select IRQ_DOMAIN
11 select HANDLE_DOMAIN_IRQ
12 select HAVE_MEMBLOCK
13 select GPIOLIB
14 select HAVE_ARCH_TRACEHOOK
15 select GENERIC_IRQ_CHIP
16 select GENERIC_IRQ_PROBE
17 select GENERIC_IRQ_SHOW
18 select GENERIC_IOMAP
19 select GENERIC_CPU_DEVICES
20 select HAVE_UID16
21 select GENERIC_ATOMIC64
22 select GENERIC_CLOCKEVENTS
23 select GENERIC_STRNCPY_FROM_USER
24 select GENERIC_STRNLEN_USER
25 select MODULES_USE_ELF_RELA
26 select HAVE_DEBUG_STACKOVERFLOW
27 select OR1K_PIC
28 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
29 select NO_BOOTMEM
30
31 config MMU
32 def_bool y
33
34 config RWSEM_GENERIC_SPINLOCK
35 def_bool y
36
37 config RWSEM_XCHGADD_ALGORITHM
38 def_bool n
39
40 config GENERIC_HWEIGHT
41 def_bool y
42
43 config NO_IOPORT_MAP
44 def_bool y
45
46 config TRACE_IRQFLAGS_SUPPORT
47 def_bool y
48
49 # For now, use generic checksum functions
50 #These can be reimplemented in assembly later if so inclined
51 config GENERIC_CSUM
52 def_bool y
53
54 source "init/Kconfig"
55
56 source "kernel/Kconfig.freezer"
57
58 menu "Processor type and features"
59
60 choice
61 prompt "Subarchitecture"
62 default OR1K_1200
63
64 config OR1K_1200
65 bool "OR1200"
66 help
67 Generic OpenRISC 1200 architecture
68
69 endchoice
70
71 config OPENRISC_BUILTIN_DTB
72 string "Builtin DTB"
73 default ""
74
75 menu "Class II Instructions"
76
77 config OPENRISC_HAVE_INST_FF1
78 bool "Have instruction l.ff1"
79 default y
80 help
81 Select this if your implementation has the Class II instruction l.ff1
82
83 config OPENRISC_HAVE_INST_FL1
84 bool "Have instruction l.fl1"
85 default y
86 help
87 Select this if your implementation has the Class II instruction l.fl1
88
89 config OPENRISC_HAVE_INST_MUL
90 bool "Have instruction l.mul for hardware multiply"
91 default y
92 help
93 Select this if your implementation has a hardware multiply instruction
94
95 config OPENRISC_HAVE_INST_DIV
96 bool "Have instruction l.div for hardware divide"
97 default y
98 help
99 Select this if your implementation has a hardware divide instruction
100 endmenu
101
102 config NR_CPUS
103 int
104 default "1"
105
106 source kernel/Kconfig.hz
107 source kernel/Kconfig.preempt
108 source "mm/Kconfig"
109
110 config OPENRISC_NO_SPR_SR_DSX
111 bool "use SPR_SR_DSX software emulation" if OR1K_1200
112 default y
113 help
114 SPR_SR_DSX bit is status register bit indicating whether
115 the last exception has happened in delay slot.
116
117 OpenRISC architecture makes it optional to have it implemented
118 in hardware and the OR1200 does not have it.
119
120 Say N here if you know that your OpenRISC processor has
121 SPR_SR_DSX bit implemented. Say Y if you are unsure.
122
123 config CMDLINE
124 string "Default kernel command string"
125 default ""
126 help
127 On some architectures there is currently no way for the boot loader
128 to pass arguments to the kernel. For these architectures, you should
129 supply some command-line options at build time by entering them
130 here.
131
132 menu "Debugging options"
133
134 config JUMP_UPON_UNHANDLED_EXCEPTION
135 bool "Try to die gracefully"
136 default y
137 help
138 Now this puts kernel into infinite loop after first oops. Till
139 your kernel crashes this doesn't have any influence.
140
141 Say Y if you are unsure.
142
143 config OPENRISC_ESR_EXCEPTION_BUG_CHECK
144 bool "Check for possible ESR exception bug"
145 default n
146 help
147 This option enables some checks that might expose some problems
148 in kernel.
149
150 Say N if you are unsure.
151
152 endmenu
153
154 endmenu
155
156 menu "Executable file formats"
157
158 source "fs/Kconfig.binfmt"
159
160 endmenu
161
162 source "net/Kconfig"
163
164 source "drivers/Kconfig"
165
166 source "fs/Kconfig"
167
168 source "security/Kconfig"
169
170 source "crypto/Kconfig"
171
172 source "lib/Kconfig"
173
174 menu "Kernel hacking"
175
176 source "lib/Kconfig.debug"
177
178 endmenu