1 /* $Id: cache.c,v 1.4 2000/01/25 00:11:38 prumpf Exp $
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
8 * Copyright (C) 1999 SuSE GmbH Nuernberg
9 * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
11 * Cache and TLB management
15 #include <linux/init.h>
16 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/seq_file.h>
20 #include <linux/pagemap.h>
23 #include <asm/cache.h>
24 #include <asm/cacheflush.h>
25 #include <asm/tlbflush.h>
26 #include <asm/system.h>
28 #include <asm/pgalloc.h>
29 #include <asm/processor.h>
30 #include <asm/sections.h>
32 int split_tlb __read_mostly
;
33 int dcache_stride __read_mostly
;
34 int icache_stride __read_mostly
;
35 EXPORT_SYMBOL(dcache_stride
);
38 #if defined(CONFIG_SMP)
39 /* On some machines (e.g. ones with the Merced bus), there can be
40 * only a single PxTLB broadcast at a time; this must be guaranteed
41 * by software. We put a spinlock around all TLB flushes to
44 DEFINE_SPINLOCK(pa_tlb_lock
);
45 EXPORT_SYMBOL(pa_tlb_lock
);
48 struct pdc_cache_info cache_info __read_mostly
;
50 static struct pdc_btlb_info btlb_info __read_mostly
;
55 flush_data_cache(void)
57 on_each_cpu(flush_data_cache_local
, NULL
, 1, 1);
60 flush_instruction_cache(void)
62 on_each_cpu(flush_instruction_cache_local
, NULL
, 1, 1);
67 flush_cache_all_local(void)
69 flush_instruction_cache_local(NULL
);
70 flush_data_cache_local(NULL
);
72 EXPORT_SYMBOL(flush_cache_all_local
);
74 /* flushes EVERYTHING (tlb & cache) */
77 flush_all_caches(void)
82 EXPORT_SYMBOL(flush_all_caches
);
85 update_mmu_cache(struct vm_area_struct
*vma
, unsigned long address
, pte_t pte
)
87 struct page
*page
= pte_page(pte
);
89 if (pfn_valid(page_to_pfn(page
)) && page_mapping(page
) &&
90 test_bit(PG_dcache_dirty
, &page
->flags
)) {
92 flush_kernel_dcache_page(page
);
93 clear_bit(PG_dcache_dirty
, &page
->flags
);
98 show_cache_info(struct seq_file
*m
)
102 seq_printf(m
, "I-cache\t\t: %ld KB\n",
103 cache_info
.ic_size
/1024 );
104 if (cache_info
.dc_loop
== 1)
105 snprintf(buf
, 32, "%lu-way associative", cache_info
.dc_loop
);
106 seq_printf(m
, "D-cache\t\t: %ld KB (%s%s, %s)\n",
107 cache_info
.dc_size
/1024,
108 (cache_info
.dc_conf
.cc_wt
? "WT":"WB"),
109 (cache_info
.dc_conf
.cc_sh
? ", shared I/D":""),
110 ((cache_info
.dc_loop
== 1) ? "direct mapped" : buf
));
111 seq_printf(m
, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
114 cache_info
.dt_conf
.tc_sh
? " - shared with ITLB":""
118 /* BTLB - Block TLB */
119 if (btlb_info
.max_size
==0) {
120 seq_printf(m
, "BTLB\t\t: not supported\n" );
123 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
124 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
125 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
126 btlb_info
.max_size
, (int)4096,
127 btlb_info
.max_size
>>8,
128 btlb_info
.fixed_range_info
.num_i
,
129 btlb_info
.fixed_range_info
.num_d
,
130 btlb_info
.fixed_range_info
.num_comb
,
131 btlb_info
.variable_range_info
.num_i
,
132 btlb_info
.variable_range_info
.num_d
,
133 btlb_info
.variable_range_info
.num_comb
140 parisc_cache_init(void)
142 if (pdc_cache_info(&cache_info
) < 0)
143 panic("parisc_cache_init: pdc_cache_info failed");
146 printk("ic_size %lx dc_size %lx it_size %lx\n",
151 printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
153 cache_info
.dc_stride
,
157 printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
158 *(unsigned long *) (&cache_info
.dc_conf
),
159 cache_info
.dc_conf
.cc_alias
,
160 cache_info
.dc_conf
.cc_block
,
161 cache_info
.dc_conf
.cc_line
,
162 cache_info
.dc_conf
.cc_shift
);
163 printk(" wt %d sh %d cst %d hv %d\n",
164 cache_info
.dc_conf
.cc_wt
,
165 cache_info
.dc_conf
.cc_sh
,
166 cache_info
.dc_conf
.cc_cst
,
167 cache_info
.dc_conf
.cc_hv
);
169 printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
171 cache_info
.ic_stride
,
175 printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
176 *(unsigned long *) (&cache_info
.ic_conf
),
177 cache_info
.ic_conf
.cc_alias
,
178 cache_info
.ic_conf
.cc_block
,
179 cache_info
.ic_conf
.cc_line
,
180 cache_info
.ic_conf
.cc_shift
);
181 printk(" wt %d sh %d cst %d hv %d\n",
182 cache_info
.ic_conf
.cc_wt
,
183 cache_info
.ic_conf
.cc_sh
,
184 cache_info
.ic_conf
.cc_cst
,
185 cache_info
.ic_conf
.cc_hv
);
187 printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
188 cache_info
.dt_conf
.tc_sh
,
189 cache_info
.dt_conf
.tc_page
,
190 cache_info
.dt_conf
.tc_cst
,
191 cache_info
.dt_conf
.tc_aid
,
192 cache_info
.dt_conf
.tc_pad1
);
194 printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
195 cache_info
.it_conf
.tc_sh
,
196 cache_info
.it_conf
.tc_page
,
197 cache_info
.it_conf
.tc_cst
,
198 cache_info
.it_conf
.tc_aid
,
199 cache_info
.it_conf
.tc_pad1
);
203 if (cache_info
.dt_conf
.tc_sh
== 0 || cache_info
.dt_conf
.tc_sh
== 2) {
204 if (cache_info
.dt_conf
.tc_sh
== 2)
205 printk(KERN_WARNING
"Unexpected TLB configuration. "
206 "Will flush I/D separately (could be optimized).\n");
211 /* "New and Improved" version from Jim Hull
212 * (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
213 * The following CAFL_STRIDE is an optimized version, see
214 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
215 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
217 #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
218 dcache_stride
= CAFL_STRIDE(cache_info
.dc_conf
);
219 icache_stride
= CAFL_STRIDE(cache_info
.ic_conf
);
223 if (pdc_btlb_info(&btlb_info
) < 0) {
224 memset(&btlb_info
, 0, sizeof btlb_info
);
228 if ((boot_cpu_data
.pdc
.capabilities
& PDC_MODEL_NVA_MASK
) ==
229 PDC_MODEL_NVA_UNSUPPORTED
) {
230 printk(KERN_WARNING
"parisc_cache_init: Only equivalent aliasing supported!\n");
232 panic("SMP kernel required to avoid non-equivalent aliasing");
237 void disable_sr_hashing(void)
241 switch (boot_cpu_data
.cpu_type
) {
242 case pcx
: /* We shouldn't get this far. setup.c should prevent it. */
249 srhash_type
= SRHASH_PCXST
;
253 srhash_type
= SRHASH_PCXL
;
256 case pcxl2
: /* pcxl2 doesn't support space register hashing */
259 default: /* Currently all PA2.0 machines use the same ins. sequence */
260 srhash_type
= SRHASH_PA20
;
264 disable_sr_hashing_asm(srhash_type
);
267 void flush_dcache_page(struct page
*page
)
269 struct address_space
*mapping
= page_mapping(page
);
270 struct vm_area_struct
*mpnt
;
271 struct prio_tree_iter iter
;
272 unsigned long offset
;
275 unsigned long pfn
= page_to_pfn(page
);
278 if (mapping
&& !mapping_mapped(mapping
)) {
279 set_bit(PG_dcache_dirty
, &page
->flags
);
283 flush_kernel_dcache_page(page
);
288 pgoff
= page
->index
<< (PAGE_CACHE_SHIFT
- PAGE_SHIFT
);
290 /* We have carefully arranged in arch_get_unmapped_area() that
291 * *any* mappings of a file are always congruently mapped (whether
292 * declared as MAP_PRIVATE or MAP_SHARED), so we only need
293 * to flush one address here for them all to become coherent */
295 flush_dcache_mmap_lock(mapping
);
296 vma_prio_tree_foreach(mpnt
, &iter
, &mapping
->i_mmap
, pgoff
, pgoff
) {
297 offset
= (pgoff
- mpnt
->vm_pgoff
) << PAGE_SHIFT
;
298 addr
= mpnt
->vm_start
+ offset
;
300 /* Flush instructions produce non access tlb misses.
301 * On PA, we nullify these instructions rather than
302 * taking a page fault if the pte doesn't exist.
303 * This is just for speed. If the page translation
304 * isn't there, there's no point exciting the
305 * nadtlb handler into a nullification frenzy.
307 * Make sure we really have this page: the private
308 * mappings may cover this area but have COW'd this
311 if (translation_exists(mpnt
, addr
, pfn
)) {
312 __flush_cache_page(mpnt
, addr
);
316 flush_dcache_mmap_unlock(mapping
);
318 EXPORT_SYMBOL(flush_dcache_page
);
320 /* Defined in arch/parisc/kernel/pacache.S */
321 EXPORT_SYMBOL(flush_kernel_dcache_range_asm
);
322 EXPORT_SYMBOL(flush_kernel_dcache_page_asm
);
323 EXPORT_SYMBOL(flush_data_cache_local
);
324 EXPORT_SYMBOL(flush_kernel_icache_range_asm
);
326 void clear_user_page_asm(void *page
, unsigned long vaddr
)
328 /* This function is implemented in assembly in pacache.S */
329 extern void __clear_user_page_asm(void *page
, unsigned long vaddr
);
332 __clear_user_page_asm(page
, vaddr
);
336 #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
337 int parisc_cache_flush_threshold __read_mostly
= FLUSH_THRESHOLD
;
339 void parisc_setup_cache_timing(void)
341 unsigned long rangetime
, alltime
;
346 alltime
= mfctl(16) - alltime
;
348 size
= (unsigned long)(_end
- _text
);
349 rangetime
= mfctl(16);
350 flush_kernel_dcache_range((unsigned long)_text
, size
);
351 rangetime
= mfctl(16) - rangetime
;
353 printk(KERN_DEBUG
"Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
354 alltime
, size
, rangetime
);
356 /* Racy, but if we see an intermediate value, it's ok too... */
357 parisc_cache_flush_threshold
= size
* alltime
/ rangetime
;
359 parisc_cache_flush_threshold
= (parisc_cache_flush_threshold
+ L1_CACHE_BYTES
- 1) &~ (L1_CACHE_BYTES
- 1);
360 if (!parisc_cache_flush_threshold
)
361 parisc_cache_flush_threshold
= FLUSH_THRESHOLD
;
363 printk(KERN_INFO
"Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold
, num_online_cpus());