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[mirror_ubuntu-artful-kernel.git] / arch / powerpc / boot / dts / mpc8548cds.dts
1 /*
2 * MPC8548 CDS Device Tree Source
3 *
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12 /dts-v1/;
13
14 / {
15 model = "MPC8548CDS";
16 compatible = "MPC8548CDS", "MPC85xxCDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 /*
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26 */
27 serial0 = &serial0;
28 serial1 = &serial1;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 pci2 = &pci2;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 PowerPC,8548@0 {
39 device_type = "cpu";
40 reg = <0x0>;
41 d-cache-line-size = <32>; // 32 bytes
42 i-cache-line-size = <32>; // 32 bytes
43 d-cache-size = <0x8000>; // L1, 32K
44 i-cache-size = <0x8000>; // L1, 32K
45 timebase-frequency = <0>; // 33 MHz, from uboot
46 bus-frequency = <0>; // 166 MHz
47 clock-frequency = <0>; // 825 MHz, from uboot
48 next-level-cache = <&L2>;
49 };
50 };
51
52 memory {
53 device_type = "memory";
54 reg = <0x0 0x8000000>; // 128M at 0x0
55 };
56
57 soc8548@e0000000 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 device_type = "soc";
61 ranges = <0x0 0xe0000000 0x100000>;
62 reg = <0xe0000000 0x1000>; // CCSRBAR
63 bus-frequency = <0>;
64
65 memory-controller@2000 {
66 compatible = "fsl,8548-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
69 interrupts = <18 2>;
70 };
71
72 L2: l2-cache-controller@20000 {
73 compatible = "fsl,8548-l2-cache-controller";
74 reg = <0x20000 0x1000>;
75 cache-line-size = <32>; // 32 bytes
76 cache-size = <0x80000>; // L2, 512K
77 interrupt-parent = <&mpic>;
78 interrupts = <16 2>;
79 };
80
81 i2c@3000 {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 cell-index = <0>;
85 compatible = "fsl-i2c";
86 reg = <0x3000 0x100>;
87 interrupts = <43 2>;
88 interrupt-parent = <&mpic>;
89 dfsrr;
90 };
91
92 i2c@3100 {
93 #address-cells = <1>;
94 #size-cells = <0>;
95 cell-index = <1>;
96 compatible = "fsl-i2c";
97 reg = <0x3100 0x100>;
98 interrupts = <43 2>;
99 interrupt-parent = <&mpic>;
100 dfsrr;
101 };
102
103 dma@21300 {
104 #address-cells = <1>;
105 #size-cells = <1>;
106 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
107 reg = <0x21300 0x4>;
108 ranges = <0x0 0x21100 0x200>;
109 cell-index = <0>;
110 dma-channel@0 {
111 compatible = "fsl,mpc8548-dma-channel",
112 "fsl,eloplus-dma-channel";
113 reg = <0x0 0x80>;
114 cell-index = <0>;
115 interrupt-parent = <&mpic>;
116 interrupts = <20 2>;
117 };
118 dma-channel@80 {
119 compatible = "fsl,mpc8548-dma-channel",
120 "fsl,eloplus-dma-channel";
121 reg = <0x80 0x80>;
122 cell-index = <1>;
123 interrupt-parent = <&mpic>;
124 interrupts = <21 2>;
125 };
126 dma-channel@100 {
127 compatible = "fsl,mpc8548-dma-channel",
128 "fsl,eloplus-dma-channel";
129 reg = <0x100 0x80>;
130 cell-index = <2>;
131 interrupt-parent = <&mpic>;
132 interrupts = <22 2>;
133 };
134 dma-channel@180 {
135 compatible = "fsl,mpc8548-dma-channel",
136 "fsl,eloplus-dma-channel";
137 reg = <0x180 0x80>;
138 cell-index = <3>;
139 interrupt-parent = <&mpic>;
140 interrupts = <23 2>;
141 };
142 };
143
144 mdio@24520 {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 compatible = "fsl,gianfar-mdio";
148 reg = <0x24520 0x20>;
149
150 phy0: ethernet-phy@0 {
151 interrupt-parent = <&mpic>;
152 interrupts = <5 1>;
153 reg = <0x0>;
154 device_type = "ethernet-phy";
155 };
156 phy1: ethernet-phy@1 {
157 interrupt-parent = <&mpic>;
158 interrupts = <5 1>;
159 reg = <0x1>;
160 device_type = "ethernet-phy";
161 };
162 phy2: ethernet-phy@2 {
163 interrupt-parent = <&mpic>;
164 interrupts = <5 1>;
165 reg = <0x2>;
166 device_type = "ethernet-phy";
167 };
168 phy3: ethernet-phy@3 {
169 interrupt-parent = <&mpic>;
170 interrupts = <5 1>;
171 reg = <0x3>;
172 device_type = "ethernet-phy";
173 };
174 };
175
176 enet0: ethernet@24000 {
177 cell-index = <0>;
178 device_type = "network";
179 model = "eTSEC";
180 compatible = "gianfar";
181 reg = <0x24000 0x1000>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <29 2 30 2 34 2>;
184 interrupt-parent = <&mpic>;
185 phy-handle = <&phy0>;
186 };
187
188 enet1: ethernet@25000 {
189 cell-index = <1>;
190 device_type = "network";
191 model = "eTSEC";
192 compatible = "gianfar";
193 reg = <0x25000 0x1000>;
194 local-mac-address = [ 00 00 00 00 00 00 ];
195 interrupts = <35 2 36 2 40 2>;
196 interrupt-parent = <&mpic>;
197 phy-handle = <&phy1>;
198 };
199
200 /* eTSEC 3/4 are currently broken
201 enet2: ethernet@26000 {
202 cell-index = <2>;
203 device_type = "network";
204 model = "eTSEC";
205 compatible = "gianfar";
206 reg = <0x26000 0x1000>;
207 local-mac-address = [ 00 00 00 00 00 00 ];
208 interrupts = <31 2 32 2 33 2>;
209 interrupt-parent = <&mpic>;
210 phy-handle = <&phy2>;
211 };
212
213 enet3: ethernet@27000 {
214 cell-index = <3>;
215 device_type = "network";
216 model = "eTSEC";
217 compatible = "gianfar";
218 reg = <0x27000 0x1000>;
219 local-mac-address = [ 00 00 00 00 00 00 ];
220 interrupts = <37 2 38 2 39 2>;
221 interrupt-parent = <&mpic>;
222 phy-handle = <&phy3>;
223 };
224 */
225
226 serial0: serial@4500 {
227 cell-index = <0>;
228 device_type = "serial";
229 compatible = "ns16550";
230 reg = <0x4500 0x100>; // reg base, size
231 clock-frequency = <0>; // should we fill in in uboot?
232 interrupts = <42 2>;
233 interrupt-parent = <&mpic>;
234 };
235
236 serial1: serial@4600 {
237 cell-index = <1>;
238 device_type = "serial";
239 compatible = "ns16550";
240 reg = <0x4600 0x100>; // reg base, size
241 clock-frequency = <0>; // should we fill in in uboot?
242 interrupts = <42 2>;
243 interrupt-parent = <&mpic>;
244 };
245
246 global-utilities@e0000 { //global utilities reg
247 compatible = "fsl,mpc8548-guts";
248 reg = <0xe0000 0x1000>;
249 fsl,has-rstcr;
250 };
251
252 crypto@30000 {
253 compatible = "fsl,sec2.1", "fsl,sec2.0";
254 reg = <0x30000 0x10000>;
255 interrupts = <45 2>;
256 interrupt-parent = <&mpic>;
257 fsl,num-channels = <4>;
258 fsl,channel-fifo-len = <24>;
259 fsl,exec-units-mask = <0xfe>;
260 fsl,descriptor-types-mask = <0x12b0ebf>;
261 };
262
263 mpic: pic@40000 {
264 interrupt-controller;
265 #address-cells = <0>;
266 #interrupt-cells = <2>;
267 reg = <0x40000 0x40000>;
268 compatible = "chrp,open-pic";
269 device_type = "open-pic";
270 };
271 };
272
273 pci0: pci@e0008000 {
274 cell-index = <0>;
275 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
276 interrupt-map = <
277 /* IDSEL 0x4 (PCIX Slot 2) */
278 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
279 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
280 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
281 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
282
283 /* IDSEL 0x5 (PCIX Slot 3) */
284 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
285 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
286 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
287 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
288
289 /* IDSEL 0x6 (PCIX Slot 4) */
290 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
291 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
292 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
293 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
294
295 /* IDSEL 0x8 (PCIX Slot 5) */
296 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
297 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
298 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
299 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
300
301 /* IDSEL 0xC (Tsi310 bridge) */
302 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
303 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
304 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
305 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
306
307 /* IDSEL 0x14 (Slot 2) */
308 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
309 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
310 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
311 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
312
313 /* IDSEL 0x15 (Slot 3) */
314 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
315 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
316 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
317 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
318
319 /* IDSEL 0x16 (Slot 4) */
320 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
321 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
322 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
323 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
324
325 /* IDSEL 0x18 (Slot 5) */
326 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
327 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
328 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
329 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
330
331 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
332 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
333 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
334 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
335 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
336
337 interrupt-parent = <&mpic>;
338 interrupts = <24 2>;
339 bus-range = <0 0>;
340 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
341 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
342 clock-frequency = <66666666>;
343 #interrupt-cells = <1>;
344 #size-cells = <2>;
345 #address-cells = <3>;
346 reg = <0xe0008000 0x1000>;
347 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
348 device_type = "pci";
349
350 pci_bridge@1c {
351 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
352 interrupt-map = <
353
354 /* IDSEL 0x00 (PrPMC Site) */
355 0000 0x0 0x0 0x1 &mpic 0x0 0x1
356 0000 0x0 0x0 0x2 &mpic 0x1 0x1
357 0000 0x0 0x0 0x3 &mpic 0x2 0x1
358 0000 0x0 0x0 0x4 &mpic 0x3 0x1
359
360 /* IDSEL 0x04 (VIA chip) */
361 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
362 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
363 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
364 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
365
366 /* IDSEL 0x05 (8139) */
367 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
368
369 /* IDSEL 0x06 (Slot 6) */
370 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
371 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
372 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
373 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
374
375 /* IDESL 0x07 (Slot 7) */
376 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
377 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
378 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
379 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
380
381 reg = <0xe000 0x0 0x0 0x0 0x0>;
382 #interrupt-cells = <1>;
383 #size-cells = <2>;
384 #address-cells = <3>;
385 ranges = <0x2000000 0x0 0x80000000
386 0x2000000 0x0 0x80000000
387 0x0 0x20000000
388 0x1000000 0x0 0x0
389 0x1000000 0x0 0x0
390 0x0 0x80000>;
391 clock-frequency = <33333333>;
392
393 isa@4 {
394 device_type = "isa";
395 #interrupt-cells = <2>;
396 #size-cells = <1>;
397 #address-cells = <2>;
398 reg = <0x2000 0x0 0x0 0x0 0x0>;
399 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
400 interrupt-parent = <&i8259>;
401
402 i8259: interrupt-controller@20 {
403 interrupt-controller;
404 device_type = "interrupt-controller";
405 reg = <0x1 0x20 0x2
406 0x1 0xa0 0x2
407 0x1 0x4d0 0x2>;
408 #address-cells = <0>;
409 #interrupt-cells = <2>;
410 compatible = "chrp,iic";
411 interrupts = <0 1>;
412 interrupt-parent = <&mpic>;
413 };
414
415 rtc@70 {
416 compatible = "pnpPNP,b00";
417 reg = <0x1 0x70 0x2>;
418 };
419 };
420 };
421 };
422
423 pci1: pci@e0009000 {
424 cell-index = <1>;
425 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
426 interrupt-map = <
427
428 /* IDSEL 0x15 */
429 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
430 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
431 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
432 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
433
434 interrupt-parent = <&mpic>;
435 interrupts = <25 2>;
436 bus-range = <0 0>;
437 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
438 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
439 clock-frequency = <66666666>;
440 #interrupt-cells = <1>;
441 #size-cells = <2>;
442 #address-cells = <3>;
443 reg = <0xe0009000 0x1000>;
444 compatible = "fsl,mpc8540-pci";
445 device_type = "pci";
446 };
447
448 pci2: pcie@e000a000 {
449 cell-index = <2>;
450 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
451 interrupt-map = <
452
453 /* IDSEL 0x0 (PEX) */
454 00000 0x0 0x0 0x1 &mpic 0x0 0x1
455 00000 0x0 0x0 0x2 &mpic 0x1 0x1
456 00000 0x0 0x0 0x3 &mpic 0x2 0x1
457 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
458
459 interrupt-parent = <&mpic>;
460 interrupts = <26 2>;
461 bus-range = <0 255>;
462 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
463 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
464 clock-frequency = <33333333>;
465 #interrupt-cells = <1>;
466 #size-cells = <2>;
467 #address-cells = <3>;
468 reg = <0xe000a000 0x1000>;
469 compatible = "fsl,mpc8548-pcie";
470 device_type = "pci";
471 pcie@0 {
472 reg = <0x0 0x0 0x0 0x0 0x0>;
473 #size-cells = <2>;
474 #address-cells = <3>;
475 device_type = "pci";
476 ranges = <0x2000000 0x0 0xa0000000
477 0x2000000 0x0 0xa0000000
478 0x0 0x20000000
479
480 0x1000000 0x0 0x0
481 0x1000000 0x0 0x0
482 0x0 0x100000>;
483 };
484 };
485 };
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