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1 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
2 #define _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
4 * PowerPC64 memory management structures
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 #include <asm/asm-compat.h>
20 * This is necessary to get the definition of PGTABLE_RANGE which we
21 * need for various slices related matters. Note that this isn't the
22 * complete pgtable.h but only a portion of it.
24 #include <asm/book3s/64/pgtable.h>
26 #include <asm/processor.h>
32 #define SLB_NUM_BOLTED 3
33 #define SLB_CACHE_ENTRIES 8
34 #define SLB_MIN_SIZE 32
36 /* Bits in the SLB ESID word */
37 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
39 /* Bits in the SLB VSID word */
40 #define SLB_VSID_SHIFT 12
41 #define SLB_VSID_SHIFT_1T 24
42 #define SLB_VSID_SSIZE_SHIFT 62
43 #define SLB_VSID_B ASM_CONST(0xc000000000000000)
44 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
45 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
46 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
47 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
48 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
49 #define SLB_VSID_L ASM_CONST(0x0000000000000100)
50 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
51 #define SLB_VSID_LP ASM_CONST(0x0000000000000030)
52 #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
53 #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
54 #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
55 #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
56 #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
58 #define SLB_VSID_KERNEL (SLB_VSID_KP)
59 #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
61 #define SLBIE_C (0x08000000)
62 #define SLBIE_SSIZE_SHIFT 25
68 #define HPTES_PER_GROUP 8
70 #define HPTE_V_SSIZE_SHIFT 62
71 #define HPTE_V_AVPN_SHIFT 7
72 #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
73 #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
74 #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
75 #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
76 #define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
77 #define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
78 #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
79 #define HPTE_V_VALID ASM_CONST(0x0000000000000001)
82 * ISA 3.0 have a different HPTE format.
84 #define HPTE_R_3_0_SSIZE_SHIFT 58
85 #define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
86 #define HPTE_R_TS ASM_CONST(0x4000000000000000)
87 #define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
88 #define HPTE_R_RPN_SHIFT 12
89 #define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
90 #define HPTE_R_PP ASM_CONST(0x0000000000000003)
91 #define HPTE_R_PPP ASM_CONST(0x8000000000000003)
92 #define HPTE_R_N ASM_CONST(0x0000000000000004)
93 #define HPTE_R_G ASM_CONST(0x0000000000000008)
94 #define HPTE_R_M ASM_CONST(0x0000000000000010)
95 #define HPTE_R_I ASM_CONST(0x0000000000000020)
96 #define HPTE_R_W ASM_CONST(0x0000000000000040)
97 #define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
98 #define HPTE_R_C ASM_CONST(0x0000000000000080)
99 #define HPTE_R_R ASM_CONST(0x0000000000000100)
100 #define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
102 #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
103 #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
105 /* Values for PP (assumes Ks=0, Kp=1) */
106 #define PP_RWXX 0 /* Supervisor read/write, User none */
107 #define PP_RWRX 1 /* Supervisor read/write, User read */
108 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
109 #define PP_RXRX 3 /* Supervisor read, User read */
110 #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
112 /* Fields for tlbiel instruction in architecture 2.06 */
113 #define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */
114 #define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */
115 #define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */
116 #define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */
117 #define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */
118 #define TLBIEL_INVAL_SET_SHIFT 12
120 #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
121 #define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */
122 #define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */
123 #define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */
132 extern struct hash_pte
*htab_address
;
133 extern unsigned long htab_size_bytes
;
134 extern unsigned long htab_hash_mask
;
137 static inline int shift_to_mmu_psize(unsigned int shift
)
141 for (psize
= 0; psize
< MMU_PAGE_COUNT
; ++psize
)
142 if (mmu_psize_defs
[psize
].shift
== shift
)
147 static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize
)
149 if (mmu_psize_defs
[mmu_psize
].shift
)
150 return mmu_psize_defs
[mmu_psize
].shift
;
154 #endif /* __ASSEMBLY__ */
158 * These are the values used by hardware in the B field of
159 * SLB entries and the first dword of MMU hashtable entries.
160 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
162 #define MMU_SEGSIZE_256M 0
163 #define MMU_SEGSIZE_1T 1
166 * encode page number shift.
167 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
168 * 12 bits. This enable us to address upto 76 bit va.
169 * For hpt hash from a va we can ignore the page size bits of va and for
170 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
171 * we work in all cases including 4k page size.
176 * HPTE Large Page (LP) details
180 #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT)
184 static inline int slb_vsid_shift(int ssize
)
186 if (ssize
== MMU_SEGSIZE_256M
)
187 return SLB_VSID_SHIFT
;
188 return SLB_VSID_SHIFT_1T
;
191 static inline int segment_shift(int ssize
)
193 if (ssize
== MMU_SEGSIZE_256M
)
199 * The current system page and segment sizes
201 extern int mmu_kernel_ssize
;
202 extern int mmu_highuser_ssize
;
203 extern u16 mmu_slb_size
;
204 extern unsigned long tce_alloc_start
, tce_alloc_end
;
207 * If the processor supports 64k normal pages but not 64k cache
208 * inhibited pages, we have to be prepared to switch processes
209 * to use 4k pages when they create cache-inhibited mappings.
210 * If this is the case, mmu_ci_restrictions will be set to 1.
212 extern int mmu_ci_restrictions
;
215 * This computes the AVPN and B fields of the first dword of a HPTE,
216 * for use when we want to match an existing PTE. The bottom 7 bits
217 * of the returned value are zero.
219 static inline unsigned long hpte_encode_avpn(unsigned long vpn
, int psize
,
224 * The AVA field omits the low-order 23 bits of the 78 bits VA.
225 * These bits are not needed in the PTE, because the
226 * low-order b of these bits are part of the byte offset
227 * into the virtual page and, if b < 23, the high-order
228 * 23-b of these bits are always used in selecting the
229 * PTEGs to be searched
231 v
= (vpn
>> (23 - VPN_SHIFT
)) & ~(mmu_psize_defs
[psize
].avpnm
);
232 v
<<= HPTE_V_AVPN_SHIFT
;
233 if (!cpu_has_feature(CPU_FTR_ARCH_300
))
234 v
|= ((unsigned long) ssize
) << HPTE_V_SSIZE_SHIFT
;
239 * This function sets the AVPN and L fields of the HPTE appropriately
240 * using the base page size and actual page size.
242 static inline unsigned long hpte_encode_v(unsigned long vpn
, int base_psize
,
243 int actual_psize
, int ssize
)
246 v
= hpte_encode_avpn(vpn
, base_psize
, ssize
);
247 if (actual_psize
!= MMU_PAGE_4K
)
253 * This function sets the ARPN, and LP fields of the HPTE appropriately
254 * for the page size. We assume the pa is already "clean" that is properly
255 * aligned for the requested page size
257 static inline unsigned long hpte_encode_r(unsigned long pa
, int base_psize
,
258 int actual_psize
, int ssize
)
261 if (cpu_has_feature(CPU_FTR_ARCH_300
))
262 pa
|= ((unsigned long) ssize
) << HPTE_R_3_0_SSIZE_SHIFT
;
264 /* A 4K page needs no special encoding */
265 if (actual_psize
== MMU_PAGE_4K
)
266 return pa
& HPTE_R_RPN
;
268 unsigned int penc
= mmu_psize_defs
[base_psize
].penc
[actual_psize
];
269 unsigned int shift
= mmu_psize_defs
[actual_psize
].shift
;
270 return (pa
& ~((1ul << shift
) - 1)) | (penc
<< LP_SHIFT
);
275 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
277 static inline unsigned long hpt_vpn(unsigned long ea
,
278 unsigned long vsid
, int ssize
)
281 int s_shift
= segment_shift(ssize
);
283 mask
= (1ul << (s_shift
- VPN_SHIFT
)) - 1;
284 return (vsid
<< (s_shift
- VPN_SHIFT
)) | ((ea
>> VPN_SHIFT
) & mask
);
288 * This hashes a virtual address
290 static inline unsigned long hpt_hash(unsigned long vpn
,
291 unsigned int shift
, int ssize
)
294 unsigned long hash
, vsid
;
296 /* VPN_SHIFT can be atmost 12 */
297 if (ssize
== MMU_SEGSIZE_256M
) {
298 mask
= (1ul << (SID_SHIFT
- VPN_SHIFT
)) - 1;
299 hash
= (vpn
>> (SID_SHIFT
- VPN_SHIFT
)) ^
300 ((vpn
& mask
) >> (shift
- VPN_SHIFT
));
302 mask
= (1ul << (SID_SHIFT_1T
- VPN_SHIFT
)) - 1;
303 vsid
= vpn
>> (SID_SHIFT_1T
- VPN_SHIFT
);
304 hash
= vsid
^ (vsid
<< 25) ^
305 ((vpn
& mask
) >> (shift
- VPN_SHIFT
)) ;
307 return hash
& 0x7fffffffffUL
;
310 #define HPTE_LOCAL_UPDATE 0x1
311 #define HPTE_NOHPTE_UPDATE 0x2
313 extern int __hash_page_4K(unsigned long ea
, unsigned long access
,
314 unsigned long vsid
, pte_t
*ptep
, unsigned long trap
,
315 unsigned long flags
, int ssize
, int subpage_prot
);
316 extern int __hash_page_64K(unsigned long ea
, unsigned long access
,
317 unsigned long vsid
, pte_t
*ptep
, unsigned long trap
,
318 unsigned long flags
, int ssize
);
320 unsigned int hash_page_do_lazy_icache(unsigned int pp
, pte_t pte
, int trap
);
321 extern int hash_page_mm(struct mm_struct
*mm
, unsigned long ea
,
322 unsigned long access
, unsigned long trap
,
323 unsigned long flags
);
324 extern int hash_page(unsigned long ea
, unsigned long access
, unsigned long trap
,
325 unsigned long dsisr
);
326 int __hash_page_huge(unsigned long ea
, unsigned long access
, unsigned long vsid
,
327 pte_t
*ptep
, unsigned long trap
, unsigned long flags
,
328 int ssize
, unsigned int shift
, unsigned int mmu_psize
);
329 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
330 extern int __hash_page_thp(unsigned long ea
, unsigned long access
,
331 unsigned long vsid
, pmd_t
*pmdp
, unsigned long trap
,
332 unsigned long flags
, int ssize
, unsigned int psize
);
334 static inline int __hash_page_thp(unsigned long ea
, unsigned long access
,
335 unsigned long vsid
, pmd_t
*pmdp
,
336 unsigned long trap
, unsigned long flags
,
337 int ssize
, unsigned int psize
)
343 extern void hash_failure_debug(unsigned long ea
, unsigned long access
,
344 unsigned long vsid
, unsigned long trap
,
345 int ssize
, int psize
, int lpsize
,
347 extern int htab_bolt_mapping(unsigned long vstart
, unsigned long vend
,
348 unsigned long pstart
, unsigned long prot
,
349 int psize
, int ssize
);
350 int htab_remove_mapping(unsigned long vstart
, unsigned long vend
,
351 int psize
, int ssize
);
352 extern void add_gpage(u64 addr
, u64 page_size
, unsigned long number_of_pages
);
353 extern void demote_segment_4k(struct mm_struct
*mm
, unsigned long addr
);
355 extern void hpte_init_native(void);
356 extern void hpte_init_lpar(void);
357 extern void hpte_init_beat(void);
358 extern void hpte_init_beat_v3(void);
360 extern void slb_initialize(void);
361 extern void slb_flush_and_rebolt(void);
363 extern void slb_vmalloc_update(void);
364 extern void slb_set_size(u16 size
);
365 #endif /* __ASSEMBLY__ */
368 * VSID allocation (256MB segment)
370 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
371 * from mmu context id and effective segment id of the address.
373 * For user processes max context id is limited to ((1ul << 19) - 5)
374 * for kernel space, we use the top 4 context ids to map address as below
375 * NOTE: each context only support 64TB now.
376 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
377 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
378 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
379 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
381 * The proto-VSIDs are then scrambled into real VSIDs with the
382 * multiplicative hash:
384 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
386 * VSID_MULTIPLIER is prime, so in particular it is
387 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
388 * Because the modulus is 2^n-1 we can compute it efficiently without
389 * a divide or extra multiply (see below). The scramble function gives
390 * robust scattering in the hash table (at least based on some initial
393 * We also consider VSID 0 special. We use VSID 0 for slb entries mapping
394 * bad address. This enables us to consolidate bad address handling in
397 * We also need to avoid the last segment of the last context, because that
398 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
399 * because of the modulo operation in vsid scramble. But the vmemmap
400 * (which is what uses region 0xf) will never be close to 64TB in size
401 * (it's 56 bytes per page of system memory).
404 #define CONTEXT_BITS 19
406 #define ESID_BITS_1T 6
410 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
411 * available for user + kernel mapping. The top 4 contexts are used for
412 * kernel mapping. Each segment contains 2^28 bytes. Each
413 * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
414 * (19 == 37 + 28 - 46).
416 #define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 5)
419 * This should be computed such that protovosid * vsid_mulitplier
420 * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
422 #define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
423 #define VSID_BITS_256M (CONTEXT_BITS + ESID_BITS)
424 #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
426 #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
427 #define VSID_BITS_1T (CONTEXT_BITS + ESID_BITS_1T)
428 #define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
431 #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
434 * This macro generates asm code to compute the VSID scramble
435 * function. Used in slb_allocate() and do_stab_bolted. The function
436 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
438 * rt = register continaing the proto-VSID and into which the
439 * VSID will be stored
440 * rx = scratch register (clobbered)
442 * - rt and rx must be different registers
443 * - The answer will end up in the low VSID_BITS bits of rt. The higher
444 * bits may contain other garbage, so you may need to mask the
447 #define ASM_VSID_SCRAMBLE(rt, rx, size) \
448 lis rx,VSID_MULTIPLIER_##size@h; \
449 ori rx,rx,VSID_MULTIPLIER_##size@l; \
450 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
452 srdi rx,rt,VSID_BITS_##size; \
453 clrldi rt,rt,(64-VSID_BITS_##size); \
454 add rt,rt,rx; /* add high and low bits */ \
455 /* NOTE: explanation based on VSID_BITS_##size = 36 \
456 * Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
457 * 2^36-1+2^28-1. That in particular means that if r3 >= \
458 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
459 * the bit clear, r3 already has the answer we want, if it \
460 * doesn't, the answer is the low 36 bits of r3+1. So in all \
461 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
463 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
466 /* 4 bits per slice and we have one slice per 1TB */
467 #define SLICE_ARRAY_SIZE (H_PGTABLE_RANGE >> 41)
471 #ifdef CONFIG_PPC_SUBPAGE_PROT
473 * For the sub-page protection option, we extend the PGD with one of
474 * these. Basically we have a 3-level tree, with the top level being
475 * the protptrs array. To optimize speed and memory consumption when
476 * only addresses < 4GB are being protected, pointers to the first
477 * four pages of sub-page protection words are stored in the low_prot
479 * Each page of sub-page protection words protects 1GB (4 bytes
480 * protects 64k). For the 3-level tree, each page of pointers then
483 struct subpage_prot_table
{
484 unsigned long maxaddr
; /* only addresses < this are protected */
485 unsigned int **protptrs
[(TASK_SIZE_USER64
>> 43)];
486 unsigned int *low_prot
[4];
489 #define SBP_L1_BITS (PAGE_SHIFT - 2)
490 #define SBP_L2_BITS (PAGE_SHIFT - 3)
491 #define SBP_L1_COUNT (1 << SBP_L1_BITS)
492 #define SBP_L2_COUNT (1 << SBP_L2_BITS)
493 #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
494 #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
496 extern void subpage_prot_free(struct mm_struct
*mm
);
497 extern void subpage_prot_init_new_context(struct mm_struct
*mm
);
499 static inline void subpage_prot_free(struct mm_struct
*mm
) {}
500 static inline void subpage_prot_init_new_context(struct mm_struct
*mm
) { }
501 #endif /* CONFIG_PPC_SUBPAGE_PROT */
505 * The code below is equivalent to this function for arguments
506 * < 2^VSID_BITS, which is all this should ever be called
507 * with. However gcc is not clever enough to compute the
508 * modulus (2^n-1) without a second multiply.
510 #define vsid_scramble(protovsid, size) \
511 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
514 #define vsid_scramble(protovsid, size) \
517 x = (protovsid) * VSID_MULTIPLIER_##size; \
518 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
519 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
523 /* Returns the segment size indicator for a user address */
524 static inline int user_segment_size(unsigned long addr
)
526 /* Use 1T segments if possible for addresses >= 1T */
527 if (addr
>= (1UL << SID_SHIFT_1T
))
528 return mmu_highuser_ssize
;
529 return MMU_SEGSIZE_256M
;
532 static inline unsigned long get_vsid(unsigned long context
, unsigned long ea
,
536 * Bad address. We return VSID 0 for that
538 if ((ea
& ~REGION_MASK
) >= H_PGTABLE_RANGE
)
541 if (ssize
== MMU_SEGSIZE_256M
)
542 return vsid_scramble((context
<< ESID_BITS
)
543 | (ea
>> SID_SHIFT
), 256M
);
544 return vsid_scramble((context
<< ESID_BITS_1T
)
545 | (ea
>> SID_SHIFT_1T
), 1T
);
549 * This is only valid for addresses >= PAGE_OFFSET
551 * For kernel space, we use the top 4 context ids to map address as below
552 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
553 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
554 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
555 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
557 static inline unsigned long get_kernel_vsid(unsigned long ea
, int ssize
)
559 unsigned long context
;
562 * kernel take the top 4 context from the available range
564 context
= (MAX_USER_CONTEXT
) + ((ea
>> 60) - 0xc) + 1;
565 return get_vsid(context
, ea
, ssize
);
568 unsigned htab_shift_for_mem_size(unsigned long mem_size
);
570 #endif /* __ASSEMBLY__ */
572 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ */