arch/powerpc/include/asm/ps3gpu.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  PS3 GPU declarations.
   4  *
   5  *  Copyright 2009 Sony Corporation
   6  */
   7
   8 #ifndef _ASM_POWERPC_PS3GPU_H
   9 #define _ASM_POWERPC_PS3GPU_H
  10
  11 #include <linux/mutex.h>
  12
  13 #include <asm/lv1call.h>
  14
  15
  16 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC    0x101
  17 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP    0x102
  18
  19 #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP        0x600
  20 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT         0x601
  21 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC    0x602
  22 #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE        0x603
  23
  24 #define L1GPU_FB_BLIT_WAIT_FOR_COMPLETION       (1ULL << 32)
  25
  26 #define L1GPU_DISPLAY_SYNC_HSYNC                1
  27 #define L1GPU_DISPLAY_SYNC_VSYNC                2
  28
  29
  30 /* mutex synchronizing GPU accesses and video mode changes */
  31 extern struct mutex ps3_gpu_mutex;
  32
  33
  34 static inline int lv1_gpu_display_sync(u64 context_handle, u64 head,
  35                                        u64 ddr_offset)
  36 {
  37         return lv1_gpu_context_attribute(context_handle,
  38                                          L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC,
  39                                          head, ddr_offset, 0, 0);
  40 }
  41
  42 static inline int lv1_gpu_display_flip(u64 context_handle, u64 head,
  43                                        u64 ddr_offset)
  44 {
  45         return lv1_gpu_context_attribute(context_handle,
  46                                          L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP,
  47                                          head, ddr_offset, 0, 0);
  48 }
  49
  50 static inline int lv1_gpu_fb_setup(u64 context_handle, u64 xdr_lpar,
  51                                    u64 xdr_size, u64 ioif_offset)
  52 {
  53         return lv1_gpu_context_attribute(context_handle,
  54                                          L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP,
  55                                          xdr_lpar, xdr_size, ioif_offset, 0);
  56 }
  57
  58 static inline int lv1_gpu_fb_blit(u64 context_handle, u64 ddr_offset,
  59                                   u64 ioif_offset, u64 sync_width, u64 pitch)
  60 {
  61         return lv1_gpu_context_attribute(context_handle,
  62                                          L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
  63                                          ddr_offset, ioif_offset, sync_width,
  64                                          pitch);
  65 }
  66
  67 static inline int lv1_gpu_fb_close(u64 context_handle)
  68 {
  69         return lv1_gpu_context_attribute(context_handle,
  70                                          L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0,
  71                                          0, 0, 0);
  72 }
  73
  74 #endif /* _ASM_POWERPC_PS3GPU_H */