2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/exception-64s.h>
24 #include <asm/book3s/64/mmu-hash.h>
30 * Use unused space in the interrupt stack to save and restore
31 * registers for winkle support.
45 #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
50 * Used by threads before entering deep idle states. Saves SPRs
51 * in interrupt stack frame
55 * Note all register i.e per-core, per-subcore or per-thread is saved
56 * here since any thread in the core might wake up first
60 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
70 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
91 * Used by threads when the lock bit of core_idle_state is set.
92 * Threads will spin in HMT_LOW until the lock bit is cleared.
93 * r14 - pointer to core_idle_state
94 * r15 - used to load contents of core_idle_state
95 * r9 - used as a temporary variable
101 andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
105 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
106 bne- core_idle_lock_held
110 * Pass requested state in r3:
111 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
112 * - Requested STOP state in POWER9
114 * To check IRQ_HAPPENED in r4
118 * Address to 'rfid' to in r5
120 pnv_powersave_common:
121 /* Use r3 to pass state nap/sleep/winkle */
122 /* NAP is a state loss, we create a regs frame on the
123 * stack, fill it up with the state we care about and
124 * stick a pointer to it in PACAR1. We really only
125 * need to save PC, some CR bits and the NV GPRs,
126 * but for now an interrupt frame will do.
130 stdu r1,-INT_FRAME_SIZE(r1)
134 /* Hard disable interrupts */
138 mtmsrd r9,1 /* hard-disable interrupts */
140 /* Check if something happened while soft-disabled */
141 lbz r0,PACAIRQHAPPENED(r13)
142 andi. r0,r0,~PACA_IRQ_HARD_DIS@l
146 addi r1,r1,INT_FRAME_SIZE
148 li r3,0 /* Return 0 (no nap) */
152 1: /* We mark irqs hard disabled as this is the state we'll
153 * be in when returning and we need to tell arch_local_irq_restore()
156 li r0,PACA_IRQ_HARD_DIS
157 stb r0,PACAIRQHAPPENED(r13)
159 /* We haven't lost state ... yet */
161 stb r0,PACA_NAPSTATELOST(r13)
163 /* Continue saving state */
172 * Go to real mode to do the nap, as required by the architecture.
173 * Also, we need to be in real mode before setting hwthread_state,
174 * because as soon as we do that, another thread can switch
175 * the MMU context to the guest.
177 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
180 mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
185 .globl pnv_enter_arch207_idle_mode
186 pnv_enter_arch207_idle_mode:
187 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
188 /* Tell KVM we're entering idle */
189 li r4,KVM_HWTHREAD_IN_IDLE
190 /******************************************************/
191 /* N O T E W E L L ! ! ! N O T E W E L L */
192 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
193 /* MUST occur in real mode, i.e. with the MMU off, */
194 /* and the MMU must stay off until we clear this flag */
195 /* and test HSTATE_HWTHREAD_REQ(r13) in */
196 /* pnv_powersave_wakeup in this file. */
197 /* The reason is that another thread can switch the */
198 /* MMU to a guest context whenever this flag is set */
199 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
200 /* that would potentially cause this thread to start */
201 /* executing instructions from guest memory in */
202 /* hypervisor mode, leading to a host crash or data */
203 /* corruption, or worse. */
204 /******************************************************/
205 stb r4,HSTATE_HWTHREAD_STATE(r13)
207 stb r3,PACA_THREAD_IDLE_STATE(r13)
208 cmpwi cr3,r3,PNV_THREAD_SLEEP
210 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
213 /* Sleep or winkle */
214 lbz r7,PACA_THREAD_MASK(r13)
215 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
218 lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h
223 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
224 bnel- core_idle_lock_held
226 add r15,r15,r5 /* Add if winkle */
227 andc r15,r15,r7 /* Clear thread bit */
229 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
232 * If cr0 = 0, then current thread is the last thread of the core entering
233 * sleep. Last thread needs to execute the hardware bug workaround code if
234 * required by the platform.
235 * Make the workaround call unconditionally here. The below branch call is
236 * patched out when the idle states are discovered if the platform does not
239 .global pnv_fastsleep_workaround_at_entry
240 pnv_fastsleep_workaround_at_entry:
241 beq fastsleep_workaround_at_entry
247 common_enter: /* common code for all the threads entering sleep or winkle */
249 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
251 fastsleep_workaround_at_entry:
252 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
257 /* Fast sleep workaround */
260 bl opal_config_cpu_idle_state
263 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
269 bl save_sprs_to_stack
271 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
274 * r3 - PSSCR value corresponding to the requested stop state.
277 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
278 /* Tell KVM we're entering idle */
279 li r4,KVM_HWTHREAD_IN_IDLE
280 /* DO THIS IN REAL MODE! See comment above. */
281 stb r4,HSTATE_HWTHREAD_STATE(r13)
284 * Check if we are executing the lite variant with ESL=EC=0
286 andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
287 clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
288 bne .Lhandle_esl_ec_set
289 IDLE_STATE_ENTER_SEQ(PPC_STOP)
290 li r3,0 /* Since we didn't lose state, return 0 */
295 * Check if the requested state is a deep idle state.
297 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
298 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
300 bge .Lhandle_deep_stop
301 IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
304 * Entering deep idle state.
305 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
306 * stack and enter stop
308 lbz r7,PACA_THREAD_MASK(r13)
309 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
313 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
314 bnel- core_idle_lock_held
315 andc r15,r15,r7 /* Clear thread bit */
321 bl save_sprs_to_stack
323 IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
326 /* Now check if user or arch enabled NAP mode */
327 LOAD_REG_ADDRBASE(r3,powersave_nap)
328 lwz r4,ADDROFF(powersave_nap)(r3)
337 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
338 b pnv_powersave_common
341 _GLOBAL(power7_sleep)
342 li r3,PNV_THREAD_SLEEP
344 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
345 b pnv_powersave_common
348 _GLOBAL(power7_winkle)
349 li r3,PNV_THREAD_WINKLE
351 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
352 b pnv_powersave_common
355 #define CHECK_HMI_INTERRUPT \
356 mfspr r0,SPRN_SRR1; \
357 BEGIN_FTR_SECTION_NESTED(66); \
358 rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
359 FTR_SECTION_ELSE_NESTED(66); \
360 rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
361 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
362 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
364 /* Invoke opal call to handle hmi */ \
365 ld r2,PACATOC(r13); \
367 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
368 li r3,0; /* NULL argument */ \
369 bl hmi_exception_realmode; \
371 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
375 * r3 - The PSSCR value corresponding to the stop state.
376 * r4 - The PSSCR mask corrresonding to the stop state.
378 _GLOBAL(power9_idle_stop)
382 std r3, PACA_REQ_PSSCR(r13)
384 LOAD_REG_ADDR(r5,power_enter_stop)
386 b pnv_powersave_common
390 * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,
391 * HSPRG0 will be set to the HSPRG0 value of one of the
392 * threads in this core. Thus the value we have in r13
393 * may not be this thread's paca pointer.
395 * Fortunately, the TIR remains invariant. Since this thread's
396 * paca pointer is recorded in all its sibling's paca, we can
397 * correctly recover this thread's paca pointer if we
398 * know the index of this thread in the core.
400 * This index can be obtained from the TIR.
402 * i.e, thread's position in the core = TIR.
403 * If this value is i, then this thread's paca is
404 * paca->thread_sibling_pacas[i].
406 power9_dd1_recover_paca:
409 * Since each entry in thread_sibling_pacas is 8 bytes
410 * we need to left-shift by 3 bits. Thus r4 = i * 8
413 /* Get &paca->thread_sibling_pacas[0] in r5 */
414 ld r5, PACA_SIBLING_PACA_PTRS(r13)
415 /* Load paca->thread_sibling_pacas[i] into r13 */
419 * Indicate that we have lost NVGPR state
420 * which needs to be restored from the stack.
423 stb r3,PACA_NAPSTATELOST(r13)
427 * Called from machine check handler for powersave wakeups.
428 * Low level machine check processing has already been done. Now just
429 * go through the wake up path to get everything in order.
431 * r3 - The original SRR1 value.
432 * Original SRR[01] have been clobbered.
435 .global pnv_powersave_wakeup_mce
436 pnv_powersave_wakeup_mce:
437 /* Set cr3 for pnv_powersave_wakeup */
438 rlwinm r11,r3,47-31,30,31
442 * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake
443 * reason into SRR1, which allows reuse of the system reset wakeup
444 * code without being mistaken for another type of wakeup.
446 oris r3,r3,SRR1_WAKEMCE_RESVD@h
449 b pnv_powersave_wakeup
452 * Called from reset vector for powersave wakeups.
453 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
455 .global pnv_powersave_wakeup
456 pnv_powersave_wakeup:
460 BEGIN_FTR_SECTION_NESTED(70)
461 bl power9_dd1_recover_paca
462 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70)
463 bl pnv_restore_hyp_resource_arch300
465 bl pnv_restore_hyp_resource_arch207
466 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
468 li r0,PNV_THREAD_RUNNING
469 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
471 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
472 li r0,KVM_HWTHREAD_IN_KERNEL
473 stb r0,HSTATE_HWTHREAD_STATE(r13)
474 /* Order setting hwthread_state vs. testing hwthread_req */
476 lbz r0,HSTATE_HWTHREAD_REQ(r13)
483 /* Return SRR1 from power7_nap() */
485 blt cr3,pnv_wakeup_noloss
489 * Check whether we have woken up with hypervisor state loss.
490 * If yes, restore hypervisor state and return back to link.
492 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
494 pnv_restore_hyp_resource_arch300:
496 * POWER ISA 3. Use PSSCR to determine if we
497 * are waking up from deep idle state
499 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
500 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
502 BEGIN_FTR_SECTION_NESTED(71)
504 * Assume that we are waking up from the state
505 * same as the Requested Level (RL) in the PSSCR
506 * which are Bits 60-63
508 ld r5,PACA_REQ_PSSCR(r13)
510 FTR_SECTION_ELSE_NESTED(71)
512 * 0-3 bits correspond to Power-Saving Level Status
513 * which indicates the idle state we are waking up from
517 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_POWER9_DD1, 71)
519 bge cr4,pnv_wakeup_tb_loss /* returns to caller */
521 blr /* Waking up without hypervisor state loss. */
523 /* Same calling convention as arch300 */
524 pnv_restore_hyp_resource_arch207:
526 * POWER ISA 2.07 or less.
527 * Check if we slept with sleep or winkle.
529 lbz r4,PACA_THREAD_IDLE_STATE(r13)
530 cmpwi cr2,r4,PNV_THREAD_NAP
531 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
534 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
535 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
536 * indicates we are waking with hypervisor state loss from nap.
540 blr /* Waking up without hypervisor state loss */
543 * Called if waking up from idle state which can cause either partial or
544 * complete hyp state loss.
545 * In POWER8, called if waking up from fastsleep or winkle
546 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
549 * cr3 - gt if waking up with partial/complete hypervisor state loss
552 * cr4 - gt or eq if waking up from complete hypervisor state loss.
555 * r4 - PACA_THREAD_IDLE_STATE
560 * Before entering any idle state, the NVGPRs are saved in the stack.
561 * If there was a state loss, or PACA_NAPSTATELOST was set, then the
562 * NVGPRs are restored. If we are here, it is likely that state is lost,
563 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
564 * here are the same as the test to restore NVGPRS:
565 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
566 * and SRR1 test for restoring NVGPRs.
568 * We are about to clobber NVGPRs now, so set NAPSTATELOST to
569 * guarantee they will always be restored. This might be tightened
570 * with careful reading of specs (particularly for ISA300) but this
571 * is already a slow wakeup path and it's simpler to be safe.
574 stb r0,PACA_NAPSTATELOST(r13)
578 * Save SRR1 and LR in NVGPRs as they might be clobbered in
579 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
580 * to determine the wakeup reason if we branch to kvm_start_guest. LR
581 * is required to return back to reset vector after hypervisor state
582 * restore is complete.
589 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
591 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
592 lbz r7,PACA_THREAD_MASK(r13)
595 * Take the core lock to synchronize against other threads.
597 * Lock bit is set in one of the 2 cases-
598 * a. In the sleep/winkle enter path, the last thread is executing
599 * fastsleep workaround code.
600 * b. In the wake up path, another thread is executing fastsleep
601 * workaround undo code or resyncing timebase or restoring context
602 * In either case loop until the lock bit is cleared.
606 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
607 bnel- core_idle_lock_held
608 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
613 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
618 * cr2 - eq if first thread to wakeup in core
619 * cr3- gt if waking up with partial/complete hypervisor state loss
621 * cr4 - gt or eq if waking up from complete hypervisor state loss.
627 * If yes, check if all threads were in winkle, decrement our
628 * winkle count, set all thread winkle bits if all were in winkle.
629 * Check if our thread has a winkle bit set, and set cr4 accordingly
630 * (to match ISA300, above). Pseudo-code for core idle state
631 * transitions for ISA207 is as follows (everything happens atomically
632 * due to store conditional and/or lock bit):
639 * core_idle_state &= ~thread_in_core
644 * bool first_in_core, first_in_subcore;
646 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
647 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
649 * core_idle_state |= thread_in_core;
654 * core_idle_state &= ~thread_in_core;
655 * core_idle_state += 1 << WINKLE_COUNT_SHIFT;
660 * bool first_in_core, first_in_subcore, winkle_state_lost;
662 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
663 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
665 * core_idle_state |= thread_in_core;
667 * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT))
668 * core_idle_state |= THREAD_WINKLE_BITS;
669 * core_idle_state -= 1 << WINKLE_COUNT_SHIFT;
671 * winkle_state_lost = core_idle_state &
672 * (thread_in_core << WINKLE_THREAD_SHIFT);
673 * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT);
677 cmpwi r18,PNV_THREAD_WINKLE
679 andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h
680 subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h
682 ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */
684 /* Shift thread bit to winkle mask, then test if this thread is set,
685 * and remove it from the winkle bits */
689 cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */
691 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
693 cmpwi r4,0 /* Check if first in subcore */
695 or r15,r15,r7 /* Set thread bit */
696 beq first_thread_in_subcore
697 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
699 or r15,r15,r7 /* Set thread bit */
700 beq cr2,first_thread_in_core
702 /* Not first thread in core or subcore to wake up */
705 first_thread_in_subcore:
707 * If waking up from sleep, subcore state is not lost. Hence
708 * skip subcore state restore
710 blt cr4,subcore_state_restored
712 /* Restore per-subcore state */
721 subcore_state_restored:
723 * Check if the thread is also the first thread in the core. If not,
724 * skip to clear_lock.
728 first_thread_in_core:
731 * First thread in the core waking up from any state which can cause
732 * partial or complete hypervisor state loss. It needs to
733 * call the fastsleep workaround code if the platform requires it.
734 * Call it unconditionally here. The below branch instruction will
735 * be patched out if the platform does not have fastsleep or does not
736 * require the workaround. Patching will be performed during the
737 * discovery of idle-states.
739 .global pnv_fastsleep_workaround_at_exit
740 pnv_fastsleep_workaround_at_exit:
741 b fastsleep_workaround_at_exit
745 * Use cr3 which indicates that we are waking up with atleast partial
746 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
748 ble cr3,.Ltb_resynced
749 /* Time base re-sync */
750 bl opal_resync_timebase;
752 * If waking up from sleep (POWER8), per core state
753 * is not lost, skip to clear_lock.
759 * First thread in the core to wake up and its waking up with
760 * complete hypervisor state loss. Restore per core hypervisor
768 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
776 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
782 * Common to all threads.
784 * If waking up from sleep, hypervisor state is not lost. Hence
785 * skip hypervisor state restore.
787 blt cr4,hypervisor_state_restored
789 /* Waking up from winkle */
791 BEGIN_MMU_FTR_SECTION
793 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
794 /* Restore SLB from PACA */
795 ld r8,PACA_SLBSHADOWPTR(r13)
798 li r3, SLBSHADOW_SAVEAREA
802 andis. r7,r5,SLB_ESID_V@h
809 /* Restore per thread state */
820 /* Call cur_cpu_spec->cpu_restore() */
821 LOAD_REG_ADDR(r4, cur_cpu_spec)
823 ld r12,CPU_SPEC_RESTORE(r4)
824 #ifdef PPC64_ELF_ABI_v1
833 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
834 hypervisor_state_restored:
838 blr /* return to pnv_powersave_wakeup */
840 fastsleep_workaround_at_exit:
843 bl opal_config_cpu_idle_state
847 * R3 here contains the value that will be returned to the caller
850 .global pnv_wakeup_loss
855 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
861 addi r1,r1,INT_FRAME_SIZE
868 * R3 here contains the value that will be returned to the caller
872 lbz r0,PACA_NAPSTATELOST(r13)
877 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
882 addi r1,r1,INT_FRAME_SIZE