2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/sched/debug.h>
21 #include <linux/kernel.h>
23 #include <linux/stddef.h>
24 #include <linux/unistd.h>
25 #include <linux/ptrace.h>
26 #include <linux/user.h>
27 #include <linux/interrupt.h>
28 #include <linux/init.h>
29 #include <linux/extable.h>
30 #include <linux/module.h> /* print_modules */
31 #include <linux/prctl.h>
32 #include <linux/delay.h>
33 #include <linux/kprobes.h>
34 #include <linux/kexec.h>
35 #include <linux/backlight.h>
36 #include <linux/bug.h>
37 #include <linux/kdebug.h>
38 #include <linux/ratelimit.h>
39 #include <linux/context_tracking.h>
41 #include <asm/emulated_ops.h>
42 #include <asm/pgtable.h>
43 #include <linux/uaccess.h>
44 #include <asm/debugfs.h>
46 #include <asm/machdep.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
58 #include <asm/kexec.h>
59 #include <asm/ppc-opcode.h>
61 #include <asm/fadump.h>
62 #include <asm/switch_to.h>
64 #include <asm/debug.h>
65 #include <asm/asm-prototypes.h>
67 #include <sysdev/fsl_pci.h>
68 #include <asm/kprobes.h>
70 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
71 int (*__debugger
)(struct pt_regs
*regs
) __read_mostly
;
72 int (*__debugger_ipi
)(struct pt_regs
*regs
) __read_mostly
;
73 int (*__debugger_bpt
)(struct pt_regs
*regs
) __read_mostly
;
74 int (*__debugger_sstep
)(struct pt_regs
*regs
) __read_mostly
;
75 int (*__debugger_iabr_match
)(struct pt_regs
*regs
) __read_mostly
;
76 int (*__debugger_break_match
)(struct pt_regs
*regs
) __read_mostly
;
77 int (*__debugger_fault_handler
)(struct pt_regs
*regs
) __read_mostly
;
79 EXPORT_SYMBOL(__debugger
);
80 EXPORT_SYMBOL(__debugger_ipi
);
81 EXPORT_SYMBOL(__debugger_bpt
);
82 EXPORT_SYMBOL(__debugger_sstep
);
83 EXPORT_SYMBOL(__debugger_iabr_match
);
84 EXPORT_SYMBOL(__debugger_break_match
);
85 EXPORT_SYMBOL(__debugger_fault_handler
);
88 /* Transactional Memory trap debug */
90 #define TM_DEBUG(x...) printk(KERN_INFO x)
92 #define TM_DEBUG(x...) do { } while(0)
96 * Trap & Exception support
99 #ifdef CONFIG_PMAC_BACKLIGHT
100 static void pmac_backlight_unblank(void)
102 mutex_lock(&pmac_backlight_mutex
);
103 if (pmac_backlight
) {
104 struct backlight_properties
*props
;
106 props
= &pmac_backlight
->props
;
107 props
->brightness
= props
->max_brightness
;
108 props
->power
= FB_BLANK_UNBLANK
;
109 backlight_update_status(pmac_backlight
);
111 mutex_unlock(&pmac_backlight_mutex
);
114 static inline void pmac_backlight_unblank(void) { }
117 static arch_spinlock_t die_lock
= __ARCH_SPIN_LOCK_UNLOCKED
;
118 static int die_owner
= -1;
119 static unsigned int die_nest_count
;
120 static int die_counter
;
122 static unsigned long oops_begin(struct pt_regs
*regs
)
129 /* racy, but better than risking deadlock. */
130 raw_local_irq_save(flags
);
131 cpu
= smp_processor_id();
132 if (!arch_spin_trylock(&die_lock
)) {
133 if (cpu
== die_owner
)
134 /* nested oops. should stop eventually */;
136 arch_spin_lock(&die_lock
);
142 if (machine_is(powermac
))
143 pmac_backlight_unblank();
146 NOKPROBE_SYMBOL(oops_begin
);
148 static void oops_end(unsigned long flags
, struct pt_regs
*regs
,
152 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
156 if (!die_nest_count
) {
157 /* Nest count reaches zero, release the lock. */
159 arch_spin_unlock(&die_lock
);
161 raw_local_irq_restore(flags
);
163 crash_fadump(regs
, "die oops");
166 * A system reset (0x100) is a request to dump, so we always send
167 * it through the crashdump code.
169 if (kexec_should_crash(current
) || (TRAP(regs
) == 0x100)) {
173 * We aren't the primary crash CPU. We need to send it
174 * to a holding pattern to avoid it ending up in the panic
177 crash_kexec_secondary(regs
);
184 * While our oops output is serialised by a spinlock, output
185 * from panic() called below can race and corrupt it. If we
186 * know we are going to panic, delay for 1 second so we have a
187 * chance to get clean backtraces from all CPUs that are oopsing.
189 if (in_interrupt() || panic_on_oops
|| !current
->pid
||
190 is_global_init(current
)) {
191 mdelay(MSEC_PER_SEC
);
195 panic("Fatal exception in interrupt");
197 panic("Fatal exception");
200 NOKPROBE_SYMBOL(oops_end
);
202 static int __die(const char *str
, struct pt_regs
*regs
, long err
)
204 printk("Oops: %s, sig: %ld [#%d]\n", str
, err
, ++die_counter
);
205 #ifdef CONFIG_PREEMPT
209 printk("SMP NR_CPUS=%d ", NR_CPUS
);
211 if (debug_pagealloc_enabled())
212 printk("DEBUG_PAGEALLOC ");
216 printk("%s\n", ppc_md
.name
? ppc_md
.name
: "");
218 if (notify_die(DIE_OOPS
, str
, regs
, err
, 255, SIGSEGV
) == NOTIFY_STOP
)
226 NOKPROBE_SYMBOL(__die
);
228 void die(const char *str
, struct pt_regs
*regs
, long err
)
235 flags
= oops_begin(regs
);
236 if (__die(str
, regs
, err
))
238 oops_end(flags
, regs
, err
);
240 NOKPROBE_SYMBOL(die
);
242 void user_single_step_siginfo(struct task_struct
*tsk
,
243 struct pt_regs
*regs
, siginfo_t
*info
)
245 memset(info
, 0, sizeof(*info
));
246 info
->si_signo
= SIGTRAP
;
247 info
->si_code
= TRAP_TRACE
;
248 info
->si_addr
= (void __user
*)regs
->nip
;
251 void _exception(int signr
, struct pt_regs
*regs
, int code
, unsigned long addr
)
254 const char fmt32
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
255 "at %08lx nip %08lx lr %08lx code %x\n";
256 const char fmt64
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
257 "at %016lx nip %016lx lr %016lx code %x\n";
259 if (!user_mode(regs
)) {
260 die("Exception in kernel mode", regs
, signr
);
264 if (show_unhandled_signals
&& unhandled_signal(current
, signr
)) {
265 printk_ratelimited(regs
->msr
& MSR_64BIT
? fmt64
: fmt32
,
266 current
->comm
, current
->pid
, signr
,
267 addr
, regs
->nip
, regs
->link
, code
);
270 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs
))
273 current
->thread
.trap_nr
= code
;
274 memset(&info
, 0, sizeof(info
));
275 info
.si_signo
= signr
;
277 info
.si_addr
= (void __user
*) addr
;
278 force_sig_info(signr
, &info
, current
);
281 void system_reset_exception(struct pt_regs
*regs
)
284 * Avoid crashes in case of nested NMI exceptions. Recoverability
285 * is determined by RI and in_nmi
287 bool nested
= in_nmi();
291 /* See if any machine dependent calls */
292 if (ppc_md
.system_reset_exception
) {
293 if (ppc_md
.system_reset_exception(regs
))
297 die("System Reset", regs
, SIGABRT
);
300 #ifdef CONFIG_PPC_BOOK3S_64
301 BUG_ON(get_paca()->in_nmi
== 0);
302 if (get_paca()->in_nmi
> 1)
303 panic("Unrecoverable nested System Reset");
305 /* Must die if the interrupt is not recoverable */
306 if (!(regs
->msr
& MSR_RI
))
307 panic("Unrecoverable System Reset");
312 /* What should we do here? We could issue a shutdown or hard reset. */
317 * This function is called in real mode. Strictly no printk's please.
319 * regs->nip and regs->msr contains srr0 and ssr1.
321 long machine_check_early(struct pt_regs
*regs
)
325 __this_cpu_inc(irq_stat
.mce_exceptions
);
327 if (cur_cpu_spec
&& cur_cpu_spec
->machine_check_early
)
328 handled
= cur_cpu_spec
->machine_check_early(regs
);
332 long hmi_exception_realmode(struct pt_regs
*regs
)
334 __this_cpu_inc(irq_stat
.hmi_exceptions
);
336 wait_for_subcore_guest_exit();
338 if (ppc_md
.hmi_exception_early
)
339 ppc_md
.hmi_exception_early(regs
);
341 wait_for_tb_resync();
349 * I/O accesses can cause machine checks on powermacs.
350 * Check if the NIP corresponds to the address of a sync
351 * instruction for which there is an entry in the exception
353 * Note that the 601 only takes a machine check on TEA
354 * (transfer error ack) signal assertion, and does not
355 * set any of the top 16 bits of SRR1.
358 static inline int check_io_access(struct pt_regs
*regs
)
361 unsigned long msr
= regs
->msr
;
362 const struct exception_table_entry
*entry
;
363 unsigned int *nip
= (unsigned int *)regs
->nip
;
365 if (((msr
& 0xffff0000) == 0 || (msr
& (0x80000 | 0x40000)))
366 && (entry
= search_exception_tables(regs
->nip
)) != NULL
) {
368 * Check that it's a sync instruction, or somewhere
369 * in the twi; isync; nop sequence that inb/inw/inl uses.
370 * As the address is in the exception table
371 * we should be able to read the instr there.
372 * For the debug message, we look at the preceding
375 if (*nip
== PPC_INST_NOP
)
377 else if (*nip
== PPC_INST_ISYNC
)
379 if (*nip
== PPC_INST_SYNC
|| (*nip
>> 26) == OP_TRAP
) {
383 rb
= (*nip
>> 11) & 0x1f;
384 printk(KERN_DEBUG
"%s bad port %lx at %p\n",
385 (*nip
& 0x100)? "OUT to": "IN from",
386 regs
->gpr
[rb
] - _IO_BASE
, nip
);
388 regs
->nip
= extable_fixup(entry
);
392 #endif /* CONFIG_PPC32 */
396 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
397 /* On 4xx, the reason for the machine check or program exception
399 #define get_reason(regs) ((regs)->dsisr)
400 #ifndef CONFIG_FSL_BOOKE
401 #define get_mc_reason(regs) ((regs)->dsisr)
403 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
405 #define REASON_FP ESR_FP
406 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
407 #define REASON_PRIVILEGED ESR_PPR
408 #define REASON_TRAP ESR_PTR
410 /* single-step stuff */
411 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
412 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
415 /* On non-4xx, the reason for the machine check or program
416 exception is in the MSR. */
417 #define get_reason(regs) ((regs)->msr)
418 #define get_mc_reason(regs) ((regs)->msr)
419 #define REASON_TM 0x200000
420 #define REASON_FP 0x100000
421 #define REASON_ILLEGAL 0x80000
422 #define REASON_PRIVILEGED 0x40000
423 #define REASON_TRAP 0x20000
425 #define single_stepping(regs) ((regs)->msr & MSR_SE)
426 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
429 #if defined(CONFIG_4xx)
430 int machine_check_4xx(struct pt_regs
*regs
)
432 unsigned long reason
= get_mc_reason(regs
);
434 if (reason
& ESR_IMCP
) {
435 printk("Instruction");
436 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
439 printk(" machine check in kernel mode.\n");
444 int machine_check_440A(struct pt_regs
*regs
)
446 unsigned long reason
= get_mc_reason(regs
);
448 printk("Machine check in kernel mode.\n");
449 if (reason
& ESR_IMCP
){
450 printk("Instruction Synchronous Machine Check exception\n");
451 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
454 u32 mcsr
= mfspr(SPRN_MCSR
);
456 printk("Instruction Read PLB Error\n");
458 printk("Data Read PLB Error\n");
460 printk("Data Write PLB Error\n");
461 if (mcsr
& MCSR_TLBP
)
462 printk("TLB Parity Error\n");
463 if (mcsr
& MCSR_ICP
){
464 flush_instruction_cache();
465 printk("I-Cache Parity Error\n");
467 if (mcsr
& MCSR_DCSP
)
468 printk("D-Cache Search Parity Error\n");
469 if (mcsr
& MCSR_DCFP
)
470 printk("D-Cache Flush Parity Error\n");
471 if (mcsr
& MCSR_IMPE
)
472 printk("Machine Check exception is imprecise\n");
475 mtspr(SPRN_MCSR
, mcsr
);
480 int machine_check_47x(struct pt_regs
*regs
)
482 unsigned long reason
= get_mc_reason(regs
);
485 printk(KERN_ERR
"Machine check in kernel mode.\n");
486 if (reason
& ESR_IMCP
) {
488 "Instruction Synchronous Machine Check exception\n");
489 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
492 mcsr
= mfspr(SPRN_MCSR
);
494 printk(KERN_ERR
"Instruction Read PLB Error\n");
496 printk(KERN_ERR
"Data Read PLB Error\n");
498 printk(KERN_ERR
"Data Write PLB Error\n");
499 if (mcsr
& MCSR_TLBP
)
500 printk(KERN_ERR
"TLB Parity Error\n");
501 if (mcsr
& MCSR_ICP
) {
502 flush_instruction_cache();
503 printk(KERN_ERR
"I-Cache Parity Error\n");
505 if (mcsr
& MCSR_DCSP
)
506 printk(KERN_ERR
"D-Cache Search Parity Error\n");
507 if (mcsr
& PPC47x_MCSR_GPR
)
508 printk(KERN_ERR
"GPR Parity Error\n");
509 if (mcsr
& PPC47x_MCSR_FPR
)
510 printk(KERN_ERR
"FPR Parity Error\n");
511 if (mcsr
& PPC47x_MCSR_IPR
)
512 printk(KERN_ERR
"Machine Check exception is imprecise\n");
515 mtspr(SPRN_MCSR
, mcsr
);
519 #elif defined(CONFIG_E500)
520 int machine_check_e500mc(struct pt_regs
*regs
)
522 unsigned long mcsr
= mfspr(SPRN_MCSR
);
523 unsigned long reason
= mcsr
;
526 if (reason
& MCSR_LD
) {
527 recoverable
= fsl_rio_mcheck_exception(regs
);
528 if (recoverable
== 1)
532 printk("Machine check in kernel mode.\n");
533 printk("Caused by (from MCSR=%lx): ", reason
);
535 if (reason
& MCSR_MCP
)
536 printk("Machine Check Signal\n");
538 if (reason
& MCSR_ICPERR
) {
539 printk("Instruction Cache Parity Error\n");
542 * This is recoverable by invalidating the i-cache.
544 mtspr(SPRN_L1CSR1
, mfspr(SPRN_L1CSR1
) | L1CSR1_ICFI
);
545 while (mfspr(SPRN_L1CSR1
) & L1CSR1_ICFI
)
549 * This will generally be accompanied by an instruction
550 * fetch error report -- only treat MCSR_IF as fatal
551 * if it wasn't due to an L1 parity error.
556 if (reason
& MCSR_DCPERR_MC
) {
557 printk("Data Cache Parity Error\n");
560 * In write shadow mode we auto-recover from the error, but it
561 * may still get logged and cause a machine check. We should
562 * only treat the non-write shadow case as non-recoverable.
564 if (!(mfspr(SPRN_L1CSR2
) & L1CSR2_DCWS
))
568 if (reason
& MCSR_L2MMU_MHIT
) {
569 printk("Hit on multiple TLB entries\n");
573 if (reason
& MCSR_NMI
)
574 printk("Non-maskable interrupt\n");
576 if (reason
& MCSR_IF
) {
577 printk("Instruction Fetch Error Report\n");
581 if (reason
& MCSR_LD
) {
582 printk("Load Error Report\n");
586 if (reason
& MCSR_ST
) {
587 printk("Store Error Report\n");
591 if (reason
& MCSR_LDG
) {
592 printk("Guarded Load Error Report\n");
596 if (reason
& MCSR_TLBSYNC
)
597 printk("Simultaneous tlbsync operations\n");
599 if (reason
& MCSR_BSL2_ERR
) {
600 printk("Level 2 Cache Error\n");
604 if (reason
& MCSR_MAV
) {
607 addr
= mfspr(SPRN_MCAR
);
608 addr
|= (u64
)mfspr(SPRN_MCARU
) << 32;
610 printk("Machine Check %s Address: %#llx\n",
611 reason
& MCSR_MEA
? "Effective" : "Physical", addr
);
615 mtspr(SPRN_MCSR
, mcsr
);
616 return mfspr(SPRN_MCSR
) == 0 && recoverable
;
619 int machine_check_e500(struct pt_regs
*regs
)
621 unsigned long reason
= get_mc_reason(regs
);
623 if (reason
& MCSR_BUS_RBERR
) {
624 if (fsl_rio_mcheck_exception(regs
))
626 if (fsl_pci_mcheck_exception(regs
))
630 printk("Machine check in kernel mode.\n");
631 printk("Caused by (from MCSR=%lx): ", reason
);
633 if (reason
& MCSR_MCP
)
634 printk("Machine Check Signal\n");
635 if (reason
& MCSR_ICPERR
)
636 printk("Instruction Cache Parity Error\n");
637 if (reason
& MCSR_DCP_PERR
)
638 printk("Data Cache Push Parity Error\n");
639 if (reason
& MCSR_DCPERR
)
640 printk("Data Cache Parity Error\n");
641 if (reason
& MCSR_BUS_IAERR
)
642 printk("Bus - Instruction Address Error\n");
643 if (reason
& MCSR_BUS_RAERR
)
644 printk("Bus - Read Address Error\n");
645 if (reason
& MCSR_BUS_WAERR
)
646 printk("Bus - Write Address Error\n");
647 if (reason
& MCSR_BUS_IBERR
)
648 printk("Bus - Instruction Data Error\n");
649 if (reason
& MCSR_BUS_RBERR
)
650 printk("Bus - Read Data Bus Error\n");
651 if (reason
& MCSR_BUS_WBERR
)
652 printk("Bus - Write Data Bus Error\n");
653 if (reason
& MCSR_BUS_IPERR
)
654 printk("Bus - Instruction Parity Error\n");
655 if (reason
& MCSR_BUS_RPERR
)
656 printk("Bus - Read Parity Error\n");
661 int machine_check_generic(struct pt_regs
*regs
)
665 #elif defined(CONFIG_E200)
666 int machine_check_e200(struct pt_regs
*regs
)
668 unsigned long reason
= get_mc_reason(regs
);
670 printk("Machine check in kernel mode.\n");
671 printk("Caused by (from MCSR=%lx): ", reason
);
673 if (reason
& MCSR_MCP
)
674 printk("Machine Check Signal\n");
675 if (reason
& MCSR_CP_PERR
)
676 printk("Cache Push Parity Error\n");
677 if (reason
& MCSR_CPERR
)
678 printk("Cache Parity Error\n");
679 if (reason
& MCSR_EXCP_ERR
)
680 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
681 if (reason
& MCSR_BUS_IRERR
)
682 printk("Bus - Read Bus Error on instruction fetch\n");
683 if (reason
& MCSR_BUS_DRERR
)
684 printk("Bus - Read Bus Error on data load\n");
685 if (reason
& MCSR_BUS_WRERR
)
686 printk("Bus - Write Bus Error on buffered store or cache line push\n");
690 #elif defined(CONFIG_PPC_8xx)
691 int machine_check_8xx(struct pt_regs
*regs
)
693 unsigned long reason
= get_mc_reason(regs
);
695 pr_err("Machine check in kernel mode.\n");
696 pr_err("Caused by (from SRR1=%lx): ", reason
);
697 if (reason
& 0x40000000)
698 pr_err("Fetch error at address %lx\n", regs
->nip
);
700 pr_err("Data access error at address %lx\n", regs
->dar
);
703 /* the qspan pci read routines can cause machine checks -- Cort
705 * yuck !!! that totally needs to go away ! There are better ways
706 * to deal with that than having a wart in the mcheck handler.
709 bad_page_fault(regs
, regs
->dar
, SIGBUS
);
716 int machine_check_generic(struct pt_regs
*regs
)
718 unsigned long reason
= get_mc_reason(regs
);
720 printk("Machine check in kernel mode.\n");
721 printk("Caused by (from SRR1=%lx): ", reason
);
722 switch (reason
& 0x601F0000) {
724 printk("Machine check signal\n");
726 case 0: /* for 601 */
728 case 0x140000: /* 7450 MSS error and TEA */
729 printk("Transfer error ack signal\n");
732 printk("Data parity error signal\n");
735 printk("Address parity error signal\n");
738 printk("L1 Data Cache error\n");
741 printk("L1 Instruction Cache error\n");
744 printk("L2 data cache parity error\n");
747 printk("Unknown values in msr\n");
751 #endif /* everything else */
753 void machine_check_exception(struct pt_regs
*regs
)
755 enum ctx_state prev_state
= exception_enter();
758 /* 64s accounts the mce in machine_check_early when in HVMODE */
759 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64
) || !cpu_has_feature(CPU_FTR_HVMODE
))
760 __this_cpu_inc(irq_stat
.mce_exceptions
);
762 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_NOW_UNRELIABLE
);
764 /* See if any machine dependent calls. In theory, we would want
765 * to call the CPU first, and call the ppc_md. one if the CPU
766 * one returns a positive number. However there is existing code
767 * that assumes the board gets a first chance, so let's keep it
768 * that way for now and fix things later. --BenH.
770 if (ppc_md
.machine_check_exception
)
771 recover
= ppc_md
.machine_check_exception(regs
);
772 else if (cur_cpu_spec
->machine_check
)
773 recover
= cur_cpu_spec
->machine_check(regs
);
778 if (debugger_fault_handler(regs
))
781 if (check_io_access(regs
))
784 die("Machine check", regs
, SIGBUS
);
786 /* Must die if the interrupt is not recoverable */
787 if (!(regs
->msr
& MSR_RI
))
788 panic("Unrecoverable Machine check");
791 exception_exit(prev_state
);
794 void SMIException(struct pt_regs
*regs
)
796 die("System Management Interrupt", regs
, SIGABRT
);
799 void handle_hmi_exception(struct pt_regs
*regs
)
801 struct pt_regs
*old_regs
;
803 old_regs
= set_irq_regs(regs
);
806 if (ppc_md
.handle_hmi_exception
)
807 ppc_md
.handle_hmi_exception(regs
);
810 set_irq_regs(old_regs
);
813 void unknown_exception(struct pt_regs
*regs
)
815 enum ctx_state prev_state
= exception_enter();
817 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
818 regs
->nip
, regs
->msr
, regs
->trap
);
820 _exception(SIGTRAP
, regs
, 0, 0);
822 exception_exit(prev_state
);
825 void instruction_breakpoint_exception(struct pt_regs
*regs
)
827 enum ctx_state prev_state
= exception_enter();
829 if (notify_die(DIE_IABR_MATCH
, "iabr_match", regs
, 5,
830 5, SIGTRAP
) == NOTIFY_STOP
)
832 if (debugger_iabr_match(regs
))
834 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
837 exception_exit(prev_state
);
840 void RunModeException(struct pt_regs
*regs
)
842 _exception(SIGTRAP
, regs
, 0, 0);
845 void single_step_exception(struct pt_regs
*regs
)
847 enum ctx_state prev_state
= exception_enter();
849 clear_single_step(regs
);
851 if (kprobe_post_handler(regs
))
854 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
855 5, SIGTRAP
) == NOTIFY_STOP
)
857 if (debugger_sstep(regs
))
860 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
863 exception_exit(prev_state
);
865 NOKPROBE_SYMBOL(single_step_exception
);
868 * After we have successfully emulated an instruction, we have to
869 * check if the instruction was being single-stepped, and if so,
870 * pretend we got a single-step exception. This was pointed out
871 * by Kumar Gala. -- paulus
873 static void emulate_single_step(struct pt_regs
*regs
)
875 if (single_stepping(regs
))
876 single_step_exception(regs
);
879 static inline int __parse_fpscr(unsigned long fpscr
)
883 /* Invalid operation */
884 if ((fpscr
& FPSCR_VE
) && (fpscr
& FPSCR_VX
))
888 else if ((fpscr
& FPSCR_OE
) && (fpscr
& FPSCR_OX
))
892 else if ((fpscr
& FPSCR_UE
) && (fpscr
& FPSCR_UX
))
896 else if ((fpscr
& FPSCR_ZE
) && (fpscr
& FPSCR_ZX
))
900 else if ((fpscr
& FPSCR_XE
) && (fpscr
& FPSCR_XX
))
906 static void parse_fpe(struct pt_regs
*regs
)
910 flush_fp_to_thread(current
);
912 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
914 _exception(SIGFPE
, regs
, code
, regs
->nip
);
918 * Illegal instruction emulation support. Originally written to
919 * provide the PVR to user applications using the mfspr rd, PVR.
920 * Return non-zero if we can't emulate, or -EFAULT if the associated
921 * memory access caused an access fault. Return zero on success.
923 * There are a couple of ways to do this, either "decode" the instruction
924 * or directly match lots of bits. In this case, matching lots of
925 * bits is faster and easier.
928 static int emulate_string_inst(struct pt_regs
*regs
, u32 instword
)
930 u8 rT
= (instword
>> 21) & 0x1f;
931 u8 rA
= (instword
>> 16) & 0x1f;
932 u8 NB_RB
= (instword
>> 11) & 0x1f;
937 /* Early out if we are an invalid form of lswx */
938 if ((instword
& PPC_INST_STRING_MASK
) == PPC_INST_LSWX
)
939 if ((rT
== rA
) || (rT
== NB_RB
))
942 EA
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
944 switch (instword
& PPC_INST_STRING_MASK
) {
948 num_bytes
= regs
->xer
& 0x7f;
952 num_bytes
= (NB_RB
== 0) ? 32 : NB_RB
;
958 while (num_bytes
!= 0)
961 u32 shift
= 8 * (3 - (pos
& 0x3));
963 /* if process is 32-bit, clear upper 32 bits of EA */
964 if ((regs
->msr
& MSR_64BIT
) == 0)
967 switch ((instword
& PPC_INST_STRING_MASK
)) {
970 if (get_user(val
, (u8 __user
*)EA
))
972 /* first time updating this reg,
976 regs
->gpr
[rT
] |= val
<< shift
;
980 val
= regs
->gpr
[rT
] >> shift
;
981 if (put_user(val
, (u8 __user
*)EA
))
985 /* move EA to next address */
989 /* manage our position within the register */
1000 static int emulate_popcntb_inst(struct pt_regs
*regs
, u32 instword
)
1005 ra
= (instword
>> 16) & 0x1f;
1006 rs
= (instword
>> 21) & 0x1f;
1008 tmp
= regs
->gpr
[rs
];
1009 tmp
= tmp
- ((tmp
>> 1) & 0x5555555555555555ULL
);
1010 tmp
= (tmp
& 0x3333333333333333ULL
) + ((tmp
>> 2) & 0x3333333333333333ULL
);
1011 tmp
= (tmp
+ (tmp
>> 4)) & 0x0f0f0f0f0f0f0f0fULL
;
1012 regs
->gpr
[ra
] = tmp
;
1017 static int emulate_isel(struct pt_regs
*regs
, u32 instword
)
1019 u8 rT
= (instword
>> 21) & 0x1f;
1020 u8 rA
= (instword
>> 16) & 0x1f;
1021 u8 rB
= (instword
>> 11) & 0x1f;
1022 u8 BC
= (instword
>> 6) & 0x1f;
1026 tmp
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
1027 bit
= (regs
->ccr
>> (31 - BC
)) & 0x1;
1029 regs
->gpr
[rT
] = bit
? tmp
: regs
->gpr
[rB
];
1034 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1035 static inline bool tm_abort_check(struct pt_regs
*regs
, int cause
)
1037 /* If we're emulating a load/store in an active transaction, we cannot
1038 * emulate it as the kernel operates in transaction suspended context.
1039 * We need to abort the transaction. This creates a persistent TM
1040 * abort so tell the user what caused it with a new code.
1042 if (MSR_TM_TRANSACTIONAL(regs
->msr
)) {
1050 static inline bool tm_abort_check(struct pt_regs
*regs
, int reason
)
1056 static int emulate_instruction(struct pt_regs
*regs
)
1061 if (!user_mode(regs
))
1063 CHECK_FULL_REGS(regs
);
1065 if (get_user(instword
, (u32 __user
*)(regs
->nip
)))
1068 /* Emulate the mfspr rD, PVR. */
1069 if ((instword
& PPC_INST_MFSPR_PVR_MASK
) == PPC_INST_MFSPR_PVR
) {
1070 PPC_WARN_EMULATED(mfpvr
, regs
);
1071 rd
= (instword
>> 21) & 0x1f;
1072 regs
->gpr
[rd
] = mfspr(SPRN_PVR
);
1076 /* Emulating the dcba insn is just a no-op. */
1077 if ((instword
& PPC_INST_DCBA_MASK
) == PPC_INST_DCBA
) {
1078 PPC_WARN_EMULATED(dcba
, regs
);
1082 /* Emulate the mcrxr insn. */
1083 if ((instword
& PPC_INST_MCRXR_MASK
) == PPC_INST_MCRXR
) {
1084 int shift
= (instword
>> 21) & 0x1c;
1085 unsigned long msk
= 0xf0000000UL
>> shift
;
1087 PPC_WARN_EMULATED(mcrxr
, regs
);
1088 regs
->ccr
= (regs
->ccr
& ~msk
) | ((regs
->xer
>> shift
) & msk
);
1089 regs
->xer
&= ~0xf0000000UL
;
1093 /* Emulate load/store string insn. */
1094 if ((instword
& PPC_INST_STRING_GEN_MASK
) == PPC_INST_STRING
) {
1095 if (tm_abort_check(regs
,
1096 TM_CAUSE_EMULATE
| TM_CAUSE_PERSISTENT
))
1098 PPC_WARN_EMULATED(string
, regs
);
1099 return emulate_string_inst(regs
, instword
);
1102 /* Emulate the popcntb (Population Count Bytes) instruction. */
1103 if ((instword
& PPC_INST_POPCNTB_MASK
) == PPC_INST_POPCNTB
) {
1104 PPC_WARN_EMULATED(popcntb
, regs
);
1105 return emulate_popcntb_inst(regs
, instword
);
1108 /* Emulate isel (Integer Select) instruction */
1109 if ((instword
& PPC_INST_ISEL_MASK
) == PPC_INST_ISEL
) {
1110 PPC_WARN_EMULATED(isel
, regs
);
1111 return emulate_isel(regs
, instword
);
1114 /* Emulate sync instruction variants */
1115 if ((instword
& PPC_INST_SYNC_MASK
) == PPC_INST_SYNC
) {
1116 PPC_WARN_EMULATED(sync
, regs
);
1117 asm volatile("sync");
1122 /* Emulate the mfspr rD, DSCR. */
1123 if ((((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
) ==
1124 PPC_INST_MFSPR_DSCR_USER
) ||
1125 ((instword
& PPC_INST_MFSPR_DSCR_MASK
) ==
1126 PPC_INST_MFSPR_DSCR
)) &&
1127 cpu_has_feature(CPU_FTR_DSCR
)) {
1128 PPC_WARN_EMULATED(mfdscr
, regs
);
1129 rd
= (instword
>> 21) & 0x1f;
1130 regs
->gpr
[rd
] = mfspr(SPRN_DSCR
);
1133 /* Emulate the mtspr DSCR, rD. */
1134 if ((((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
) ==
1135 PPC_INST_MTSPR_DSCR_USER
) ||
1136 ((instword
& PPC_INST_MTSPR_DSCR_MASK
) ==
1137 PPC_INST_MTSPR_DSCR
)) &&
1138 cpu_has_feature(CPU_FTR_DSCR
)) {
1139 PPC_WARN_EMULATED(mtdscr
, regs
);
1140 rd
= (instword
>> 21) & 0x1f;
1141 current
->thread
.dscr
= regs
->gpr
[rd
];
1142 current
->thread
.dscr_inherit
= 1;
1143 mtspr(SPRN_DSCR
, current
->thread
.dscr
);
1151 int is_valid_bugaddr(unsigned long addr
)
1153 return is_kernel_addr(addr
);
1156 #ifdef CONFIG_MATH_EMULATION
1157 static int emulate_math(struct pt_regs
*regs
)
1160 extern int do_mathemu(struct pt_regs
*regs
);
1162 ret
= do_mathemu(regs
);
1164 PPC_WARN_EMULATED(math
, regs
);
1168 emulate_single_step(regs
);
1172 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
1173 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1177 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1184 static inline int emulate_math(struct pt_regs
*regs
) { return -1; }
1187 void program_check_exception(struct pt_regs
*regs
)
1189 enum ctx_state prev_state
= exception_enter();
1190 unsigned int reason
= get_reason(regs
);
1192 /* We can now get here via a FP Unavailable exception if the core
1193 * has no FPU, in that case the reason flags will be 0 */
1195 if (reason
& REASON_FP
) {
1196 /* IEEE FP exception */
1200 if (reason
& REASON_TRAP
) {
1201 unsigned long bugaddr
;
1202 /* Debugger is first in line to stop recursive faults in
1203 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1204 if (debugger_bpt(regs
))
1207 if (kprobe_handler(regs
))
1210 /* trap exception */
1211 if (notify_die(DIE_BPT
, "breakpoint", regs
, 5, 5, SIGTRAP
)
1215 bugaddr
= regs
->nip
;
1217 * Fixup bugaddr for BUG_ON() in real mode
1219 if (!is_kernel_addr(bugaddr
) && !(regs
->msr
& MSR_IR
))
1220 bugaddr
+= PAGE_OFFSET
;
1222 if (!(regs
->msr
& MSR_PR
) && /* not user-mode */
1223 report_bug(bugaddr
, regs
) == BUG_TRAP_TYPE_WARN
) {
1227 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1230 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1231 if (reason
& REASON_TM
) {
1232 /* This is a TM "Bad Thing Exception" program check.
1234 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1235 * transition in TM states.
1236 * - A trechkpt is attempted when transactional.
1237 * - A treclaim is attempted when non transactional.
1238 * - A tend is illegally attempted.
1239 * - writing a TM SPR when transactional.
1241 if (!user_mode(regs
) &&
1242 report_bug(regs
->nip
, regs
) == BUG_TRAP_TYPE_WARN
) {
1246 /* If usermode caused this, it's done something illegal and
1247 * gets a SIGILL slap on the wrist. We call it an illegal
1248 * operand to distinguish from the instruction just being bad
1249 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1250 * illegal /placement/ of a valid instruction.
1252 if (user_mode(regs
)) {
1253 _exception(SIGILL
, regs
, ILL_ILLOPN
, regs
->nip
);
1256 printk(KERN_EMERG
"Unexpected TM Bad Thing exception "
1257 "at %lx (msr 0x%x)\n", regs
->nip
, reason
);
1258 die("Unrecoverable exception", regs
, SIGABRT
);
1264 * If we took the program check in the kernel skip down to sending a
1265 * SIGILL. The subsequent cases all relate to emulating instructions
1266 * which we should only do for userspace. We also do not want to enable
1267 * interrupts for kernel faults because that might lead to further
1268 * faults, and loose the context of the original exception.
1270 if (!user_mode(regs
))
1273 /* We restore the interrupt state now */
1274 if (!arch_irq_disabled_regs(regs
))
1277 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1278 * but there seems to be a hardware bug on the 405GP (RevD)
1279 * that means ESR is sometimes set incorrectly - either to
1280 * ESR_DST (!?) or 0. In the process of chasing this with the
1281 * hardware people - not sure if it can happen on any illegal
1282 * instruction or only on FP instructions, whether there is a
1283 * pattern to occurrences etc. -dgibson 31/Mar/2003
1285 if (!emulate_math(regs
))
1288 /* Try to emulate it if we should. */
1289 if (reason
& (REASON_ILLEGAL
| REASON_PRIVILEGED
)) {
1290 switch (emulate_instruction(regs
)) {
1293 emulate_single_step(regs
);
1296 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1302 if (reason
& REASON_PRIVILEGED
)
1303 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1305 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1308 exception_exit(prev_state
);
1310 NOKPROBE_SYMBOL(program_check_exception
);
1313 * This occurs when running in hypervisor mode on POWER6 or later
1314 * and an illegal instruction is encountered.
1316 void emulation_assist_interrupt(struct pt_regs
*regs
)
1318 regs
->msr
|= REASON_ILLEGAL
;
1319 program_check_exception(regs
);
1321 NOKPROBE_SYMBOL(emulation_assist_interrupt
);
1323 void alignment_exception(struct pt_regs
*regs
)
1325 enum ctx_state prev_state
= exception_enter();
1326 int sig
, code
, fixed
= 0;
1328 /* We restore the interrupt state now */
1329 if (!arch_irq_disabled_regs(regs
))
1332 if (tm_abort_check(regs
, TM_CAUSE_ALIGNMENT
| TM_CAUSE_PERSISTENT
))
1335 /* we don't implement logging of alignment exceptions */
1336 if (!(current
->thread
.align_ctl
& PR_UNALIGN_SIGBUS
))
1337 fixed
= fix_alignment(regs
);
1340 regs
->nip
+= 4; /* skip over emulated instruction */
1341 emulate_single_step(regs
);
1345 /* Operand address was bad */
1346 if (fixed
== -EFAULT
) {
1353 if (user_mode(regs
))
1354 _exception(sig
, regs
, code
, regs
->dar
);
1356 bad_page_fault(regs
, regs
->dar
, sig
);
1359 exception_exit(prev_state
);
1362 void slb_miss_bad_addr(struct pt_regs
*regs
)
1364 enum ctx_state prev_state
= exception_enter();
1366 if (user_mode(regs
))
1367 _exception(SIGSEGV
, regs
, SEGV_BNDERR
, regs
->dar
);
1369 bad_page_fault(regs
, regs
->dar
, SIGSEGV
);
1371 exception_exit(prev_state
);
1374 void StackOverflow(struct pt_regs
*regs
)
1376 printk(KERN_CRIT
"Kernel stack overflow in process %p, r1=%lx\n",
1377 current
, regs
->gpr
[1]);
1380 panic("kernel stack overflow");
1383 void nonrecoverable_exception(struct pt_regs
*regs
)
1385 printk(KERN_ERR
"Non-recoverable exception at PC=%lx MSR=%lx\n",
1386 regs
->nip
, regs
->msr
);
1388 die("nonrecoverable exception", regs
, SIGKILL
);
1391 void kernel_fp_unavailable_exception(struct pt_regs
*regs
)
1393 enum ctx_state prev_state
= exception_enter();
1395 printk(KERN_EMERG
"Unrecoverable FP Unavailable Exception "
1396 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1397 die("Unrecoverable FP Unavailable Exception", regs
, SIGABRT
);
1399 exception_exit(prev_state
);
1402 void altivec_unavailable_exception(struct pt_regs
*regs
)
1404 enum ctx_state prev_state
= exception_enter();
1406 if (user_mode(regs
)) {
1407 /* A user program has executed an altivec instruction,
1408 but this kernel doesn't support altivec. */
1409 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1413 printk(KERN_EMERG
"Unrecoverable VMX/Altivec Unavailable Exception "
1414 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1415 die("Unrecoverable VMX/Altivec Unavailable Exception", regs
, SIGABRT
);
1418 exception_exit(prev_state
);
1421 void vsx_unavailable_exception(struct pt_regs
*regs
)
1423 if (user_mode(regs
)) {
1424 /* A user program has executed an vsx instruction,
1425 but this kernel doesn't support vsx. */
1426 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1430 printk(KERN_EMERG
"Unrecoverable VSX Unavailable Exception "
1431 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1432 die("Unrecoverable VSX Unavailable Exception", regs
, SIGABRT
);
1436 static void tm_unavailable(struct pt_regs
*regs
)
1438 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1439 if (user_mode(regs
)) {
1440 current
->thread
.load_tm
++;
1441 regs
->msr
|= MSR_TM
;
1443 tm_restore_sprs(¤t
->thread
);
1447 pr_emerg("Unrecoverable TM Unavailable Exception "
1448 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1449 die("Unrecoverable TM Unavailable Exception", regs
, SIGABRT
);
1452 void facility_unavailable_exception(struct pt_regs
*regs
)
1454 static char *facility_strings
[] = {
1455 [FSCR_FP_LG
] = "FPU",
1456 [FSCR_VECVSX_LG
] = "VMX/VSX",
1457 [FSCR_DSCR_LG
] = "DSCR",
1458 [FSCR_PM_LG
] = "PMU SPRs",
1459 [FSCR_BHRB_LG
] = "BHRB",
1460 [FSCR_TM_LG
] = "TM",
1461 [FSCR_EBB_LG
] = "EBB",
1462 [FSCR_TAR_LG
] = "TAR",
1463 [FSCR_MSGP_LG
] = "MSGP",
1464 [FSCR_SCV_LG
] = "SCV",
1466 char *facility
= "unknown";
1472 hv
= (regs
->trap
== 0xf80);
1474 value
= mfspr(SPRN_HFSCR
);
1476 value
= mfspr(SPRN_FSCR
);
1478 status
= value
>> 56;
1479 if (status
== FSCR_DSCR_LG
) {
1481 * User is accessing the DSCR register using the problem
1482 * state only SPR number (0x03) either through a mfspr or
1483 * a mtspr instruction. If it is a write attempt through
1484 * a mtspr, then we set the inherit bit. This also allows
1485 * the user to write or read the register directly in the
1486 * future by setting via the FSCR DSCR bit. But in case it
1487 * is a read DSCR attempt through a mfspr instruction, we
1488 * just emulate the instruction instead. This code path will
1489 * always emulate all the mfspr instructions till the user
1490 * has attempted at least one mtspr instruction. This way it
1491 * preserves the same behaviour when the user is accessing
1492 * the DSCR through privilege level only SPR number (0x11)
1493 * which is emulated through illegal instruction exception.
1494 * We always leave HFSCR DSCR set.
1496 if (get_user(instword
, (u32 __user
*)(regs
->nip
))) {
1497 pr_err("Failed to fetch the user instruction\n");
1501 /* Write into DSCR (mtspr 0x03, RS) */
1502 if ((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
)
1503 == PPC_INST_MTSPR_DSCR_USER
) {
1504 rd
= (instword
>> 21) & 0x1f;
1505 current
->thread
.dscr
= regs
->gpr
[rd
];
1506 current
->thread
.dscr_inherit
= 1;
1507 current
->thread
.fscr
|= FSCR_DSCR
;
1508 mtspr(SPRN_FSCR
, current
->thread
.fscr
);
1511 /* Read from DSCR (mfspr RT, 0x03) */
1512 if ((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
)
1513 == PPC_INST_MFSPR_DSCR_USER
) {
1514 if (emulate_instruction(regs
)) {
1515 pr_err("DSCR based mfspr emulation failed\n");
1519 emulate_single_step(regs
);
1524 if (status
== FSCR_TM_LG
) {
1526 * If we're here then the hardware is TM aware because it
1527 * generated an exception with FSRM_TM set.
1529 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1530 * told us not to do TM, or the kernel is not built with TM
1533 * If both of those things are true, then userspace can spam the
1534 * console by triggering the printk() below just by continually
1535 * doing tbegin (or any TM instruction). So in that case just
1536 * send the process a SIGILL immediately.
1538 if (!cpu_has_feature(CPU_FTR_TM
))
1541 tm_unavailable(regs
);
1545 if ((hv
|| status
>= 2) &&
1546 (status
< ARRAY_SIZE(facility_strings
)) &&
1547 facility_strings
[status
])
1548 facility
= facility_strings
[status
];
1550 /* We restore the interrupt state now */
1551 if (!arch_irq_disabled_regs(regs
))
1554 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1555 hv
? "Hypervisor " : "", facility
, status
, regs
->nip
, regs
->msr
);
1558 if (user_mode(regs
)) {
1559 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1563 die("Unexpected facility unavailable exception", regs
, SIGABRT
);
1567 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1569 void fp_unavailable_tm(struct pt_regs
*regs
)
1571 /* Note: This does not handle any kind of FP laziness. */
1573 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1574 regs
->nip
, regs
->msr
);
1576 /* We can only have got here if the task started using FP after
1577 * beginning the transaction. So, the transactional regs are just a
1578 * copy of the checkpointed ones. But, we still need to recheckpoint
1579 * as we're enabling FP for the process; it will return, abort the
1580 * transaction, and probably retry but now with FP enabled. So the
1581 * checkpointed FP registers need to be loaded.
1583 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1584 /* Reclaim didn't save out any FPRs to transact_fprs. */
1586 /* Enable FP for the task: */
1587 regs
->msr
|= (MSR_FP
| current
->thread
.fpexc_mode
);
1589 /* This loads and recheckpoints the FP registers from
1590 * thread.fpr[]. They will remain in registers after the
1591 * checkpoint so we don't need to reload them after.
1592 * If VMX is in use, the VRs now hold checkpointed values,
1593 * so we don't want to load the VRs from the thread_struct.
1595 tm_recheckpoint(¤t
->thread
, MSR_FP
);
1597 /* If VMX is in use, get the transactional values back */
1598 if (regs
->msr
& MSR_VEC
) {
1599 msr_check_and_set(MSR_VEC
);
1600 load_vr_state(¤t
->thread
.vr_state
);
1601 /* At this point all the VSX state is loaded, so enable it */
1602 regs
->msr
|= MSR_VSX
;
1606 void altivec_unavailable_tm(struct pt_regs
*regs
)
1608 /* See the comments in fp_unavailable_tm(). This function operates
1612 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1614 regs
->nip
, regs
->msr
);
1615 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1616 regs
->msr
|= MSR_VEC
;
1617 tm_recheckpoint(¤t
->thread
, MSR_VEC
);
1618 current
->thread
.used_vr
= 1;
1620 if (regs
->msr
& MSR_FP
) {
1621 msr_check_and_set(MSR_FP
);
1622 load_fp_state(¤t
->thread
.fp_state
);
1623 regs
->msr
|= MSR_VSX
;
1627 void vsx_unavailable_tm(struct pt_regs
*regs
)
1629 unsigned long orig_msr
= regs
->msr
;
1631 /* See the comments in fp_unavailable_tm(). This works similarly,
1632 * though we're loading both FP and VEC registers in here.
1634 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1635 * regs. Either way, set MSR_VSX.
1638 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1640 regs
->nip
, regs
->msr
);
1642 current
->thread
.used_vsr
= 1;
1644 /* If FP and VMX are already loaded, we have all the state we need */
1645 if ((orig_msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
)) {
1646 regs
->msr
|= MSR_VSX
;
1650 /* This reclaims FP and/or VR regs if they're already enabled */
1651 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1653 regs
->msr
|= MSR_VEC
| MSR_FP
| current
->thread
.fpexc_mode
|
1656 /* This loads & recheckpoints FP and VRs; but we have
1657 * to be sure not to overwrite previously-valid state.
1659 tm_recheckpoint(¤t
->thread
, regs
->msr
& ~orig_msr
);
1661 msr_check_and_set(orig_msr
& (MSR_FP
| MSR_VEC
));
1663 if (orig_msr
& MSR_FP
)
1664 load_fp_state(¤t
->thread
.fp_state
);
1665 if (orig_msr
& MSR_VEC
)
1666 load_vr_state(¤t
->thread
.vr_state
);
1668 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1670 void performance_monitor_exception(struct pt_regs
*regs
)
1672 __this_cpu_inc(irq_stat
.pmu_irqs
);
1678 void SoftwareEmulation(struct pt_regs
*regs
)
1680 CHECK_FULL_REGS(regs
);
1682 if (!user_mode(regs
)) {
1684 die("Kernel Mode Unimplemented Instruction or SW FPU Emulation",
1688 if (!emulate_math(regs
))
1691 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1693 #endif /* CONFIG_8xx */
1695 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1696 static void handle_debug(struct pt_regs
*regs
, unsigned long debug_status
)
1700 * Determine the cause of the debug event, clear the
1701 * event flags and send a trap to the handler. Torez
1703 if (debug_status
& (DBSR_DAC1R
| DBSR_DAC1W
)) {
1704 dbcr_dac(current
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
1705 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1706 current
->thread
.debug
.dbcr2
&= ~DBCR2_DAC12MODE
;
1708 do_send_trap(regs
, mfspr(SPRN_DAC1
), debug_status
, TRAP_HWBKPT
,
1711 } else if (debug_status
& (DBSR_DAC2R
| DBSR_DAC2W
)) {
1712 dbcr_dac(current
) &= ~(DBCR_DAC2R
| DBCR_DAC2W
);
1713 do_send_trap(regs
, mfspr(SPRN_DAC2
), debug_status
, TRAP_HWBKPT
,
1716 } else if (debug_status
& DBSR_IAC1
) {
1717 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC1
;
1718 dbcr_iac_range(current
) &= ~DBCR_IAC12MODE
;
1719 do_send_trap(regs
, mfspr(SPRN_IAC1
), debug_status
, TRAP_HWBKPT
,
1722 } else if (debug_status
& DBSR_IAC2
) {
1723 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC2
;
1724 do_send_trap(regs
, mfspr(SPRN_IAC2
), debug_status
, TRAP_HWBKPT
,
1727 } else if (debug_status
& DBSR_IAC3
) {
1728 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC3
;
1729 dbcr_iac_range(current
) &= ~DBCR_IAC34MODE
;
1730 do_send_trap(regs
, mfspr(SPRN_IAC3
), debug_status
, TRAP_HWBKPT
,
1733 } else if (debug_status
& DBSR_IAC4
) {
1734 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC4
;
1735 do_send_trap(regs
, mfspr(SPRN_IAC4
), debug_status
, TRAP_HWBKPT
,
1740 * At the point this routine was called, the MSR(DE) was turned off.
1741 * Check all other debug flags and see if that bit needs to be turned
1744 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1745 current
->thread
.debug
.dbcr1
))
1746 regs
->msr
|= MSR_DE
;
1748 /* Make sure the IDM flag is off */
1749 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1752 mtspr(SPRN_DBCR0
, current
->thread
.debug
.dbcr0
);
1755 void DebugException(struct pt_regs
*regs
, unsigned long debug_status
)
1757 current
->thread
.debug
.dbsr
= debug_status
;
1759 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1760 * on server, it stops on the target of the branch. In order to simulate
1761 * the server behaviour, we thus restart right away with a single step
1762 * instead of stopping here when hitting a BT
1764 if (debug_status
& DBSR_BT
) {
1765 regs
->msr
&= ~MSR_DE
;
1768 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_BT
);
1769 /* Clear the BT event */
1770 mtspr(SPRN_DBSR
, DBSR_BT
);
1772 /* Do the single step trick only when coming from userspace */
1773 if (user_mode(regs
)) {
1774 current
->thread
.debug
.dbcr0
&= ~DBCR0_BT
;
1775 current
->thread
.debug
.dbcr0
|= DBCR0_IDM
| DBCR0_IC
;
1776 regs
->msr
|= MSR_DE
;
1780 if (kprobe_post_handler(regs
))
1783 if (notify_die(DIE_SSTEP
, "block_step", regs
, 5,
1784 5, SIGTRAP
) == NOTIFY_STOP
) {
1787 if (debugger_sstep(regs
))
1789 } else if (debug_status
& DBSR_IC
) { /* Instruction complete */
1790 regs
->msr
&= ~MSR_DE
;
1792 /* Disable instruction completion */
1793 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_IC
);
1794 /* Clear the instruction completion event */
1795 mtspr(SPRN_DBSR
, DBSR_IC
);
1797 if (kprobe_post_handler(regs
))
1800 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
1801 5, SIGTRAP
) == NOTIFY_STOP
) {
1805 if (debugger_sstep(regs
))
1808 if (user_mode(regs
)) {
1809 current
->thread
.debug
.dbcr0
&= ~DBCR0_IC
;
1810 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1811 current
->thread
.debug
.dbcr1
))
1812 regs
->msr
|= MSR_DE
;
1814 /* Make sure the IDM bit is off */
1815 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1818 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
1820 handle_debug(regs
, debug_status
);
1822 NOKPROBE_SYMBOL(DebugException
);
1823 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1825 #if !defined(CONFIG_TAU_INT)
1826 void TAUException(struct pt_regs
*regs
)
1828 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1829 regs
->nip
, regs
->msr
, regs
->trap
, print_tainted());
1831 #endif /* CONFIG_INT_TAU */
1833 #ifdef CONFIG_ALTIVEC
1834 void altivec_assist_exception(struct pt_regs
*regs
)
1838 if (!user_mode(regs
)) {
1839 printk(KERN_EMERG
"VMX/Altivec assist exception in kernel mode"
1840 " at %lx\n", regs
->nip
);
1841 die("Kernel VMX/Altivec assist exception", regs
, SIGILL
);
1844 flush_altivec_to_thread(current
);
1846 PPC_WARN_EMULATED(altivec
, regs
);
1847 err
= emulate_altivec(regs
);
1849 regs
->nip
+= 4; /* skip emulated instruction */
1850 emulate_single_step(regs
);
1854 if (err
== -EFAULT
) {
1855 /* got an error reading the instruction */
1856 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1858 /* didn't recognize the instruction */
1859 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1860 printk_ratelimited(KERN_ERR
"Unrecognized altivec instruction "
1861 "in %s at %lx\n", current
->comm
, regs
->nip
);
1862 current
->thread
.vr_state
.vscr
.u
[3] |= 0x10000;
1865 #endif /* CONFIG_ALTIVEC */
1867 #ifdef CONFIG_FSL_BOOKE
1868 void CacheLockingException(struct pt_regs
*regs
, unsigned long address
,
1869 unsigned long error_code
)
1871 /* We treat cache locking instructions from the user
1872 * as priv ops, in the future we could try to do
1875 if (error_code
& (ESR_DLK
|ESR_ILK
))
1876 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1879 #endif /* CONFIG_FSL_BOOKE */
1882 void SPEFloatingPointException(struct pt_regs
*regs
)
1884 extern int do_spe_mathemu(struct pt_regs
*regs
);
1885 unsigned long spefscr
;
1890 flush_spe_to_thread(current
);
1892 spefscr
= current
->thread
.spefscr
;
1893 fpexc_mode
= current
->thread
.fpexc_mode
;
1895 if ((spefscr
& SPEFSCR_FOVF
) && (fpexc_mode
& PR_FP_EXC_OVF
)) {
1898 else if ((spefscr
& SPEFSCR_FUNF
) && (fpexc_mode
& PR_FP_EXC_UND
)) {
1901 else if ((spefscr
& SPEFSCR_FDBZ
) && (fpexc_mode
& PR_FP_EXC_DIV
))
1903 else if ((spefscr
& SPEFSCR_FINV
) && (fpexc_mode
& PR_FP_EXC_INV
)) {
1906 else if ((spefscr
& (SPEFSCR_FG
| SPEFSCR_FX
)) && (fpexc_mode
& PR_FP_EXC_RES
))
1909 err
= do_spe_mathemu(regs
);
1911 regs
->nip
+= 4; /* skip emulated instruction */
1912 emulate_single_step(regs
);
1916 if (err
== -EFAULT
) {
1917 /* got an error reading the instruction */
1918 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1919 } else if (err
== -EINVAL
) {
1920 /* didn't recognize the instruction */
1921 printk(KERN_ERR
"unrecognized spe instruction "
1922 "in %s at %lx\n", current
->comm
, regs
->nip
);
1924 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1930 void SPEFloatingPointRoundException(struct pt_regs
*regs
)
1932 extern int speround_handler(struct pt_regs
*regs
);
1936 if (regs
->msr
& MSR_SPE
)
1937 giveup_spe(current
);
1941 err
= speround_handler(regs
);
1943 regs
->nip
+= 4; /* skip emulated instruction */
1944 emulate_single_step(regs
);
1948 if (err
== -EFAULT
) {
1949 /* got an error reading the instruction */
1950 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1951 } else if (err
== -EINVAL
) {
1952 /* didn't recognize the instruction */
1953 printk(KERN_ERR
"unrecognized spe instruction "
1954 "in %s at %lx\n", current
->comm
, regs
->nip
);
1956 _exception(SIGFPE
, regs
, 0, regs
->nip
);
1963 * We enter here if we get an unrecoverable exception, that is, one
1964 * that happened at a point where the RI (recoverable interrupt) bit
1965 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1966 * we therefore lost state by taking this exception.
1968 void unrecoverable_exception(struct pt_regs
*regs
)
1970 printk(KERN_EMERG
"Unrecoverable exception %lx at %lx\n",
1971 regs
->trap
, regs
->nip
);
1972 die("Unrecoverable exception", regs
, SIGABRT
);
1974 NOKPROBE_SYMBOL(unrecoverable_exception
);
1976 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1978 * Default handler for a Watchdog exception,
1979 * spins until a reboot occurs
1981 void __attribute__ ((weak
)) WatchdogHandler(struct pt_regs
*regs
)
1983 /* Generic WatchdogHandler, implement your own */
1984 mtspr(SPRN_TCR
, mfspr(SPRN_TCR
)&(~TCR_WIE
));
1988 void WatchdogException(struct pt_regs
*regs
)
1990 printk (KERN_EMERG
"PowerPC Book-E Watchdog Exception\n");
1991 WatchdogHandler(regs
);
1996 * We enter here if we discover during exception entry that we are
1997 * running in supervisor mode with a userspace value in the stack pointer.
1999 void kernel_bad_stack(struct pt_regs
*regs
)
2001 printk(KERN_EMERG
"Bad kernel stack pointer %lx at %lx\n",
2002 regs
->gpr
[1], regs
->nip
);
2003 die("Bad kernel stack pointer", regs
, SIGABRT
);
2005 NOKPROBE_SYMBOL(kernel_bad_stack
);
2007 void __init
trap_init(void)
2012 #ifdef CONFIG_PPC_EMULATED_STATS
2014 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
2016 struct ppc_emulated ppc_emulated
= {
2017 #ifdef CONFIG_ALTIVEC
2018 WARN_EMULATED_SETUP(altivec
),
2020 WARN_EMULATED_SETUP(dcba
),
2021 WARN_EMULATED_SETUP(dcbz
),
2022 WARN_EMULATED_SETUP(fp_pair
),
2023 WARN_EMULATED_SETUP(isel
),
2024 WARN_EMULATED_SETUP(mcrxr
),
2025 WARN_EMULATED_SETUP(mfpvr
),
2026 WARN_EMULATED_SETUP(multiple
),
2027 WARN_EMULATED_SETUP(popcntb
),
2028 WARN_EMULATED_SETUP(spe
),
2029 WARN_EMULATED_SETUP(string
),
2030 WARN_EMULATED_SETUP(sync
),
2031 WARN_EMULATED_SETUP(unaligned
),
2032 #ifdef CONFIG_MATH_EMULATION
2033 WARN_EMULATED_SETUP(math
),
2036 WARN_EMULATED_SETUP(vsx
),
2039 WARN_EMULATED_SETUP(mfdscr
),
2040 WARN_EMULATED_SETUP(mtdscr
),
2041 WARN_EMULATED_SETUP(lq_stq
),
2045 u32 ppc_warn_emulated
;
2047 void ppc_warn_emulated_print(const char *type
)
2049 pr_warn_ratelimited("%s used emulated %s instruction\n", current
->comm
,
2053 static int __init
ppc_warn_emulated_init(void)
2055 struct dentry
*dir
, *d
;
2057 struct ppc_emulated_entry
*entries
= (void *)&ppc_emulated
;
2059 if (!powerpc_debugfs_root
)
2062 dir
= debugfs_create_dir("emulated_instructions",
2063 powerpc_debugfs_root
);
2067 d
= debugfs_create_u32("do_warn", S_IRUGO
| S_IWUSR
, dir
,
2068 &ppc_warn_emulated
);
2072 for (i
= 0; i
< sizeof(ppc_emulated
)/sizeof(*entries
); i
++) {
2073 d
= debugfs_create_u32(entries
[i
].name
, S_IRUGO
| S_IWUSR
, dir
,
2074 (u32
*)&entries
[i
].val
.counter
);
2082 debugfs_remove_recursive(dir
);
2086 device_initcall(ppc_warn_emulated_init
);
2088 #endif /* CONFIG_PPC_EMULATED_STATS */