arch/powerpc/platforms/chrp/setup.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  *  Adapted from 'alpha' version by Gary Thomas
   4  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   5  */
   6
   7 /*
   8  * bootup setup stuff..
   9  */
  10
  11 #include <linux/errno.h>
  12 #include <linux/sched.h>
  13 #include <linux/kernel.h>
  14 #include <linux/mm.h>
  15 #include <linux/stddef.h>
  16 #include <linux/unistd.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/slab.h>
  19 #include <linux/user.h>
  20 #include <linux/a.out.h>
  21 #include <linux/tty.h>
  22 #include <linux/major.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/reboot.h>
  25 #include <linux/init.h>
  26 #include <linux/pci.h>
  27 #include <linux/utsrelease.h>
  28 #include <linux/adb.h>
  29 #include <linux/module.h>
  30 #include <linux/delay.h>
  31 #include <linux/console.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/root_dev.h>
  34 #include <linux/initrd.h>
  35 #include <linux/timer.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/prom.h>
  40 #include <asm/pci-bridge.h>
  41 #include <asm/dma.h>
  42 #include <asm/machdep.h>
  43 #include <asm/irq.h>
  44 #include <asm/hydra.h>
  45 #include <asm/sections.h>
  46 #include <asm/time.h>
  47 #include <asm/i8259.h>
  48 #include <asm/mpic.h>
  49 #include <asm/rtas.h>
  50 #include <asm/xmon.h>
  51
  52 #include "chrp.h"
  53 #include "gg2.h"
  54
  55 void rtas_indicator_progress(char *, unsigned short);
  56
  57 int _chrp_type;
  58 EXPORT_SYMBOL(_chrp_type);
  59
  60 static struct mpic *chrp_mpic;
  61
  62 /* Used for doing CHRP event-scans */
  63 DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
  64 unsigned long event_scan_interval;
  65
  66 extern unsigned long loops_per_jiffy;
  67
  68 /* To be replaced by RTAS when available */
  69 static unsigned int __iomem *briq_SPOR;
  70
  71 #ifdef CONFIG_SMP
  72 extern struct smp_ops_t chrp_smp_ops;
  73 #endif
  74
  75 static const char *gg2_memtypes[4] = {
  76         "FPM", "SDRAM", "EDO", "BEDO"
  77 };
  78 static const char *gg2_cachesizes[4] = {
  79         "256 KB", "512 KB", "1 MB", "Reserved"
  80 };
  81 static const char *gg2_cachetypes[4] = {
  82         "Asynchronous", "Reserved", "Flow-Through Synchronous",
  83         "Pipelined Synchronous"
  84 };
  85 static const char *gg2_cachemodes[4] = {
  86         "Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
  87 };
  88
  89 static const char *chrp_names[] = {
  90         "Unknown",
  91         "","","",
  92         "Motorola",
  93         "IBM or Longtrail",
  94         "Genesi Pegasos",
  95         "Total Impact Briq"
  96 };
  97
  98 void chrp_show_cpuinfo(struct seq_file *m)
  99 {
 100         int i, sdramen;
 101         unsigned int t;
 102         struct device_node *root;
 103         const char *model = "";
 104
 105         root = of_find_node_by_path("/");
 106         if (root)
 107                 model = of_get_property(root, "model", NULL);
 108         seq_printf(m, "machine\t\t: CHRP %s\n", model);
 109
 110         /* longtrail (goldengate) stuff */
 111         if (model && !strncmp(model, "IBM,LongTrail", 13)) {
 112                 /* VLSI VAS96011/12 `Golden Gate 2' */
 113                 /* Memory banks */
 114                 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
 115                            >>31) & 1;
 116                 for (i = 0; i < (sdramen ? 4 : 6); i++) {
 117                         t = in_le32(gg2_pci_config_base+
 118                                                  GG2_PCI_DRAM_BANK0+
 119                                                  i*4);
 120                         if (!(t & 1))
 121                                 continue;
 122                         switch ((t>>8) & 0x1f) {
 123                         case 0x1f:
 124                                 model = "4 MB";
 125                                 break;
 126                         case 0x1e:
 127                                 model = "8 MB";
 128                                 break;
 129                         case 0x1c:
 130                                 model = "16 MB";
 131                                 break;
 132                         case 0x18:
 133                                 model = "32 MB";
 134                                 break;
 135                         case 0x10:
 136                                 model = "64 MB";
 137                                 break;
 138                         case 0x00:
 139                                 model = "128 MB";
 140                                 break;
 141                         default:
 142                                 model = "Reserved";
 143                                 break;
 144                         }
 145                         seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
 146                                    gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
 147                 }
 148                 /* L2 cache */
 149                 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
 150                 seq_printf(m, "board l2\t: %s %s (%s)\n",
 151                            gg2_cachesizes[(t>>7) & 3],
 152                            gg2_cachetypes[(t>>2) & 3],
 153                            gg2_cachemodes[t & 3]);
 154         }
 155         of_node_put(root);
 156 }
 157
 158 /*
 159  *  Fixes for the National Semiconductor PC78308VUL SuperI/O
 160  *
 161  *  Some versions of Open Firmware incorrectly initialize the IRQ settings
 162  *  for keyboard and mouse
 163  */
 164 static inline void __init sio_write(u8 val, u8 index)
 165 {
 166         outb(index, 0x15c);
 167         outb(val, 0x15d);
 168 }
 169
 170 static inline u8 __init sio_read(u8 index)
 171 {
 172         outb(index, 0x15c);
 173         return inb(0x15d);
 174 }
 175
 176 static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
 177                                      u8 type)
 178 {
 179         u8 level0, type0, active;
 180
 181         /* select logical device */
 182         sio_write(device, 0x07);
 183         active = sio_read(0x30);
 184         level0 = sio_read(0x70);
 185         type0 = sio_read(0x71);
 186         if (level0 != level || type0 != type || !active) {
 187                 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
 188                        "remapping to level %d, type %d, active\n",
 189                        name, level0, type0, !active ? "in" : "", level, type);
 190                 sio_write(0x01, 0x30);
 191                 sio_write(level, 0x70);
 192                 sio_write(type, 0x71);
 193         }
 194 }
 195
 196 static void __init sio_init(void)
 197 {
 198         struct device_node *root;
 199         const char *model;
 200
 201         root = of_find_node_by_path("/");
 202         if (!root)
 203                 return;
 204
 205         model = of_get_property(root, "model", NULL);
 206         if (model && !strncmp(model, "IBM,LongTrail", 13)) {
 207                 /* logical device 0 (KBC/Keyboard) */
 208                 sio_fixup_irq("keyboard", 0, 1, 2);
 209                 /* select logical device 1 (KBC/Mouse) */
 210                 sio_fixup_irq("mouse", 1, 12, 2);
 211         }
 212
 213         of_node_put(root);
 214 }
 215
 216
 217 static void __init pegasos_set_l2cr(void)
 218 {
 219         struct device_node *np;
 220
 221         /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
 222         if (_chrp_type != _CHRP_Pegasos)
 223                 return;
 224
 225         /* Enable L2 cache if needed */
 226         np = of_find_node_by_type(NULL, "cpu");
 227         if (np != NULL) {
 228                 const unsigned int *l2cr = of_get_property(np, "l2cr", NULL);
 229                 if (l2cr == NULL) {
 230                         printk ("Pegasos l2cr : no cpu l2cr property found\n");
 231                         goto out;
 232                 }
 233                 if (!((*l2cr) & 0x80000000)) {
 234                         printk ("Pegasos l2cr : L2 cache was not active, "
 235                                 "activating\n");
 236                         _set_L2CR(0);
 237                         _set_L2CR((*l2cr) | 0x80000000);
 238                 }
 239         }
 240 out:
 241         of_node_put(np);
 242 }
 243
 244 static void briq_restart(char *cmd)
 245 {
 246         local_irq_disable();
 247         if (briq_SPOR)
 248                 out_be32(briq_SPOR, 0);
 249         for(;;);
 250 }
 251
 252 /*
 253  * Per default, input/output-device points to the keyboard/screen
 254  * If no card is installed, the built-in serial port is used as a fallback.
 255  * But unfortunately, the firmware does not connect /chosen/{stdin,stdout}
 256  * the the built-in serial node. Instead, a /failsafe node is created.
 257  */
 258 static void chrp_init_early(void)
 259 {
 260         struct device_node *node;
 261         const char *property;
 262
 263         if (strstr(cmd_line, "console="))
 264                 return;
 265         /* find the boot console from /chosen/stdout */
 266         if (!of_chosen)
 267                 return;
 268         node = of_find_node_by_path("/");
 269         if (!node)
 270                 return;
 271         property = of_get_property(node, "model", NULL);
 272         if (!property)
 273                 goto out_put;
 274         if (strcmp(property, "Pegasos2"))
 275                 goto out_put;
 276         /* this is a Pegasos2 */
 277         property = of_get_property(of_chosen, "linux,stdout-path", NULL);
 278         if (!property)
 279                 goto out_put;
 280         of_node_put(node);
 281         node = of_find_node_by_path(property);
 282         if (!node)
 283                 return;
 284         property = of_get_property(node, "device_type", NULL);
 285         if (!property)
 286                 goto out_put;
 287         if (strcmp(property, "serial"))
 288                 goto out_put;
 289         /*
 290          * The 9pin connector is either /failsafe
 291          * or /pci@80000000/isa@C/serial@i2F8
 292          * The optional graphics card has also type 'serial' in VGA mode.
 293          */
 294         property = of_get_property(node, "name", NULL);
 295         if (!property)
 296                 goto out_put;
 297         if (!strcmp(property, "failsafe") || !strcmp(property, "serial"))
 298                 add_preferred_console("ttyS", 0, NULL);
 299 out_put:
 300         of_node_put(node);
 301 }
 302
 303 void __init chrp_setup_arch(void)
 304 {
 305         struct device_node *root = of_find_node_by_path("/");
 306         const char *machine = NULL;
 307
 308         /* init to some ~sane value until calibrate_delay() runs */
 309         loops_per_jiffy = 50000000/HZ;
 310
 311         if (root)
 312                 machine = of_get_property(root, "model", NULL);
 313         if (machine && strncmp(machine, "Pegasos", 7) == 0) {
 314                 _chrp_type = _CHRP_Pegasos;
 315         } else if (machine && strncmp(machine, "IBM", 3) == 0) {
 316                 _chrp_type = _CHRP_IBM;
 317         } else if (machine && strncmp(machine, "MOT", 3) == 0) {
 318                 _chrp_type = _CHRP_Motorola;
 319         } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
 320                 _chrp_type = _CHRP_briq;
 321                 /* Map the SPOR register on briq and change the restart hook */
 322                 briq_SPOR = ioremap(0xff0000e8, 4);
 323                 ppc_md.restart = briq_restart;
 324         } else {
 325                 /* Let's assume it is an IBM chrp if all else fails */
 326                 _chrp_type = _CHRP_IBM;
 327         }
 328         of_node_put(root);
 329         printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
 330
 331         rtas_initialize();
 332         if (rtas_token("display-character") >= 0)
 333                 ppc_md.progress = rtas_progress;
 334
 335         /* use RTAS time-of-day routines if available */
 336         if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
 337                 ppc_md.get_boot_time    = rtas_get_boot_time;
 338                 ppc_md.get_rtc_time     = rtas_get_rtc_time;
 339                 ppc_md.set_rtc_time     = rtas_set_rtc_time;
 340         }
 341
 342         /* On pegasos, enable the L2 cache if not already done by OF */
 343         pegasos_set_l2cr();
 344
 345         /* Lookup PCI host bridges */
 346         chrp_find_bridges();
 347
 348         /*
 349          *  Temporary fixes for PCI devices.
 350          *  -- Geert
 351          */
 352         hydra_init();           /* Mac I/O */
 353
 354         /*
 355          *  Fix the Super I/O configuration
 356          */
 357         sio_init();
 358
 359         pci_create_OF_bus_map();
 360
 361         /*
 362          * Print the banner, then scroll down so boot progress
 363          * can be printed.  -- Cort
 364          */
 365         if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
 366 }
 367
 368 void
 369 chrp_event_scan(unsigned long unused)
 370 {
 371         unsigned char log[1024];
 372         int ret = 0;
 373
 374         /* XXX: we should loop until the hardware says no more error logs -- Cort */
 375         rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
 376                   __pa(log), 1024);
 377         mod_timer(&__get_cpu_var(heartbeat_timer),
 378                   jiffies + event_scan_interval);
 379 }
 380
 381 static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc)
 382 {
 383         unsigned int cascade_irq = i8259_irq();
 384         if (cascade_irq != NO_IRQ)
 385                 generic_handle_irq(cascade_irq);
 386         desc->chip->eoi(irq);
 387 }
 388
 389 /*
 390  * Finds the open-pic node and sets up the mpic driver.
 391  */
 392 static void __init chrp_find_openpic(void)
 393 {
 394         struct device_node *np, *root;
 395         int len, i, j;
 396         int isu_size, idu_size;
 397         const unsigned int *iranges, *opprop = NULL;
 398         int oplen = 0;
 399         unsigned long opaddr;
 400         int na = 1;
 401
 402         np = of_find_node_by_type(NULL, "open-pic");
 403         if (np == NULL)
 404                 return;
 405         root = of_find_node_by_path("/");
 406         if (root) {
 407                 opprop = of_get_property(root, "platform-open-pic", &oplen);
 408                 na = of_n_addr_cells(root);
 409         }
 410         if (opprop && oplen >= na * sizeof(unsigned int)) {
 411                 opaddr = opprop[na-1];  /* assume 32-bit */
 412                 oplen /= na * sizeof(unsigned int);
 413         } else {
 414                 struct resource r;
 415                 if (of_address_to_resource(np, 0, &r)) {
 416                         goto bail;
 417                 }
 418                 opaddr = r.start;
 419                 oplen = 0;
 420         }
 421
 422         printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
 423
 424         iranges = of_get_property(np, "interrupt-ranges", &len);
 425         if (iranges == NULL)
 426                 len = 0;        /* non-distributed mpic */
 427         else
 428                 len /= 2 * sizeof(unsigned int);
 429
 430         /*
 431          * The first pair of cells in interrupt-ranges refers to the
 432          * IDU; subsequent pairs refer to the ISUs.
 433          */
 434         if (oplen < len) {
 435                 printk(KERN_ERR "Insufficient addresses for distributed"
 436                        " OpenPIC (%d < %d)\n", oplen, len);
 437                 len = oplen;
 438         }
 439
 440         isu_size = 0;
 441         idu_size = 0;
 442         if (len > 0 && iranges[1] != 0) {
 443                 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
 444                        iranges[0], iranges[0] + iranges[1] - 1);
 445                 idu_size = iranges[1];
 446         }
 447         if (len > 1)
 448                 isu_size = iranges[3];
 449
 450         chrp_mpic = mpic_alloc(np, opaddr, MPIC_PRIMARY,
 451                                isu_size, 0, " MPIC    ");
 452         if (chrp_mpic == NULL) {
 453                 printk(KERN_ERR "Failed to allocate MPIC structure\n");
 454                 goto bail;
 455         }
 456         j = na - 1;
 457         for (i = 1; i < len; ++i) {
 458                 iranges += 2;
 459                 j += na;
 460                 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
 461                        iranges[0], iranges[0] + iranges[1] - 1,
 462                        opprop[j]);
 463                 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
 464         }
 465
 466         mpic_init(chrp_mpic);
 467         ppc_md.get_irq = mpic_get_irq;
 468  bail:
 469         of_node_put(root);
 470         of_node_put(np);
 471 }
 472
 473 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
 474 static struct irqaction xmon_irqaction = {
 475         .handler = xmon_irq,
 476         .mask = CPU_MASK_NONE,
 477         .name = "XMON break",
 478 };
 479 #endif
 480
 481 static void __init chrp_find_8259(void)
 482 {
 483         struct device_node *np, *pic = NULL;
 484         unsigned long chrp_int_ack = 0;
 485         unsigned int cascade_irq;
 486
 487         /* Look for cascade */
 488         for_each_node_by_type(np, "interrupt-controller")
 489                 if (of_device_is_compatible(np, "chrp,iic")) {
 490                         pic = np;
 491                         break;
 492                 }
 493         /* Ok, 8259 wasn't found. We need to handle the case where
 494          * we have a pegasos that claims to be chrp but doesn't have
 495          * a proper interrupt tree
 496          */
 497         if (pic == NULL && chrp_mpic != NULL) {
 498                 printk(KERN_ERR "i8259: Not found in device-tree"
 499                        " assuming no legacy interrupts\n");
 500                 return;
 501         }
 502
 503         /* Look for intack. In a perfect world, we would look for it on
 504          * the ISA bus that holds the 8259 but heh... Works that way. If
 505          * we ever see a problem, we can try to re-use the pSeries code here.
 506          * Also, Pegasos-type platforms don't have a proper node to start
 507          * from anyway
 508          */
 509         for_each_node_by_name(np, "pci") {
 510                 const unsigned int *addrp = of_get_property(np,
 511                                 "8259-interrupt-acknowledge", NULL);
 512
 513                 if (addrp == NULL)
 514                         continue;
 515                 chrp_int_ack = addrp[of_n_addr_cells(np)-1];
 516                 break;
 517         }
 518         of_node_put(np);
 519         if (np == NULL)
 520                 printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
 521                        " address, polling\n");
 522
 523         i8259_init(pic, chrp_int_ack);
 524         if (ppc_md.get_irq == NULL) {
 525                 ppc_md.get_irq = i8259_irq;
 526                 irq_set_default_host(i8259_get_host());
 527         }
 528         if (chrp_mpic != NULL) {
 529                 cascade_irq = irq_of_parse_and_map(pic, 0);
 530                 if (cascade_irq == NO_IRQ)
 531                         printk(KERN_ERR "i8259: failed to map cascade irq\n");
 532                 else
 533                         set_irq_chained_handler(cascade_irq,
 534                                                 chrp_8259_cascade);
 535         }
 536 }
 537
 538 void __init chrp_init_IRQ(void)
 539 {
 540 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
 541         struct device_node *kbd;
 542 #endif
 543         chrp_find_openpic();
 544         chrp_find_8259();
 545
 546 #ifdef CONFIG_SMP
 547         /* Pegasos has no MPIC, those ops would make it crash. It might be an
 548          * option to move setting them to after we probe the PIC though
 549          */
 550         if (chrp_mpic != NULL)
 551                 smp_ops = &chrp_smp_ops;
 552 #endif /* CONFIG_SMP */
 553
 554         if (_chrp_type == _CHRP_Pegasos)
 555                 ppc_md.get_irq        = i8259_irq;
 556
 557 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
 558         /* see if there is a keyboard in the device tree
 559            with a parent of type "adb" */
 560         for_each_node_by_name(kbd, "keyboard")
 561                 if (kbd->parent && kbd->parent->type
 562                     && strcmp(kbd->parent->type, "adb") == 0)
 563                         break;
 564         of_node_put(kbd);
 565         if (kbd)
 566                 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
 567 #endif
 568 }
 569
 570 void __init
 571 chrp_init2(void)
 572 {
 573         struct device_node *device;
 574         const unsigned int *p = NULL;
 575
 576 #ifdef CONFIG_NVRAM
 577         chrp_nvram_init();
 578 #endif
 579
 580         request_region(0x20,0x20,"pic1");
 581         request_region(0xa0,0x20,"pic2");
 582         request_region(0x00,0x20,"dma1");
 583         request_region(0x40,0x20,"timer");
 584         request_region(0x80,0x10,"dma page reg");
 585         request_region(0xc0,0x20,"dma2");
 586
 587         /* Get the event scan rate for the rtas so we know how
 588          * often it expects a heartbeat. -- Cort
 589          */
 590         device = of_find_node_by_name(NULL, "rtas");
 591         if (device)
 592                 p = of_get_property(device, "rtas-event-scan-rate", NULL);
 593         if (p && *p) {
 594                 /*
 595                  * Arrange to call chrp_event_scan at least *p times
 596                  * per minute.  We use 59 rather than 60 here so that
 597                  * the rate will be slightly higher than the minimum.
 598                  * This all assumes we don't do hotplug CPU on any
 599                  * machine that needs the event scans done.
 600                  */
 601                 unsigned long interval, offset;
 602                 int cpu, ncpus;
 603                 struct timer_list *timer;
 604
 605                 interval = HZ * 59 / *p;
 606                 offset = HZ;
 607                 ncpus = num_online_cpus();
 608                 event_scan_interval = ncpus * interval;
 609                 for (cpu = 0; cpu < ncpus; ++cpu) {
 610                         timer = &per_cpu(heartbeat_timer, cpu);
 611                         setup_timer(timer, chrp_event_scan, 0);
 612                         timer->expires = jiffies + offset;
 613                         add_timer_on(timer, cpu);
 614                         offset += interval;
 615                 }
 616                 printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
 617                        *p, interval);
 618         }
 619         of_node_put(device);
 620
 621         if (ppc_md.progress)
 622                 ppc_md.progress("  Have fun!    ", 0x7777);
 623 }
 624
 625 static int __init chrp_probe(void)
 626 {
 627         char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
 628                                           "device_type", NULL);
 629         if (dtype == NULL)
 630                 return 0;
 631         if (strcmp(dtype, "chrp"))
 632                 return 0;
 633
 634         ISA_DMA_THRESHOLD = ~0L;
 635         DMA_MODE_READ = 0x44;
 636         DMA_MODE_WRITE = 0x48;
 637
 638         return 1;
 639 }
 640
 641 define_machine(chrp) {
 642         .name                   = "CHRP",
 643         .probe                  = chrp_probe,
 644         .setup_arch             = chrp_setup_arch,
 645         .init                   = chrp_init2,
 646         .init_early             = chrp_init_early,
 647         .show_cpuinfo           = chrp_show_cpuinfo,
 648         .init_IRQ               = chrp_init_IRQ,
 649         .restart                = rtas_restart,
 650         .power_off              = rtas_power_off,
 651         .halt                   = rtas_halt,
 652         .time_init              = chrp_time_init,
 653         .set_rtc_time           = chrp_set_rtc_time,
 654         .get_rtc_time           = chrp_get_rtc_time,
 655         .calibrate_decr         = generic_calibrate_decr,
 656         .phys_mem_access_prot   = pci_phys_mem_access_prot,
 657 };