2 * arch/ppc/platforms/4xx/ebony.c
4 * Ebony board specific routines
6 * Matt Porter <mporter@kernel.crashing.org>
7 * Copyright 2002-2005 MontaVista Software Inc.
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003-2005 Zultys Technologies
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/config.h>
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/reboot.h>
24 #include <linux/pci.h>
25 #include <linux/kdev_t.h>
26 #include <linux/types.h>
27 #include <linux/major.h>
28 #include <linux/blkdev.h>
29 #include <linux/console.h>
30 #include <linux/delay.h>
31 #include <linux/ide.h>
32 #include <linux/initrd.h>
33 #include <linux/irq.h>
34 #include <linux/seq_file.h>
35 #include <linux/root_dev.h>
36 #include <linux/tty.h>
37 #include <linux/serial.h>
38 #include <linux/serial_core.h>
40 #include <asm/system.h>
41 #include <asm/pgtable.h>
45 #include <asm/machdep.h>
47 #include <asm/pci-bridge.h>
50 #include <asm/bootinfo.h>
51 #include <asm/ppc4xx_pic.h>
52 #include <asm/ppcboot.h>
53 #include <asm/tlbflush.h>
55 #include <syslib/gen550.h>
56 #include <syslib/ibm440gp_common.h>
59 * This is a horrible kludge, we eventually need to abstract this
60 * generic PHY stuff, so the standard phy mode defines can be
61 * easily used from arch code.
63 #include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
67 static struct ibm44x_clocks clocks __initdata
;
70 * Ebony external IRQ triggering/polarity settings
72 unsigned char ppc4xx_uic_ext_irq_cfg
[] __initdata
= {
73 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ0: PCI slot 0 */
74 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ1: PCI slot 1 */
75 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ2: PCI slot 2 */
76 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ3: PCI slot 3 */
77 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* IRQ4: IRDA */
78 (IRQ_SENSE_EDGE
| IRQ_POLARITY_NEGATIVE
), /* IRQ5: SMI pushbutton */
79 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ6: PHYs */
80 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* IRQ7: AUX */
81 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ8: EXT */
82 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ9: EXT */
83 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ10: EXT */
84 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ11: EXT */
85 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* IRQ12: EXT */
89 ebony_calibrate_decr(void)
94 * Determine system clock speed
96 * If we are on Rev. B silicon, then use
97 * default external system clock. If we are
98 * on Rev. C silicon then errata forces us to
99 * use the internal clock.
101 switch (PVR_REV(mfspr(SPRN_PVR
))) {
102 case PVR_REV(PVR_440GP_RB
):
103 freq
= EBONY_440GP_RB_SYSCLK
;
105 case PVR_REV(PVR_440GP_RC1
):
107 freq
= EBONY_440GP_RC_SYSCLK
;
111 ibm44x_calibrate_decr(freq
);
115 ebony_show_cpuinfo(struct seq_file
*m
)
117 seq_printf(m
, "vendor\t\t: IBM\n");
118 seq_printf(m
, "machine\t\t: Ebony\n");
124 ebony_map_irq(struct pci_dev
*dev
, unsigned char idsel
, unsigned char pin
)
126 static char pci_irq_table
[][4] =
128 * PCI IDSEL/INTPIN->INTLINE
132 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
133 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
134 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
135 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
138 const long min_idsel
= 1, max_idsel
= 4, irqs_per_slot
= 4;
139 return PCI_IRQ_TABLE_LOOKUP
;
142 #define PCIX_WRITEL(value, offset) \
143 (writel(value, pcix_reg_base + offset))
146 * FIXME: This is only here to "make it work". This will move
147 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
148 * configuration library. -Matt
151 ebony_setup_pcix(void)
153 void __iomem
*pcix_reg_base
;
155 pcix_reg_base
= ioremap64(PCIX0_REG_BASE
, PCIX_REG_SIZE
);
157 /* Disable all windows */
158 PCIX_WRITEL(0, PCIX0_POM0SA
);
159 PCIX_WRITEL(0, PCIX0_POM1SA
);
160 PCIX_WRITEL(0, PCIX0_POM2SA
);
161 PCIX_WRITEL(0, PCIX0_PIM0SA
);
162 PCIX_WRITEL(0, PCIX0_PIM1SA
);
163 PCIX_WRITEL(0, PCIX0_PIM2SA
);
165 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
166 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH
);
167 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL
);
168 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH
);
169 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL
);
170 PCIX_WRITEL(0x80000001, PCIX0_POM0SA
);
172 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
173 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH
);
174 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL
);
175 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA
);
181 ebony_setup_hose(void)
183 struct pci_controller
*hose
;
185 /* Configure windows on the PCI-X host bridge */
188 hose
= pcibios_alloc_controller();
193 hose
->first_busno
= 0;
194 hose
->last_busno
= 0xff;
196 hose
->pci_mem_offset
= EBONY_PCI_MEM_OFFSET
;
198 pci_init_resource(&hose
->io_resource
,
204 pci_init_resource(&hose
->mem_resources
[0],
210 hose
->io_space
.start
= EBONY_PCI_LOWER_IO
;
211 hose
->io_space
.end
= EBONY_PCI_UPPER_IO
;
212 hose
->mem_space
.start
= EBONY_PCI_LOWER_MEM
;
213 hose
->mem_space
.end
= EBONY_PCI_UPPER_MEM
;
214 hose
->io_base_virt
= ioremap64(EBONY_PCI_IO_BASE
, EBONY_PCI_IO_SIZE
);
215 isa_io_base
= (unsigned long)hose
->io_base_virt
;
217 setup_indirect_pci(hose
,
218 EBONY_PCI_CFGA_PLB32
,
219 EBONY_PCI_CFGD_PLB32
);
220 hose
->set_cfg_type
= 1;
222 hose
->last_busno
= pciauto_bus_scan(hose
, hose
->first_busno
);
224 ppc_md
.pci_swizzle
= common_swizzle
;
225 ppc_md
.pci_map_irq
= ebony_map_irq
;
231 ebony_early_serial_map(void)
233 struct uart_port port
;
235 /* Setup ioremapped serial port access */
236 memset(&port
, 0, sizeof(port
));
237 port
.membase
= ioremap64(PPC440GP_UART0_ADDR
, 8);
239 port
.uartclk
= clocks
.uart0
;
241 port
.iotype
= SERIAL_IO_MEM
;
242 port
.flags
= ASYNC_BOOT_AUTOCONF
| ASYNC_SKIP_TEST
;
245 if (early_serial_setup(&port
) != 0) {
246 printk("Early serial init of port 0 failed\n");
249 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
250 /* Configure debug serial access */
251 gen550_init(0, &port
);
253 /* Purge TLB entry added in head_44x.S for early serial access */
254 _tlbie(UART0_IO_BASE
);
257 port
.membase
= ioremap64(PPC440GP_UART1_ADDR
, 8);
259 port
.uartclk
= clocks
.uart1
;
262 if (early_serial_setup(&port
) != 0) {
263 printk("Early serial init of port 1 failed\n");
266 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
267 /* Configure debug serial access */
268 gen550_init(1, &port
);
273 ebony_setup_arch(void)
276 struct ocp_func_emac_data
*emacdata
;
278 /* Set mac_addr for each EMAC */
279 def
= ocp_get_one_device(OCP_VENDOR_IBM
, OCP_FUNC_EMAC
, 0);
280 emacdata
= def
->additions
;
281 emacdata
->phy_map
= 0x00000001; /* Skip 0x00 */
282 emacdata
->phy_mode
= PHY_MODE_RMII
;
283 memcpy(emacdata
->mac_addr
, __res
.bi_enetaddr
, 6);
285 def
= ocp_get_one_device(OCP_VENDOR_IBM
, OCP_FUNC_EMAC
, 1);
286 emacdata
= def
->additions
;
287 emacdata
->phy_map
= 0x00000001; /* Skip 0x00 */
288 emacdata
->phy_mode
= PHY_MODE_RMII
;
289 memcpy(emacdata
->mac_addr
, __res
.bi_enet1addr
, 6);
292 * Determine various clocks.
293 * To be completely correct we should get SysClk
294 * from FPGA, because it can be changed by on-board switches
297 ibm440gp_get_clocks(&clocks
, 33333333, 6 * 1843200);
298 ocp_sys_info
.opb_bus_freq
= clocks
.opb
;
300 /* Setup TODC access */
301 TODC_INIT(TODC_TYPE_DS1743
,
304 ioremap64(EBONY_RTC_ADDR
, EBONY_RTC_SIZE
),
307 /* init to some ~sane value until calibrate_delay() runs */
308 loops_per_jiffy
= 50000000/HZ
;
310 /* Setup PCI host bridge */
313 #ifdef CONFIG_BLK_DEV_INITRD
315 ROOT_DEV
= Root_RAM0
;
318 #ifdef CONFIG_ROOT_NFS
321 ROOT_DEV
= Root_HDA1
;
324 ebony_early_serial_map();
326 /* Identify the system */
327 printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
330 void __init
platform_init(unsigned long r3
, unsigned long r4
,
331 unsigned long r5
, unsigned long r6
, unsigned long r7
)
333 parse_bootinfo(find_bootinfo());
336 * If we were passed in a board information, copy it into the
337 * residual data area.
340 __res
= *(bd_t
*)(r3
+ KERNELBASE
);
342 ibm44x_platform_init();
344 ppc_md
.setup_arch
= ebony_setup_arch
;
345 ppc_md
.show_cpuinfo
= ebony_show_cpuinfo
;
346 ppc_md
.get_irq
= NULL
; /* Set in ppc4xx_pic_init() */
348 ppc_md
.calibrate_decr
= ebony_calibrate_decr
;
349 ppc_md
.time_init
= todc_time_init
;
350 ppc_md
.set_rtc_time
= todc_set_rtc_time
;
351 ppc_md
.get_rtc_time
= todc_get_rtc_time
;
353 ppc_md
.nvram_read_val
= todc_direct_read_val
;
354 ppc_md
.nvram_write_val
= todc_direct_write_val
;
356 ppc_md
.early_serial_map
= ebony_early_serial_map
;