arch/ppc/platforms/4xx/ibm405ep.c

   1 /*
   2  * Support for IBM PPC 405EP processors.
   3  *
   4  * Author: SAW (IBM), derived from ibmnp405l.c.
   5  *         Maintained by MontaVista Software <source@mvista.com>
   6  *
   7  * 2003 (c) MontaVista Softare Inc.  This file is licensed under the
   8  * terms of the GNU General Public License version 2. This program is
   9  * licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12
  13 #include <linux/init.h>
  14 #include <linux/smp.h>
  15 #include <linux/threads.h>
  16 #include <linux/param.h>
  17 #include <linux/string.h>
  18
  19 #include <asm/ibm4xx.h>
  20 #include <asm/ocp.h>
  21 #include <asm/ppc4xx_pic.h>
  22
  23 #include <platforms/4xx/ibm405ep.h>
  24
  25 static struct ocp_func_mal_data ibm405ep_mal0_def = {
  26         .num_tx_chans   = 4,            /* Number of TX channels */
  27         .num_rx_chans   = 2,            /* Number of RX channels */
  28         .txeob_irq      = 11,           /* TX End Of Buffer IRQ  */
  29         .rxeob_irq      = 12,           /* RX End Of Buffer IRQ  */
  30         .txde_irq       = 13,           /* TX Descriptor Error IRQ */
  31         .rxde_irq       = 14,           /* RX Descriptor Error IRQ */
  32         .serr_irq       = 10,           /* MAL System Error IRQ    */
  33         .dcr_base       = DCRN_MAL_BASE /* MAL0_CFG DCR number */
  34 };
  35 OCP_SYSFS_MAL_DATA()
  36
  37 static struct ocp_func_emac_data ibm405ep_emac0_def = {
  38         .rgmii_idx      = -1,           /* No RGMII */
  39         .rgmii_mux      = -1,           /* No RGMII */
  40         .zmii_idx       = -1,           /* ZMII device index */
  41         .zmii_mux       = 0,            /* ZMII input of this EMAC */
  42         .mal_idx        = 0,            /* MAL device index */
  43         .mal_rx_chan    = 0,            /* MAL rx channel number */
  44         .mal_tx_chan    = 0,            /* MAL tx channel number */
  45         .wol_irq        = 9,            /* WOL interrupt number */
  46         .mdio_idx       = 0,            /* MDIO via EMAC0 */
  47         .tah_idx        = -1,           /* No TAH */
  48 };
  49
  50 static struct ocp_func_emac_data ibm405ep_emac1_def = {
  51         .rgmii_idx      = -1,           /* No RGMII */
  52         .rgmii_mux      = -1,           /* No RGMII */
  53         .zmii_idx       = -1,           /* ZMII device index */
  54         .zmii_mux       = 0,            /* ZMII input of this EMAC */
  55         .mal_idx        = 0,            /* MAL device index */
  56         .mal_rx_chan    = 1,            /* MAL rx channel number */
  57         .mal_tx_chan    = 2,            /* MAL tx channel number */
  58         .wol_irq        = 9,            /* WOL interrupt number */
  59         .mdio_idx       = 0,            /* MDIO via EMAC0 */
  60         .tah_idx        = -1,           /* No TAH */
  61 };
  62 OCP_SYSFS_EMAC_DATA()
  63
  64 static struct ocp_func_iic_data ibm405ep_iic0_def = {
  65         .fast_mode      = 0,            /* Use standad mode (100Khz) */
  66 };
  67 OCP_SYSFS_IIC_DATA()
  68
  69 struct ocp_def core_ocp[] = {
  70         { .vendor       = OCP_VENDOR_IBM,
  71           .function     = OCP_FUNC_OPB,
  72           .index        = 0,
  73           .paddr        = 0xEF600000,
  74           .irq          = OCP_IRQ_NA,
  75           .pm           = OCP_CPM_NA,
  76         },
  77         { .vendor       = OCP_VENDOR_IBM,
  78           .function     = OCP_FUNC_16550,
  79           .index        = 0,
  80           .paddr        = UART0_IO_BASE,
  81           .irq          = UART0_INT,
  82           .pm           = IBM_CPM_UART0
  83         },
  84         { .vendor       = OCP_VENDOR_IBM,
  85           .function     = OCP_FUNC_16550,
  86           .index        = 1,
  87           .paddr        = UART1_IO_BASE,
  88           .irq          = UART1_INT,
  89           .pm           = IBM_CPM_UART1
  90         },
  91         { .vendor       = OCP_VENDOR_IBM,
  92           .function     = OCP_FUNC_IIC,
  93           .paddr        = 0xEF600500,
  94           .irq          = 2,
  95           .pm           = IBM_CPM_IIC0,
  96           .additions    = &ibm405ep_iic0_def,
  97           .show         = &ocp_show_iic_data
  98         },
  99         { .vendor       = OCP_VENDOR_IBM,
 100           .function     = OCP_FUNC_GPIO,
 101           .paddr        = 0xEF600700,
 102           .irq          = OCP_IRQ_NA,
 103           .pm           = IBM_CPM_GPIO0
 104         },
 105         { .vendor       = OCP_VENDOR_IBM,
 106           .function     = OCP_FUNC_MAL,
 107           .paddr        = OCP_PADDR_NA,
 108           .irq          = OCP_IRQ_NA,
 109           .pm           = OCP_CPM_NA,
 110           .additions    = &ibm405ep_mal0_def,
 111           .show         = &ocp_show_mal_data
 112         },
 113         { .vendor       = OCP_VENDOR_IBM,
 114           .function     = OCP_FUNC_EMAC,
 115           .index        = 0,
 116           .paddr        = EMAC0_BASE,
 117           .irq          = 15,
 118           .pm           = OCP_CPM_NA,
 119           .additions    = &ibm405ep_emac0_def,
 120           .show         = &ocp_show_emac_data
 121         },
 122         { .vendor       = OCP_VENDOR_IBM,
 123           .function     = OCP_FUNC_EMAC,
 124           .index        = 1,
 125           .paddr        = 0xEF600900,
 126           .irq          = 17,
 127           .pm           = OCP_CPM_NA,
 128           .additions    = &ibm405ep_emac1_def,
 129           .show         = &ocp_show_emac_data
 130         },
 131         { .vendor       = OCP_VENDOR_INVALID
 132         }
 133 };
 134
 135 /* Polarity and triggering settings for internal interrupt sources */
 136 struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
 137         { .polarity     = 0xffff7f80,
 138           .triggering   = 0x00000000,
 139           .ext_irq_mask = 0x0000007f,   /* IRQ0 - IRQ6 */
 140         }
 141 };