2 * arch/ppc/platforms/radstone_ppc7d.c
4 * Board setup routines for the Radstone PPC7D boards.
6 * Author: James Chapman <jchapman@katalix.com>
8 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
9 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
17 /* Radstone PPC7D boards are rugged VME boards with PPC 7447A CPUs,
18 * Discovery-II, dual gigabit ethernet, dual PMC, USB, keyboard/mouse,
19 * 4 serial ports, 2 high speed serial ports (MPSCs) and optional
23 #include <linux/config.h>
24 #include <linux/stddef.h>
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/errno.h>
28 #include <linux/reboot.h>
29 #include <linux/pci.h>
30 #include <linux/kdev_t.h>
31 #include <linux/major.h>
32 #include <linux/initrd.h>
33 #include <linux/console.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/ide.h>
37 #include <linux/seq_file.h>
38 #include <linux/root_dev.h>
39 #include <linux/serial.h>
40 #include <linux/tty.h> /* for linux/serial_core.h */
41 #include <linux/serial_core.h>
42 #include <linux/mv643xx.h>
43 #include <linux/netdevice.h>
45 #include <asm/system.h>
46 #include <asm/pgtable.h>
51 #include <asm/machdep.h>
55 #include <asm/open_pic.h>
56 #include <asm/i8259.h>
58 #include <asm/bootinfo.h>
59 #include <asm/mpc10x.h>
60 #include <asm/pci-bridge.h>
61 #include <asm/mv64x60.h>
62 #include <asm/i8259.h>
64 #include "radstone_ppc7d.h"
68 #define PPC7D_RST_PIN 17 /* GPP17 */
70 extern u32 mv64360_irq_base
;
72 static struct mv64x60_handle bh
;
73 static int ppc7d_has_alma
;
75 extern void gen550_progress(char *, unsigned short);
76 extern void gen550_init(int, struct uart_port
*);
79 unsigned char __res
[sizeof(bd_t
)];
81 /*****************************************************************************
83 *****************************************************************************/
85 #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
86 static void __init
ppc7d_early_serial_map(void)
88 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
89 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE
);
90 #elif defined(CONFIG_SERIAL_8250)
91 struct uart_port serial_req
;
93 /* Setup serial port access */
94 memset(&serial_req
, 0, sizeof(serial_req
));
95 serial_req
.uartclk
= UART_CLK
;
97 serial_req
.flags
= STD_COM_FLAGS
;
98 serial_req
.iotype
= SERIAL_IO_MEM
;
99 serial_req
.membase
= (u_char
*) PPC7D_SERIAL_0
;
101 gen550_init(0, &serial_req
);
102 if (early_serial_setup(&serial_req
) != 0)
103 printk(KERN_ERR
"Early serial init of port 0 failed\n");
105 /* Assume early_serial_setup() doesn't modify serial_req */
108 serial_req
.membase
= (u_char
*) PPC7D_SERIAL_1
;
110 gen550_init(1, &serial_req
);
111 if (early_serial_setup(&serial_req
) != 0)
112 printk(KERN_ERR
"Early serial init of port 1 failed\n");
114 #error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
117 #endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */
119 /*****************************************************************************
120 * Low-level board support code
121 *****************************************************************************/
123 static unsigned long __init
ppc7d_find_end_of_memory(void)
125 bd_t
*bp
= (bd_t
*) __res
;
128 return bp
->bi_memsize
;
130 return (256 * 1024 * 1024);
133 static void __init
ppc7d_map_io(void)
135 /* remove temporary mapping */
136 mtspr(SPRN_DBAT3U
, 0x00000000);
137 mtspr(SPRN_DBAT3L
, 0x00000000);
139 io_block_mapping(0xe8000000, 0xe8000000, 0x08000000, _PAGE_IO
);
140 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO
);
143 static void ppc7d_restart(char *cmd
)
147 /* Disable GPP17 interrupt */
148 data
= mv64x60_read(&bh
, MV64x60_GPP_INTR_MASK
);
149 data
&= ~(1 << PPC7D_RST_PIN
);
150 mv64x60_write(&bh
, MV64x60_GPP_INTR_MASK
, data
);
152 /* Configure MPP17 as GPP */
153 data
= mv64x60_read(&bh
, MV64x60_MPP_CNTL_2
);
154 data
&= ~(0x0000000f << 4);
155 mv64x60_write(&bh
, MV64x60_MPP_CNTL_2
, data
);
157 /* Enable pin GPP17 for output */
158 data
= mv64x60_read(&bh
, MV64x60_GPP_IO_CNTL
);
159 data
|= (1 << PPC7D_RST_PIN
);
160 mv64x60_write(&bh
, MV64x60_GPP_IO_CNTL
, data
);
162 /* Toggle GPP9 pin to reset the board */
163 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, 1 << PPC7D_RST_PIN
);
164 mv64x60_write(&bh
, MV64x60_GPP_VALUE_SET
, 1 << PPC7D_RST_PIN
);
166 for (;;) ; /* Spin until reset happens */
170 static void ppc7d_power_off(void)
176 /* Ensure that internal MV643XX watchdog is disabled.
177 * The Disco watchdog uses MPP17 on this hardware.
179 data
= mv64x60_read(&bh
, MV64x60_MPP_CNTL_2
);
180 data
&= ~(0x0000000f << 4);
181 mv64x60_write(&bh
, MV64x60_MPP_CNTL_2
, data
);
183 data
= mv64x60_read(&bh
, MV64x60_WDT_WDC
);
184 if (data
& 0x80000000) {
185 mv64x60_write(&bh
, MV64x60_WDT_WDC
, 1 << 24);
186 mv64x60_write(&bh
, MV64x60_WDT_WDC
, 2 << 24);
189 for (;;) ; /* No way to shut power off with software */
193 static void ppc7d_halt(void)
199 static unsigned long ppc7d_led_no_pulse
;
201 static int __init
ppc7d_led_pulse_disable(char *str
)
203 ppc7d_led_no_pulse
= 1;
207 /* This kernel option disables the heartbeat pulsing of a board LED */
208 __setup("ledoff", ppc7d_led_pulse_disable
);
210 static void ppc7d_heartbeat(void)
214 static int max706_wdog
= 0;
216 /* Unfortunately we can't access the LED control registers
217 * during early init because they're on the CPLD which is the
218 * other side of a PCI bridge which goes unreachable during
219 * PCI scan. So write the LEDs only if the MV64360 watchdog is
220 * enabled (i.e. userspace apps are running so kernel is up)..
222 data32
= mv64x60_read(&bh
, MV64x60_WDT_WDC
);
223 if (data32
& 0x80000000) {
224 /* Enable MAX706 watchdog if not done already */
226 outb(3, PPC7D_CPLD_RESET
);
230 /* Hit the MAX706 watchdog */
231 outb(0, PPC7D_CPLD_WATCHDOG_TRIG
);
233 /* Pulse LED DS219 if not disabled */
234 if (!ppc7d_led_no_pulse
) {
235 static int led_on
= 0;
237 data8
= inb(PPC7D_CPLD_LEDS
);
239 data8
&= ~PPC7D_CPLD_LEDS_DS219_MASK
;
241 data8
|= PPC7D_CPLD_LEDS_DS219_MASK
;
243 outb(data8
, PPC7D_CPLD_LEDS
);
247 ppc_md
.heartbeat_count
= ppc_md
.heartbeat_reset
;
250 static int ppc7d_show_cpuinfo(struct seq_file
*m
)
254 static int flash_sizes
[4] = { 64, 32, 0, 16 };
255 static int flash_banks
[4] = { 4, 3, 2, 1 };
256 static char *pci_modes
[] = { "PCI33", "PCI66",
257 "Unknown", "Unknown",
262 seq_printf(m
, "vendor\t\t: Radstone Technology\n");
263 seq_printf(m
, "machine\t\t: PPC7D\n");
265 val
= inb(PPC7D_CPLD_BOARD_REVISION
);
266 val1
= (val
& PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK
) >> 5;
267 val2
= (val
& PPC7D_CPLD_BOARD_REVISION_LETTER_MASK
);
268 seq_printf(m
, "revision\t: %hd%c%c\n",
270 (val2
<= 0x18) ? 'A' + val2
: 'Y',
271 (val2
> 0x18) ? 'A' + (val2
- 0x19) : ' ');
273 val
= inb(PPC7D_CPLD_MOTHERBOARD_TYPE
);
274 val1
= val
& PPC7D_CPLD_MB_TYPE_PLL_MASK
;
275 val2
= val
& (PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK
|
276 PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK
);
277 seq_printf(m
, "bus speed\t: %dMHz\n",
278 (val1
== PPC7D_CPLD_MB_TYPE_PLL_133
) ? 133 :
279 (val1
== PPC7D_CPLD_MB_TYPE_PLL_100
) ? 100 :
280 (val1
== PPC7D_CPLD_MB_TYPE_PLL_64
) ? 64 : 0);
282 val
= inb(PPC7D_CPLD_MEM_CONFIG_EXTEND
);
283 val1
= val
& PPC7D_CPLD_SDRAM_BANK_SIZE_MASK
;
284 seq_printf(m
, "SDRAM\t\t: %d%c",
285 (val1
== PPC7D_CPLD_SDRAM_BANK_SIZE_128M
) ? 128 :
286 (val1
== PPC7D_CPLD_SDRAM_BANK_SIZE_256M
) ? 256 :
287 (val1
== PPC7D_CPLD_SDRAM_BANK_SIZE_512M
) ? 512 : 1,
288 (val1
== PPC7D_CPLD_SDRAM_BANK_SIZE_1G
) ? 'G' : 'M');
289 if (val2
& PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK
) {
290 seq_printf(m
, " [ECC %sabled]",
291 (val2
& PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK
) ? "en" :
296 val1
= (val
& PPC7D_CPLD_FLASH_DEV_SIZE_MASK
);
297 val2
= (val
& PPC7D_CPLD_FLASH_BANK_NUM_MASK
) >> 2;
298 seq_printf(m
, "FLASH\t\t: %d banks of %dM, total %dM\n",
299 flash_banks
[val2
], flash_sizes
[val1
],
300 flash_banks
[val2
] * flash_sizes
[val1
]);
302 val
= inb(PPC7D_CPLD_FLASH_WRITE_CNTL
);
303 val1
= inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT
);
304 seq_printf(m
, " write links\t: %s%s%s%s\n",
305 (val
& PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK
) ? "WRITE " : "",
306 (val
& PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK
) ? "BOOT " : "",
307 (val
& PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK
) ? "USER " : "",
308 (val
& (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK
|
309 PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK
|
310 PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK
)) ==
312 seq_printf(m
, " write sector h/w enables: %s%s%s%s%s\n",
313 (val
& PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK
) ? "RECOVERY " :
315 (val
& PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK
) ? "BOOT " : "",
316 (val
& PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK
) ? "USER " : "",
317 (val1
& PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK
) ? "NVRAM " :
320 (PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK
|
321 PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK
|
322 PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK
)) == 0)
323 && ((val1
& PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK
) ==
326 inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT
) &
327 (PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK
|
328 PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK
);
329 seq_printf(m
, " software sector enables: %s%s%s\n",
330 (val1
& PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK
) ? "SYSBOOT "
332 (val1
& PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK
) ? "USER " : "",
333 (val1
== 0) ? "NONE " : "");
335 seq_printf(m
, "Boot options\t: %s%s%s%s\n",
336 (val
& PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK
) ?
338 (val
& PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK
) ? "VME " :
340 (val
& PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK
) ? "RECOVERY "
343 (PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK
|
344 PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK
|
345 PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK
)) ==
348 val
= inb(PPC7D_CPLD_EQUIPMENT_PRESENT_1
);
349 seq_printf(m
, "Fitted modules\t: %s%s%s%s\n",
350 (val
& PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK
) ? "" : "PMC1 ",
351 (val
& PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK
) ? "" : "PMC2 ",
352 (val
& PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK
) ? "AFIX " : "",
353 ((val
& (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK
|
354 PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK
|
355 PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK
)) ==
356 (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK
|
357 PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK
)) ? "NONE" : "");
359 if (val
& PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK
) {
360 static const char *ids
[] = {
362 "1553 (Dual Channel)",
363 "1553 (Single Channel)",
366 "1553 (Single Channel with sideband)",
367 "1553 (Dual Channel with sideband)",
370 u8 id
= __raw_readb((void *)PPC7D_AFIX_REG_BASE
+ 0x03);
371 seq_printf(m
, "AFIX module\t: 0x%hx [%s]\n", id
,
372 id
< 7 ? ids
[id
] : "unknown");
375 val
= inb(PPC7D_CPLD_PCI_CONFIG
);
376 val1
= (val
& PPC7D_CPLD_PCI_CONFIG_PCI0_MASK
) >> 4;
377 val2
= (val
& PPC7D_CPLD_PCI_CONFIG_PCI1_MASK
);
378 seq_printf(m
, "PCI#0\t\t: %s\nPCI#1\t\t: %s\n",
379 pci_modes
[val1
], pci_modes
[val2
]);
381 val
= inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2
);
382 seq_printf(m
, "PMC1\t\t: %s\nPMC2\t\t: %s\n",
383 (val
& PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK
) ? "3.3v" : "5v",
384 (val
& PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK
) ? "3.3v" : "5v");
385 seq_printf(m
, "PMC power source: %s\n",
386 (val
& PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK
) ? "VME" :
389 val
= inb(PPC7D_CPLD_EQUIPMENT_PRESENT_4
);
390 val2
= inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2
);
391 seq_printf(m
, "Fit options\t: %s%s%s%s%s%s%s\n",
392 (val
& PPC7D_CPLD_EQPT_PRES_4_LPT_MASK
) ? "LPT " : "",
393 (val
& PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED
) ? "PS2 " : "",
394 (val
& PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED
) ? "USB2 " : "",
395 (val2
& PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK
) ? "VME " : "",
396 (val2
& PPC7D_CPLD_EQPT_PRES_2_COM36_MASK
) ? "COM3-6 " : "",
397 (val2
& PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK
) ? "eth0 " : "",
398 (val2
& PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK
) ? "eth1 " :
401 val
= inb(PPC7D_CPLD_ID_LINK
);
402 val1
= val
& (PPC7D_CPLD_ID_LINK_E6_MASK
|
403 PPC7D_CPLD_ID_LINK_E7_MASK
|
404 PPC7D_CPLD_ID_LINK_E12_MASK
|
405 PPC7D_CPLD_ID_LINK_E13_MASK
);
407 val
= inb(PPC7D_CPLD_FLASH_WRITE_CNTL
) &
408 (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK
|
409 PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK
|
410 PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK
);
412 seq_printf(m
, "Board links present: %s%s%s%s%s%s%s%s\n",
413 (val1
& PPC7D_CPLD_ID_LINK_E6_MASK
) ? "E6 " : "",
414 (val1
& PPC7D_CPLD_ID_LINK_E7_MASK
) ? "E7 " : "",
415 (val
& PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK
) ? "E9 " : "",
416 (val
& PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK
) ? "E10 " : "",
417 (val
& PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK
) ? "E11 " : "",
418 (val1
& PPC7D_CPLD_ID_LINK_E12_MASK
) ? "E12 " : "",
419 (val1
& PPC7D_CPLD_ID_LINK_E13_MASK
) ? "E13 " : "",
420 ((val
== 0) && (val1
== 0)) ? "NONE" : "");
422 val
= inb(PPC7D_CPLD_WDOG_RESETSW_MASK
);
423 seq_printf(m
, "Front panel reset switch: %sabled\n",
424 (val
& PPC7D_CPLD_WDOG_RESETSW_MASK
) ? "dis" : "en");
429 static void __init
ppc7d_calibrate_decr(void)
433 freq
= 100000000 / 4;
435 pr_debug("time_init: decrementer frequency = %lu.%.6lu MHz\n",
436 freq
/ 1000000, freq
% 1000000);
438 tb_ticks_per_jiffy
= freq
/ HZ
;
439 tb_to_us
= mulhwu_scale_factor(freq
, 1000000);
442 /*****************************************************************************
444 *****************************************************************************/
446 static irqreturn_t
ppc7d_i8259_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
448 u32 temp
= mv64x60_read(&bh
, MV64x60_GPP_INTR_CAUSE
);
449 if (temp
& (1 << 28)) {
451 mv64x60_write(&bh
, MV64x60_GPP_INTR_CAUSE
, temp
& (~(1 << 28)));
459 * Each interrupt cause is assigned an IRQ number.
460 * Southbridge has 16*2 (two 8259's) interrupts.
461 * Discovery-II has 96 interrupts (cause-hi, cause-lo, gpp x 32).
462 * If multiple interrupts are pending, get_irq() returns the
463 * lowest pending irq number first.
466 * IRQ # Source Trig Active
467 * =============================================================
472 * =============================================================
473 * 0 ISA High Resolution Counter Edge
475 * 2 Cascade From (IRQ 8-15) Edge
476 * 3 Com 2 (Uart 2) Edge
477 * 4 Com 1 (Uart 1) Edge
478 * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level
482 * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
483 * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
486 * 13 Reserved internally by Ali M1535+
487 * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level
490 * 16..112 Discovery-II...
492 * MPP28 Southbridge Edge High
495 * Interrupts are cascaded through to the Discovery-II.
499 * CPLD --> ALI1535 -------> DISCOVERY-II
502 static void __init
ppc7d_init_irq(void)
506 pr_debug("%s\n", __FUNCTION__
);
510 /* IRQ 0..15 are handled by the cascaded 8259's of the Ali1535 */
511 for (irq
= 0; irq
< 16; irq
++) {
512 irq_desc
[irq
].handler
= &i8259_pic
;
514 /* IRQs 5,6,9,10,11,14,15 are level sensitive */
515 irq_desc
[5].status
|= IRQ_LEVEL
;
516 irq_desc
[6].status
|= IRQ_LEVEL
;
517 irq_desc
[9].status
|= IRQ_LEVEL
;
518 irq_desc
[10].status
|= IRQ_LEVEL
;
519 irq_desc
[11].status
|= IRQ_LEVEL
;
520 irq_desc
[14].status
|= IRQ_LEVEL
;
521 irq_desc
[15].status
|= IRQ_LEVEL
;
523 /* GPP28 is edge triggered */
524 irq_desc
[mv64360_irq_base
+ MV64x60_IRQ_GPP28
].status
&= ~IRQ_LEVEL
;
527 static u32
ppc7d_irq_canonicalize(u32 irq
)
529 if ((irq
>= 16) && (irq
< (16 + 96)))
535 static int ppc7d_get_irq(struct pt_regs
*regs
)
539 irq
= mv64360_get_irq(regs
);
540 if (irq
== (mv64360_irq_base
+ MV64x60_IRQ_GPP28
))
541 irq
= i8259_irq(regs
);
546 * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
547 * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
548 * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level
549 * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level
551 static int __init
ppc7d_map_irq(struct pci_dev
*dev
, unsigned char idsel
,
554 static const char pci_irq_table
[][4] =
556 * PCI IDSEL/INTPIN->INTLINE
560 {10, 14, 5, 9}, /* IDSEL 10 - PMC2 / AFIX IRQW */
561 {9, 10, 14, 5}, /* IDSEL 11 - PMC1 / AFIX IRQX */
562 {5, 9, 10, 14}, /* IDSEL 12 - AFIX IRQY */
563 {14, 5, 9, 10}, /* IDSEL 13 - AFIX IRQZ */
565 const long min_idsel
= 10, max_idsel
= 14, irqs_per_slot
= 4;
567 pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __FUNCTION__
,
568 dev
->vendor
, dev
->device
, PCI_FUNC(dev
->devfn
), idsel
, pin
);
570 return PCI_IRQ_TABLE_LOOKUP
;
573 void __init
ppc7d_intr_setup(void)
578 * Define GPP 28 interrupt polarity as active high
579 * input signal and level triggered
581 data
= mv64x60_read(&bh
, MV64x60_GPP_LEVEL_CNTL
);
583 mv64x60_write(&bh
, MV64x60_GPP_LEVEL_CNTL
, data
);
584 data
= mv64x60_read(&bh
, MV64x60_GPP_IO_CNTL
);
586 mv64x60_write(&bh
, MV64x60_GPP_IO_CNTL
, data
);
588 /* Config GPP intr ctlr to respond to level trigger */
589 data
= mv64x60_read(&bh
, MV64x60_COMM_ARBITER_CNTL
);
591 mv64x60_write(&bh
, MV64x60_COMM_ARBITER_CNTL
, data
);
593 /* XXXX Erranum FEr PCI-#8 */
594 data
= mv64x60_read(&bh
, MV64x60_PCI0_CMD
);
595 data
&= ~((1 << 5) | (1 << 9));
596 mv64x60_write(&bh
, MV64x60_PCI0_CMD
, data
);
597 data
= mv64x60_read(&bh
, MV64x60_PCI1_CMD
);
598 data
&= ~((1 << 5) | (1 << 9));
599 mv64x60_write(&bh
, MV64x60_PCI1_CMD
, data
);
602 * Dismiss and then enable interrupt on GPP interrupt cause
605 mv64x60_write(&bh
, MV64x60_GPP_INTR_CAUSE
, ~(1 << 28));
606 data
= mv64x60_read(&bh
, MV64x60_GPP_INTR_MASK
);
608 mv64x60_write(&bh
, MV64x60_GPP_INTR_MASK
, data
);
611 * Dismiss and then enable interrupt on CPU #0 high cause reg
612 * BIT27 summarizes GPP interrupts 23-31
614 mv64x60_write(&bh
, MV64360_IC_MAIN_CAUSE_HI
, ~(1 << 27));
615 data
= mv64x60_read(&bh
, MV64360_IC_CPU0_INTR_MASK_HI
);
617 mv64x60_write(&bh
, MV64360_IC_CPU0_INTR_MASK_HI
, data
);
620 /*****************************************************************************
621 * Platform device data fixup routines.
622 *****************************************************************************/
624 #if defined(CONFIG_SERIAL_MPSC)
625 static void __init
ppc7d_fixup_mpsc_pdata(struct platform_device
*pdev
)
627 struct mpsc_pdata
*pdata
;
629 pdata
= (struct mpsc_pdata
*)pdev
->dev
.platform_data
;
631 pdata
->max_idle
= 40;
632 pdata
->default_baud
= PPC7D_DEFAULT_BAUD
;
633 pdata
->brg_clk_src
= PPC7D_MPSC_CLK_SRC
;
634 pdata
->brg_clk_freq
= PPC7D_MPSC_CLK_FREQ
;
640 #if defined(CONFIG_MV643XX_ETH)
641 static void __init
ppc7d_fixup_eth_pdata(struct platform_device
*pdev
)
643 struct mv643xx_eth_platform_data
*eth_pd
;
644 static u16 phy_addr
[] = {
651 eth_pd
= pdev
->dev
.platform_data
;
652 eth_pd
->force_phy_addr
= 1;
653 eth_pd
->phy_addr
= phy_addr
[pdev
->id
];
654 eth_pd
->tx_queue_size
= PPC7D_ETH_TX_QUEUE_SIZE
;
655 eth_pd
->rx_queue_size
= PPC7D_ETH_RX_QUEUE_SIZE
;
657 /* Adjust IRQ by mv64360_irq_base */
658 for (i
= 0; i
< pdev
->num_resources
; i
++) {
659 struct resource
*r
= &pdev
->resource
[i
];
661 if (r
->flags
& IORESOURCE_IRQ
) {
662 r
->start
+= mv64360_irq_base
;
663 r
->end
+= mv64360_irq_base
;
664 pr_debug("%s, uses IRQ %d\n", pdev
->name
,
672 #if defined(CONFIG_I2C_MV64XXX)
674 ppc7d_fixup_i2c_pdata(struct platform_device
*pdev
)
676 struct mv64xxx_i2c_pdata
*pdata
;
679 pdata
= pdev
->dev
.platform_data
;
681 pdata
= kmalloc(sizeof(*pdata
), GFP_KERNEL
);
685 memset(pdata
, 0, sizeof(*pdata
));
686 pdev
->dev
.platform_data
= pdata
;
689 /* divisors M=8, N=3 for 100kHz I2C from 133MHz system clock */
692 pdata
->timeout
= 500;
695 /* Adjust IRQ by mv64360_irq_base */
696 for (i
= 0; i
< pdev
->num_resources
; i
++) {
697 struct resource
*r
= &pdev
->resource
[i
];
699 if (r
->flags
& IORESOURCE_IRQ
) {
700 r
->start
+= mv64360_irq_base
;
701 r
->end
+= mv64360_irq_base
;
702 pr_debug("%s, uses IRQ %d\n", pdev
->name
, (int) r
->start
);
708 static int __init
ppc7d_platform_notify(struct device
*dev
)
712 void ((*rtn
) (struct platform_device
* pdev
));
714 #if defined(CONFIG_SERIAL_MPSC)
715 { MPSC_CTLR_NAME
".0", ppc7d_fixup_mpsc_pdata
},
716 { MPSC_CTLR_NAME
".1", ppc7d_fixup_mpsc_pdata
},
718 #if defined(CONFIG_MV643XX_ETH)
719 { MV643XX_ETH_NAME
".0", ppc7d_fixup_eth_pdata
},
720 { MV643XX_ETH_NAME
".1", ppc7d_fixup_eth_pdata
},
721 { MV643XX_ETH_NAME
".2", ppc7d_fixup_eth_pdata
},
723 #if defined(CONFIG_I2C_MV64XXX)
724 { MV64XXX_I2C_CTLR_NAME
".0", ppc7d_fixup_i2c_pdata
},
727 struct platform_device
*pdev
;
730 if (dev
&& dev
->bus_id
)
731 for (i
= 0; i
< ARRAY_SIZE(dev_map
); i
++)
732 if (!strncmp(dev
->bus_id
, dev_map
[i
].bus_id
,
735 pdev
= container_of(dev
,
736 struct platform_device
,
738 dev_map
[i
].rtn(pdev
);
744 /*****************************************************************************
746 * These aren't really fixups per se. They are used to init devices as they
747 * are found during PCI scan.
749 * The PPC7D has an HB8 PCI-X bridge which must be set up during a PCI
750 * scan in order to find other devices on its secondary side.
751 *****************************************************************************/
753 static void __init
ppc7d_fixup_hb8(struct pci_dev
*dev
)
757 if (dev
->bus
->number
== 0) {
758 pr_debug("PCI: HB8 init\n");
760 pci_write_config_byte(dev
, 0x1c,
761 ((PPC7D_PCI0_IO_START_PCI_ADDR
& 0xf000)
763 pci_write_config_byte(dev
, 0x1d,
764 (((PPC7D_PCI0_IO_START_PCI_ADDR
+
766 1) & 0xf000) >> 8) | 0x01);
767 pci_write_config_word(dev
, 0x30,
768 PPC7D_PCI0_IO_START_PCI_ADDR
>> 16);
769 pci_write_config_word(dev
, 0x32,
770 ((PPC7D_PCI0_IO_START_PCI_ADDR
+
774 pci_write_config_word(dev
, 0x20,
775 PPC7D_PCI0_MEM0_START_PCI_LO_ADDR
>> 16);
776 pci_write_config_word(dev
, 0x22,
777 ((PPC7D_PCI0_MEM0_START_PCI_LO_ADDR
+
778 PPC7D_PCI0_MEM0_SIZE
-
780 pci_write_config_word(dev
, 0x24, 0);
781 pci_write_config_word(dev
, 0x26, 0);
782 pci_write_config_dword(dev
, 0x28, 0);
783 pci_write_config_dword(dev
, 0x2c, 0);
785 pci_read_config_word(dev
, 0x3e, &val16
);
786 val16
|= ((1 << 5) | (1 << 1)); /* signal master aborts and
789 val16
&= ~(1 << 2); /* ISA disable, so all ISA
790 * ports forwarded to secondary
792 pci_write_config_word(dev
, 0x3e, val16
);
796 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT
, 0x0028, ppc7d_fixup_hb8
);
798 /* This should perhaps be a separate driver as we're actually initializing
799 * the chip for this board here. It's hardly a fixup...
801 static void __init
ppc7d_fixup_ali1535(struct pci_dev
*dev
)
803 pr_debug("PCI: ALI1535 init\n");
805 if (dev
->bus
->number
== 1) {
806 /* Configure the ISA Port Settings */
807 pci_write_config_byte(dev
, 0x43, 0x00);
809 /* Disable PCI Interrupt polling mode */
810 pci_write_config_byte(dev
, 0x45, 0x00);
812 /* Multifunction pin select INTFJ -> INTF */
813 pci_write_config_byte(dev
, 0x78, 0x00);
815 /* Set PCI INT -> IRQ Routing control in for external
818 pci_write_config_byte(dev
, 0x48, 0x31); /* [7-4] INT B -> IRQ10
819 * [3-0] INT A -> IRQ9
821 pci_write_config_byte(dev
, 0x49, 0x5D); /* [7-4] INT D -> IRQ5
822 * [3-0] INT C -> IRQ14
826 /* NEC USB device on IRQ 11 (INTE) - INTF disabled */
827 pci_write_config_byte(dev
, 0x4A, 0x09);
830 pci_write_config_byte(dev
, 0x76, 0x07);
832 /* SIRQ I (COMS 5/6) use IRQ line 15.
833 * Positive (not subtractive) address decode.
835 pci_write_config_byte(dev
, 0x44, 0x0f);
837 /* SIRQ II disabled */
838 pci_write_config_byte(dev
, 0x75, 0x0);
840 /* On board USB and RTC disabled */
841 pci_write_config_word(dev
, 0x52, (1 << 14));
842 pci_write_config_byte(dev
, 0x74, 0x00);
844 /* On board IDE disabled */
845 pci_write_config_byte(dev
, 0x58, 0x00);
847 /* Decode 32-bit addresses */
848 pci_write_config_byte(dev
, 0x5b, 0);
850 /* Disable docking IO */
851 pci_write_config_word(dev
, 0x5c, 0x0000);
853 /* Disable modem, enable sound */
854 pci_write_config_byte(dev
, 0x77, (1 << 6));
856 /* Disable hot-docking mode */
857 pci_write_config_byte(dev
, 0x7d, 0x00);
861 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, 0x1533, ppc7d_fixup_ali1535
);
863 static int ppc7d_pci_exclude_device(u8 bus
, u8 devfn
)
865 /* Early versions of this board were fitted with IBM ALMA
866 * PCI-VME bridge chips. The PCI config space of these devices
867 * was not set up correctly and causes PCI scan problems.
869 if ((bus
== 1) && (PCI_SLOT(devfn
) == 4) && ppc7d_has_alma
)
870 return PCIBIOS_DEVICE_NOT_FOUND
;
872 return mv64x60_pci_exclude_device(bus
, devfn
);
875 /* This hook is called when each PCI bus is probed.
877 static void ppc7d_pci_fixup_bus(struct pci_bus
*bus
)
879 pr_debug("PCI BUS %hu: %lx/%lx %lx/%lx %lx/%lx %lx/%lx\n",
881 bus
->resource
[0] ? bus
->resource
[0]->start
: 0,
882 bus
->resource
[0] ? bus
->resource
[0]->end
: 0,
883 bus
->resource
[1] ? bus
->resource
[1]->start
: 0,
884 bus
->resource
[1] ? bus
->resource
[1]->end
: 0,
885 bus
->resource
[2] ? bus
->resource
[2]->start
: 0,
886 bus
->resource
[2] ? bus
->resource
[2]->end
: 0,
887 bus
->resource
[3] ? bus
->resource
[3]->start
: 0,
888 bus
->resource
[3] ? bus
->resource
[3]->end
: 0);
890 if ((bus
->number
== 1) && (bus
->resource
[2] != NULL
)) {
891 /* Hide PCI window 2 of Bus 1 which is used only to
892 * map legacy ISA memory space.
894 bus
->resource
[2]->start
= 0;
895 bus
->resource
[2]->end
= 0;
896 bus
->resource
[2]->flags
= 0;
900 /*****************************************************************************
901 * Board device setup code
902 *****************************************************************************/
904 void __init
ppc7d_setup_peripherals(void)
908 /* Set up windows for boot CS */
909 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2BOOT_WIN
,
910 PPC7D_BOOT_WINDOW_BASE
, PPC7D_BOOT_WINDOW_SIZE
,
912 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2BOOT_WIN
);
914 /* Boot firmware configures the following DevCS addresses.
915 * DevCS0 - board control/status
916 * DevCS1 - test registers
917 * DevCS2 - AFIX port/address registers (for identifying)
920 * We don't use DevCS0, DevCS1.
922 val32
= mv64x60_read(&bh
, MV64360_CPU_BAR_ENABLE
);
923 val32
|= ((1 << 4) | (1 << 5));
924 mv64x60_write(&bh
, MV64360_CPU_BAR_ENABLE
, val32
);
925 mv64x60_write(&bh
, MV64x60_CPU2DEV_0_BASE
, 0);
926 mv64x60_write(&bh
, MV64x60_CPU2DEV_0_SIZE
, 0);
927 mv64x60_write(&bh
, MV64x60_CPU2DEV_1_BASE
, 0);
928 mv64x60_write(&bh
, MV64x60_CPU2DEV_1_SIZE
, 0);
930 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_2_WIN
,
931 PPC7D_AFIX_REG_BASE
, PPC7D_AFIX_REG_SIZE
, 0);
932 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2DEV_2_WIN
);
934 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_3_WIN
,
935 PPC7D_FLASH_BASE
, PPC7D_FLASH_SIZE_ACTUAL
, 0);
936 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2DEV_3_WIN
);
938 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2SRAM_WIN
,
939 PPC7D_INTERNAL_SRAM_BASE
, MV64360_SRAM_SIZE
,
941 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2SRAM_WIN
);
943 /* Set up Enet->SRAM window */
944 mv64x60_set_32bit_window(&bh
, MV64x60_ENET2MEM_4_WIN
,
945 PPC7D_INTERNAL_SRAM_BASE
, MV64360_SRAM_SIZE
,
947 bh
.ci
->enable_window_32bit(&bh
, MV64x60_ENET2MEM_4_WIN
);
949 /* Give enet r/w access to memory region */
950 val32
= mv64x60_read(&bh
, MV64360_ENET2MEM_ACC_PROT_0
);
951 val32
|= (0x3 << (4 << 1));
952 mv64x60_write(&bh
, MV64360_ENET2MEM_ACC_PROT_0
, val32
);
953 val32
= mv64x60_read(&bh
, MV64360_ENET2MEM_ACC_PROT_1
);
954 val32
|= (0x3 << (4 << 1));
955 mv64x60_write(&bh
, MV64360_ENET2MEM_ACC_PROT_1
, val32
);
956 val32
= mv64x60_read(&bh
, MV64360_ENET2MEM_ACC_PROT_2
);
957 val32
|= (0x3 << (4 << 1));
958 mv64x60_write(&bh
, MV64360_ENET2MEM_ACC_PROT_2
, val32
);
960 val32
= mv64x60_read(&bh
, MV64x60_TIMR_CNTR_0_3_CNTL
);
961 val32
&= ~((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24));
962 mv64x60_write(&bh
, MV64x60_TIMR_CNTR_0_3_CNTL
, val32
);
964 /* Enumerate pci bus.
966 * We scan PCI#0 first (the bus with the HB8 and other
967 * on-board peripherals). We must configure the 64360 before
968 * each scan, according to the bus number assignments. Busses
969 * are assigned incrementally, starting at 0. PCI#0 is
970 * usually assigned bus#0, the secondary side of the HB8 gets
971 * bus#1 and PCI#1 (second PMC site) gets bus#2. However, if
972 * any PMC card has a PCI bridge, these bus assignments will
976 /* Turn off PCI retries */
977 val32
= mv64x60_read(&bh
, MV64x60_CPU_CONFIG
);
979 mv64x60_write(&bh
, MV64x60_CPU_CONFIG
, val32
);
982 mv64x60_set_bus(&bh
, 0, 0);
983 bh
.hose_a
->first_busno
= 0;
984 bh
.hose_a
->last_busno
= 0xff;
985 bh
.hose_a
->last_busno
= pciauto_bus_scan(bh
.hose_a
, 0);
986 printk(KERN_INFO
"PCI#0: first=%d last=%d\n",
987 bh
.hose_a
->first_busno
, bh
.hose_a
->last_busno
);
990 bh
.hose_b
->first_busno
= bh
.hose_a
->last_busno
+ 1;
991 mv64x60_set_bus(&bh
, 1, bh
.hose_b
->first_busno
);
992 bh
.hose_b
->last_busno
= 0xff;
993 bh
.hose_b
->last_busno
= pciauto_bus_scan(bh
.hose_b
,
994 bh
.hose_b
->first_busno
);
995 printk(KERN_INFO
"PCI#1: first=%d last=%d\n",
996 bh
.hose_b
->first_busno
, bh
.hose_b
->last_busno
);
998 /* Turn on PCI retries */
999 val32
= mv64x60_read(&bh
, MV64x60_CPU_CONFIG
);
1000 val32
&= ~(1 << 17);
1001 mv64x60_write(&bh
, MV64x60_CPU_CONFIG
, val32
);
1003 /* Setup interrupts */
1007 static void __init
ppc7d_setup_bridge(void)
1009 struct mv64x60_setup_info si
;
1013 mv64360_irq_base
= 16; /* first 16 intrs are 2 x 8259's */
1015 memset(&si
, 0, sizeof(si
));
1017 si
.phys_reg_base
= CONFIG_MV64X60_NEW_BASE
;
1019 si
.pci_0
.enable_bus
= 1;
1020 si
.pci_0
.pci_io
.cpu_base
= PPC7D_PCI0_IO_START_PROC_ADDR
;
1021 si
.pci_0
.pci_io
.pci_base_hi
= 0;
1022 si
.pci_0
.pci_io
.pci_base_lo
= PPC7D_PCI0_IO_START_PCI_ADDR
;
1023 si
.pci_0
.pci_io
.size
= PPC7D_PCI0_IO_SIZE
;
1024 si
.pci_0
.pci_io
.swap
= MV64x60_CPU2PCI_SWAP_NONE
;
1025 si
.pci_0
.pci_mem
[0].cpu_base
= PPC7D_PCI0_MEM0_START_PROC_ADDR
;
1026 si
.pci_0
.pci_mem
[0].pci_base_hi
= PPC7D_PCI0_MEM0_START_PCI_HI_ADDR
;
1027 si
.pci_0
.pci_mem
[0].pci_base_lo
= PPC7D_PCI0_MEM0_START_PCI_LO_ADDR
;
1028 si
.pci_0
.pci_mem
[0].size
= PPC7D_PCI0_MEM0_SIZE
;
1029 si
.pci_0
.pci_mem
[0].swap
= MV64x60_CPU2PCI_SWAP_NONE
;
1030 si
.pci_0
.pci_mem
[1].cpu_base
= PPC7D_PCI0_MEM1_START_PROC_ADDR
;
1031 si
.pci_0
.pci_mem
[1].pci_base_hi
= PPC7D_PCI0_MEM1_START_PCI_HI_ADDR
;
1032 si
.pci_0
.pci_mem
[1].pci_base_lo
= PPC7D_PCI0_MEM1_START_PCI_LO_ADDR
;
1033 si
.pci_0
.pci_mem
[1].size
= PPC7D_PCI0_MEM1_SIZE
;
1034 si
.pci_0
.pci_mem
[1].swap
= MV64x60_CPU2PCI_SWAP_NONE
;
1035 si
.pci_0
.pci_cmd_bits
= 0;
1036 si
.pci_0
.latency_timer
= 0x80;
1038 si
.pci_1
.enable_bus
= 1;
1039 si
.pci_1
.pci_io
.cpu_base
= PPC7D_PCI1_IO_START_PROC_ADDR
;
1040 si
.pci_1
.pci_io
.pci_base_hi
= 0;
1041 si
.pci_1
.pci_io
.pci_base_lo
= PPC7D_PCI1_IO_START_PCI_ADDR
;
1042 si
.pci_1
.pci_io
.size
= PPC7D_PCI1_IO_SIZE
;
1043 si
.pci_1
.pci_io
.swap
= MV64x60_CPU2PCI_SWAP_NONE
;
1044 si
.pci_1
.pci_mem
[0].cpu_base
= PPC7D_PCI1_MEM0_START_PROC_ADDR
;
1045 si
.pci_1
.pci_mem
[0].pci_base_hi
= PPC7D_PCI1_MEM0_START_PCI_HI_ADDR
;
1046 si
.pci_1
.pci_mem
[0].pci_base_lo
= PPC7D_PCI1_MEM0_START_PCI_LO_ADDR
;
1047 si
.pci_1
.pci_mem
[0].size
= PPC7D_PCI1_MEM0_SIZE
;
1048 si
.pci_1
.pci_mem
[0].swap
= MV64x60_CPU2PCI_SWAP_NONE
;
1049 si
.pci_1
.pci_mem
[1].cpu_base
= PPC7D_PCI1_MEM1_START_PROC_ADDR
;
1050 si
.pci_1
.pci_mem
[1].pci_base_hi
= PPC7D_PCI1_MEM1_START_PCI_HI_ADDR
;
1051 si
.pci_1
.pci_mem
[1].pci_base_lo
= PPC7D_PCI1_MEM1_START_PCI_LO_ADDR
;
1052 si
.pci_1
.pci_mem
[1].size
= PPC7D_PCI1_MEM1_SIZE
;
1053 si
.pci_1
.pci_mem
[1].swap
= MV64x60_CPU2PCI_SWAP_NONE
;
1054 si
.pci_1
.pci_cmd_bits
= 0;
1055 si
.pci_1
.latency_timer
= 0x80;
1057 /* Don't clear the SRAM window since we use it for debug */
1058 si
.window_preserve_mask_32_lo
= (1 << MV64x60_CPU2SRAM_WIN
);
1060 printk(KERN_INFO
"PCI: MV64360 PCI#0 IO at %x, size %x\n",
1061 si
.pci_0
.pci_io
.cpu_base
, si
.pci_0
.pci_io
.size
);
1062 printk(KERN_INFO
"PCI: MV64360 PCI#1 IO at %x, size %x\n",
1063 si
.pci_1
.pci_io
.cpu_base
, si
.pci_1
.pci_io
.size
);
1065 for (i
= 0; i
< MV64x60_CPU2MEM_WINDOWS
; i
++) {
1066 #if defined(CONFIG_NOT_COHERENT_CACHE)
1067 si
.cpu_prot_options
[i
] = 0;
1068 si
.enet_options
[i
] = MV64360_ENET2MEM_SNOOP_NONE
;
1069 si
.mpsc_options
[i
] = MV64360_MPSC2MEM_SNOOP_NONE
;
1070 si
.idma_options
[i
] = MV64360_IDMA2MEM_SNOOP_NONE
;
1072 si
.pci_0
.acc_cntl_options
[i
] =
1073 MV64360_PCI_ACC_CNTL_SNOOP_NONE
|
1074 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
1075 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES
|
1076 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES
;
1078 si
.pci_1
.acc_cntl_options
[i
] =
1079 MV64360_PCI_ACC_CNTL_SNOOP_NONE
|
1080 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
1081 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES
|
1082 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES
;
1084 si
.cpu_prot_options
[i
] = 0;
1085 /* All PPC7D hardware uses B0 or newer MV64360 silicon which
1086 * does not have snoop bugs.
1088 si
.enet_options
[i
] = MV64360_ENET2MEM_SNOOP_WB
;
1089 si
.mpsc_options
[i
] = MV64360_MPSC2MEM_SNOOP_WB
;
1090 si
.idma_options
[i
] = MV64360_IDMA2MEM_SNOOP_WB
;
1092 si
.pci_0
.acc_cntl_options
[i
] =
1093 MV64360_PCI_ACC_CNTL_SNOOP_WB
|
1094 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
1095 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES
|
1096 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES
;
1098 si
.pci_1
.acc_cntl_options
[i
] =
1099 MV64360_PCI_ACC_CNTL_SNOOP_WB
|
1100 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
1101 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES
|
1102 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES
;
1106 /* Lookup PCI host bridges */
1107 if (mv64x60_init(&bh
, &si
))
1108 printk(KERN_ERR
"MV64360 initialization failed.\n");
1110 pr_debug("MV64360 regs @ %lx/%p\n", bh
.p_base
, bh
.v_base
);
1112 /* Enable WB Cache coherency on SRAM */
1113 temp
= mv64x60_read(&bh
, MV64360_SRAM_CONFIG
);
1114 pr_debug("SRAM_CONFIG: %x\n", temp
);
1115 #if defined(CONFIG_NOT_COHERENT_CACHE)
1116 mv64x60_write(&bh
, MV64360_SRAM_CONFIG
, temp
& ~0x2);
1118 mv64x60_write(&bh
, MV64360_SRAM_CONFIG
, temp
| 0x2);
1120 /* If system operates with internal bus arbiter (CPU master
1121 * control bit8) clear AACK Delay bit [25] in CPU
1122 * configuration register.
1124 temp
= mv64x60_read(&bh
, MV64x60_CPU_MASTER_CNTL
);
1125 if (temp
& (1 << 8)) {
1126 temp
= mv64x60_read(&bh
, MV64x60_CPU_CONFIG
);
1127 mv64x60_write(&bh
, MV64x60_CPU_CONFIG
, (temp
& ~(1 << 25)));
1130 /* Data and address parity is enabled */
1131 temp
= mv64x60_read(&bh
, MV64x60_CPU_CONFIG
);
1132 mv64x60_write(&bh
, MV64x60_CPU_CONFIG
,
1133 (temp
| (1 << 26) | (1 << 19)));
1135 pci_dram_offset
= 0; /* sys mem at same addr on PCI & cpu bus */
1136 ppc_md
.pci_swizzle
= common_swizzle
;
1137 ppc_md
.pci_map_irq
= ppc7d_map_irq
;
1138 ppc_md
.pci_exclude_device
= ppc7d_pci_exclude_device
;
1140 mv64x60_set_bus(&bh
, 0, 0);
1141 bh
.hose_a
->first_busno
= 0;
1142 bh
.hose_a
->last_busno
= 0xff;
1143 bh
.hose_a
->mem_space
.start
= PPC7D_PCI0_MEM0_START_PCI_LO_ADDR
;
1144 bh
.hose_a
->mem_space
.end
=
1145 PPC7D_PCI0_MEM0_START_PCI_LO_ADDR
+ PPC7D_PCI0_MEM0_SIZE
;
1147 /* These will be set later, as a result of PCI0 scan */
1148 bh
.hose_b
->first_busno
= 0;
1149 bh
.hose_b
->last_busno
= 0xff;
1150 bh
.hose_b
->mem_space
.start
= PPC7D_PCI1_MEM0_START_PCI_LO_ADDR
;
1151 bh
.hose_b
->mem_space
.end
=
1152 PPC7D_PCI1_MEM0_START_PCI_LO_ADDR
+ PPC7D_PCI1_MEM0_SIZE
;
1154 pr_debug("MV64360: PCI#0 IO decode %08x/%08x IO remap %08x\n",
1155 mv64x60_read(&bh
, 0x48), mv64x60_read(&bh
, 0x50),
1156 mv64x60_read(&bh
, 0xf0));
1159 static void __init
ppc7d_setup_arch(void)
1163 loops_per_jiffy
= 100000000 / HZ
;
1165 #ifdef CONFIG_BLK_DEV_INITRD
1167 ROOT_DEV
= Root_RAM0
;
1170 #ifdef CONFIG_ROOT_NFS
1171 ROOT_DEV
= Root_NFS
;
1173 ROOT_DEV
= Root_HDA1
;
1176 if ((cur_cpu_spec
[0]->cpu_features
& CPU_FTR_SPEC7450
) ||
1177 (cur_cpu_spec
[0]->cpu_features
& CPU_FTR_L3CR
))
1178 /* 745x is different. We only want to pass along enable. */
1179 _set_L2CR(L2CR_L2E
);
1180 else if (cur_cpu_spec
[0]->cpu_features
& CPU_FTR_L2CR
)
1181 /* All modules have 1MB of L2. We also assume that an
1182 * L2 divisor of 3 will work.
1184 _set_L2CR(L2CR_L2E
| L2CR_L2SIZ_1MB
| L2CR_L2CLK_DIV3
1185 | L2CR_L2RAM_PIPE
| L2CR_L2OH_1_0
| L2CR_L2DF
);
1187 if (cur_cpu_spec
[0]->cpu_features
& CPU_FTR_L3CR
)
1191 #ifdef CONFIG_DUMMY_CONSOLE
1192 conswitchp
= &dummy_con
;
1195 /* Lookup PCI host bridges */
1196 if (ppc_md
.progress
)
1197 ppc_md
.progress("ppc7d_setup_arch: calling setup_bridge", 0);
1199 ppc7d_setup_bridge();
1200 ppc7d_setup_peripherals();
1202 /* Disable ethernet. It might have been setup by the bootrom */
1203 for (port
= 0; port
< 3; port
++)
1204 mv64x60_write(&bh
, MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port
),
1207 /* Clear queue pointers to ensure they are all initialized,
1208 * otherwise since queues 1-7 are unused, they have random
1209 * pointers which look strange in register dumps. Don't bother
1210 * with queue 0 since it will be initialized later.
1212 for (port
= 0; port
< 3; port
++) {
1214 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port
),
1217 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port
),
1220 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port
),
1223 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port
),
1226 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port
),
1229 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port
),
1232 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port
),
1236 printk(KERN_INFO
"Radstone Technology PPC7D\n");
1237 if (ppc_md
.progress
)
1238 ppc_md
.progress("ppc7d_setup_arch: exit", 0);
1241 /* This kernel command line parameter can be used to have the target
1242 * wait for a JTAG debugger to attach. Of course, a JTAG debugger
1243 * with hardware breakpoint support can have the target stop at any
1244 * location during init, but this is a convenience feature that makes
1245 * it easier in the common case of loading the code using the ppcboot
1248 static unsigned long ppc7d_wait_debugger
;
1250 static int __init
ppc7d_waitdbg(char *str
)
1252 ppc7d_wait_debugger
= 1;
1256 __setup("waitdbg", ppc7d_waitdbg
);
1258 /* Second phase board init, called after other (architecture common)
1259 * low-level services have been initialized.
1261 static void ppc7d_init2(void)
1263 unsigned long flags
;
1267 pr_debug("%s: enter\n", __FUNCTION__
);
1269 /* Wait for debugger? */
1270 if (ppc7d_wait_debugger
) {
1271 printk("Waiting for debugger...\n");
1273 while (readl(&ppc7d_wait_debugger
)) ;
1276 /* Hook up i8259 interrupt which is connected to GPP28 */
1277 request_irq(mv64360_irq_base
+ MV64x60_IRQ_GPP28
, ppc7d_i8259_intr
,
1278 SA_INTERRUPT
, "I8259 (GPP28) interrupt", (void *)0);
1280 /* Configure MPP16 as watchdog NMI, MPP17 as watchdog WDE */
1281 spin_lock_irqsave(&mv64x60_lock
, flags
);
1282 data
= mv64x60_read(&bh
, MV64x60_MPP_CNTL_2
);
1283 data
&= ~(0x0000000f << 0);
1284 data
|= (0x00000004 << 0);
1285 data
&= ~(0x0000000f << 4);
1286 data
|= (0x00000004 << 4);
1287 mv64x60_write(&bh
, MV64x60_MPP_CNTL_2
, data
);
1288 spin_unlock_irqrestore(&mv64x60_lock
, flags
);
1291 data8
= inb(PPC7D_CPLD_LEDS
);
1294 outb(data8
, PPC7D_CPLD_LEDS
);
1296 pr_debug("%s: exit\n", __FUNCTION__
);
1299 /* Called from machine_init(), early, before any of the __init functions
1300 * have run. We must init software-configurable pins before other functions
1301 * such as interrupt controllers are initialised.
1303 void __init
platform_init(unsigned long r3
, unsigned long r4
, unsigned long r5
,
1304 unsigned long r6
, unsigned long r7
)
1309 /* Map 0xe0000000-0xffffffff early because we need access to SRAM
1310 * and the ISA memory space (for serial port) here. This mapping
1311 * is redone properly in ppc7d_map_io() later.
1313 mtspr(SPRN_DBAT3U
, 0xe0003fff);
1314 mtspr(SPRN_DBAT3L
, 0xe000002a);
1317 * Zero SRAM. Note that this generates parity errors on
1318 * internal data path in SRAM if it's first time accessing it
1321 * We do this ASAP to avoid parity errors when reading
1322 * uninitialized SRAM.
1324 memset((void *)PPC7D_INTERNAL_SRAM_BASE
, 0, MV64360_SRAM_SIZE
);
1326 pr_debug("platform_init: r3-r7: %lx %lx %lx %lx %lx\n",
1327 r3
, r4
, r5
, r6
, r7
);
1329 parse_bootinfo(find_bootinfo());
1331 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
1332 * are non-zero, then we should use the board info from the bd_t
1333 * structure and the cmdline pointed to by r6 instead of the
1334 * information from birecs, if any. Otherwise, use the information
1335 * from birecs as discovered by the preceeding call to
1336 * parse_bootinfo(). This rule should work with both PPCBoot, which
1337 * uses a bd_t board info structure, and the kernel boot wrapper,
1338 * which uses birecs.
1341 bd_t
*bp
= (bd_t
*) __res
;
1343 /* copy board info structure */
1344 memcpy((void *)__res
, (void *)(r3
+ KERNELBASE
), sizeof(bd_t
));
1345 /* copy command line */
1346 *(char *)(r7
+ KERNELBASE
) = 0;
1347 strcpy(cmd_line
, (char *)(r6
+ KERNELBASE
));
1349 printk(KERN_INFO
"Board info data:-\n");
1350 printk(KERN_INFO
" Internal freq: %lu MHz, bus freq: %lu MHz\n",
1351 bp
->bi_intfreq
, bp
->bi_busfreq
);
1352 printk(KERN_INFO
" Memory: %lx, size %lx\n", bp
->bi_memstart
,
1354 printk(KERN_INFO
" Console baudrate: %lu\n", bp
->bi_baudrate
);
1355 printk(KERN_INFO
" Ethernet address: "
1356 "%02x:%02x:%02x:%02x:%02x:%02x\n",
1357 bp
->bi_enetaddr
[0], bp
->bi_enetaddr
[1],
1358 bp
->bi_enetaddr
[2], bp
->bi_enetaddr
[3],
1359 bp
->bi_enetaddr
[4], bp
->bi_enetaddr
[5]);
1361 #ifdef CONFIG_BLK_DEV_INITRD
1362 /* take care of initrd if we have one */
1364 initrd_start
= r4
+ KERNELBASE
;
1365 initrd_end
= r5
+ KERNELBASE
;
1366 printk(KERN_INFO
"INITRD @ %lx/%lx\n", initrd_start
, initrd_end
);
1368 #endif /* CONFIG_BLK_DEV_INITRD */
1370 /* Map in board regs, etc. */
1371 isa_io_base
= 0xe8000000;
1372 isa_mem_base
= 0xe8000000;
1373 pci_dram_offset
= 0x00000000;
1374 ISA_DMA_THRESHOLD
= 0x00ffffff;
1375 DMA_MODE_READ
= 0x44;
1376 DMA_MODE_WRITE
= 0x48;
1378 ppc_md
.setup_arch
= ppc7d_setup_arch
;
1379 ppc_md
.init
= ppc7d_init2
;
1380 ppc_md
.show_cpuinfo
= ppc7d_show_cpuinfo
;
1381 ppc_md
.irq_canonicalize
= ppc7d_irq_canonicalize
;
1382 ppc_md
.init_IRQ
= ppc7d_init_irq
;
1383 ppc_md
.get_irq
= ppc7d_get_irq
;
1385 ppc_md
.restart
= ppc7d_restart
;
1386 ppc_md
.power_off
= ppc7d_power_off
;
1387 ppc_md
.halt
= ppc7d_halt
;
1389 ppc_md
.find_end_of_memory
= ppc7d_find_end_of_memory
;
1390 ppc_md
.setup_io_mappings
= ppc7d_map_io
;
1392 ppc_md
.time_init
= NULL
;
1393 ppc_md
.set_rtc_time
= NULL
;
1394 ppc_md
.get_rtc_time
= NULL
;
1395 ppc_md
.calibrate_decr
= ppc7d_calibrate_decr
;
1396 ppc_md
.nvram_read_val
= NULL
;
1397 ppc_md
.nvram_write_val
= NULL
;
1399 ppc_md
.heartbeat
= ppc7d_heartbeat
;
1400 ppc_md
.heartbeat_reset
= HZ
;
1401 ppc_md
.heartbeat_count
= ppc_md
.heartbeat_reset
;
1403 ppc_md
.pcibios_fixup_bus
= ppc7d_pci_fixup_bus
;
1405 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \
1406 defined(CONFIG_I2C_MV64XXX)
1407 platform_notify
= ppc7d_platform_notify
;
1410 #ifdef CONFIG_SERIAL_MPSC
1411 /* On PPC7D, we must configure MPSC support via CPLD control
1414 outb(PPC7D_CPLD_RTS_COM4_SCLK
|
1415 PPC7D_CPLD_RTS_COM56_ENABLED
, PPC7D_CPLD_RTS
);
1416 outb(PPC7D_CPLD_COMS_COM3_TCLKEN
|
1417 PPC7D_CPLD_COMS_COM3_TXEN
|
1418 PPC7D_CPLD_COMS_COM4_TCLKEN
|
1419 PPC7D_CPLD_COMS_COM4_TXEN
, PPC7D_CPLD_COMS
);
1420 #endif /* CONFIG_SERIAL_MPSC */
1422 #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
1423 ppc7d_early_serial_map();
1424 #ifdef CONFIG_SERIAL_TEXT_DEBUG
1425 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
1426 ppc_md
.progress
= mv64x60_mpsc_progress
;
1427 #elif defined(CONFIG_SERIAL_8250)
1428 ppc_md
.progress
= gen550_progress
;
1430 #error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
1431 #endif /* CONFIG_SERIAL_8250 */
1432 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
1433 #endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */
1435 /* Enable write access to user flash. This is necessary for
1438 val8
= readb((void *)isa_io_base
+ PPC7D_CPLD_SW_FLASH_WRITE_PROTECT
);
1439 writeb(val8
| (PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED
&
1440 PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK
),
1441 (void *)isa_io_base
+ PPC7D_CPLD_SW_FLASH_WRITE_PROTECT
);
1443 /* Determine if this board has IBM ALMA VME devices */
1444 val8
= readb((void *)isa_io_base
+ PPC7D_CPLD_BOARD_REVISION
);
1445 rev_num
= (val8
& PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK
) >> 5;
1450 console_printk
[0] = 8;