1 // SPDX-License-Identifier: GPL-2.0
3 * BPF Jit compiler for s390.
5 * Minimum build requirements:
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
13 * Copyright IBM Corp. 2012,2015
15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
16 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
19 #define KMSG_COMPONENT "bpf_jit"
20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
22 #include <linux/netdevice.h>
23 #include <linux/filter.h>
24 #include <linux/init.h>
25 #include <linux/bpf.h>
26 #include <asm/cacheflush.h>
28 #include <asm/set_memory.h>
31 int bpf_jit_enable __read_mostly
;
34 u32 seen
; /* Flags to remember seen eBPF instructions */
35 u32 seen_reg
[16]; /* Array to remember which registers are used */
36 u32
*addrs
; /* Array with relative instruction addresses */
37 u8
*prg_buf
; /* Start of program */
38 int size
; /* Size of program and literal pool */
39 int size_prg
; /* Size of program */
40 int prg
; /* Current position in program */
41 int lit_start
; /* Start of literal pool */
42 int lit
; /* Current position in literal pool */
43 int base_ip
; /* Base address for literal pool */
44 int ret0_ip
; /* Address of return 0 */
45 int exit_ip
; /* Address of exit */
46 int tail_call_start
; /* Tail call start offset */
47 int labels
[1]; /* Labels for local jumps */
50 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */
52 #define SEEN_SKB 1 /* skb access */
53 #define SEEN_MEM 2 /* use mem[] for temporary storage */
54 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */
55 #define SEEN_LITERAL 8 /* code uses literals */
56 #define SEEN_FUNC 16 /* calls C functions */
57 #define SEEN_TAIL_CALL 32 /* code uses tail calls */
58 #define SEEN_REG_AX 64 /* code uses constant blinding */
59 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB)
64 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
65 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
66 #define REG_SKB_DATA (MAX_BPF_JIT_REG + 2) /* SKB data register */
67 #define REG_L (MAX_BPF_JIT_REG + 3) /* Literal pool register */
68 #define REG_15 (MAX_BPF_JIT_REG + 4) /* Register 15 */
69 #define REG_0 REG_W0 /* Register 0 */
70 #define REG_1 REG_W1 /* Register 1 */
71 #define REG_2 BPF_REG_1 /* Register 2 */
72 #define REG_14 BPF_REG_0 /* Register 14 */
75 * Mapping of BPF registers to s390 registers
77 static const int reg2hex
[] = {
80 /* Function parameters */
86 /* Call saved registers */
91 /* BPF stack pointer */
93 /* Register for blinding (shared with REG_SKB_DATA) */
95 /* SKB data pointer */
97 /* Work registers for s390x backend */
104 static inline u32
reg(u32 dst_reg
, u32 src_reg
)
106 return reg2hex
[dst_reg
] << 4 | reg2hex
[src_reg
];
109 static inline u32
reg_high(u32 reg
)
111 return reg2hex
[reg
] << 4;
114 static inline void reg_set_seen(struct bpf_jit
*jit
, u32 b1
)
116 u32 r1
= reg2hex
[b1
];
118 if (!jit
->seen_reg
[r1
] && r1
>= 6 && r1
<= 15)
119 jit
->seen_reg
[r1
] = 1;
122 #define REG_SET_SEEN(b1) \
124 reg_set_seen(jit, b1); \
127 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
130 * EMIT macros for code generation
136 *(u16 *) (jit->prg_buf + jit->prg) = op; \
140 #define EMIT2(op, b1, b2) \
142 _EMIT2(op | reg(b1, b2)); \
150 *(u32 *) (jit->prg_buf + jit->prg) = op; \
154 #define EMIT4(op, b1, b2) \
156 _EMIT4(op | reg(b1, b2)); \
161 #define EMIT4_RRF(op, b1, b2, b3) \
163 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
169 #define _EMIT4_DISP(op, disp) \
171 unsigned int __disp = (disp) & 0xfff; \
172 _EMIT4(op | __disp); \
175 #define EMIT4_DISP(op, b1, b2, disp) \
177 _EMIT4_DISP(op | reg_high(b1) << 16 | \
178 reg_high(b2) << 8, disp); \
183 #define EMIT4_IMM(op, b1, imm) \
185 unsigned int __imm = (imm) & 0xffff; \
186 _EMIT4(op | reg_high(b1) << 16 | __imm); \
190 #define EMIT4_PCREL(op, pcrel) \
192 long __pcrel = ((pcrel) >> 1) & 0xffff; \
193 _EMIT4(op | __pcrel); \
196 #define _EMIT6(op1, op2) \
198 if (jit->prg_buf) { \
199 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
200 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
205 #define _EMIT6_DISP(op1, op2, disp) \
207 unsigned int __disp = (disp) & 0xfff; \
208 _EMIT6(op1 | __disp, op2); \
211 #define _EMIT6_DISP_LH(op1, op2, disp) \
213 u32 _disp = (u32) disp; \
214 unsigned int __disp_h = _disp & 0xff000; \
215 unsigned int __disp_l = _disp & 0x00fff; \
216 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
219 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
221 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
222 reg_high(b3) << 8, op2, disp); \
228 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
230 int rel = (jit->labels[label] - jit->prg) >> 1; \
231 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
237 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
239 int rel = (jit->labels[label] - jit->prg) >> 1; \
240 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
241 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
243 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
246 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
248 /* Branch instruction needs 6 bytes */ \
249 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
250 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
255 #define _EMIT6_IMM(op, imm) \
257 unsigned int __imm = (imm); \
258 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
261 #define EMIT6_IMM(op, b1, imm) \
263 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
267 #define EMIT_CONST_U32(val) \
270 ret = jit->lit - jit->base_ip; \
271 jit->seen |= SEEN_LITERAL; \
273 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
278 #define EMIT_CONST_U64(val) \
281 ret = jit->lit - jit->base_ip; \
282 jit->seen |= SEEN_LITERAL; \
284 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
289 #define EMIT_ZERO(b1) \
291 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
292 EMIT4(0xb9160000, b1, b1); \
297 * Fill whole space with illegal instructions
299 static void jit_fill_hole(void *area
, unsigned int size
)
301 memset(area
, 0, size
);
305 * Save registers from "rs" (register start) to "re" (register end) on stack
307 static void save_regs(struct bpf_jit
*jit
, u32 rs
, u32 re
)
309 u32 off
= STK_OFF_R6
+ (rs
- 6) * 8;
312 /* stg %rs,off(%r15) */
313 _EMIT6(0xe300f000 | rs
<< 20 | off
, 0x0024);
315 /* stmg %rs,%re,off(%r15) */
316 _EMIT6_DISP(0xeb00f000 | rs
<< 20 | re
<< 16, 0x0024, off
);
320 * Restore registers from "rs" (register start) to "re" (register end) on stack
322 static void restore_regs(struct bpf_jit
*jit
, u32 rs
, u32 re
, u32 stack_depth
)
324 u32 off
= STK_OFF_R6
+ (rs
- 6) * 8;
326 if (jit
->seen
& SEEN_STACK
)
327 off
+= STK_OFF
+ stack_depth
;
330 /* lg %rs,off(%r15) */
331 _EMIT6(0xe300f000 | rs
<< 20 | off
, 0x0004);
333 /* lmg %rs,%re,off(%r15) */
334 _EMIT6_DISP(0xeb00f000 | rs
<< 20 | re
<< 16, 0x0004, off
);
338 * Return first seen register (from start)
340 static int get_start(struct bpf_jit
*jit
, int start
)
344 for (i
= start
; i
<= 15; i
++) {
345 if (jit
->seen_reg
[i
])
352 * Return last seen register (from start) (gap >= 2)
354 static int get_end(struct bpf_jit
*jit
, int start
)
358 for (i
= start
; i
< 15; i
++) {
359 if (!jit
->seen_reg
[i
] && !jit
->seen_reg
[i
+ 1])
362 return jit
->seen_reg
[15] ? 15 : 14;
366 #define REGS_RESTORE 0
368 * Save and restore clobbered registers (6-15) on stack.
369 * We save/restore registers in chunks with gap >= 2 registers.
371 static void save_restore_regs(struct bpf_jit
*jit
, int op
, u32 stack_depth
)
377 rs
= get_start(jit
, re
);
380 re
= get_end(jit
, rs
+ 1);
382 save_regs(jit
, rs
, re
);
384 restore_regs(jit
, rs
, re
, stack_depth
);
390 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S"
391 * we store the SKB header length on the stack and the SKB data
392 * pointer in REG_SKB_DATA if BPF_REG_AX is not used.
394 static void emit_load_skb_data_hlen(struct bpf_jit
*jit
)
396 /* Header length: llgf %w1,<len>(%b1) */
397 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1
, REG_0
, BPF_REG_1
,
398 offsetof(struct sk_buff
, len
));
399 /* s %w1,<data_len>(%b1) */
400 EMIT4_DISP(0x5b000000, REG_W1
, BPF_REG_1
,
401 offsetof(struct sk_buff
, data_len
));
402 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */
403 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1
, REG_0
, REG_15
, STK_OFF_HLEN
);
404 if (!(jit
->seen
& SEEN_REG_AX
))
405 /* lg %skb_data,data_off(%b1) */
406 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA
, REG_0
,
407 BPF_REG_1
, offsetof(struct sk_buff
, data
));
411 * Emit function prologue
413 * Save registers and create stack frame if necessary.
414 * See stack frame layout desription in "bpf_jit.h"!
416 static void bpf_jit_prologue(struct bpf_jit
*jit
, u32 stack_depth
)
418 if (jit
->seen
& SEEN_TAIL_CALL
) {
419 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
420 _EMIT6(0xd703f000 | STK_OFF_TCCNT
, 0xf000 | STK_OFF_TCCNT
);
422 /* j tail_call_start: NOP if no tail calls are used */
423 EMIT4_PCREL(0xa7f40000, 6);
426 /* Tail calls have to skip above initialization */
427 jit
->tail_call_start
= jit
->prg
;
429 save_restore_regs(jit
, REGS_SAVE
, stack_depth
);
430 /* Setup literal pool */
431 if (jit
->seen
& SEEN_LITERAL
) {
433 EMIT2(0x0d00, REG_L
, REG_0
);
434 jit
->base_ip
= jit
->prg
;
436 /* Setup stack and backchain */
437 if (jit
->seen
& SEEN_STACK
) {
438 if (jit
->seen
& SEEN_FUNC
)
439 /* lgr %w1,%r15 (backchain) */
440 EMIT4(0xb9040000, REG_W1
, REG_15
);
441 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
442 EMIT4_DISP(0x41000000, BPF_REG_FP
, REG_15
, STK_160_UNUSED
);
443 /* aghi %r15,-STK_OFF */
444 EMIT4_IMM(0xa70b0000, REG_15
, -(STK_OFF
+ stack_depth
));
445 if (jit
->seen
& SEEN_FUNC
)
446 /* stg %w1,152(%r15) (backchain) */
447 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1
, REG_0
,
450 if (jit
->seen
& SEEN_SKB
) {
451 emit_load_skb_data_hlen(jit
);
452 /* stg %b1,ST_OFF_SKBP(%r0,%r15) */
453 EMIT6_DISP_LH(0xe3000000, 0x0024, BPF_REG_1
, REG_0
, REG_15
,
461 static void bpf_jit_epilogue(struct bpf_jit
*jit
, u32 stack_depth
)
464 if (jit
->seen
& SEEN_RET0
) {
465 jit
->ret0_ip
= jit
->prg
;
467 EMIT4_IMM(0xa7090000, BPF_REG_0
, 0);
469 jit
->exit_ip
= jit
->prg
;
470 /* Load exit code: lgr %r2,%b0 */
471 EMIT4(0xb9040000, REG_2
, BPF_REG_0
);
472 /* Restore registers */
473 save_restore_regs(jit
, REGS_RESTORE
, stack_depth
);
479 * Compile one eBPF instruction into s390x code
481 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
482 * stack space for the large switch statement.
484 static noinline
int bpf_jit_insn(struct bpf_jit
*jit
, struct bpf_prog
*fp
, int i
)
486 struct bpf_insn
*insn
= &fp
->insnsi
[i
];
487 int jmp_off
, last
, insn_count
= 1;
488 unsigned int func_addr
, mask
;
489 u32 dst_reg
= insn
->dst_reg
;
490 u32 src_reg
= insn
->src_reg
;
491 u32
*addrs
= jit
->addrs
;
495 if (dst_reg
== BPF_REG_AX
|| src_reg
== BPF_REG_AX
)
496 jit
->seen
|= SEEN_REG_AX
;
497 switch (insn
->code
) {
501 case BPF_ALU
| BPF_MOV
| BPF_X
: /* dst = (u32) src */
502 /* llgfr %dst,%src */
503 EMIT4(0xb9160000, dst_reg
, src_reg
);
505 case BPF_ALU64
| BPF_MOV
| BPF_X
: /* dst = src */
507 EMIT4(0xb9040000, dst_reg
, src_reg
);
509 case BPF_ALU
| BPF_MOV
| BPF_K
: /* dst = (u32) imm */
511 EMIT6_IMM(0xc00f0000, dst_reg
, imm
);
513 case BPF_ALU64
| BPF_MOV
| BPF_K
: /* dst = imm */
515 EMIT6_IMM(0xc0010000, dst_reg
, imm
);
520 case BPF_LD
| BPF_IMM
| BPF_DW
: /* dst = (u64) imm */
522 /* 16 byte instruction that uses two 'struct bpf_insn' */
525 imm64
= (u64
)(u32
) insn
[0].imm
| ((u64
)(u32
) insn
[1].imm
) << 32;
526 /* lg %dst,<d(imm)>(%l) */
527 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg
, REG_0
, REG_L
,
528 EMIT_CONST_U64(imm64
));
535 case BPF_ALU
| BPF_ADD
| BPF_X
: /* dst = (u32) dst + (u32) src */
537 EMIT2(0x1a00, dst_reg
, src_reg
);
540 case BPF_ALU64
| BPF_ADD
| BPF_X
: /* dst = dst + src */
542 EMIT4(0xb9080000, dst_reg
, src_reg
);
544 case BPF_ALU
| BPF_ADD
| BPF_K
: /* dst = (u32) dst + (u32) imm */
548 EMIT6_IMM(0xc20b0000, dst_reg
, imm
);
551 case BPF_ALU64
| BPF_ADD
| BPF_K
: /* dst = dst + imm */
555 EMIT6_IMM(0xc2080000, dst_reg
, imm
);
560 case BPF_ALU
| BPF_SUB
| BPF_X
: /* dst = (u32) dst - (u32) src */
562 EMIT2(0x1b00, dst_reg
, src_reg
);
565 case BPF_ALU64
| BPF_SUB
| BPF_X
: /* dst = dst - src */
567 EMIT4(0xb9090000, dst_reg
, src_reg
);
569 case BPF_ALU
| BPF_SUB
| BPF_K
: /* dst = (u32) dst - (u32) imm */
573 EMIT6_IMM(0xc20b0000, dst_reg
, -imm
);
576 case BPF_ALU64
| BPF_SUB
| BPF_K
: /* dst = dst - imm */
580 EMIT6_IMM(0xc2080000, dst_reg
, -imm
);
585 case BPF_ALU
| BPF_MUL
| BPF_X
: /* dst = (u32) dst * (u32) src */
587 EMIT4(0xb2520000, dst_reg
, src_reg
);
590 case BPF_ALU64
| BPF_MUL
| BPF_X
: /* dst = dst * src */
592 EMIT4(0xb90c0000, dst_reg
, src_reg
);
594 case BPF_ALU
| BPF_MUL
| BPF_K
: /* dst = (u32) dst * (u32) imm */
598 EMIT6_IMM(0xc2010000, dst_reg
, imm
);
601 case BPF_ALU64
| BPF_MUL
| BPF_K
: /* dst = dst * imm */
605 EMIT6_IMM(0xc2000000, dst_reg
, imm
);
610 case BPF_ALU
| BPF_DIV
| BPF_X
: /* dst = (u32) dst / (u32) src */
611 case BPF_ALU
| BPF_MOD
| BPF_X
: /* dst = (u32) dst % (u32) src */
613 int rc_reg
= BPF_OP(insn
->code
) == BPF_DIV
? REG_W1
: REG_W0
;
615 jit
->seen
|= SEEN_RET0
;
616 /* ltr %src,%src (if src == 0 goto fail) */
617 EMIT2(0x1200, src_reg
, src_reg
);
619 EMIT4_PCREL(0xa7840000, jit
->ret0_ip
- jit
->prg
);
621 EMIT4_IMM(0xa7080000, REG_W0
, 0);
623 EMIT2(0x1800, REG_W1
, dst_reg
);
625 EMIT4(0xb9970000, REG_W0
, src_reg
);
627 EMIT4(0xb9160000, dst_reg
, rc_reg
);
630 case BPF_ALU64
| BPF_DIV
| BPF_X
: /* dst = dst / src */
631 case BPF_ALU64
| BPF_MOD
| BPF_X
: /* dst = dst % src */
633 int rc_reg
= BPF_OP(insn
->code
) == BPF_DIV
? REG_W1
: REG_W0
;
635 jit
->seen
|= SEEN_RET0
;
636 /* ltgr %src,%src (if src == 0 goto fail) */
637 EMIT4(0xb9020000, src_reg
, src_reg
);
639 EMIT4_PCREL(0xa7840000, jit
->ret0_ip
- jit
->prg
);
641 EMIT4_IMM(0xa7090000, REG_W0
, 0);
643 EMIT4(0xb9040000, REG_W1
, dst_reg
);
645 EMIT4(0xb9870000, REG_W0
, src_reg
);
647 EMIT4(0xb9040000, dst_reg
, rc_reg
);
650 case BPF_ALU
| BPF_DIV
| BPF_K
: /* dst = (u32) dst / (u32) imm */
651 case BPF_ALU
| BPF_MOD
| BPF_K
: /* dst = (u32) dst % (u32) imm */
653 int rc_reg
= BPF_OP(insn
->code
) == BPF_DIV
? REG_W1
: REG_W0
;
656 if (BPF_OP(insn
->code
) == BPF_MOD
)
658 EMIT4_IMM(0xa7090000, dst_reg
, 0);
662 EMIT4_IMM(0xa7080000, REG_W0
, 0);
664 EMIT2(0x1800, REG_W1
, dst_reg
);
665 /* dl %w0,<d(imm)>(%l) */
666 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0
, REG_0
, REG_L
,
667 EMIT_CONST_U32(imm
));
669 EMIT4(0xb9160000, dst_reg
, rc_reg
);
672 case BPF_ALU64
| BPF_DIV
| BPF_K
: /* dst = dst / imm */
673 case BPF_ALU64
| BPF_MOD
| BPF_K
: /* dst = dst % imm */
675 int rc_reg
= BPF_OP(insn
->code
) == BPF_DIV
? REG_W1
: REG_W0
;
678 if (BPF_OP(insn
->code
) == BPF_MOD
)
680 EMIT4_IMM(0xa7090000, dst_reg
, 0);
684 EMIT4_IMM(0xa7090000, REG_W0
, 0);
686 EMIT4(0xb9040000, REG_W1
, dst_reg
);
687 /* dlg %w0,<d(imm)>(%l) */
688 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0
, REG_0
, REG_L
,
689 EMIT_CONST_U64(imm
));
691 EMIT4(0xb9040000, dst_reg
, rc_reg
);
697 case BPF_ALU
| BPF_AND
| BPF_X
: /* dst = (u32) dst & (u32) src */
699 EMIT2(0x1400, dst_reg
, src_reg
);
702 case BPF_ALU64
| BPF_AND
| BPF_X
: /* dst = dst & src */
704 EMIT4(0xb9800000, dst_reg
, src_reg
);
706 case BPF_ALU
| BPF_AND
| BPF_K
: /* dst = (u32) dst & (u32) imm */
708 EMIT6_IMM(0xc00b0000, dst_reg
, imm
);
711 case BPF_ALU64
| BPF_AND
| BPF_K
: /* dst = dst & imm */
712 /* ng %dst,<d(imm)>(%l) */
713 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg
, REG_0
, REG_L
,
714 EMIT_CONST_U64(imm
));
719 case BPF_ALU
| BPF_OR
| BPF_X
: /* dst = (u32) dst | (u32) src */
721 EMIT2(0x1600, dst_reg
, src_reg
);
724 case BPF_ALU64
| BPF_OR
| BPF_X
: /* dst = dst | src */
726 EMIT4(0xb9810000, dst_reg
, src_reg
);
728 case BPF_ALU
| BPF_OR
| BPF_K
: /* dst = (u32) dst | (u32) imm */
730 EMIT6_IMM(0xc00d0000, dst_reg
, imm
);
733 case BPF_ALU64
| BPF_OR
| BPF_K
: /* dst = dst | imm */
734 /* og %dst,<d(imm)>(%l) */
735 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg
, REG_0
, REG_L
,
736 EMIT_CONST_U64(imm
));
741 case BPF_ALU
| BPF_XOR
| BPF_X
: /* dst = (u32) dst ^ (u32) src */
743 EMIT2(0x1700, dst_reg
, src_reg
);
746 case BPF_ALU64
| BPF_XOR
| BPF_X
: /* dst = dst ^ src */
748 EMIT4(0xb9820000, dst_reg
, src_reg
);
750 case BPF_ALU
| BPF_XOR
| BPF_K
: /* dst = (u32) dst ^ (u32) imm */
754 EMIT6_IMM(0xc0070000, dst_reg
, imm
);
757 case BPF_ALU64
| BPF_XOR
| BPF_K
: /* dst = dst ^ imm */
758 /* xg %dst,<d(imm)>(%l) */
759 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg
, REG_0
, REG_L
,
760 EMIT_CONST_U64(imm
));
765 case BPF_ALU
| BPF_LSH
| BPF_X
: /* dst = (u32) dst << (u32) src */
766 /* sll %dst,0(%src) */
767 EMIT4_DISP(0x89000000, dst_reg
, src_reg
, 0);
770 case BPF_ALU64
| BPF_LSH
| BPF_X
: /* dst = dst << src */
771 /* sllg %dst,%dst,0(%src) */
772 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg
, dst_reg
, src_reg
, 0);
774 case BPF_ALU
| BPF_LSH
| BPF_K
: /* dst = (u32) dst << (u32) imm */
777 /* sll %dst,imm(%r0) */
778 EMIT4_DISP(0x89000000, dst_reg
, REG_0
, imm
);
781 case BPF_ALU64
| BPF_LSH
| BPF_K
: /* dst = dst << imm */
784 /* sllg %dst,%dst,imm(%r0) */
785 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg
, dst_reg
, REG_0
, imm
);
790 case BPF_ALU
| BPF_RSH
| BPF_X
: /* dst = (u32) dst >> (u32) src */
791 /* srl %dst,0(%src) */
792 EMIT4_DISP(0x88000000, dst_reg
, src_reg
, 0);
795 case BPF_ALU64
| BPF_RSH
| BPF_X
: /* dst = dst >> src */
796 /* srlg %dst,%dst,0(%src) */
797 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg
, dst_reg
, src_reg
, 0);
799 case BPF_ALU
| BPF_RSH
| BPF_K
: /* dst = (u32) dst >> (u32) imm */
802 /* srl %dst,imm(%r0) */
803 EMIT4_DISP(0x88000000, dst_reg
, REG_0
, imm
);
806 case BPF_ALU64
| BPF_RSH
| BPF_K
: /* dst = dst >> imm */
809 /* srlg %dst,%dst,imm(%r0) */
810 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg
, dst_reg
, REG_0
, imm
);
815 case BPF_ALU64
| BPF_ARSH
| BPF_X
: /* ((s64) dst) >>= src */
816 /* srag %dst,%dst,0(%src) */
817 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg
, dst_reg
, src_reg
, 0);
819 case BPF_ALU64
| BPF_ARSH
| BPF_K
: /* ((s64) dst) >>= imm */
822 /* srag %dst,%dst,imm(%r0) */
823 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg
, dst_reg
, REG_0
, imm
);
828 case BPF_ALU
| BPF_NEG
: /* dst = (u32) -dst */
830 EMIT2(0x1300, dst_reg
, dst_reg
);
833 case BPF_ALU64
| BPF_NEG
: /* dst = -dst */
835 EMIT4(0xb9130000, dst_reg
, dst_reg
);
840 case BPF_ALU
| BPF_END
| BPF_FROM_BE
:
841 /* s390 is big endian, therefore only clear high order bytes */
843 case 16: /* dst = (u16) cpu_to_be16(dst) */
844 /* llghr %dst,%dst */
845 EMIT4(0xb9850000, dst_reg
, dst_reg
);
847 case 32: /* dst = (u32) cpu_to_be32(dst) */
848 /* llgfr %dst,%dst */
849 EMIT4(0xb9160000, dst_reg
, dst_reg
);
851 case 64: /* dst = (u64) cpu_to_be64(dst) */
855 case BPF_ALU
| BPF_END
| BPF_FROM_LE
:
857 case 16: /* dst = (u16) cpu_to_le16(dst) */
859 EMIT4(0xb91f0000, dst_reg
, dst_reg
);
860 /* srl %dst,16(%r0) */
861 EMIT4_DISP(0x88000000, dst_reg
, REG_0
, 16);
862 /* llghr %dst,%dst */
863 EMIT4(0xb9850000, dst_reg
, dst_reg
);
865 case 32: /* dst = (u32) cpu_to_le32(dst) */
867 EMIT4(0xb91f0000, dst_reg
, dst_reg
);
868 /* llgfr %dst,%dst */
869 EMIT4(0xb9160000, dst_reg
, dst_reg
);
871 case 64: /* dst = (u64) cpu_to_le64(dst) */
872 /* lrvgr %dst,%dst */
873 EMIT4(0xb90f0000, dst_reg
, dst_reg
);
880 case BPF_STX
| BPF_MEM
| BPF_B
: /* *(u8 *)(dst + off) = src_reg */
881 /* stcy %src,off(%dst) */
882 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg
, dst_reg
, REG_0
, off
);
883 jit
->seen
|= SEEN_MEM
;
885 case BPF_STX
| BPF_MEM
| BPF_H
: /* (u16 *)(dst + off) = src */
886 /* sthy %src,off(%dst) */
887 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg
, dst_reg
, REG_0
, off
);
888 jit
->seen
|= SEEN_MEM
;
890 case BPF_STX
| BPF_MEM
| BPF_W
: /* *(u32 *)(dst + off) = src */
891 /* sty %src,off(%dst) */
892 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg
, dst_reg
, REG_0
, off
);
893 jit
->seen
|= SEEN_MEM
;
895 case BPF_STX
| BPF_MEM
| BPF_DW
: /* (u64 *)(dst + off) = src */
896 /* stg %src,off(%dst) */
897 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg
, dst_reg
, REG_0
, off
);
898 jit
->seen
|= SEEN_MEM
;
900 case BPF_ST
| BPF_MEM
| BPF_B
: /* *(u8 *)(dst + off) = imm */
902 EMIT4_IMM(0xa7080000, REG_W0
, (u8
) imm
);
903 /* stcy %w0,off(dst) */
904 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0
, dst_reg
, REG_0
, off
);
905 jit
->seen
|= SEEN_MEM
;
907 case BPF_ST
| BPF_MEM
| BPF_H
: /* (u16 *)(dst + off) = imm */
909 EMIT4_IMM(0xa7080000, REG_W0
, (u16
) imm
);
910 /* sthy %w0,off(dst) */
911 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0
, dst_reg
, REG_0
, off
);
912 jit
->seen
|= SEEN_MEM
;
914 case BPF_ST
| BPF_MEM
| BPF_W
: /* *(u32 *)(dst + off) = imm */
916 EMIT6_IMM(0xc00f0000, REG_W0
, (u32
) imm
);
917 /* sty %w0,off(%dst) */
918 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0
, dst_reg
, REG_0
, off
);
919 jit
->seen
|= SEEN_MEM
;
921 case BPF_ST
| BPF_MEM
| BPF_DW
: /* *(u64 *)(dst + off) = imm */
923 EMIT6_IMM(0xc0010000, REG_W0
, imm
);
924 /* stg %w0,off(%dst) */
925 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0
, dst_reg
, REG_0
, off
);
926 jit
->seen
|= SEEN_MEM
;
929 * BPF_STX XADD (atomic_add)
931 case BPF_STX
| BPF_XADD
| BPF_W
: /* *(u32 *)(dst + off) += src */
932 /* laal %w0,%src,off(%dst) */
933 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0
, src_reg
,
935 jit
->seen
|= SEEN_MEM
;
937 case BPF_STX
| BPF_XADD
| BPF_DW
: /* *(u64 *)(dst + off) += src */
938 /* laalg %w0,%src,off(%dst) */
939 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0
, src_reg
,
941 jit
->seen
|= SEEN_MEM
;
946 case BPF_LDX
| BPF_MEM
| BPF_B
: /* dst = *(u8 *)(ul) (src + off) */
947 /* llgc %dst,0(off,%src) */
948 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg
, src_reg
, REG_0
, off
);
949 jit
->seen
|= SEEN_MEM
;
951 case BPF_LDX
| BPF_MEM
| BPF_H
: /* dst = *(u16 *)(ul) (src + off) */
952 /* llgh %dst,0(off,%src) */
953 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg
, src_reg
, REG_0
, off
);
954 jit
->seen
|= SEEN_MEM
;
956 case BPF_LDX
| BPF_MEM
| BPF_W
: /* dst = *(u32 *)(ul) (src + off) */
957 /* llgf %dst,off(%src) */
958 jit
->seen
|= SEEN_MEM
;
959 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg
, src_reg
, REG_0
, off
);
961 case BPF_LDX
| BPF_MEM
| BPF_DW
: /* dst = *(u64 *)(ul) (src + off) */
962 /* lg %dst,0(off,%src) */
963 jit
->seen
|= SEEN_MEM
;
964 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg
, src_reg
, REG_0
, off
);
969 case BPF_JMP
| BPF_CALL
:
972 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
974 const u64 func
= (u64
)__bpf_call_base
+ imm
;
976 REG_SET_SEEN(BPF_REG_5
);
977 jit
->seen
|= SEEN_FUNC
;
978 /* lg %w1,<d(imm)>(%l) */
979 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1
, REG_0
, REG_L
,
980 EMIT_CONST_U64(func
));
982 EMIT2(0x0d00, REG_14
, REG_W1
);
983 /* lgr %b0,%r2: load return value into %b0 */
984 EMIT4(0xb9040000, BPF_REG_0
, REG_2
);
985 if ((jit
->seen
& SEEN_SKB
) &&
986 bpf_helper_changes_pkt_data((void *)func
)) {
987 /* lg %b1,ST_OFF_SKBP(%r15) */
988 EMIT6_DISP_LH(0xe3000000, 0x0004, BPF_REG_1
, REG_0
,
989 REG_15
, STK_OFF_SKBP
);
990 emit_load_skb_data_hlen(jit
);
994 case BPF_JMP
| BPF_TAIL_CALL
:
998 * B2: pointer to bpf_array
999 * B3: index in bpf_array
1001 jit
->seen
|= SEEN_TAIL_CALL
;
1004 * if (index >= array->map.max_entries)
1008 /* llgf %w1,map.max_entries(%b2) */
1009 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1
, REG_0
, BPF_REG_2
,
1010 offsetof(struct bpf_array
, map
.max_entries
));
1011 /* clgrj %b3,%w1,0xa,label0: if %b3 >= %w1 goto out */
1012 EMIT6_PCREL_LABEL(0xec000000, 0x0065, BPF_REG_3
,
1016 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1020 if (jit
->seen
& SEEN_STACK
)
1021 off
= STK_OFF_TCCNT
+ STK_OFF
+ fp
->aux
->stack_depth
;
1023 off
= STK_OFF_TCCNT
;
1025 EMIT4_IMM(0xa7080000, REG_W0
, 1);
1026 /* laal %w1,%w0,off(%r15) */
1027 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1
, REG_W0
, REG_15
, off
);
1028 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1029 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1
,
1030 MAX_TAIL_CALL_CNT
, 0, 0x2);
1033 * prog = array->ptrs[index];
1038 /* sllg %r1,%b3,3: %r1 = index * 8 */
1039 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1
, BPF_REG_3
, REG_0
, 3);
1040 /* lg %r1,prog(%b2,%r1) */
1041 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1
, BPF_REG_2
,
1042 REG_1
, offsetof(struct bpf_array
, ptrs
));
1043 /* clgij %r1,0,0x8,label0 */
1044 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1
, 0, 0, 0x8);
1047 * Restore registers before calling function
1049 save_restore_regs(jit
, REGS_RESTORE
, fp
->aux
->stack_depth
);
1052 * goto *(prog->bpf_func + tail_call_start);
1055 /* lg %r1,bpf_func(%r1) */
1056 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1
, REG_1
, REG_0
,
1057 offsetof(struct bpf_prog
, bpf_func
));
1058 /* bc 0xf,tail_call_start(%r1) */
1059 _EMIT4(0x47f01000 + jit
->tail_call_start
);
1061 jit
->labels
[0] = jit
->prg
;
1063 case BPF_JMP
| BPF_EXIT
: /* return b0 */
1064 last
= (i
== fp
->len
- 1) ? 1 : 0;
1065 if (last
&& !(jit
->seen
& SEEN_RET0
))
1068 EMIT4_PCREL(0xa7f40000, jit
->exit_ip
- jit
->prg
);
1071 * Branch relative (number of skipped instructions) to offset on
1074 * Condition code to mask mapping:
1076 * CC | Description | Mask
1077 * ------------------------------
1078 * 0 | Operands equal | 8
1079 * 1 | First operand low | 4
1080 * 2 | First operand high | 2
1083 * For s390x relative branches: ip = ip + off_bytes
1084 * For BPF relative branches: insn = insn + off_insns + 1
1086 * For example for s390x with offset 0 we jump to the branch
1087 * instruction itself (loop) and for BPF with offset 0 we
1088 * branch to the instruction behind the branch.
1090 case BPF_JMP
| BPF_JA
: /* if (true) */
1091 mask
= 0xf000; /* j */
1093 case BPF_JMP
| BPF_JSGT
| BPF_K
: /* ((s64) dst > (s64) imm) */
1094 mask
= 0x2000; /* jh */
1096 case BPF_JMP
| BPF_JSLT
| BPF_K
: /* ((s64) dst < (s64) imm) */
1097 mask
= 0x4000; /* jl */
1099 case BPF_JMP
| BPF_JSGE
| BPF_K
: /* ((s64) dst >= (s64) imm) */
1100 mask
= 0xa000; /* jhe */
1102 case BPF_JMP
| BPF_JSLE
| BPF_K
: /* ((s64) dst <= (s64) imm) */
1103 mask
= 0xc000; /* jle */
1105 case BPF_JMP
| BPF_JGT
| BPF_K
: /* (dst_reg > imm) */
1106 mask
= 0x2000; /* jh */
1108 case BPF_JMP
| BPF_JLT
| BPF_K
: /* (dst_reg < imm) */
1109 mask
= 0x4000; /* jl */
1111 case BPF_JMP
| BPF_JGE
| BPF_K
: /* (dst_reg >= imm) */
1112 mask
= 0xa000; /* jhe */
1114 case BPF_JMP
| BPF_JLE
| BPF_K
: /* (dst_reg <= imm) */
1115 mask
= 0xc000; /* jle */
1117 case BPF_JMP
| BPF_JNE
| BPF_K
: /* (dst_reg != imm) */
1118 mask
= 0x7000; /* jne */
1120 case BPF_JMP
| BPF_JEQ
| BPF_K
: /* (dst_reg == imm) */
1121 mask
= 0x8000; /* je */
1123 case BPF_JMP
| BPF_JSET
| BPF_K
: /* (dst_reg & imm) */
1124 mask
= 0x7000; /* jnz */
1125 /* lgfi %w1,imm (load sign extend imm) */
1126 EMIT6_IMM(0xc0010000, REG_W1
, imm
);
1128 EMIT4(0xb9800000, REG_W1
, dst_reg
);
1131 case BPF_JMP
| BPF_JSGT
| BPF_X
: /* ((s64) dst > (s64) src) */
1132 mask
= 0x2000; /* jh */
1134 case BPF_JMP
| BPF_JSLT
| BPF_X
: /* ((s64) dst < (s64) src) */
1135 mask
= 0x4000; /* jl */
1137 case BPF_JMP
| BPF_JSGE
| BPF_X
: /* ((s64) dst >= (s64) src) */
1138 mask
= 0xa000; /* jhe */
1140 case BPF_JMP
| BPF_JSLE
| BPF_X
: /* ((s64) dst <= (s64) src) */
1141 mask
= 0xc000; /* jle */
1143 case BPF_JMP
| BPF_JGT
| BPF_X
: /* (dst > src) */
1144 mask
= 0x2000; /* jh */
1146 case BPF_JMP
| BPF_JLT
| BPF_X
: /* (dst < src) */
1147 mask
= 0x4000; /* jl */
1149 case BPF_JMP
| BPF_JGE
| BPF_X
: /* (dst >= src) */
1150 mask
= 0xa000; /* jhe */
1152 case BPF_JMP
| BPF_JLE
| BPF_X
: /* (dst <= src) */
1153 mask
= 0xc000; /* jle */
1155 case BPF_JMP
| BPF_JNE
| BPF_X
: /* (dst != src) */
1156 mask
= 0x7000; /* jne */
1158 case BPF_JMP
| BPF_JEQ
| BPF_X
: /* (dst == src) */
1159 mask
= 0x8000; /* je */
1161 case BPF_JMP
| BPF_JSET
| BPF_X
: /* (dst & src) */
1162 mask
= 0x7000; /* jnz */
1163 /* ngrk %w1,%dst,%src */
1164 EMIT4_RRF(0xb9e40000, REG_W1
, dst_reg
, src_reg
);
1167 /* lgfi %w1,imm (load sign extend imm) */
1168 EMIT6_IMM(0xc0010000, REG_W1
, imm
);
1169 /* cgrj %dst,%w1,mask,off */
1170 EMIT6_PCREL(0xec000000, 0x0064, dst_reg
, REG_W1
, i
, off
, mask
);
1173 /* lgfi %w1,imm (load sign extend imm) */
1174 EMIT6_IMM(0xc0010000, REG_W1
, imm
);
1175 /* clgrj %dst,%w1,mask,off */
1176 EMIT6_PCREL(0xec000000, 0x0065, dst_reg
, REG_W1
, i
, off
, mask
);
1179 /* cgrj %dst,%src,mask,off */
1180 EMIT6_PCREL(0xec000000, 0x0064, dst_reg
, src_reg
, i
, off
, mask
);
1183 /* clgrj %dst,%src,mask,off */
1184 EMIT6_PCREL(0xec000000, 0x0065, dst_reg
, src_reg
, i
, off
, mask
);
1187 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1188 jmp_off
= addrs
[i
+ off
+ 1] - (addrs
[i
+ 1] - 4);
1189 EMIT4_PCREL(0xa7040000 | mask
<< 8, jmp_off
);
1194 case BPF_LD
| BPF_ABS
| BPF_B
: /* b0 = *(u8 *) (skb->data+imm) */
1195 case BPF_LD
| BPF_IND
| BPF_B
: /* b0 = *(u8 *) (skb->data+imm+src) */
1196 if ((BPF_MODE(insn
->code
) == BPF_ABS
) && (imm
>= 0))
1197 func_addr
= __pa(sk_load_byte_pos
);
1199 func_addr
= __pa(sk_load_byte
);
1201 case BPF_LD
| BPF_ABS
| BPF_H
: /* b0 = *(u16 *) (skb->data+imm) */
1202 case BPF_LD
| BPF_IND
| BPF_H
: /* b0 = *(u16 *) (skb->data+imm+src) */
1203 if ((BPF_MODE(insn
->code
) == BPF_ABS
) && (imm
>= 0))
1204 func_addr
= __pa(sk_load_half_pos
);
1206 func_addr
= __pa(sk_load_half
);
1208 case BPF_LD
| BPF_ABS
| BPF_W
: /* b0 = *(u32 *) (skb->data+imm) */
1209 case BPF_LD
| BPF_IND
| BPF_W
: /* b0 = *(u32 *) (skb->data+imm+src) */
1210 if ((BPF_MODE(insn
->code
) == BPF_ABS
) && (imm
>= 0))
1211 func_addr
= __pa(sk_load_word_pos
);
1213 func_addr
= __pa(sk_load_word
);
1216 jit
->seen
|= SEEN_SKB
| SEEN_RET0
| SEEN_FUNC
;
1217 REG_SET_SEEN(REG_14
); /* Return address of possible func call */
1221 * BPF_REG_6 (R7) : skb pointer
1222 * REG_SKB_DATA (R12): skb data pointer (if no BPF_REG_AX)
1225 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb
1226 * BPF_REG_5 (R6) : return address
1229 * BPF_REG_0 (R14): data read from skb
1231 * Scratch registers (BPF_REG_1-5)
1234 /* Call function: llilf %w1,func_addr */
1235 EMIT6_IMM(0xc00f0000, REG_W1
, func_addr
);
1237 /* Offset: lgfi %b2,imm */
1238 EMIT6_IMM(0xc0010000, BPF_REG_2
, imm
);
1239 if (BPF_MODE(insn
->code
) == BPF_IND
)
1240 /* agfr %b2,%src (%src is s32 here) */
1241 EMIT4(0xb9180000, BPF_REG_2
, src_reg
);
1243 /* Reload REG_SKB_DATA if BPF_REG_AX is used */
1244 if (jit
->seen
& SEEN_REG_AX
)
1245 /* lg %skb_data,data_off(%b6) */
1246 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA
, REG_0
,
1247 BPF_REG_6
, offsetof(struct sk_buff
, data
));
1248 /* basr %b5,%w1 (%b5 is call saved) */
1249 EMIT2(0x0d00, BPF_REG_5
, REG_W1
);
1252 * Note: For fast access we jump directly after the
1253 * jnz instruction from bpf_jit.S
1256 EMIT4_PCREL(0xa7740000, jit
->ret0_ip
- jit
->prg
);
1258 default: /* too complex, give up */
1259 pr_err("Unknown opcode %02x\n", insn
->code
);
1266 * Compile eBPF program into s390x code
1268 static int bpf_jit_prog(struct bpf_jit
*jit
, struct bpf_prog
*fp
)
1272 jit
->lit
= jit
->lit_start
;
1275 bpf_jit_prologue(jit
, fp
->aux
->stack_depth
);
1276 for (i
= 0; i
< fp
->len
; i
+= insn_count
) {
1277 insn_count
= bpf_jit_insn(jit
, fp
, i
);
1280 /* Next instruction address */
1281 jit
->addrs
[i
+ insn_count
] = jit
->prg
;
1283 bpf_jit_epilogue(jit
, fp
->aux
->stack_depth
);
1285 jit
->lit_start
= jit
->prg
;
1286 jit
->size
= jit
->lit
;
1287 jit
->size_prg
= jit
->prg
;
1292 * Compile eBPF program "fp"
1294 struct bpf_prog
*bpf_int_jit_compile(struct bpf_prog
*fp
)
1296 struct bpf_prog
*tmp
, *orig_fp
= fp
;
1297 struct bpf_binary_header
*header
;
1298 bool tmp_blinded
= false;
1302 if (!bpf_jit_enable
)
1305 tmp
= bpf_jit_blind_constants(fp
);
1307 * If blinding was requested and we failed during blinding,
1308 * we must fall back to the interpreter.
1317 memset(&jit
, 0, sizeof(jit
));
1318 jit
.addrs
= kcalloc(fp
->len
+ 1, sizeof(*jit
.addrs
), GFP_KERNEL
);
1319 if (jit
.addrs
== NULL
) {
1324 * Three initial passes:
1325 * - 1/2: Determine clobbered registers
1326 * - 3: Calculate program size and addrs arrray
1328 for (pass
= 1; pass
<= 3; pass
++) {
1329 if (bpf_jit_prog(&jit
, fp
)) {
1335 * Final pass: Allocate and generate program
1337 if (jit
.size
>= BPF_SIZE_MAX
) {
1341 header
= bpf_jit_binary_alloc(jit
.size
, &jit
.prg_buf
, 2, jit_fill_hole
);
1346 if (bpf_jit_prog(&jit
, fp
)) {
1350 if (bpf_jit_enable
> 1) {
1351 bpf_jit_dump(fp
->len
, jit
.size
, pass
, jit
.prg_buf
);
1352 print_fn_code(jit
.prg_buf
, jit
.size_prg
);
1354 bpf_jit_binary_lock_ro(header
);
1355 fp
->bpf_func
= (void *) jit
.prg_buf
;
1357 fp
->jited_len
= jit
.size
;
1362 bpf_jit_prog_release_other(fp
, fp
== orig_fp
?