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1 /*
2 * linux/arch/sh/boards/se/7722/setup.c
3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu
5 * Copyright (C) 2012 Paul Mundt
6 *
7 * Hitachi UL SolutionEngine 7722 Support.
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 *
13 */
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/ata_platform.h>
17 #include <linux/input.h>
18 #include <linux/input/sh_keysc.h>
19 #include <linux/irqdomain.h>
20 #include <linux/smc91x.h>
21 #include <mach-se/mach/se7722.h>
22 #include <mach-se/mach/mrshpc.h>
23 #include <asm/machvec.h>
24 #include <asm/clock.h>
25 #include <asm/io.h>
26 #include <asm/heartbeat.h>
27 #include <cpu/sh7722.h>
28
29 /* Heartbeat */
30 static struct resource heartbeat_resource = {
31 .start = PA_LED,
32 .end = PA_LED,
33 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
34 };
35
36 static struct platform_device heartbeat_device = {
37 .name = "heartbeat",
38 .id = -1,
39 .num_resources = 1,
40 .resource = &heartbeat_resource,
41 };
42
43 /* SMC91x */
44 static struct smc91x_platdata smc91x_info = {
45 .flags = SMC91X_USE_16BIT,
46 };
47
48 static struct resource smc91x_eth_resources[] = {
49 [0] = {
50 .name = "smc91x-regs" ,
51 .start = PA_LAN + 0x300,
52 .end = PA_LAN + 0x300 + 0x10 ,
53 .flags = IORESOURCE_MEM,
54 },
55 [1] = {
56 /* Filled in later */
57 .flags = IORESOURCE_IRQ,
58 },
59 };
60
61 static struct platform_device smc91x_eth_device = {
62 .name = "smc91x",
63 .id = 0,
64 .dev = {
65 .dma_mask = NULL, /* don't use dma */
66 .coherent_dma_mask = 0xffffffff,
67 .platform_data = &smc91x_info,
68 },
69 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
70 .resource = smc91x_eth_resources,
71 };
72
73 static struct resource cf_ide_resources[] = {
74 [0] = {
75 .start = PA_MRSHPC_IO + 0x1f0,
76 .end = PA_MRSHPC_IO + 0x1f0 + 8 ,
77 .flags = IORESOURCE_IO,
78 },
79 [1] = {
80 .start = PA_MRSHPC_IO + 0x1f0 + 0x206,
81 .end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8,
82 .flags = IORESOURCE_IO,
83 },
84 [2] = {
85 /* Filled in later */
86 .flags = IORESOURCE_IRQ,
87 },
88 };
89
90 static struct platform_device cf_ide_device = {
91 .name = "pata_platform",
92 .id = -1,
93 .num_resources = ARRAY_SIZE(cf_ide_resources),
94 .resource = cf_ide_resources,
95 };
96
97 static struct sh_keysc_info sh_keysc_info = {
98 .mode = SH_KEYSC_MODE_1, /* KEYOUT0->5, KEYIN0->4 */
99 .scan_timing = 3,
100 .delay = 5,
101 .keycodes = { /* SW1 -> SW30 */
102 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
103 KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
104 KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
105 KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T,
106 KEY_U, KEY_V, KEY_W, KEY_X, KEY_Y,
107 KEY_Z,
108 KEY_HOME, KEY_SLEEP, KEY_WAKEUP, KEY_COFFEE, /* life */
109 },
110 };
111
112 static struct resource sh_keysc_resources[] = {
113 [0] = {
114 .start = 0x044b0000,
115 .end = 0x044b000f,
116 .flags = IORESOURCE_MEM,
117 },
118 [1] = {
119 .start = 79,
120 .flags = IORESOURCE_IRQ,
121 },
122 };
123
124 static struct platform_device sh_keysc_device = {
125 .name = "sh_keysc",
126 .id = 0, /* "keysc0" clock */
127 .num_resources = ARRAY_SIZE(sh_keysc_resources),
128 .resource = sh_keysc_resources,
129 .dev = {
130 .platform_data = &sh_keysc_info,
131 },
132 };
133
134 static struct platform_device *se7722_devices[] __initdata = {
135 &heartbeat_device,
136 &smc91x_eth_device,
137 &cf_ide_device,
138 &sh_keysc_device,
139 };
140
141 static int __init se7722_devices_setup(void)
142 {
143 mrshpc_setup_windows();
144
145 /* Wire-up dynamic vectors */
146 cf_ide_resources[2].start = cf_ide_resources[2].end =
147 irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_MRSHPC0);
148
149 smc91x_eth_resources[1].start = smc91x_eth_resources[1].end =
150 irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_SMC);
151
152 return platform_add_devices(se7722_devices, ARRAY_SIZE(se7722_devices));
153 }
154 device_initcall(se7722_devices_setup);
155
156 static void __init se7722_setup(char **cmdline_p)
157 {
158 __raw_writew(0x010D, FPGA_OUT); /* FPGA */
159
160 __raw_writew(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */
161 __raw_writew(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */
162
163 /* LCDC I/O */
164 __raw_writew(0x0020, PORT_PSELD);
165
166 /* SIOF1*/
167 __raw_writew(0x0003, PORT_PSELB);
168 __raw_writew(0xe000, PORT_PSELC);
169 __raw_writew(0x0000, PORT_PKCR);
170
171 /* LCDC */
172 __raw_writew(0x4020, PORT_PHCR);
173 __raw_writew(0x0000, PORT_PLCR);
174 __raw_writew(0x0000, PORT_PMCR);
175 __raw_writew(0x0002, PORT_PRCR);
176 __raw_writew(0x0000, PORT_PXCR); /* LCDC,CS6A */
177
178 /* KEYSC */
179 __raw_writew(0x0A10, PORT_PSELA); /* BS,SHHID2 */
180 __raw_writew(0x0000, PORT_PYCR);
181 __raw_writew(0x0000, PORT_PZCR);
182 __raw_writew(__raw_readw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
183 __raw_writew(__raw_readw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
184 }
185
186 /*
187 * The Machine Vector
188 */
189 static struct sh_machine_vector mv_se7722 __initmv = {
190 .mv_name = "Solution Engine 7722" ,
191 .mv_setup = se7722_setup ,
192 .mv_init_irq = init_se7722_IRQ,
193 };