arch/sparc/include/asm/trap_block.h

   1 #ifndef _SPARC_TRAP_BLOCK_H
   2 #define _SPARC_TRAP_BLOCK_H
   3
   4 #include <asm/hypervisor.h>
   5 #include <asm/asi.h>
   6
   7 #ifndef __ASSEMBLY__
   8
   9 /* Trap handling code needs to get at a few critical values upon
  10  * trap entry and to process TSB misses.  These cannot be in the
  11  * per_cpu() area as we really need to lock them into the TLB and
  12  * thus make them part of the main kernel image.  As a result we
  13  * try to make this as small as possible.
  14  *
  15  * This is padded out and aligned to 64-bytes to avoid false sharing
  16  * on SMP.
  17  */
  18
  19 /* If you modify the size of this structure, please update
  20  * TRAP_BLOCK_SZ_SHIFT below.
  21  */
  22 struct thread_info;
  23 struct trap_per_cpu {
  24 /* D-cache line 1: Basic thread information, cpu and device mondo queues */
  25         struct thread_info      *thread;
  26         unsigned long           pgd_paddr;
  27         unsigned long           cpu_mondo_pa;
  28         unsigned long           dev_mondo_pa;
  29
  30 /* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
  31         unsigned long           resum_mondo_pa;
  32         unsigned long           resum_kernel_buf_pa;
  33         unsigned long           nonresum_mondo_pa;
  34         unsigned long           nonresum_kernel_buf_pa;
  35
  36 /* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
  37         struct hv_fault_status  fault_info;
  38
  39 /* Dcache line 7: Physical addresses of CPU send mondo block and CPU list.  */
  40         unsigned long           cpu_mondo_block_pa;
  41         unsigned long           cpu_list_pa;
  42         unsigned long           tsb_huge;
  43         unsigned long           tsb_huge_temp;
  44
  45 /* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size.  */
  46         unsigned long           irq_worklist_pa;
  47         unsigned int            cpu_mondo_qmask;
  48         unsigned int            dev_mondo_qmask;
  49         unsigned int            resum_qmask;
  50         unsigned int            nonresum_qmask;
  51         unsigned long           __per_cpu_base;
  52 } __attribute__((aligned(64)));
  53 extern struct trap_per_cpu trap_block[NR_CPUS];
  54 void init_cur_cpu_trap(struct thread_info *);
  55 void setup_tba(void);
  56 extern int ncpus_probed;
  57 extern u64 cpu_mondo_counter[NR_CPUS];
  58
  59 unsigned long real_hard_smp_processor_id(void);
  60
  61 struct cpuid_patch_entry {
  62         unsigned int    addr;
  63         unsigned int    cheetah_safari[4];
  64         unsigned int    cheetah_jbus[4];
  65         unsigned int    starfire[4];
  66         unsigned int    sun4v[4];
  67 };
  68 extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
  69
  70 struct sun4v_1insn_patch_entry {
  71         unsigned int    addr;
  72         unsigned int    insn;
  73 };
  74 extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
  75         __sun4v_1insn_patch_end;
  76 extern struct sun4v_1insn_patch_entry __fast_win_ctrl_1insn_patch,
  77         __fast_win_ctrl_1insn_patch_end;
  78
  79 struct sun4v_2insn_patch_entry {
  80         unsigned int    addr;
  81         unsigned int    insns[2];
  82 };
  83 extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
  84         __sun4v_2insn_patch_end;
  85 extern struct sun4v_2insn_patch_entry __sun_m7_2insn_patch,
  86         __sun_m7_2insn_patch_end;
  87
  88
  89 #endif /* !(__ASSEMBLY__) */
  90
  91 #define TRAP_PER_CPU_THREAD             0x00
  92 #define TRAP_PER_CPU_PGD_PADDR          0x08
  93 #define TRAP_PER_CPU_CPU_MONDO_PA       0x10
  94 #define TRAP_PER_CPU_DEV_MONDO_PA       0x18
  95 #define TRAP_PER_CPU_RESUM_MONDO_PA     0x20
  96 #define TRAP_PER_CPU_RESUM_KBUF_PA      0x28
  97 #define TRAP_PER_CPU_NONRESUM_MONDO_PA  0x30
  98 #define TRAP_PER_CPU_NONRESUM_KBUF_PA   0x38
  99 #define TRAP_PER_CPU_FAULT_INFO         0x40
 100 #define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
 101 #define TRAP_PER_CPU_CPU_LIST_PA        0xc8
 102 #define TRAP_PER_CPU_TSB_HUGE           0xd0
 103 #define TRAP_PER_CPU_TSB_HUGE_TEMP      0xd8
 104 #define TRAP_PER_CPU_IRQ_WORKLIST_PA    0xe0
 105 #define TRAP_PER_CPU_CPU_MONDO_QMASK    0xe8
 106 #define TRAP_PER_CPU_DEV_MONDO_QMASK    0xec
 107 #define TRAP_PER_CPU_RESUM_QMASK        0xf0
 108 #define TRAP_PER_CPU_NONRESUM_QMASK     0xf4
 109 #define TRAP_PER_CPU_PER_CPU_BASE       0xf8
 110
 111 #define TRAP_BLOCK_SZ_SHIFT             8
 112
 113 #include <asm/scratchpad.h>
 114
 115 #define __GET_CPUID(REG)                                \
 116         /* Spitfire implementation (default). */        \
 117 661:    ldxa            [%g0] ASI_UPA_CONFIG, REG;      \
 118         srlx            REG, 17, REG;                   \
 119          and            REG, 0x1f, REG;                 \
 120         nop;                                            \
 121         .section        .cpuid_patch, "ax";             \
 122         /* Instruction location. */                     \
 123         .word           661b;                           \
 124         /* Cheetah Safari implementation. */            \
 125         ldxa            [%g0] ASI_SAFARI_CONFIG, REG;   \
 126         srlx            REG, 17, REG;                   \
 127         and             REG, 0x3ff, REG;                \
 128         nop;                                            \
 129         /* Cheetah JBUS implementation. */              \
 130         ldxa            [%g0] ASI_JBUS_CONFIG, REG;     \
 131         srlx            REG, 17, REG;                   \
 132         and             REG, 0x1f, REG;                 \
 133         nop;                                            \
 134         /* Starfire implementation. */                  \
 135         sethi           %hi(0x1fff40000d0 >> 9), REG;   \
 136         sllx            REG, 9, REG;                    \
 137         or              REG, 0xd0, REG;                 \
 138         lduwa           [REG] ASI_PHYS_BYPASS_EC_E, REG;\
 139         /* sun4v implementation. */                     \
 140         mov             SCRATCHPAD_CPUID, REG;          \
 141         ldxa            [REG] ASI_SCRATCHPAD, REG;      \
 142         nop;                                            \
 143         nop;                                            \
 144         .previous;
 145
 146 #ifdef CONFIG_SMP
 147
 148 #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 149         __GET_CPUID(TMP)                        \
 150         sethi   %hi(trap_block), DEST;          \
 151         sllx    TMP, TRAP_BLOCK_SZ_SHIFT, TMP;  \
 152         or      DEST, %lo(trap_block), DEST;    \
 153         add     DEST, TMP, DEST;                \
 154
 155 /* Clobbers TMP, current address space PGD phys address into DEST.  */
 156 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
 157         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 158         ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
 159
 160 /* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
 161 #define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)        \
 162         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 163         add     DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
 164
 165 /* Clobbers TMP, loads DEST with current thread info pointer.  */
 166 #define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
 167         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 168         ldx     [DEST + TRAP_PER_CPU_THREAD], DEST;
 169
 170 /* Given the current thread info pointer in THR, load the per-cpu
 171  * area base of the current processor into DEST.  REG1, REG2, and REG3 are
 172  * clobbered.
 173  *
 174  * You absolutely cannot use DEST as a temporary in this code.  The
 175  * reason is that traps can happen during execution, and return from
 176  * trap will load the fully resolved DEST per-cpu base.  This can corrupt
 177  * the calculations done by the macro mid-stream.
 178  */
 179 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)  \
 180         lduh    [THR + TI_CPU], REG1;                   \
 181         sethi   %hi(trap_block), REG2;                  \
 182         sllx    REG1, TRAP_BLOCK_SZ_SHIFT, REG1;        \
 183         or      REG2, %lo(trap_block), REG2;            \
 184         add     REG2, REG1, REG2;                       \
 185         ldx     [REG2 + TRAP_PER_CPU_PER_CPU_BASE], DEST;
 186
 187 #else
 188
 189 #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 190         sethi   %hi(trap_block), DEST;          \
 191         or      DEST, %lo(trap_block), DEST;    \
 192
 193 /* Uniprocessor versions, we know the cpuid is zero.  */
 194 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
 195         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 196         ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
 197
 198 /* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
 199 #define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)        \
 200         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 201         add     DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
 202
 203 #define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
 204         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 205         ldx     [DEST + TRAP_PER_CPU_THREAD], DEST;
 206
 207 /* No per-cpu areas on uniprocessor, so no need to load DEST.  */
 208 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
 209
 210 #endif /* !(CONFIG_SMP) */
 211
 212 #endif /* _SPARC_TRAP_BLOCK_H */