4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/stddef.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/export.h>
15 #include <linux/nmi.h>
17 #include <asm/cpufeature.h>
18 #include <asm/hardirq.h>
19 #include <asm/intel-family.h>
22 #include "../perf_event.h"
25 * Intel PerfMon, used on Core and later.
27 static u64 intel_perfmon_event_map
[PERF_COUNT_HW_MAX
] __read_mostly
=
29 [PERF_COUNT_HW_CPU_CYCLES
] = 0x003c,
30 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
31 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x4f2e,
32 [PERF_COUNT_HW_CACHE_MISSES
] = 0x412e,
33 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
34 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
35 [PERF_COUNT_HW_BUS_CYCLES
] = 0x013c,
36 [PERF_COUNT_HW_REF_CPU_CYCLES
] = 0x0300, /* pseudo-encoding */
39 static struct event_constraint intel_core_event_constraints
[] __read_mostly
=
41 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
42 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
43 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
44 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
45 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
46 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
50 static struct event_constraint intel_core2_event_constraints
[] __read_mostly
=
52 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
53 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
54 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
55 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
56 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
57 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
58 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
59 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
60 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
61 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
62 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
63 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
64 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
68 static struct event_constraint intel_nehalem_event_constraints
[] __read_mostly
=
70 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
71 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
72 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
73 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
74 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
75 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
76 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
77 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
78 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
79 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
80 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
84 static struct extra_reg intel_nehalem_extra_regs
[] __read_mostly
=
86 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
87 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0xffff, RSP_0
),
88 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
92 static struct event_constraint intel_westmere_event_constraints
[] __read_mostly
=
94 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
95 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
96 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
97 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
98 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
99 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
100 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
104 static struct event_constraint intel_snb_event_constraints
[] __read_mostly
=
106 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
107 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
108 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
109 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
110 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
112 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
113 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
114 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
115 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
120 * When HT is off these events can only run on the bottom 4 counters
121 * When HT is on, they are impacted by the HT bug and require EXCL access
123 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
124 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
125 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
126 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
131 static struct event_constraint intel_ivb_event_constraints
[] __read_mostly
=
133 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
134 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
135 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
136 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
138 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
139 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
141 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
142 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
144 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
148 * When HT is off these events can only run on the bottom 4 counters
149 * When HT is on, they are impacted by the HT bug and require EXCL access
151 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
152 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
153 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
154 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
159 static struct extra_reg intel_westmere_extra_regs
[] __read_mostly
=
161 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
162 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0xffff, RSP_0
),
163 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1
, 0xffff, RSP_1
),
164 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
168 static struct event_constraint intel_v1_event_constraints
[] __read_mostly
=
173 static struct event_constraint intel_gen_event_constraints
[] __read_mostly
=
175 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
176 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
177 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
181 static struct event_constraint intel_slm_event_constraints
[] __read_mostly
=
183 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
184 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
185 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
189 static struct event_constraint intel_skl_event_constraints
[] = {
190 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
191 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
192 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
193 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
196 * when HT is off, these can only run on the bottom 4 counters
198 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
199 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
200 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
201 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
202 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
207 static struct extra_reg intel_knl_extra_regs
[] __read_mostly
= {
208 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0x799ffbb6e7ull
, RSP_0
),
209 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1
, 0x399ffbffe7ull
, RSP_1
),
213 static struct extra_reg intel_snb_extra_regs
[] __read_mostly
= {
214 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
215 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0x3f807f8fffull
, RSP_0
),
216 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1
, 0x3f807f8fffull
, RSP_1
),
217 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
221 static struct extra_reg intel_snbep_extra_regs
[] __read_mostly
= {
222 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
223 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0x3fffff8fffull
, RSP_0
),
224 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1
, 0x3fffff8fffull
, RSP_1
),
225 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
229 static struct extra_reg intel_skl_extra_regs
[] __read_mostly
= {
230 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0x3fffff8fffull
, RSP_0
),
231 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1
, 0x3fffff8fffull
, RSP_1
),
232 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
234 * Note the low 8 bits eventsel code is not a continuous field, containing
235 * some #GPing bits. These are masked out.
237 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND
, 0x7fff17, FE
),
241 EVENT_ATTR_STR(mem
-loads
, mem_ld_nhm
, "event=0x0b,umask=0x10,ldlat=3");
242 EVENT_ATTR_STR(mem
-loads
, mem_ld_snb
, "event=0xcd,umask=0x1,ldlat=3");
243 EVENT_ATTR_STR(mem
-stores
, mem_st_snb
, "event=0xcd,umask=0x2");
245 static struct attribute
*nhm_events_attrs
[] = {
246 EVENT_PTR(mem_ld_nhm
),
251 * topdown events for Intel Core CPUs.
253 * The events are all in slots, which is a free slot in a 4 wide
254 * pipeline. Some events are already reported in slots, for cycle
255 * events we multiply by the pipeline width (4).
257 * With Hyper Threading on, topdown metrics are either summed or averaged
258 * between the threads of a core: (count_t0 + count_t1).
260 * For the average case the metric is always scaled to pipeline width,
261 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
264 EVENT_ATTR_STR_HT(topdown
-total
-slots
, td_total_slots
,
265 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
266 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
267 EVENT_ATTR_STR_HT(topdown
-total
-slots
.scale
, td_total_slots_scale
, "4", "2");
268 EVENT_ATTR_STR(topdown
-slots
-issued
, td_slots_issued
,
269 "event=0xe,umask=0x1"); /* uops_issued.any */
270 EVENT_ATTR_STR(topdown
-slots
-retired
, td_slots_retired
,
271 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
272 EVENT_ATTR_STR(topdown
-fetch
-bubbles
, td_fetch_bubbles
,
273 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
274 EVENT_ATTR_STR_HT(topdown
-recovery
-bubbles
, td_recovery_bubbles
,
275 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
276 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
277 EVENT_ATTR_STR_HT(topdown
-recovery
-bubbles
.scale
, td_recovery_bubbles_scale
,
280 static struct attribute
*snb_events_attrs
[] = {
281 EVENT_PTR(mem_ld_snb
),
282 EVENT_PTR(mem_st_snb
),
283 EVENT_PTR(td_slots_issued
),
284 EVENT_PTR(td_slots_retired
),
285 EVENT_PTR(td_fetch_bubbles
),
286 EVENT_PTR(td_total_slots
),
287 EVENT_PTR(td_total_slots_scale
),
288 EVENT_PTR(td_recovery_bubbles
),
289 EVENT_PTR(td_recovery_bubbles_scale
),
293 static struct event_constraint intel_hsw_event_constraints
[] = {
294 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
295 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
296 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
297 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
298 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
299 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
300 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
301 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
302 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
303 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
304 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
305 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
308 * When HT is off these events can only run on the bottom 4 counters
309 * When HT is on, they are impacted by the HT bug and require EXCL access
311 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
312 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
313 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
314 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
319 static struct event_constraint intel_bdw_event_constraints
[] = {
320 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
321 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
322 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
323 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
324 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
326 * when HT is off, these can only run on the bottom 4 counters
328 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
329 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
330 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
331 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
335 static u64
intel_pmu_event_map(int hw_event
)
337 return intel_perfmon_event_map
[hw_event
];
341 * Notes on the events:
342 * - data reads do not include code reads (comparable to earlier tables)
343 * - data counts include speculative execution (except L1 write, dtlb, bpu)
344 * - remote node access includes remote memory, remote cache, remote mmio.
345 * - prefetches are not included in the counts.
346 * - icache miss does not include decoded icache
349 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
350 #define SKL_DEMAND_RFO BIT_ULL(1)
351 #define SKL_ANY_RESPONSE BIT_ULL(16)
352 #define SKL_SUPPLIER_NONE BIT_ULL(17)
353 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
354 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
355 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
356 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
357 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
358 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
359 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
360 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
361 #define SKL_SPL_HIT BIT_ULL(30)
362 #define SKL_SNOOP_NONE BIT_ULL(31)
363 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
364 #define SKL_SNOOP_MISS BIT_ULL(33)
365 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
366 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
367 #define SKL_SNOOP_HITM BIT_ULL(36)
368 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
369 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
370 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
371 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
372 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
373 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
374 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
375 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
376 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
377 SKL_SNOOP_HITM|SKL_SPL_HIT)
378 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
379 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
380 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
381 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
382 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
384 static __initconst
const u64 skl_hw_cache_event_ids
385 [PERF_COUNT_HW_CACHE_MAX
]
386 [PERF_COUNT_HW_CACHE_OP_MAX
]
387 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
391 [ C(RESULT_ACCESS
) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
392 [ C(RESULT_MISS
) ] = 0x151, /* L1D.REPLACEMENT */
395 [ C(RESULT_ACCESS
) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
396 [ C(RESULT_MISS
) ] = 0x0,
398 [ C(OP_PREFETCH
) ] = {
399 [ C(RESULT_ACCESS
) ] = 0x0,
400 [ C(RESULT_MISS
) ] = 0x0,
405 [ C(RESULT_ACCESS
) ] = 0x0,
406 [ C(RESULT_MISS
) ] = 0x283, /* ICACHE_64B.MISS */
409 [ C(RESULT_ACCESS
) ] = -1,
410 [ C(RESULT_MISS
) ] = -1,
412 [ C(OP_PREFETCH
) ] = {
413 [ C(RESULT_ACCESS
) ] = 0x0,
414 [ C(RESULT_MISS
) ] = 0x0,
419 [ C(RESULT_ACCESS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
420 [ C(RESULT_MISS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
423 [ C(RESULT_ACCESS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
424 [ C(RESULT_MISS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
426 [ C(OP_PREFETCH
) ] = {
427 [ C(RESULT_ACCESS
) ] = 0x0,
428 [ C(RESULT_MISS
) ] = 0x0,
433 [ C(RESULT_ACCESS
) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
434 [ C(RESULT_MISS
) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
437 [ C(RESULT_ACCESS
) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
438 [ C(RESULT_MISS
) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
440 [ C(OP_PREFETCH
) ] = {
441 [ C(RESULT_ACCESS
) ] = 0x0,
442 [ C(RESULT_MISS
) ] = 0x0,
447 [ C(RESULT_ACCESS
) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
448 [ C(RESULT_MISS
) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
451 [ C(RESULT_ACCESS
) ] = -1,
452 [ C(RESULT_MISS
) ] = -1,
454 [ C(OP_PREFETCH
) ] = {
455 [ C(RESULT_ACCESS
) ] = -1,
456 [ C(RESULT_MISS
) ] = -1,
461 [ C(RESULT_ACCESS
) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
462 [ C(RESULT_MISS
) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
465 [ C(RESULT_ACCESS
) ] = -1,
466 [ C(RESULT_MISS
) ] = -1,
468 [ C(OP_PREFETCH
) ] = {
469 [ C(RESULT_ACCESS
) ] = -1,
470 [ C(RESULT_MISS
) ] = -1,
475 [ C(RESULT_ACCESS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
476 [ C(RESULT_MISS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
479 [ C(RESULT_ACCESS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
480 [ C(RESULT_MISS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
482 [ C(OP_PREFETCH
) ] = {
483 [ C(RESULT_ACCESS
) ] = 0x0,
484 [ C(RESULT_MISS
) ] = 0x0,
489 static __initconst
const u64 skl_hw_cache_extra_regs
490 [PERF_COUNT_HW_CACHE_MAX
]
491 [PERF_COUNT_HW_CACHE_OP_MAX
]
492 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
496 [ C(RESULT_ACCESS
) ] = SKL_DEMAND_READ
|
497 SKL_LLC_ACCESS
|SKL_ANY_SNOOP
,
498 [ C(RESULT_MISS
) ] = SKL_DEMAND_READ
|
499 SKL_L3_MISS
|SKL_ANY_SNOOP
|
503 [ C(RESULT_ACCESS
) ] = SKL_DEMAND_WRITE
|
504 SKL_LLC_ACCESS
|SKL_ANY_SNOOP
,
505 [ C(RESULT_MISS
) ] = SKL_DEMAND_WRITE
|
506 SKL_L3_MISS
|SKL_ANY_SNOOP
|
509 [ C(OP_PREFETCH
) ] = {
510 [ C(RESULT_ACCESS
) ] = 0x0,
511 [ C(RESULT_MISS
) ] = 0x0,
516 [ C(RESULT_ACCESS
) ] = SKL_DEMAND_READ
|
517 SKL_L3_MISS_LOCAL_DRAM
|SKL_SNOOP_DRAM
,
518 [ C(RESULT_MISS
) ] = SKL_DEMAND_READ
|
519 SKL_L3_MISS_REMOTE
|SKL_SNOOP_DRAM
,
522 [ C(RESULT_ACCESS
) ] = SKL_DEMAND_WRITE
|
523 SKL_L3_MISS_LOCAL_DRAM
|SKL_SNOOP_DRAM
,
524 [ C(RESULT_MISS
) ] = SKL_DEMAND_WRITE
|
525 SKL_L3_MISS_REMOTE
|SKL_SNOOP_DRAM
,
527 [ C(OP_PREFETCH
) ] = {
528 [ C(RESULT_ACCESS
) ] = 0x0,
529 [ C(RESULT_MISS
) ] = 0x0,
534 #define SNB_DMND_DATA_RD (1ULL << 0)
535 #define SNB_DMND_RFO (1ULL << 1)
536 #define SNB_DMND_IFETCH (1ULL << 2)
537 #define SNB_DMND_WB (1ULL << 3)
538 #define SNB_PF_DATA_RD (1ULL << 4)
539 #define SNB_PF_RFO (1ULL << 5)
540 #define SNB_PF_IFETCH (1ULL << 6)
541 #define SNB_LLC_DATA_RD (1ULL << 7)
542 #define SNB_LLC_RFO (1ULL << 8)
543 #define SNB_LLC_IFETCH (1ULL << 9)
544 #define SNB_BUS_LOCKS (1ULL << 10)
545 #define SNB_STRM_ST (1ULL << 11)
546 #define SNB_OTHER (1ULL << 15)
547 #define SNB_RESP_ANY (1ULL << 16)
548 #define SNB_NO_SUPP (1ULL << 17)
549 #define SNB_LLC_HITM (1ULL << 18)
550 #define SNB_LLC_HITE (1ULL << 19)
551 #define SNB_LLC_HITS (1ULL << 20)
552 #define SNB_LLC_HITF (1ULL << 21)
553 #define SNB_LOCAL (1ULL << 22)
554 #define SNB_REMOTE (0xffULL << 23)
555 #define SNB_SNP_NONE (1ULL << 31)
556 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
557 #define SNB_SNP_MISS (1ULL << 33)
558 #define SNB_NO_FWD (1ULL << 34)
559 #define SNB_SNP_FWD (1ULL << 35)
560 #define SNB_HITM (1ULL << 36)
561 #define SNB_NON_DRAM (1ULL << 37)
563 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
564 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
565 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
567 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
568 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
571 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
572 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
574 #define SNB_L3_ACCESS SNB_RESP_ANY
575 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
577 static __initconst
const u64 snb_hw_cache_extra_regs
578 [PERF_COUNT_HW_CACHE_MAX
]
579 [PERF_COUNT_HW_CACHE_OP_MAX
]
580 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
584 [ C(RESULT_ACCESS
) ] = SNB_DMND_READ
|SNB_L3_ACCESS
,
585 [ C(RESULT_MISS
) ] = SNB_DMND_READ
|SNB_L3_MISS
,
588 [ C(RESULT_ACCESS
) ] = SNB_DMND_WRITE
|SNB_L3_ACCESS
,
589 [ C(RESULT_MISS
) ] = SNB_DMND_WRITE
|SNB_L3_MISS
,
591 [ C(OP_PREFETCH
) ] = {
592 [ C(RESULT_ACCESS
) ] = SNB_DMND_PREFETCH
|SNB_L3_ACCESS
,
593 [ C(RESULT_MISS
) ] = SNB_DMND_PREFETCH
|SNB_L3_MISS
,
598 [ C(RESULT_ACCESS
) ] = SNB_DMND_READ
|SNB_DRAM_ANY
,
599 [ C(RESULT_MISS
) ] = SNB_DMND_READ
|SNB_DRAM_REMOTE
,
602 [ C(RESULT_ACCESS
) ] = SNB_DMND_WRITE
|SNB_DRAM_ANY
,
603 [ C(RESULT_MISS
) ] = SNB_DMND_WRITE
|SNB_DRAM_REMOTE
,
605 [ C(OP_PREFETCH
) ] = {
606 [ C(RESULT_ACCESS
) ] = SNB_DMND_PREFETCH
|SNB_DRAM_ANY
,
607 [ C(RESULT_MISS
) ] = SNB_DMND_PREFETCH
|SNB_DRAM_REMOTE
,
612 static __initconst
const u64 snb_hw_cache_event_ids
613 [PERF_COUNT_HW_CACHE_MAX
]
614 [PERF_COUNT_HW_CACHE_OP_MAX
]
615 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
619 [ C(RESULT_ACCESS
) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
620 [ C(RESULT_MISS
) ] = 0x0151, /* L1D.REPLACEMENT */
623 [ C(RESULT_ACCESS
) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
624 [ C(RESULT_MISS
) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
626 [ C(OP_PREFETCH
) ] = {
627 [ C(RESULT_ACCESS
) ] = 0x0,
628 [ C(RESULT_MISS
) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
633 [ C(RESULT_ACCESS
) ] = 0x0,
634 [ C(RESULT_MISS
) ] = 0x0280, /* ICACHE.MISSES */
637 [ C(RESULT_ACCESS
) ] = -1,
638 [ C(RESULT_MISS
) ] = -1,
640 [ C(OP_PREFETCH
) ] = {
641 [ C(RESULT_ACCESS
) ] = 0x0,
642 [ C(RESULT_MISS
) ] = 0x0,
647 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
648 [ C(RESULT_ACCESS
) ] = 0x01b7,
649 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
650 [ C(RESULT_MISS
) ] = 0x01b7,
653 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
654 [ C(RESULT_ACCESS
) ] = 0x01b7,
655 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
656 [ C(RESULT_MISS
) ] = 0x01b7,
658 [ C(OP_PREFETCH
) ] = {
659 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
660 [ C(RESULT_ACCESS
) ] = 0x01b7,
661 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
662 [ C(RESULT_MISS
) ] = 0x01b7,
667 [ C(RESULT_ACCESS
) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
668 [ C(RESULT_MISS
) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
671 [ C(RESULT_ACCESS
) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
672 [ C(RESULT_MISS
) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
674 [ C(OP_PREFETCH
) ] = {
675 [ C(RESULT_ACCESS
) ] = 0x0,
676 [ C(RESULT_MISS
) ] = 0x0,
681 [ C(RESULT_ACCESS
) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
682 [ C(RESULT_MISS
) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
685 [ C(RESULT_ACCESS
) ] = -1,
686 [ C(RESULT_MISS
) ] = -1,
688 [ C(OP_PREFETCH
) ] = {
689 [ C(RESULT_ACCESS
) ] = -1,
690 [ C(RESULT_MISS
) ] = -1,
695 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
696 [ C(RESULT_MISS
) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
699 [ C(RESULT_ACCESS
) ] = -1,
700 [ C(RESULT_MISS
) ] = -1,
702 [ C(OP_PREFETCH
) ] = {
703 [ C(RESULT_ACCESS
) ] = -1,
704 [ C(RESULT_MISS
) ] = -1,
709 [ C(RESULT_ACCESS
) ] = 0x01b7,
710 [ C(RESULT_MISS
) ] = 0x01b7,
713 [ C(RESULT_ACCESS
) ] = 0x01b7,
714 [ C(RESULT_MISS
) ] = 0x01b7,
716 [ C(OP_PREFETCH
) ] = {
717 [ C(RESULT_ACCESS
) ] = 0x01b7,
718 [ C(RESULT_MISS
) ] = 0x01b7,
725 * Notes on the events:
726 * - data reads do not include code reads (comparable to earlier tables)
727 * - data counts include speculative execution (except L1 write, dtlb, bpu)
728 * - remote node access includes remote memory, remote cache, remote mmio.
729 * - prefetches are not included in the counts because they are not
733 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
734 #define HSW_DEMAND_RFO BIT_ULL(1)
735 #define HSW_ANY_RESPONSE BIT_ULL(16)
736 #define HSW_SUPPLIER_NONE BIT_ULL(17)
737 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
738 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
739 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
740 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
741 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
742 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
743 HSW_L3_MISS_REMOTE_HOP2P)
744 #define HSW_SNOOP_NONE BIT_ULL(31)
745 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
746 #define HSW_SNOOP_MISS BIT_ULL(33)
747 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
748 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
749 #define HSW_SNOOP_HITM BIT_ULL(36)
750 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
751 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
752 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
753 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
754 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
755 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
756 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
757 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
758 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
759 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
760 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
762 #define BDW_L3_MISS_LOCAL BIT(26)
763 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
764 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
765 HSW_L3_MISS_REMOTE_HOP2P)
768 static __initconst
const u64 hsw_hw_cache_event_ids
769 [PERF_COUNT_HW_CACHE_MAX
]
770 [PERF_COUNT_HW_CACHE_OP_MAX
]
771 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
775 [ C(RESULT_ACCESS
) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
776 [ C(RESULT_MISS
) ] = 0x151, /* L1D.REPLACEMENT */
779 [ C(RESULT_ACCESS
) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
780 [ C(RESULT_MISS
) ] = 0x0,
782 [ C(OP_PREFETCH
) ] = {
783 [ C(RESULT_ACCESS
) ] = 0x0,
784 [ C(RESULT_MISS
) ] = 0x0,
789 [ C(RESULT_ACCESS
) ] = 0x0,
790 [ C(RESULT_MISS
) ] = 0x280, /* ICACHE.MISSES */
793 [ C(RESULT_ACCESS
) ] = -1,
794 [ C(RESULT_MISS
) ] = -1,
796 [ C(OP_PREFETCH
) ] = {
797 [ C(RESULT_ACCESS
) ] = 0x0,
798 [ C(RESULT_MISS
) ] = 0x0,
803 [ C(RESULT_ACCESS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
804 [ C(RESULT_MISS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
807 [ C(RESULT_ACCESS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
808 [ C(RESULT_MISS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
810 [ C(OP_PREFETCH
) ] = {
811 [ C(RESULT_ACCESS
) ] = 0x0,
812 [ C(RESULT_MISS
) ] = 0x0,
817 [ C(RESULT_ACCESS
) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
818 [ C(RESULT_MISS
) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
821 [ C(RESULT_ACCESS
) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
822 [ C(RESULT_MISS
) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
824 [ C(OP_PREFETCH
) ] = {
825 [ C(RESULT_ACCESS
) ] = 0x0,
826 [ C(RESULT_MISS
) ] = 0x0,
831 [ C(RESULT_ACCESS
) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
832 [ C(RESULT_MISS
) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
835 [ C(RESULT_ACCESS
) ] = -1,
836 [ C(RESULT_MISS
) ] = -1,
838 [ C(OP_PREFETCH
) ] = {
839 [ C(RESULT_ACCESS
) ] = -1,
840 [ C(RESULT_MISS
) ] = -1,
845 [ C(RESULT_ACCESS
) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
846 [ C(RESULT_MISS
) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
849 [ C(RESULT_ACCESS
) ] = -1,
850 [ C(RESULT_MISS
) ] = -1,
852 [ C(OP_PREFETCH
) ] = {
853 [ C(RESULT_ACCESS
) ] = -1,
854 [ C(RESULT_MISS
) ] = -1,
859 [ C(RESULT_ACCESS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
860 [ C(RESULT_MISS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
863 [ C(RESULT_ACCESS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
864 [ C(RESULT_MISS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
866 [ C(OP_PREFETCH
) ] = {
867 [ C(RESULT_ACCESS
) ] = 0x0,
868 [ C(RESULT_MISS
) ] = 0x0,
873 static __initconst
const u64 hsw_hw_cache_extra_regs
874 [PERF_COUNT_HW_CACHE_MAX
]
875 [PERF_COUNT_HW_CACHE_OP_MAX
]
876 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
880 [ C(RESULT_ACCESS
) ] = HSW_DEMAND_READ
|
882 [ C(RESULT_MISS
) ] = HSW_DEMAND_READ
|
883 HSW_L3_MISS
|HSW_ANY_SNOOP
,
886 [ C(RESULT_ACCESS
) ] = HSW_DEMAND_WRITE
|
888 [ C(RESULT_MISS
) ] = HSW_DEMAND_WRITE
|
889 HSW_L3_MISS
|HSW_ANY_SNOOP
,
891 [ C(OP_PREFETCH
) ] = {
892 [ C(RESULT_ACCESS
) ] = 0x0,
893 [ C(RESULT_MISS
) ] = 0x0,
898 [ C(RESULT_ACCESS
) ] = HSW_DEMAND_READ
|
899 HSW_L3_MISS_LOCAL_DRAM
|
901 [ C(RESULT_MISS
) ] = HSW_DEMAND_READ
|
906 [ C(RESULT_ACCESS
) ] = HSW_DEMAND_WRITE
|
907 HSW_L3_MISS_LOCAL_DRAM
|
909 [ C(RESULT_MISS
) ] = HSW_DEMAND_WRITE
|
913 [ C(OP_PREFETCH
) ] = {
914 [ C(RESULT_ACCESS
) ] = 0x0,
915 [ C(RESULT_MISS
) ] = 0x0,
920 static __initconst
const u64 westmere_hw_cache_event_ids
921 [PERF_COUNT_HW_CACHE_MAX
]
922 [PERF_COUNT_HW_CACHE_OP_MAX
]
923 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
927 [ C(RESULT_ACCESS
) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
928 [ C(RESULT_MISS
) ] = 0x0151, /* L1D.REPL */
931 [ C(RESULT_ACCESS
) ] = 0x020b, /* MEM_INST_RETURED.STORES */
932 [ C(RESULT_MISS
) ] = 0x0251, /* L1D.M_REPL */
934 [ C(OP_PREFETCH
) ] = {
935 [ C(RESULT_ACCESS
) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
936 [ C(RESULT_MISS
) ] = 0x024e, /* L1D_PREFETCH.MISS */
941 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
942 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
945 [ C(RESULT_ACCESS
) ] = -1,
946 [ C(RESULT_MISS
) ] = -1,
948 [ C(OP_PREFETCH
) ] = {
949 [ C(RESULT_ACCESS
) ] = 0x0,
950 [ C(RESULT_MISS
) ] = 0x0,
955 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
956 [ C(RESULT_ACCESS
) ] = 0x01b7,
957 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
958 [ C(RESULT_MISS
) ] = 0x01b7,
961 * Use RFO, not WRITEBACK, because a write miss would typically occur
965 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
966 [ C(RESULT_ACCESS
) ] = 0x01b7,
967 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
968 [ C(RESULT_MISS
) ] = 0x01b7,
970 [ C(OP_PREFETCH
) ] = {
971 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
972 [ C(RESULT_ACCESS
) ] = 0x01b7,
973 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
974 [ C(RESULT_MISS
) ] = 0x01b7,
979 [ C(RESULT_ACCESS
) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
980 [ C(RESULT_MISS
) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
983 [ C(RESULT_ACCESS
) ] = 0x020b, /* MEM_INST_RETURED.STORES */
984 [ C(RESULT_MISS
) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
986 [ C(OP_PREFETCH
) ] = {
987 [ C(RESULT_ACCESS
) ] = 0x0,
988 [ C(RESULT_MISS
) ] = 0x0,
993 [ C(RESULT_ACCESS
) ] = 0x01c0, /* INST_RETIRED.ANY_P */
994 [ C(RESULT_MISS
) ] = 0x0185, /* ITLB_MISSES.ANY */
997 [ C(RESULT_ACCESS
) ] = -1,
998 [ C(RESULT_MISS
) ] = -1,
1000 [ C(OP_PREFETCH
) ] = {
1001 [ C(RESULT_ACCESS
) ] = -1,
1002 [ C(RESULT_MISS
) ] = -1,
1007 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1008 [ C(RESULT_MISS
) ] = 0x03e8, /* BPU_CLEARS.ANY */
1011 [ C(RESULT_ACCESS
) ] = -1,
1012 [ C(RESULT_MISS
) ] = -1,
1014 [ C(OP_PREFETCH
) ] = {
1015 [ C(RESULT_ACCESS
) ] = -1,
1016 [ C(RESULT_MISS
) ] = -1,
1021 [ C(RESULT_ACCESS
) ] = 0x01b7,
1022 [ C(RESULT_MISS
) ] = 0x01b7,
1025 [ C(RESULT_ACCESS
) ] = 0x01b7,
1026 [ C(RESULT_MISS
) ] = 0x01b7,
1028 [ C(OP_PREFETCH
) ] = {
1029 [ C(RESULT_ACCESS
) ] = 0x01b7,
1030 [ C(RESULT_MISS
) ] = 0x01b7,
1036 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1037 * See IA32 SDM Vol 3B 30.6.1.3
1040 #define NHM_DMND_DATA_RD (1 << 0)
1041 #define NHM_DMND_RFO (1 << 1)
1042 #define NHM_DMND_IFETCH (1 << 2)
1043 #define NHM_DMND_WB (1 << 3)
1044 #define NHM_PF_DATA_RD (1 << 4)
1045 #define NHM_PF_DATA_RFO (1 << 5)
1046 #define NHM_PF_IFETCH (1 << 6)
1047 #define NHM_OFFCORE_OTHER (1 << 7)
1048 #define NHM_UNCORE_HIT (1 << 8)
1049 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1050 #define NHM_OTHER_CORE_HITM (1 << 10)
1052 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1053 #define NHM_REMOTE_DRAM (1 << 13)
1054 #define NHM_LOCAL_DRAM (1 << 14)
1055 #define NHM_NON_DRAM (1 << 15)
1057 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1058 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1060 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1061 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1062 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1064 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1065 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1066 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1068 static __initconst
const u64 nehalem_hw_cache_extra_regs
1069 [PERF_COUNT_HW_CACHE_MAX
]
1070 [PERF_COUNT_HW_CACHE_OP_MAX
]
1071 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
1075 [ C(RESULT_ACCESS
) ] = NHM_DMND_READ
|NHM_L3_ACCESS
,
1076 [ C(RESULT_MISS
) ] = NHM_DMND_READ
|NHM_L3_MISS
,
1079 [ C(RESULT_ACCESS
) ] = NHM_DMND_WRITE
|NHM_L3_ACCESS
,
1080 [ C(RESULT_MISS
) ] = NHM_DMND_WRITE
|NHM_L3_MISS
,
1082 [ C(OP_PREFETCH
) ] = {
1083 [ C(RESULT_ACCESS
) ] = NHM_DMND_PREFETCH
|NHM_L3_ACCESS
,
1084 [ C(RESULT_MISS
) ] = NHM_DMND_PREFETCH
|NHM_L3_MISS
,
1089 [ C(RESULT_ACCESS
) ] = NHM_DMND_READ
|NHM_LOCAL
|NHM_REMOTE
,
1090 [ C(RESULT_MISS
) ] = NHM_DMND_READ
|NHM_REMOTE
,
1093 [ C(RESULT_ACCESS
) ] = NHM_DMND_WRITE
|NHM_LOCAL
|NHM_REMOTE
,
1094 [ C(RESULT_MISS
) ] = NHM_DMND_WRITE
|NHM_REMOTE
,
1096 [ C(OP_PREFETCH
) ] = {
1097 [ C(RESULT_ACCESS
) ] = NHM_DMND_PREFETCH
|NHM_LOCAL
|NHM_REMOTE
,
1098 [ C(RESULT_MISS
) ] = NHM_DMND_PREFETCH
|NHM_REMOTE
,
1103 static __initconst
const u64 nehalem_hw_cache_event_ids
1104 [PERF_COUNT_HW_CACHE_MAX
]
1105 [PERF_COUNT_HW_CACHE_OP_MAX
]
1106 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
1110 [ C(RESULT_ACCESS
) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1111 [ C(RESULT_MISS
) ] = 0x0151, /* L1D.REPL */
1114 [ C(RESULT_ACCESS
) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1115 [ C(RESULT_MISS
) ] = 0x0251, /* L1D.M_REPL */
1117 [ C(OP_PREFETCH
) ] = {
1118 [ C(RESULT_ACCESS
) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1119 [ C(RESULT_MISS
) ] = 0x024e, /* L1D_PREFETCH.MISS */
1124 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
1125 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
1128 [ C(RESULT_ACCESS
) ] = -1,
1129 [ C(RESULT_MISS
) ] = -1,
1131 [ C(OP_PREFETCH
) ] = {
1132 [ C(RESULT_ACCESS
) ] = 0x0,
1133 [ C(RESULT_MISS
) ] = 0x0,
1138 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1139 [ C(RESULT_ACCESS
) ] = 0x01b7,
1140 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1141 [ C(RESULT_MISS
) ] = 0x01b7,
1144 * Use RFO, not WRITEBACK, because a write miss would typically occur
1148 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1149 [ C(RESULT_ACCESS
) ] = 0x01b7,
1150 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1151 [ C(RESULT_MISS
) ] = 0x01b7,
1153 [ C(OP_PREFETCH
) ] = {
1154 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1155 [ C(RESULT_ACCESS
) ] = 0x01b7,
1156 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1157 [ C(RESULT_MISS
) ] = 0x01b7,
1162 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1163 [ C(RESULT_MISS
) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1166 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1167 [ C(RESULT_MISS
) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1169 [ C(OP_PREFETCH
) ] = {
1170 [ C(RESULT_ACCESS
) ] = 0x0,
1171 [ C(RESULT_MISS
) ] = 0x0,
1176 [ C(RESULT_ACCESS
) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1177 [ C(RESULT_MISS
) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1180 [ C(RESULT_ACCESS
) ] = -1,
1181 [ C(RESULT_MISS
) ] = -1,
1183 [ C(OP_PREFETCH
) ] = {
1184 [ C(RESULT_ACCESS
) ] = -1,
1185 [ C(RESULT_MISS
) ] = -1,
1190 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1191 [ C(RESULT_MISS
) ] = 0x03e8, /* BPU_CLEARS.ANY */
1194 [ C(RESULT_ACCESS
) ] = -1,
1195 [ C(RESULT_MISS
) ] = -1,
1197 [ C(OP_PREFETCH
) ] = {
1198 [ C(RESULT_ACCESS
) ] = -1,
1199 [ C(RESULT_MISS
) ] = -1,
1204 [ C(RESULT_ACCESS
) ] = 0x01b7,
1205 [ C(RESULT_MISS
) ] = 0x01b7,
1208 [ C(RESULT_ACCESS
) ] = 0x01b7,
1209 [ C(RESULT_MISS
) ] = 0x01b7,
1211 [ C(OP_PREFETCH
) ] = {
1212 [ C(RESULT_ACCESS
) ] = 0x01b7,
1213 [ C(RESULT_MISS
) ] = 0x01b7,
1218 static __initconst
const u64 core2_hw_cache_event_ids
1219 [PERF_COUNT_HW_CACHE_MAX
]
1220 [PERF_COUNT_HW_CACHE_OP_MAX
]
1221 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
1225 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1226 [ C(RESULT_MISS
) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1229 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1230 [ C(RESULT_MISS
) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1232 [ C(OP_PREFETCH
) ] = {
1233 [ C(RESULT_ACCESS
) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1234 [ C(RESULT_MISS
) ] = 0,
1239 [ C(RESULT_ACCESS
) ] = 0x0080, /* L1I.READS */
1240 [ C(RESULT_MISS
) ] = 0x0081, /* L1I.MISSES */
1243 [ C(RESULT_ACCESS
) ] = -1,
1244 [ C(RESULT_MISS
) ] = -1,
1246 [ C(OP_PREFETCH
) ] = {
1247 [ C(RESULT_ACCESS
) ] = 0,
1248 [ C(RESULT_MISS
) ] = 0,
1253 [ C(RESULT_ACCESS
) ] = 0x4f29, /* L2_LD.MESI */
1254 [ C(RESULT_MISS
) ] = 0x4129, /* L2_LD.ISTATE */
1257 [ C(RESULT_ACCESS
) ] = 0x4f2A, /* L2_ST.MESI */
1258 [ C(RESULT_MISS
) ] = 0x412A, /* L2_ST.ISTATE */
1260 [ C(OP_PREFETCH
) ] = {
1261 [ C(RESULT_ACCESS
) ] = 0,
1262 [ C(RESULT_MISS
) ] = 0,
1267 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1268 [ C(RESULT_MISS
) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1271 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1272 [ C(RESULT_MISS
) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1274 [ C(OP_PREFETCH
) ] = {
1275 [ C(RESULT_ACCESS
) ] = 0,
1276 [ C(RESULT_MISS
) ] = 0,
1281 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1282 [ C(RESULT_MISS
) ] = 0x1282, /* ITLBMISSES */
1285 [ C(RESULT_ACCESS
) ] = -1,
1286 [ C(RESULT_MISS
) ] = -1,
1288 [ C(OP_PREFETCH
) ] = {
1289 [ C(RESULT_ACCESS
) ] = -1,
1290 [ C(RESULT_MISS
) ] = -1,
1295 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1296 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1299 [ C(RESULT_ACCESS
) ] = -1,
1300 [ C(RESULT_MISS
) ] = -1,
1302 [ C(OP_PREFETCH
) ] = {
1303 [ C(RESULT_ACCESS
) ] = -1,
1304 [ C(RESULT_MISS
) ] = -1,
1309 static __initconst
const u64 atom_hw_cache_event_ids
1310 [PERF_COUNT_HW_CACHE_MAX
]
1311 [PERF_COUNT_HW_CACHE_OP_MAX
]
1312 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
1316 [ C(RESULT_ACCESS
) ] = 0x2140, /* L1D_CACHE.LD */
1317 [ C(RESULT_MISS
) ] = 0,
1320 [ C(RESULT_ACCESS
) ] = 0x2240, /* L1D_CACHE.ST */
1321 [ C(RESULT_MISS
) ] = 0,
1323 [ C(OP_PREFETCH
) ] = {
1324 [ C(RESULT_ACCESS
) ] = 0x0,
1325 [ C(RESULT_MISS
) ] = 0,
1330 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
1331 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
1334 [ C(RESULT_ACCESS
) ] = -1,
1335 [ C(RESULT_MISS
) ] = -1,
1337 [ C(OP_PREFETCH
) ] = {
1338 [ C(RESULT_ACCESS
) ] = 0,
1339 [ C(RESULT_MISS
) ] = 0,
1344 [ C(RESULT_ACCESS
) ] = 0x4f29, /* L2_LD.MESI */
1345 [ C(RESULT_MISS
) ] = 0x4129, /* L2_LD.ISTATE */
1348 [ C(RESULT_ACCESS
) ] = 0x4f2A, /* L2_ST.MESI */
1349 [ C(RESULT_MISS
) ] = 0x412A, /* L2_ST.ISTATE */
1351 [ C(OP_PREFETCH
) ] = {
1352 [ C(RESULT_ACCESS
) ] = 0,
1353 [ C(RESULT_MISS
) ] = 0,
1358 [ C(RESULT_ACCESS
) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1359 [ C(RESULT_MISS
) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1362 [ C(RESULT_ACCESS
) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1363 [ C(RESULT_MISS
) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1365 [ C(OP_PREFETCH
) ] = {
1366 [ C(RESULT_ACCESS
) ] = 0,
1367 [ C(RESULT_MISS
) ] = 0,
1372 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1373 [ C(RESULT_MISS
) ] = 0x0282, /* ITLB.MISSES */
1376 [ C(RESULT_ACCESS
) ] = -1,
1377 [ C(RESULT_MISS
) ] = -1,
1379 [ C(OP_PREFETCH
) ] = {
1380 [ C(RESULT_ACCESS
) ] = -1,
1381 [ C(RESULT_MISS
) ] = -1,
1386 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1387 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1390 [ C(RESULT_ACCESS
) ] = -1,
1391 [ C(RESULT_MISS
) ] = -1,
1393 [ C(OP_PREFETCH
) ] = {
1394 [ C(RESULT_ACCESS
) ] = -1,
1395 [ C(RESULT_MISS
) ] = -1,
1400 EVENT_ATTR_STR(topdown
-total
-slots
, td_total_slots_slm
, "event=0x3c");
1401 EVENT_ATTR_STR(topdown
-total
-slots
.scale
, td_total_slots_scale_slm
, "2");
1402 /* no_alloc_cycles.not_delivered */
1403 EVENT_ATTR_STR(topdown
-fetch
-bubbles
, td_fetch_bubbles_slm
,
1404 "event=0xca,umask=0x50");
1405 EVENT_ATTR_STR(topdown
-fetch
-bubbles
.scale
, td_fetch_bubbles_scale_slm
, "2");
1406 /* uops_retired.all */
1407 EVENT_ATTR_STR(topdown
-slots
-issued
, td_slots_issued_slm
,
1408 "event=0xc2,umask=0x10");
1409 /* uops_retired.all */
1410 EVENT_ATTR_STR(topdown
-slots
-retired
, td_slots_retired_slm
,
1411 "event=0xc2,umask=0x10");
1413 static struct attribute
*slm_events_attrs
[] = {
1414 EVENT_PTR(td_total_slots_slm
),
1415 EVENT_PTR(td_total_slots_scale_slm
),
1416 EVENT_PTR(td_fetch_bubbles_slm
),
1417 EVENT_PTR(td_fetch_bubbles_scale_slm
),
1418 EVENT_PTR(td_slots_issued_slm
),
1419 EVENT_PTR(td_slots_retired_slm
),
1423 static struct extra_reg intel_slm_extra_regs
[] __read_mostly
=
1425 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1426 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0x768005ffffull
, RSP_0
),
1427 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1
, 0x368005ffffull
, RSP_1
),
1431 #define SLM_DMND_READ SNB_DMND_DATA_RD
1432 #define SLM_DMND_WRITE SNB_DMND_RFO
1433 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1435 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1436 #define SLM_LLC_ACCESS SNB_RESP_ANY
1437 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1439 static __initconst
const u64 slm_hw_cache_extra_regs
1440 [PERF_COUNT_HW_CACHE_MAX
]
1441 [PERF_COUNT_HW_CACHE_OP_MAX
]
1442 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
1446 [ C(RESULT_ACCESS
) ] = SLM_DMND_READ
|SLM_LLC_ACCESS
,
1447 [ C(RESULT_MISS
) ] = 0,
1450 [ C(RESULT_ACCESS
) ] = SLM_DMND_WRITE
|SLM_LLC_ACCESS
,
1451 [ C(RESULT_MISS
) ] = SLM_DMND_WRITE
|SLM_LLC_MISS
,
1453 [ C(OP_PREFETCH
) ] = {
1454 [ C(RESULT_ACCESS
) ] = SLM_DMND_PREFETCH
|SLM_LLC_ACCESS
,
1455 [ C(RESULT_MISS
) ] = SLM_DMND_PREFETCH
|SLM_LLC_MISS
,
1460 static __initconst
const u64 slm_hw_cache_event_ids
1461 [PERF_COUNT_HW_CACHE_MAX
]
1462 [PERF_COUNT_HW_CACHE_OP_MAX
]
1463 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
1467 [ C(RESULT_ACCESS
) ] = 0,
1468 [ C(RESULT_MISS
) ] = 0x0104, /* LD_DCU_MISS */
1471 [ C(RESULT_ACCESS
) ] = 0,
1472 [ C(RESULT_MISS
) ] = 0,
1474 [ C(OP_PREFETCH
) ] = {
1475 [ C(RESULT_ACCESS
) ] = 0,
1476 [ C(RESULT_MISS
) ] = 0,
1481 [ C(RESULT_ACCESS
) ] = 0x0380, /* ICACHE.ACCESSES */
1482 [ C(RESULT_MISS
) ] = 0x0280, /* ICACGE.MISSES */
1485 [ C(RESULT_ACCESS
) ] = -1,
1486 [ C(RESULT_MISS
) ] = -1,
1488 [ C(OP_PREFETCH
) ] = {
1489 [ C(RESULT_ACCESS
) ] = 0,
1490 [ C(RESULT_MISS
) ] = 0,
1495 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1496 [ C(RESULT_ACCESS
) ] = 0x01b7,
1497 [ C(RESULT_MISS
) ] = 0,
1500 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1501 [ C(RESULT_ACCESS
) ] = 0x01b7,
1502 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1503 [ C(RESULT_MISS
) ] = 0x01b7,
1505 [ C(OP_PREFETCH
) ] = {
1506 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1507 [ C(RESULT_ACCESS
) ] = 0x01b7,
1508 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1509 [ C(RESULT_MISS
) ] = 0x01b7,
1514 [ C(RESULT_ACCESS
) ] = 0,
1515 [ C(RESULT_MISS
) ] = 0x0804, /* LD_DTLB_MISS */
1518 [ C(RESULT_ACCESS
) ] = 0,
1519 [ C(RESULT_MISS
) ] = 0,
1521 [ C(OP_PREFETCH
) ] = {
1522 [ C(RESULT_ACCESS
) ] = 0,
1523 [ C(RESULT_MISS
) ] = 0,
1528 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1529 [ C(RESULT_MISS
) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1532 [ C(RESULT_ACCESS
) ] = -1,
1533 [ C(RESULT_MISS
) ] = -1,
1535 [ C(OP_PREFETCH
) ] = {
1536 [ C(RESULT_ACCESS
) ] = -1,
1537 [ C(RESULT_MISS
) ] = -1,
1542 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1543 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1546 [ C(RESULT_ACCESS
) ] = -1,
1547 [ C(RESULT_MISS
) ] = -1,
1549 [ C(OP_PREFETCH
) ] = {
1550 [ C(RESULT_ACCESS
) ] = -1,
1551 [ C(RESULT_MISS
) ] = -1,
1556 EVENT_ATTR_STR(topdown
-total
-slots
, td_total_slots_glm
, "event=0x3c");
1557 EVENT_ATTR_STR(topdown
-total
-slots
.scale
, td_total_slots_scale_glm
, "3");
1558 /* UOPS_NOT_DELIVERED.ANY */
1559 EVENT_ATTR_STR(topdown
-fetch
-bubbles
, td_fetch_bubbles_glm
, "event=0x9c");
1560 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1561 EVENT_ATTR_STR(topdown
-recovery
-bubbles
, td_recovery_bubbles_glm
, "event=0xca,umask=0x02");
1562 /* UOPS_RETIRED.ANY */
1563 EVENT_ATTR_STR(topdown
-slots
-retired
, td_slots_retired_glm
, "event=0xc2");
1564 /* UOPS_ISSUED.ANY */
1565 EVENT_ATTR_STR(topdown
-slots
-issued
, td_slots_issued_glm
, "event=0x0e");
1567 static struct attribute
*glm_events_attrs
[] = {
1568 EVENT_PTR(td_total_slots_glm
),
1569 EVENT_PTR(td_total_slots_scale_glm
),
1570 EVENT_PTR(td_fetch_bubbles_glm
),
1571 EVENT_PTR(td_recovery_bubbles_glm
),
1572 EVENT_PTR(td_slots_issued_glm
),
1573 EVENT_PTR(td_slots_retired_glm
),
1577 static struct extra_reg intel_glm_extra_regs
[] __read_mostly
= {
1578 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1579 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0x760005ffbfull
, RSP_0
),
1580 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1
, 0x360005ffbfull
, RSP_1
),
1584 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1585 #define GLM_DEMAND_RFO BIT_ULL(1)
1586 #define GLM_ANY_RESPONSE BIT_ULL(16)
1587 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1588 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1589 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1590 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1591 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1592 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1593 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1595 static __initconst
const u64 glm_hw_cache_event_ids
1596 [PERF_COUNT_HW_CACHE_MAX
]
1597 [PERF_COUNT_HW_CACHE_OP_MAX
]
1598 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
1601 [C(RESULT_ACCESS
)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1602 [C(RESULT_MISS
)] = 0x0,
1605 [C(RESULT_ACCESS
)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1606 [C(RESULT_MISS
)] = 0x0,
1608 [C(OP_PREFETCH
)] = {
1609 [C(RESULT_ACCESS
)] = 0x0,
1610 [C(RESULT_MISS
)] = 0x0,
1615 [C(RESULT_ACCESS
)] = 0x0380, /* ICACHE.ACCESSES */
1616 [C(RESULT_MISS
)] = 0x0280, /* ICACHE.MISSES */
1619 [C(RESULT_ACCESS
)] = -1,
1620 [C(RESULT_MISS
)] = -1,
1622 [C(OP_PREFETCH
)] = {
1623 [C(RESULT_ACCESS
)] = 0x0,
1624 [C(RESULT_MISS
)] = 0x0,
1629 [C(RESULT_ACCESS
)] = 0x1b7, /* OFFCORE_RESPONSE */
1630 [C(RESULT_MISS
)] = 0x1b7, /* OFFCORE_RESPONSE */
1633 [C(RESULT_ACCESS
)] = 0x1b7, /* OFFCORE_RESPONSE */
1634 [C(RESULT_MISS
)] = 0x1b7, /* OFFCORE_RESPONSE */
1636 [C(OP_PREFETCH
)] = {
1637 [C(RESULT_ACCESS
)] = 0x1b7, /* OFFCORE_RESPONSE */
1638 [C(RESULT_MISS
)] = 0x1b7, /* OFFCORE_RESPONSE */
1643 [C(RESULT_ACCESS
)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1644 [C(RESULT_MISS
)] = 0x0,
1647 [C(RESULT_ACCESS
)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1648 [C(RESULT_MISS
)] = 0x0,
1650 [C(OP_PREFETCH
)] = {
1651 [C(RESULT_ACCESS
)] = 0x0,
1652 [C(RESULT_MISS
)] = 0x0,
1657 [C(RESULT_ACCESS
)] = 0x00c0, /* INST_RETIRED.ANY_P */
1658 [C(RESULT_MISS
)] = 0x0481, /* ITLB.MISS */
1661 [C(RESULT_ACCESS
)] = -1,
1662 [C(RESULT_MISS
)] = -1,
1664 [C(OP_PREFETCH
)] = {
1665 [C(RESULT_ACCESS
)] = -1,
1666 [C(RESULT_MISS
)] = -1,
1671 [C(RESULT_ACCESS
)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1672 [C(RESULT_MISS
)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1675 [C(RESULT_ACCESS
)] = -1,
1676 [C(RESULT_MISS
)] = -1,
1678 [C(OP_PREFETCH
)] = {
1679 [C(RESULT_ACCESS
)] = -1,
1680 [C(RESULT_MISS
)] = -1,
1685 static __initconst
const u64 glm_hw_cache_extra_regs
1686 [PERF_COUNT_HW_CACHE_MAX
]
1687 [PERF_COUNT_HW_CACHE_OP_MAX
]
1688 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
1691 [C(RESULT_ACCESS
)] = GLM_DEMAND_READ
|
1693 [C(RESULT_MISS
)] = GLM_DEMAND_READ
|
1697 [C(RESULT_ACCESS
)] = GLM_DEMAND_WRITE
|
1699 [C(RESULT_MISS
)] = GLM_DEMAND_WRITE
|
1702 [C(OP_PREFETCH
)] = {
1703 [C(RESULT_ACCESS
)] = GLM_DEMAND_PREFETCH
|
1705 [C(RESULT_MISS
)] = GLM_DEMAND_PREFETCH
|
1711 static __initconst
const u64 glp_hw_cache_event_ids
1712 [PERF_COUNT_HW_CACHE_MAX
]
1713 [PERF_COUNT_HW_CACHE_OP_MAX
]
1714 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
1717 [C(RESULT_ACCESS
)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1718 [C(RESULT_MISS
)] = 0x0,
1721 [C(RESULT_ACCESS
)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1722 [C(RESULT_MISS
)] = 0x0,
1724 [C(OP_PREFETCH
)] = {
1725 [C(RESULT_ACCESS
)] = 0x0,
1726 [C(RESULT_MISS
)] = 0x0,
1731 [C(RESULT_ACCESS
)] = 0x0380, /* ICACHE.ACCESSES */
1732 [C(RESULT_MISS
)] = 0x0280, /* ICACHE.MISSES */
1735 [C(RESULT_ACCESS
)] = -1,
1736 [C(RESULT_MISS
)] = -1,
1738 [C(OP_PREFETCH
)] = {
1739 [C(RESULT_ACCESS
)] = 0x0,
1740 [C(RESULT_MISS
)] = 0x0,
1745 [C(RESULT_ACCESS
)] = 0x1b7, /* OFFCORE_RESPONSE */
1746 [C(RESULT_MISS
)] = 0x1b7, /* OFFCORE_RESPONSE */
1749 [C(RESULT_ACCESS
)] = 0x1b7, /* OFFCORE_RESPONSE */
1750 [C(RESULT_MISS
)] = 0x1b7, /* OFFCORE_RESPONSE */
1752 [C(OP_PREFETCH
)] = {
1753 [C(RESULT_ACCESS
)] = 0x0,
1754 [C(RESULT_MISS
)] = 0x0,
1759 [C(RESULT_ACCESS
)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1760 [C(RESULT_MISS
)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1763 [C(RESULT_ACCESS
)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1764 [C(RESULT_MISS
)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1766 [C(OP_PREFETCH
)] = {
1767 [C(RESULT_ACCESS
)] = 0x0,
1768 [C(RESULT_MISS
)] = 0x0,
1773 [C(RESULT_ACCESS
)] = 0x00c0, /* INST_RETIRED.ANY_P */
1774 [C(RESULT_MISS
)] = 0x0481, /* ITLB.MISS */
1777 [C(RESULT_ACCESS
)] = -1,
1778 [C(RESULT_MISS
)] = -1,
1780 [C(OP_PREFETCH
)] = {
1781 [C(RESULT_ACCESS
)] = -1,
1782 [C(RESULT_MISS
)] = -1,
1787 [C(RESULT_ACCESS
)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1788 [C(RESULT_MISS
)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1791 [C(RESULT_ACCESS
)] = -1,
1792 [C(RESULT_MISS
)] = -1,
1794 [C(OP_PREFETCH
)] = {
1795 [C(RESULT_ACCESS
)] = -1,
1796 [C(RESULT_MISS
)] = -1,
1801 static __initconst
const u64 glp_hw_cache_extra_regs
1802 [PERF_COUNT_HW_CACHE_MAX
]
1803 [PERF_COUNT_HW_CACHE_OP_MAX
]
1804 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
1807 [C(RESULT_ACCESS
)] = GLM_DEMAND_READ
|
1809 [C(RESULT_MISS
)] = GLM_DEMAND_READ
|
1813 [C(RESULT_ACCESS
)] = GLM_DEMAND_WRITE
|
1815 [C(RESULT_MISS
)] = GLM_DEMAND_WRITE
|
1818 [C(OP_PREFETCH
)] = {
1819 [C(RESULT_ACCESS
)] = 0x0,
1820 [C(RESULT_MISS
)] = 0x0,
1825 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1826 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1827 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
1828 #define KNL_MCDRAM_FAR BIT_ULL(22)
1829 #define KNL_DDR_LOCAL BIT_ULL(23)
1830 #define KNL_DDR_FAR BIT_ULL(24)
1831 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1832 KNL_DDR_LOCAL | KNL_DDR_FAR)
1833 #define KNL_L2_READ SLM_DMND_READ
1834 #define KNL_L2_WRITE SLM_DMND_WRITE
1835 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1836 #define KNL_L2_ACCESS SLM_LLC_ACCESS
1837 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1838 KNL_DRAM_ANY | SNB_SNP_ANY | \
1841 static __initconst
const u64 knl_hw_cache_extra_regs
1842 [PERF_COUNT_HW_CACHE_MAX
]
1843 [PERF_COUNT_HW_CACHE_OP_MAX
]
1844 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
1847 [C(RESULT_ACCESS
)] = KNL_L2_READ
| KNL_L2_ACCESS
,
1848 [C(RESULT_MISS
)] = 0,
1851 [C(RESULT_ACCESS
)] = KNL_L2_WRITE
| KNL_L2_ACCESS
,
1852 [C(RESULT_MISS
)] = KNL_L2_WRITE
| KNL_L2_MISS
,
1854 [C(OP_PREFETCH
)] = {
1855 [C(RESULT_ACCESS
)] = KNL_L2_PREFETCH
| KNL_L2_ACCESS
,
1856 [C(RESULT_MISS
)] = KNL_L2_PREFETCH
| KNL_L2_MISS
,
1862 * Used from PMIs where the LBRs are already disabled.
1864 * This function could be called consecutively. It is required to remain in
1865 * disabled state if called consecutively.
1867 * During consecutive calls, the same disable value will be written to related
1868 * registers, so the PMU state remains unchanged.
1870 * intel_bts events don't coexist with intel PMU's BTS events because of
1871 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
1872 * disabled around intel PMU's event batching etc, only inside the PMI handler.
1874 static void __intel_pmu_disable_all(void)
1876 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1878 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
1880 if (test_bit(INTEL_PMC_IDX_FIXED_BTS
, cpuc
->active_mask
))
1881 intel_pmu_disable_bts();
1883 intel_pmu_pebs_disable_all();
1886 static void intel_pmu_disable_all(void)
1888 __intel_pmu_disable_all();
1889 intel_pmu_lbr_disable_all();
1892 static void __intel_pmu_enable_all(int added
, bool pmi
)
1894 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1896 intel_pmu_pebs_enable_all();
1897 intel_pmu_lbr_enable_all(pmi
);
1898 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
,
1899 x86_pmu
.intel_ctrl
& ~cpuc
->intel_ctrl_guest_mask
);
1901 if (test_bit(INTEL_PMC_IDX_FIXED_BTS
, cpuc
->active_mask
)) {
1902 struct perf_event
*event
=
1903 cpuc
->events
[INTEL_PMC_IDX_FIXED_BTS
];
1905 if (WARN_ON_ONCE(!event
))
1908 intel_pmu_enable_bts(event
->hw
.config
);
1912 static void intel_pmu_enable_all(int added
)
1914 __intel_pmu_enable_all(added
, false);
1919 * Intel Errata AAK100 (model 26)
1920 * Intel Errata AAP53 (model 30)
1921 * Intel Errata BD53 (model 44)
1923 * The official story:
1924 * These chips need to be 'reset' when adding counters by programming the
1925 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1926 * in sequence on the same PMC or on different PMCs.
1928 * In practise it appears some of these events do in fact count, and
1929 * we need to programm all 4 events.
1931 static void intel_pmu_nhm_workaround(void)
1933 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1934 static const unsigned long nhm_magic
[4] = {
1940 struct perf_event
*event
;
1944 * The Errata requires below steps:
1945 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1946 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1947 * the corresponding PMCx;
1948 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1949 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1950 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1954 * The real steps we choose are a little different from above.
1955 * A) To reduce MSR operations, we don't run step 1) as they
1956 * are already cleared before this function is called;
1957 * B) Call x86_perf_event_update to save PMCx before configuring
1958 * PERFEVTSELx with magic number;
1959 * C) With step 5), we do clear only when the PERFEVTSELx is
1960 * not used currently.
1961 * D) Call x86_perf_event_set_period to restore PMCx;
1964 /* We always operate 4 pairs of PERF Counters */
1965 for (i
= 0; i
< 4; i
++) {
1966 event
= cpuc
->events
[i
];
1968 x86_perf_event_update(event
);
1971 for (i
= 0; i
< 4; i
++) {
1972 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ i
, nhm_magic
[i
]);
1973 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0
+ i
, 0x0);
1976 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0xf);
1977 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0x0);
1979 for (i
= 0; i
< 4; i
++) {
1980 event
= cpuc
->events
[i
];
1983 x86_perf_event_set_period(event
);
1984 __x86_pmu_enable_event(&event
->hw
,
1985 ARCH_PERFMON_EVENTSEL_ENABLE
);
1987 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ i
, 0x0);
1991 static void intel_pmu_nhm_enable_all(int added
)
1994 intel_pmu_nhm_workaround();
1995 intel_pmu_enable_all(added
);
1998 static void intel_set_tfa(struct cpu_hw_events
*cpuc
, bool on
)
2000 u64 val
= on
? MSR_TFA_RTM_FORCE_ABORT
: 0;
2002 if (cpuc
->tfa_shadow
!= val
) {
2003 cpuc
->tfa_shadow
= val
;
2004 wrmsrl(MSR_TSX_FORCE_ABORT
, val
);
2008 static void intel_tfa_commit_scheduling(struct cpu_hw_events
*cpuc
, int idx
, int cntr
)
2011 * We're going to use PMC3, make sure TFA is set before we touch it.
2013 if (cntr
== 3 && !cpuc
->is_fake
)
2014 intel_set_tfa(cpuc
, true);
2017 static void intel_tfa_pmu_enable_all(int added
)
2019 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
2022 * If we find PMC3 is no longer used when we enable the PMU, we can
2025 if (!test_bit(3, cpuc
->active_mask
))
2026 intel_set_tfa(cpuc
, false);
2028 intel_pmu_enable_all(added
);
2031 static inline u64
intel_pmu_get_status(void)
2035 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
2040 static inline void intel_pmu_ack_status(u64 ack
)
2042 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
2045 static void intel_pmu_disable_fixed(struct hw_perf_event
*hwc
)
2047 int idx
= hwc
->idx
- INTEL_PMC_IDX_FIXED
;
2050 mask
= 0xfULL
<< (idx
* 4);
2052 rdmsrl(hwc
->config_base
, ctrl_val
);
2054 wrmsrl(hwc
->config_base
, ctrl_val
);
2057 static inline bool event_is_checkpointed(struct perf_event
*event
)
2059 return (event
->hw
.config
& HSW_IN_TX_CHECKPOINTED
) != 0;
2062 static void intel_pmu_disable_event(struct perf_event
*event
)
2064 struct hw_perf_event
*hwc
= &event
->hw
;
2065 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
2067 if (unlikely(hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
)) {
2068 intel_pmu_disable_bts();
2069 intel_pmu_drain_bts_buffer();
2073 cpuc
->intel_ctrl_guest_mask
&= ~(1ull << hwc
->idx
);
2074 cpuc
->intel_ctrl_host_mask
&= ~(1ull << hwc
->idx
);
2075 cpuc
->intel_cp_status
&= ~(1ull << hwc
->idx
);
2077 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
2078 intel_pmu_disable_fixed(hwc
);
2080 x86_pmu_disable_event(event
);
2082 if (unlikely(event
->attr
.precise_ip
))
2083 intel_pmu_pebs_disable(event
);
2086 static void intel_pmu_del_event(struct perf_event
*event
)
2088 if (needs_branch_stack(event
))
2089 intel_pmu_lbr_del(event
);
2090 if (event
->attr
.precise_ip
)
2091 intel_pmu_pebs_del(event
);
2094 static void intel_pmu_enable_fixed(struct hw_perf_event
*hwc
)
2096 int idx
= hwc
->idx
- INTEL_PMC_IDX_FIXED
;
2097 u64 ctrl_val
, bits
, mask
;
2100 * Enable IRQ generation (0x8),
2101 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2105 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_USR
)
2107 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
2111 * ANY bit is supported in v3 and up
2113 if (x86_pmu
.version
> 2 && hwc
->config
& ARCH_PERFMON_EVENTSEL_ANY
)
2117 mask
= 0xfULL
<< (idx
* 4);
2119 rdmsrl(hwc
->config_base
, ctrl_val
);
2122 wrmsrl(hwc
->config_base
, ctrl_val
);
2125 static void intel_pmu_enable_event(struct perf_event
*event
)
2127 struct hw_perf_event
*hwc
= &event
->hw
;
2128 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
2130 if (unlikely(hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
)) {
2131 if (!__this_cpu_read(cpu_hw_events
.enabled
))
2134 intel_pmu_enable_bts(hwc
->config
);
2138 if (event
->attr
.exclude_host
)
2139 cpuc
->intel_ctrl_guest_mask
|= (1ull << hwc
->idx
);
2140 if (event
->attr
.exclude_guest
)
2141 cpuc
->intel_ctrl_host_mask
|= (1ull << hwc
->idx
);
2143 if (unlikely(event_is_checkpointed(event
)))
2144 cpuc
->intel_cp_status
|= (1ull << hwc
->idx
);
2146 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
2147 intel_pmu_enable_fixed(hwc
);
2151 if (unlikely(event
->attr
.precise_ip
))
2152 intel_pmu_pebs_enable(event
);
2154 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
2157 static void intel_pmu_add_event(struct perf_event
*event
)
2159 if (event
->attr
.precise_ip
)
2160 intel_pmu_pebs_add(event
);
2161 if (needs_branch_stack(event
))
2162 intel_pmu_lbr_add(event
);
2166 * Save and restart an expired event. Called by NMI contexts,
2167 * so it has to be careful about preempting normal event ops:
2169 int intel_pmu_save_and_restart(struct perf_event
*event
)
2171 x86_perf_event_update(event
);
2173 * For a checkpointed counter always reset back to 0. This
2174 * avoids a situation where the counter overflows, aborts the
2175 * transaction and is then set back to shortly before the
2176 * overflow, and overflows and aborts again.
2178 if (unlikely(event_is_checkpointed(event
))) {
2179 /* No race with NMIs because the counter should not be armed */
2180 wrmsrl(event
->hw
.event_base
, 0);
2181 local64_set(&event
->hw
.prev_count
, 0);
2183 return x86_perf_event_set_period(event
);
2186 static void intel_pmu_reset(void)
2188 struct debug_store
*ds
= __this_cpu_read(cpu_hw_events
.ds
);
2189 unsigned long flags
;
2192 if (!x86_pmu
.num_counters
)
2195 local_irq_save(flags
);
2197 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2199 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
2200 wrmsrl_safe(x86_pmu_config_addr(idx
), 0ull);
2201 wrmsrl_safe(x86_pmu_event_addr(idx
), 0ull);
2203 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++)
2204 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, 0ull);
2207 ds
->bts_index
= ds
->bts_buffer_base
;
2209 /* Ack all overflows and disable fixed counters */
2210 if (x86_pmu
.version
>= 2) {
2211 intel_pmu_ack_status(intel_pmu_get_status());
2212 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
2215 /* Reset LBRs and LBR freezing */
2216 if (x86_pmu
.lbr_nr
) {
2217 update_debugctlmsr(get_debugctlmsr() &
2218 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI
|DEBUGCTLMSR_LBR
));
2221 local_irq_restore(flags
);
2225 * This handler is triggered by the local APIC, so the APIC IRQ handling
2228 static int intel_pmu_handle_irq(struct pt_regs
*regs
)
2230 struct perf_sample_data data
;
2231 struct cpu_hw_events
*cpuc
;
2237 cpuc
= this_cpu_ptr(&cpu_hw_events
);
2240 * Save the PMU state.
2241 * It needs to be restored when leaving the handler.
2243 pmu_enabled
= cpuc
->enabled
;
2245 * No known reason to not always do late ACK,
2246 * but just in case do it opt-in.
2248 if (!x86_pmu
.late_ack
)
2249 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
2250 intel_bts_disable_local();
2252 __intel_pmu_disable_all();
2253 handled
= intel_pmu_drain_bts_buffer();
2254 handled
+= intel_bts_interrupt();
2255 status
= intel_pmu_get_status();
2261 intel_pmu_lbr_read();
2262 intel_pmu_ack_status(status
);
2263 if (++loops
> 100) {
2264 static bool warned
= false;
2266 WARN(1, "perfevents: irq loop stuck!\n");
2267 perf_event_print_debug();
2274 inc_irq_stat(apic_perf_irqs
);
2278 * Ignore a range of extra bits in status that do not indicate
2279 * overflow by themselves.
2281 status
&= ~(GLOBAL_STATUS_COND_CHG
|
2282 GLOBAL_STATUS_ASIF
|
2283 GLOBAL_STATUS_LBRS_FROZEN
);
2287 * In case multiple PEBS events are sampled at the same time,
2288 * it is possible to have GLOBAL_STATUS bit 62 set indicating
2289 * PEBS buffer overflow and also seeing at most 3 PEBS counters
2290 * having their bits set in the status register. This is a sign
2291 * that there was at least one PEBS record pending at the time
2292 * of the PMU interrupt. PEBS counters must only be processed
2293 * via the drain_pebs() calls and not via the regular sample
2294 * processing loop coming after that the function, otherwise
2295 * phony regular samples may be generated in the sampling buffer
2296 * not marked with the EXACT tag. Another possibility is to have
2297 * one PEBS event and at least one non-PEBS event whic hoverflows
2298 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2299 * not be set, yet the overflow status bit for the PEBS counter will
2302 * To avoid this problem, we systematically ignore the PEBS-enabled
2303 * counters from the GLOBAL_STATUS mask and we always process PEBS
2304 * events via drain_pebs().
2306 status
&= ~(cpuc
->pebs_enabled
& PEBS_COUNTER_MASK
);
2309 * PEBS overflow sets bit 62 in the global status register
2311 if (__test_and_clear_bit(62, (unsigned long *)&status
)) {
2313 x86_pmu
.drain_pebs(regs
);
2314 status
&= x86_pmu
.intel_ctrl
| GLOBAL_STATUS_TRACE_TOPAPMI
;
2320 if (__test_and_clear_bit(55, (unsigned long *)&status
)) {
2322 intel_pt_interrupt();
2326 * Checkpointed counters can lead to 'spurious' PMIs because the
2327 * rollback caused by the PMI will have cleared the overflow status
2328 * bit. Therefore always force probe these counters.
2330 status
|= cpuc
->intel_cp_status
;
2332 for_each_set_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
2333 struct perf_event
*event
= cpuc
->events
[bit
];
2337 if (!test_bit(bit
, cpuc
->active_mask
))
2340 if (!intel_pmu_save_and_restart(event
))
2343 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
2345 if (has_branch_stack(event
))
2346 data
.br_stack
= &cpuc
->lbr_stack
;
2348 if (perf_event_overflow(event
, &data
, regs
))
2349 x86_pmu_stop(event
, 0);
2353 * Repeat if there is more work to be done:
2355 status
= intel_pmu_get_status();
2360 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2361 cpuc
->enabled
= pmu_enabled
;
2363 __intel_pmu_enable_all(0, true);
2364 intel_bts_enable_local();
2367 * Only unmask the NMI after the overflow counters
2368 * have been reset. This avoids spurious NMIs on
2371 if (x86_pmu
.late_ack
)
2372 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
2376 static struct event_constraint
*
2377 intel_bts_constraints(struct perf_event
*event
)
2379 if (unlikely(intel_pmu_has_bts(event
)))
2380 return &bts_constraint
;
2385 static int intel_alt_er(int idx
, u64 config
)
2389 if (!(x86_pmu
.flags
& PMU_FL_HAS_RSP_1
))
2392 if (idx
== EXTRA_REG_RSP_0
)
2393 alt_idx
= EXTRA_REG_RSP_1
;
2395 if (idx
== EXTRA_REG_RSP_1
)
2396 alt_idx
= EXTRA_REG_RSP_0
;
2398 if (config
& ~x86_pmu
.extra_regs
[alt_idx
].valid_mask
)
2404 static void intel_fixup_er(struct perf_event
*event
, int idx
)
2406 event
->hw
.extra_reg
.idx
= idx
;
2408 if (idx
== EXTRA_REG_RSP_0
) {
2409 event
->hw
.config
&= ~INTEL_ARCH_EVENT_MASK
;
2410 event
->hw
.config
|= x86_pmu
.extra_regs
[EXTRA_REG_RSP_0
].event
;
2411 event
->hw
.extra_reg
.reg
= MSR_OFFCORE_RSP_0
;
2412 } else if (idx
== EXTRA_REG_RSP_1
) {
2413 event
->hw
.config
&= ~INTEL_ARCH_EVENT_MASK
;
2414 event
->hw
.config
|= x86_pmu
.extra_regs
[EXTRA_REG_RSP_1
].event
;
2415 event
->hw
.extra_reg
.reg
= MSR_OFFCORE_RSP_1
;
2420 * manage allocation of shared extra msr for certain events
2423 * per-cpu: to be shared between the various events on a single PMU
2424 * per-core: per-cpu + shared by HT threads
2426 static struct event_constraint
*
2427 __intel_shared_reg_get_constraints(struct cpu_hw_events
*cpuc
,
2428 struct perf_event
*event
,
2429 struct hw_perf_event_extra
*reg
)
2431 struct event_constraint
*c
= &emptyconstraint
;
2432 struct er_account
*era
;
2433 unsigned long flags
;
2437 * reg->alloc can be set due to existing state, so for fake cpuc we
2438 * need to ignore this, otherwise we might fail to allocate proper fake
2439 * state for this extra reg constraint. Also see the comment below.
2441 if (reg
->alloc
&& !cpuc
->is_fake
)
2442 return NULL
; /* call x86_get_event_constraint() */
2445 era
= &cpuc
->shared_regs
->regs
[idx
];
2447 * we use spin_lock_irqsave() to avoid lockdep issues when
2448 * passing a fake cpuc
2450 raw_spin_lock_irqsave(&era
->lock
, flags
);
2452 if (!atomic_read(&era
->ref
) || era
->config
== reg
->config
) {
2455 * If its a fake cpuc -- as per validate_{group,event}() we
2456 * shouldn't touch event state and we can avoid doing so
2457 * since both will only call get_event_constraints() once
2458 * on each event, this avoids the need for reg->alloc.
2460 * Not doing the ER fixup will only result in era->reg being
2461 * wrong, but since we won't actually try and program hardware
2462 * this isn't a problem either.
2464 if (!cpuc
->is_fake
) {
2465 if (idx
!= reg
->idx
)
2466 intel_fixup_er(event
, idx
);
2469 * x86_schedule_events() can call get_event_constraints()
2470 * multiple times on events in the case of incremental
2471 * scheduling(). reg->alloc ensures we only do the ER
2477 /* lock in msr value */
2478 era
->config
= reg
->config
;
2479 era
->reg
= reg
->reg
;
2482 atomic_inc(&era
->ref
);
2485 * need to call x86_get_event_constraint()
2486 * to check if associated event has constraints
2490 idx
= intel_alt_er(idx
, reg
->config
);
2491 if (idx
!= reg
->idx
) {
2492 raw_spin_unlock_irqrestore(&era
->lock
, flags
);
2496 raw_spin_unlock_irqrestore(&era
->lock
, flags
);
2502 __intel_shared_reg_put_constraints(struct cpu_hw_events
*cpuc
,
2503 struct hw_perf_event_extra
*reg
)
2505 struct er_account
*era
;
2508 * Only put constraint if extra reg was actually allocated. Also takes
2509 * care of event which do not use an extra shared reg.
2511 * Also, if this is a fake cpuc we shouldn't touch any event state
2512 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2513 * either since it'll be thrown out.
2515 if (!reg
->alloc
|| cpuc
->is_fake
)
2518 era
= &cpuc
->shared_regs
->regs
[reg
->idx
];
2520 /* one fewer user */
2521 atomic_dec(&era
->ref
);
2523 /* allocate again next time */
2527 static struct event_constraint
*
2528 intel_shared_regs_constraints(struct cpu_hw_events
*cpuc
,
2529 struct perf_event
*event
)
2531 struct event_constraint
*c
= NULL
, *d
;
2532 struct hw_perf_event_extra
*xreg
, *breg
;
2534 xreg
= &event
->hw
.extra_reg
;
2535 if (xreg
->idx
!= EXTRA_REG_NONE
) {
2536 c
= __intel_shared_reg_get_constraints(cpuc
, event
, xreg
);
2537 if (c
== &emptyconstraint
)
2540 breg
= &event
->hw
.branch_reg
;
2541 if (breg
->idx
!= EXTRA_REG_NONE
) {
2542 d
= __intel_shared_reg_get_constraints(cpuc
, event
, breg
);
2543 if (d
== &emptyconstraint
) {
2544 __intel_shared_reg_put_constraints(cpuc
, xreg
);
2551 struct event_constraint
*
2552 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, int idx
,
2553 struct perf_event
*event
)
2555 struct event_constraint
*c
;
2557 if (x86_pmu
.event_constraints
) {
2558 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
2559 if ((event
->hw
.config
& c
->cmask
) == c
->code
) {
2560 event
->hw
.flags
|= c
->flags
;
2566 return &unconstrained
;
2569 static struct event_constraint
*
2570 __intel_get_event_constraints(struct cpu_hw_events
*cpuc
, int idx
,
2571 struct perf_event
*event
)
2573 struct event_constraint
*c
;
2575 c
= intel_bts_constraints(event
);
2579 c
= intel_shared_regs_constraints(cpuc
, event
);
2583 c
= intel_pebs_constraints(event
);
2587 return x86_get_event_constraints(cpuc
, idx
, event
);
2591 intel_start_scheduling(struct cpu_hw_events
*cpuc
)
2593 struct intel_excl_cntrs
*excl_cntrs
= cpuc
->excl_cntrs
;
2594 struct intel_excl_states
*xl
;
2595 int tid
= cpuc
->excl_thread_id
;
2598 * nothing needed if in group validation mode
2600 if (cpuc
->is_fake
|| !is_ht_workaround_enabled())
2604 * no exclusion needed
2606 if (WARN_ON_ONCE(!excl_cntrs
))
2609 xl
= &excl_cntrs
->states
[tid
];
2611 xl
->sched_started
= true;
2613 * lock shared state until we are done scheduling
2614 * in stop_event_scheduling()
2615 * makes scheduling appear as a transaction
2617 raw_spin_lock(&excl_cntrs
->lock
);
2620 static void intel_commit_scheduling(struct cpu_hw_events
*cpuc
, int idx
, int cntr
)
2622 struct intel_excl_cntrs
*excl_cntrs
= cpuc
->excl_cntrs
;
2623 struct event_constraint
*c
= cpuc
->event_constraint
[idx
];
2624 struct intel_excl_states
*xl
;
2625 int tid
= cpuc
->excl_thread_id
;
2627 if (cpuc
->is_fake
|| !is_ht_workaround_enabled())
2630 if (WARN_ON_ONCE(!excl_cntrs
))
2633 if (!(c
->flags
& PERF_X86_EVENT_DYNAMIC
))
2636 xl
= &excl_cntrs
->states
[tid
];
2638 lockdep_assert_held(&excl_cntrs
->lock
);
2640 if (c
->flags
& PERF_X86_EVENT_EXCL
)
2641 xl
->state
[cntr
] = INTEL_EXCL_EXCLUSIVE
;
2643 xl
->state
[cntr
] = INTEL_EXCL_SHARED
;
2647 intel_stop_scheduling(struct cpu_hw_events
*cpuc
)
2649 struct intel_excl_cntrs
*excl_cntrs
= cpuc
->excl_cntrs
;
2650 struct intel_excl_states
*xl
;
2651 int tid
= cpuc
->excl_thread_id
;
2654 * nothing needed if in group validation mode
2656 if (cpuc
->is_fake
|| !is_ht_workaround_enabled())
2659 * no exclusion needed
2661 if (WARN_ON_ONCE(!excl_cntrs
))
2664 xl
= &excl_cntrs
->states
[tid
];
2666 xl
->sched_started
= false;
2668 * release shared state lock (acquired in intel_start_scheduling())
2670 raw_spin_unlock(&excl_cntrs
->lock
);
2673 static struct event_constraint
*
2674 dyn_constraint(struct cpu_hw_events
*cpuc
, struct event_constraint
*c
, int idx
)
2676 WARN_ON_ONCE(!cpuc
->constraint_list
);
2678 if (!(c
->flags
& PERF_X86_EVENT_DYNAMIC
)) {
2679 struct event_constraint
*cx
;
2682 * grab pre-allocated constraint entry
2684 cx
= &cpuc
->constraint_list
[idx
];
2687 * initialize dynamic constraint
2688 * with static constraint
2693 * mark constraint as dynamic
2695 cx
->flags
|= PERF_X86_EVENT_DYNAMIC
;
2702 static struct event_constraint
*
2703 intel_get_excl_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
,
2704 int idx
, struct event_constraint
*c
)
2706 struct intel_excl_cntrs
*excl_cntrs
= cpuc
->excl_cntrs
;
2707 struct intel_excl_states
*xlo
;
2708 int tid
= cpuc
->excl_thread_id
;
2712 * validating a group does not require
2713 * enforcing cross-thread exclusion
2715 if (cpuc
->is_fake
|| !is_ht_workaround_enabled())
2719 * no exclusion needed
2721 if (WARN_ON_ONCE(!excl_cntrs
))
2725 * because we modify the constraint, we need
2726 * to make a copy. Static constraints come
2727 * from static const tables.
2729 * only needed when constraint has not yet
2730 * been cloned (marked dynamic)
2732 c
= dyn_constraint(cpuc
, c
, idx
);
2735 * From here on, the constraint is dynamic.
2736 * Either it was just allocated above, or it
2737 * was allocated during a earlier invocation
2742 * state of sibling HT
2744 xlo
= &excl_cntrs
->states
[tid
^ 1];
2747 * event requires exclusive counter access
2750 is_excl
= c
->flags
& PERF_X86_EVENT_EXCL
;
2751 if (is_excl
&& !(event
->hw
.flags
& PERF_X86_EVENT_EXCL_ACCT
)) {
2752 event
->hw
.flags
|= PERF_X86_EVENT_EXCL_ACCT
;
2753 if (!cpuc
->n_excl
++)
2754 WRITE_ONCE(excl_cntrs
->has_exclusive
[tid
], 1);
2758 * Modify static constraint with current dynamic
2761 * EXCLUSIVE: sibling counter measuring exclusive event
2762 * SHARED : sibling counter measuring non-exclusive event
2763 * UNUSED : sibling counter unused
2765 for_each_set_bit(i
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
2767 * exclusive event in sibling counter
2768 * our corresponding counter cannot be used
2769 * regardless of our event
2771 if (xlo
->state
[i
] == INTEL_EXCL_EXCLUSIVE
)
2772 __clear_bit(i
, c
->idxmsk
);
2774 * if measuring an exclusive event, sibling
2775 * measuring non-exclusive, then counter cannot
2778 if (is_excl
&& xlo
->state
[i
] == INTEL_EXCL_SHARED
)
2779 __clear_bit(i
, c
->idxmsk
);
2783 * recompute actual bit weight for scheduling algorithm
2785 c
->weight
= hweight64(c
->idxmsk64
);
2788 * if we return an empty mask, then switch
2789 * back to static empty constraint to avoid
2790 * the cost of freeing later on
2793 c
= &emptyconstraint
;
2798 static struct event_constraint
*
2799 intel_get_event_constraints(struct cpu_hw_events
*cpuc
, int idx
,
2800 struct perf_event
*event
)
2802 struct event_constraint
*c1
= NULL
;
2803 struct event_constraint
*c2
;
2805 if (idx
>= 0) /* fake does < 0 */
2806 c1
= cpuc
->event_constraint
[idx
];
2810 * - static constraint: no change across incremental scheduling calls
2811 * - dynamic constraint: handled by intel_get_excl_constraints()
2813 c2
= __intel_get_event_constraints(cpuc
, idx
, event
);
2814 if (c1
&& (c1
->flags
& PERF_X86_EVENT_DYNAMIC
)) {
2815 bitmap_copy(c1
->idxmsk
, c2
->idxmsk
, X86_PMC_IDX_MAX
);
2816 c1
->weight
= c2
->weight
;
2820 if (cpuc
->excl_cntrs
)
2821 return intel_get_excl_constraints(cpuc
, event
, idx
, c2
);
2826 static void intel_put_excl_constraints(struct cpu_hw_events
*cpuc
,
2827 struct perf_event
*event
)
2829 struct hw_perf_event
*hwc
= &event
->hw
;
2830 struct intel_excl_cntrs
*excl_cntrs
= cpuc
->excl_cntrs
;
2831 int tid
= cpuc
->excl_thread_id
;
2832 struct intel_excl_states
*xl
;
2835 * nothing needed if in group validation mode
2840 if (WARN_ON_ONCE(!excl_cntrs
))
2843 if (hwc
->flags
& PERF_X86_EVENT_EXCL_ACCT
) {
2844 hwc
->flags
&= ~PERF_X86_EVENT_EXCL_ACCT
;
2845 if (!--cpuc
->n_excl
)
2846 WRITE_ONCE(excl_cntrs
->has_exclusive
[tid
], 0);
2850 * If event was actually assigned, then mark the counter state as
2853 if (hwc
->idx
>= 0) {
2854 xl
= &excl_cntrs
->states
[tid
];
2857 * put_constraint may be called from x86_schedule_events()
2858 * which already has the lock held so here make locking
2861 if (!xl
->sched_started
)
2862 raw_spin_lock(&excl_cntrs
->lock
);
2864 xl
->state
[hwc
->idx
] = INTEL_EXCL_UNUSED
;
2866 if (!xl
->sched_started
)
2867 raw_spin_unlock(&excl_cntrs
->lock
);
2872 intel_put_shared_regs_event_constraints(struct cpu_hw_events
*cpuc
,
2873 struct perf_event
*event
)
2875 struct hw_perf_event_extra
*reg
;
2877 reg
= &event
->hw
.extra_reg
;
2878 if (reg
->idx
!= EXTRA_REG_NONE
)
2879 __intel_shared_reg_put_constraints(cpuc
, reg
);
2881 reg
= &event
->hw
.branch_reg
;
2882 if (reg
->idx
!= EXTRA_REG_NONE
)
2883 __intel_shared_reg_put_constraints(cpuc
, reg
);
2886 static void intel_put_event_constraints(struct cpu_hw_events
*cpuc
,
2887 struct perf_event
*event
)
2889 intel_put_shared_regs_event_constraints(cpuc
, event
);
2892 * is PMU has exclusive counter restrictions, then
2893 * all events are subject to and must call the
2894 * put_excl_constraints() routine
2896 if (cpuc
->excl_cntrs
)
2897 intel_put_excl_constraints(cpuc
, event
);
2900 static void intel_pebs_aliases_core2(struct perf_event
*event
)
2902 if ((event
->hw
.config
& X86_RAW_EVENT_MASK
) == 0x003c) {
2904 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2905 * (0x003c) so that we can use it with PEBS.
2907 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2908 * PEBS capable. However we can use INST_RETIRED.ANY_P
2909 * (0x00c0), which is a PEBS capable event, to get the same
2912 * INST_RETIRED.ANY_P counts the number of cycles that retires
2913 * CNTMASK instructions. By setting CNTMASK to a value (16)
2914 * larger than the maximum number of instructions that can be
2915 * retired per cycle (4) and then inverting the condition, we
2916 * count all cycles that retire 16 or less instructions, which
2919 * Thereby we gain a PEBS capable cycle counter.
2921 u64 alt_config
= X86_CONFIG(.event
=0xc0, .inv
=1, .cmask
=16);
2923 alt_config
|= (event
->hw
.config
& ~X86_RAW_EVENT_MASK
);
2924 event
->hw
.config
= alt_config
;
2928 static void intel_pebs_aliases_snb(struct perf_event
*event
)
2930 if ((event
->hw
.config
& X86_RAW_EVENT_MASK
) == 0x003c) {
2932 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2933 * (0x003c) so that we can use it with PEBS.
2935 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2936 * PEBS capable. However we can use UOPS_RETIRED.ALL
2937 * (0x01c2), which is a PEBS capable event, to get the same
2940 * UOPS_RETIRED.ALL counts the number of cycles that retires
2941 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2942 * larger than the maximum number of micro-ops that can be
2943 * retired per cycle (4) and then inverting the condition, we
2944 * count all cycles that retire 16 or less micro-ops, which
2947 * Thereby we gain a PEBS capable cycle counter.
2949 u64 alt_config
= X86_CONFIG(.event
=0xc2, .umask
=0x01, .inv
=1, .cmask
=16);
2951 alt_config
|= (event
->hw
.config
& ~X86_RAW_EVENT_MASK
);
2952 event
->hw
.config
= alt_config
;
2956 static void intel_pebs_aliases_precdist(struct perf_event
*event
)
2958 if ((event
->hw
.config
& X86_RAW_EVENT_MASK
) == 0x003c) {
2960 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2961 * (0x003c) so that we can use it with PEBS.
2963 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2964 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
2965 * (0x01c0), which is a PEBS capable event, to get the same
2968 * The PREC_DIST event has special support to minimize sample
2969 * shadowing effects. One drawback is that it can be
2970 * only programmed on counter 1, but that seems like an
2971 * acceptable trade off.
2973 u64 alt_config
= X86_CONFIG(.event
=0xc0, .umask
=0x01, .inv
=1, .cmask
=16);
2975 alt_config
|= (event
->hw
.config
& ~X86_RAW_EVENT_MASK
);
2976 event
->hw
.config
= alt_config
;
2980 static void intel_pebs_aliases_ivb(struct perf_event
*event
)
2982 if (event
->attr
.precise_ip
< 3)
2983 return intel_pebs_aliases_snb(event
);
2984 return intel_pebs_aliases_precdist(event
);
2987 static void intel_pebs_aliases_skl(struct perf_event
*event
)
2989 if (event
->attr
.precise_ip
< 3)
2990 return intel_pebs_aliases_core2(event
);
2991 return intel_pebs_aliases_precdist(event
);
2994 static unsigned long intel_pmu_free_running_flags(struct perf_event
*event
)
2996 unsigned long flags
= x86_pmu
.free_running_flags
;
2998 if (event
->attr
.use_clockid
)
2999 flags
&= ~PERF_SAMPLE_TIME
;
3000 if (!event
->attr
.exclude_kernel
)
3001 flags
&= ~PERF_SAMPLE_REGS_USER
;
3002 if (event
->attr
.sample_regs_user
& ~PEBS_GP_REGS
)
3003 flags
&= ~(PERF_SAMPLE_REGS_USER
| PERF_SAMPLE_REGS_INTR
);
3007 static int intel_pmu_bts_config(struct perf_event
*event
)
3009 struct perf_event_attr
*attr
= &event
->attr
;
3011 if (unlikely(intel_pmu_has_bts(event
))) {
3012 /* BTS is not supported by this architecture. */
3013 if (!x86_pmu
.bts_active
)
3016 /* BTS is currently only allowed for user-mode. */
3017 if (!attr
->exclude_kernel
)
3020 /* BTS is not allowed for precise events. */
3021 if (attr
->precise_ip
)
3024 /* disallow bts if conflicting events are present */
3025 if (x86_add_exclusive(x86_lbr_exclusive_lbr
))
3028 event
->destroy
= hw_perf_lbr_event_destroy
;
3034 static int core_pmu_hw_config(struct perf_event
*event
)
3036 int ret
= x86_pmu_hw_config(event
);
3041 return intel_pmu_bts_config(event
);
3044 static int intel_pmu_hw_config(struct perf_event
*event
)
3046 int ret
= x86_pmu_hw_config(event
);
3051 ret
= intel_pmu_bts_config(event
);
3055 if (event
->attr
.precise_ip
) {
3056 if (!(event
->attr
.freq
|| (event
->attr
.wakeup_events
&& !event
->attr
.watermark
))) {
3057 event
->hw
.flags
|= PERF_X86_EVENT_AUTO_RELOAD
;
3058 if (!(event
->attr
.sample_type
&
3059 ~intel_pmu_free_running_flags(event
)))
3060 event
->hw
.flags
|= PERF_X86_EVENT_FREERUNNING
;
3062 if (x86_pmu
.pebs_aliases
)
3063 x86_pmu
.pebs_aliases(event
);
3066 if (needs_branch_stack(event
)) {
3067 ret
= intel_pmu_setup_lbr_filter(event
);
3072 * BTS is set up earlier in this path, so don't account twice
3074 if (!unlikely(intel_pmu_has_bts(event
))) {
3075 /* disallow lbr if conflicting events are present */
3076 if (x86_add_exclusive(x86_lbr_exclusive_lbr
))
3079 event
->destroy
= hw_perf_lbr_event_destroy
;
3083 if (event
->attr
.type
!= PERF_TYPE_RAW
)
3086 if (!(event
->attr
.config
& ARCH_PERFMON_EVENTSEL_ANY
))
3089 if (x86_pmu
.version
< 3)
3092 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN
))
3095 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_ANY
;
3100 struct perf_guest_switch_msr
*perf_guest_get_msrs(int *nr
)
3102 if (x86_pmu
.guest_get_msrs
)
3103 return x86_pmu
.guest_get_msrs(nr
);
3107 EXPORT_SYMBOL_GPL(perf_guest_get_msrs
);
3109 static struct perf_guest_switch_msr
*intel_guest_get_msrs(int *nr
)
3111 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
3112 struct perf_guest_switch_msr
*arr
= cpuc
->guest_switch_msrs
;
3114 arr
[0].msr
= MSR_CORE_PERF_GLOBAL_CTRL
;
3115 arr
[0].host
= x86_pmu
.intel_ctrl
& ~cpuc
->intel_ctrl_guest_mask
;
3116 arr
[0].guest
= x86_pmu
.intel_ctrl
& ~cpuc
->intel_ctrl_host_mask
;
3118 * If PMU counter has PEBS enabled it is not enough to disable counter
3119 * on a guest entry since PEBS memory write can overshoot guest entry
3120 * and corrupt guest memory. Disabling PEBS solves the problem.
3122 arr
[1].msr
= MSR_IA32_PEBS_ENABLE
;
3123 arr
[1].host
= cpuc
->pebs_enabled
;
3130 static struct perf_guest_switch_msr
*core_guest_get_msrs(int *nr
)
3132 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
3133 struct perf_guest_switch_msr
*arr
= cpuc
->guest_switch_msrs
;
3136 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
3137 struct perf_event
*event
= cpuc
->events
[idx
];
3139 arr
[idx
].msr
= x86_pmu_config_addr(idx
);
3140 arr
[idx
].host
= arr
[idx
].guest
= 0;
3142 if (!test_bit(idx
, cpuc
->active_mask
))
3145 arr
[idx
].host
= arr
[idx
].guest
=
3146 event
->hw
.config
| ARCH_PERFMON_EVENTSEL_ENABLE
;
3148 if (event
->attr
.exclude_host
)
3149 arr
[idx
].host
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
3150 else if (event
->attr
.exclude_guest
)
3151 arr
[idx
].guest
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
3154 *nr
= x86_pmu
.num_counters
;
3158 static void core_pmu_enable_event(struct perf_event
*event
)
3160 if (!event
->attr
.exclude_host
)
3161 x86_pmu_enable_event(event
);
3164 static void core_pmu_enable_all(int added
)
3166 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
3169 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
3170 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
3172 if (!test_bit(idx
, cpuc
->active_mask
) ||
3173 cpuc
->events
[idx
]->attr
.exclude_host
)
3176 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
3180 static int hsw_hw_config(struct perf_event
*event
)
3182 int ret
= intel_pmu_hw_config(event
);
3186 if (!boot_cpu_has(X86_FEATURE_RTM
) && !boot_cpu_has(X86_FEATURE_HLE
))
3188 event
->hw
.config
|= event
->attr
.config
& (HSW_IN_TX
|HSW_IN_TX_CHECKPOINTED
);
3191 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
3192 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
3195 if ((event
->hw
.config
& (HSW_IN_TX
|HSW_IN_TX_CHECKPOINTED
)) &&
3196 ((event
->hw
.config
& ARCH_PERFMON_EVENTSEL_ANY
) ||
3197 event
->attr
.precise_ip
> 0))
3200 if (event_is_checkpointed(event
)) {
3202 * Sampling of checkpointed events can cause situations where
3203 * the CPU constantly aborts because of a overflow, which is
3204 * then checkpointed back and ignored. Forbid checkpointing
3207 * But still allow a long sampling period, so that perf stat
3210 if (event
->attr
.sample_period
> 0 &&
3211 event
->attr
.sample_period
< 0x7fffffff)
3217 static struct event_constraint counter0_constraint
=
3218 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3220 static struct event_constraint counter2_constraint
=
3221 EVENT_CONSTRAINT(0, 0x4, 0);
3223 static struct event_constraint
*
3224 hsw_get_event_constraints(struct cpu_hw_events
*cpuc
, int idx
,
3225 struct perf_event
*event
)
3227 struct event_constraint
*c
;
3229 c
= intel_get_event_constraints(cpuc
, idx
, event
);
3231 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
3232 if (event
->hw
.config
& HSW_IN_TX_CHECKPOINTED
) {
3233 if (c
->idxmsk64
& (1U << 2))
3234 return &counter2_constraint
;
3235 return &emptyconstraint
;
3241 static struct event_constraint
*
3242 glp_get_event_constraints(struct cpu_hw_events
*cpuc
, int idx
,
3243 struct perf_event
*event
)
3245 struct event_constraint
*c
;
3247 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
3248 if (event
->attr
.precise_ip
== 3)
3249 return &counter0_constraint
;
3251 c
= intel_get_event_constraints(cpuc
, idx
, event
);
3256 static bool allow_tsx_force_abort
= true;
3258 static struct event_constraint
*
3259 tfa_get_event_constraints(struct cpu_hw_events
*cpuc
, int idx
,
3260 struct perf_event
*event
)
3262 struct event_constraint
*c
= hsw_get_event_constraints(cpuc
, idx
, event
);
3265 * Without TFA we must not use PMC3.
3267 if (!allow_tsx_force_abort
&& test_bit(3, c
->idxmsk
) && idx
>= 0) {
3268 c
= dyn_constraint(cpuc
, c
, idx
);
3269 c
->idxmsk64
&= ~(1ULL << 3);
3279 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
3280 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
3281 * the two to enforce a minimum period of 128 (the smallest value that has bits
3282 * 0-5 cleared and >= 100).
3284 * Because of how the code in x86_perf_event_set_period() works, the truncation
3285 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
3286 * to make up for the 'lost' events due to carrying the 'error' in period_left.
3288 * Therefore the effective (average) period matches the requested period,
3289 * despite coarser hardware granularity.
3291 static u64
bdw_limit_period(struct perf_event
*event
, u64 left
)
3293 if ((event
->hw
.config
& INTEL_ARCH_EVENT_MASK
) ==
3294 X86_CONFIG(.event
=0xc0, .umask
=0x01)) {
3302 static u64
nhm_limit_period(struct perf_event
*event
, u64 left
)
3304 return max(left
, 32ULL);
3307 PMU_FORMAT_ATTR(event
, "config:0-7" );
3308 PMU_FORMAT_ATTR(umask
, "config:8-15" );
3309 PMU_FORMAT_ATTR(edge
, "config:18" );
3310 PMU_FORMAT_ATTR(pc
, "config:19" );
3311 PMU_FORMAT_ATTR(any
, "config:21" ); /* v3 + */
3312 PMU_FORMAT_ATTR(inv
, "config:23" );
3313 PMU_FORMAT_ATTR(cmask
, "config:24-31" );
3314 PMU_FORMAT_ATTR(in_tx
, "config:32");
3315 PMU_FORMAT_ATTR(in_tx_cp
, "config:33");
3317 static struct attribute
*intel_arch_formats_attr
[] = {
3318 &format_attr_event
.attr
,
3319 &format_attr_umask
.attr
,
3320 &format_attr_edge
.attr
,
3321 &format_attr_pc
.attr
,
3322 &format_attr_inv
.attr
,
3323 &format_attr_cmask
.attr
,
3327 ssize_t
intel_event_sysfs_show(char *page
, u64 config
)
3329 u64 event
= (config
& ARCH_PERFMON_EVENTSEL_EVENT
);
3331 return x86_event_sysfs_show(page
, config
, event
);
3334 static struct intel_shared_regs
*allocate_shared_regs(int cpu
)
3336 struct intel_shared_regs
*regs
;
3339 regs
= kzalloc_node(sizeof(struct intel_shared_regs
),
3340 GFP_KERNEL
, cpu_to_node(cpu
));
3343 * initialize the locks to keep lockdep happy
3345 for (i
= 0; i
< EXTRA_REG_MAX
; i
++)
3346 raw_spin_lock_init(®s
->regs
[i
].lock
);
3353 static struct intel_excl_cntrs
*allocate_excl_cntrs(int cpu
)
3355 struct intel_excl_cntrs
*c
;
3357 c
= kzalloc_node(sizeof(struct intel_excl_cntrs
),
3358 GFP_KERNEL
, cpu_to_node(cpu
));
3360 raw_spin_lock_init(&c
->lock
);
3367 int intel_cpuc_prepare(struct cpu_hw_events
*cpuc
, int cpu
)
3369 if (x86_pmu
.extra_regs
|| x86_pmu
.lbr_sel_map
) {
3370 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
3371 if (!cpuc
->shared_regs
)
3375 if (x86_pmu
.flags
& (PMU_FL_EXCL_CNTRS
| PMU_FL_TFA
)) {
3376 size_t sz
= X86_PMC_IDX_MAX
* sizeof(struct event_constraint
);
3378 cpuc
->constraint_list
= kzalloc_node(sz
, GFP_KERNEL
, cpu_to_node(cpu
));
3379 if (!cpuc
->constraint_list
)
3380 goto err_shared_regs
;
3383 if (x86_pmu
.flags
& PMU_FL_EXCL_CNTRS
) {
3384 cpuc
->excl_cntrs
= allocate_excl_cntrs(cpu
);
3385 if (!cpuc
->excl_cntrs
)
3386 goto err_constraint_list
;
3388 cpuc
->excl_thread_id
= 0;
3393 err_constraint_list
:
3394 kfree(cpuc
->constraint_list
);
3395 cpuc
->constraint_list
= NULL
;
3398 kfree(cpuc
->shared_regs
);
3399 cpuc
->shared_regs
= NULL
;
3405 static int intel_pmu_cpu_prepare(int cpu
)
3407 return intel_cpuc_prepare(&per_cpu(cpu_hw_events
, cpu
), cpu
);
3410 static void flip_smm_bit(void *data
)
3412 unsigned long set
= *(unsigned long *)data
;
3415 msr_set_bit(MSR_IA32_DEBUGCTLMSR
,
3416 DEBUGCTLMSR_FREEZE_IN_SMM_BIT
);
3418 msr_clear_bit(MSR_IA32_DEBUGCTLMSR
,
3419 DEBUGCTLMSR_FREEZE_IN_SMM_BIT
);
3423 static void intel_pmu_cpu_starting(int cpu
)
3425 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
3426 int core_id
= topology_core_id(cpu
);
3429 init_debug_store_on_cpu(cpu
);
3431 * Deal with CPUs that don't clear their LBRs on power-up.
3433 intel_pmu_lbr_reset();
3435 cpuc
->lbr_sel
= NULL
;
3437 if (x86_pmu
.flags
& PMU_FL_TFA
) {
3438 WARN_ON_ONCE(cpuc
->tfa_shadow
);
3439 cpuc
->tfa_shadow
= ~0ULL;
3440 intel_set_tfa(cpuc
, false);
3443 if (x86_pmu
.version
> 1)
3444 flip_smm_bit(&x86_pmu
.attr_freeze_on_smi
);
3446 if (!cpuc
->shared_regs
)
3449 if (!(x86_pmu
.flags
& PMU_FL_NO_HT_SHARING
)) {
3450 for_each_cpu(i
, topology_sibling_cpumask(cpu
)) {
3451 struct intel_shared_regs
*pc
;
3453 pc
= per_cpu(cpu_hw_events
, i
).shared_regs
;
3454 if (pc
&& pc
->core_id
== core_id
) {
3455 cpuc
->kfree_on_online
[0] = cpuc
->shared_regs
;
3456 cpuc
->shared_regs
= pc
;
3460 cpuc
->shared_regs
->core_id
= core_id
;
3461 cpuc
->shared_regs
->refcnt
++;
3464 if (x86_pmu
.lbr_sel_map
)
3465 cpuc
->lbr_sel
= &cpuc
->shared_regs
->regs
[EXTRA_REG_LBR
];
3467 if (x86_pmu
.flags
& PMU_FL_EXCL_CNTRS
) {
3468 for_each_cpu(i
, topology_sibling_cpumask(cpu
)) {
3469 struct cpu_hw_events
*sibling
;
3470 struct intel_excl_cntrs
*c
;
3472 sibling
= &per_cpu(cpu_hw_events
, i
);
3473 c
= sibling
->excl_cntrs
;
3474 if (c
&& c
->core_id
== core_id
) {
3475 cpuc
->kfree_on_online
[1] = cpuc
->excl_cntrs
;
3476 cpuc
->excl_cntrs
= c
;
3477 if (!sibling
->excl_thread_id
)
3478 cpuc
->excl_thread_id
= 1;
3482 cpuc
->excl_cntrs
->core_id
= core_id
;
3483 cpuc
->excl_cntrs
->refcnt
++;
3487 static void free_excl_cntrs(struct cpu_hw_events
*cpuc
)
3489 struct intel_excl_cntrs
*c
;
3491 c
= cpuc
->excl_cntrs
;
3493 if (c
->core_id
== -1 || --c
->refcnt
== 0)
3495 cpuc
->excl_cntrs
= NULL
;
3498 kfree(cpuc
->constraint_list
);
3499 cpuc
->constraint_list
= NULL
;
3502 static void intel_pmu_cpu_dying(int cpu
)
3504 fini_debug_store_on_cpu(cpu
);
3507 void intel_cpuc_finish(struct cpu_hw_events
*cpuc
)
3509 struct intel_shared_regs
*pc
;
3511 pc
= cpuc
->shared_regs
;
3513 if (pc
->core_id
== -1 || --pc
->refcnt
== 0)
3515 cpuc
->shared_regs
= NULL
;
3518 free_excl_cntrs(cpuc
);
3521 static void intel_pmu_cpu_dead(int cpu
)
3523 intel_cpuc_finish(&per_cpu(cpu_hw_events
, cpu
));
3526 static void intel_pmu_sched_task(struct perf_event_context
*ctx
,
3529 intel_pmu_pebs_sched_task(ctx
, sched_in
);
3530 intel_pmu_lbr_sched_task(ctx
, sched_in
);
3533 static int intel_pmu_check_period(struct perf_event
*event
, u64 value
)
3535 return intel_pmu_has_bts_period(event
, value
) ? -EINVAL
: 0;
3538 PMU_FORMAT_ATTR(offcore_rsp
, "config1:0-63");
3540 PMU_FORMAT_ATTR(ldlat
, "config1:0-15");
3542 PMU_FORMAT_ATTR(frontend
, "config1:0-23");
3544 static struct attribute
*intel_arch3_formats_attr
[] = {
3545 &format_attr_event
.attr
,
3546 &format_attr_umask
.attr
,
3547 &format_attr_edge
.attr
,
3548 &format_attr_pc
.attr
,
3549 &format_attr_any
.attr
,
3550 &format_attr_inv
.attr
,
3551 &format_attr_cmask
.attr
,
3555 static struct attribute
*hsw_format_attr
[] = {
3556 &format_attr_in_tx
.attr
,
3557 &format_attr_in_tx_cp
.attr
,
3558 &format_attr_offcore_rsp
.attr
,
3559 &format_attr_ldlat
.attr
,
3563 static struct attribute
*nhm_format_attr
[] = {
3564 &format_attr_offcore_rsp
.attr
,
3565 &format_attr_ldlat
.attr
,
3569 static struct attribute
*slm_format_attr
[] = {
3570 &format_attr_offcore_rsp
.attr
,
3574 static struct attribute
*skl_format_attr
[] = {
3575 &format_attr_frontend
.attr
,
3579 static __initconst
const struct x86_pmu core_pmu
= {
3581 .handle_irq
= x86_pmu_handle_irq
,
3582 .disable_all
= x86_pmu_disable_all
,
3583 .enable_all
= core_pmu_enable_all
,
3584 .enable
= core_pmu_enable_event
,
3585 .disable
= x86_pmu_disable_event
,
3586 .hw_config
= core_pmu_hw_config
,
3587 .schedule_events
= x86_schedule_events
,
3588 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
3589 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
3590 .event_map
= intel_pmu_event_map
,
3591 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
3593 .free_running_flags
= PEBS_FREERUNNING_FLAGS
,
3596 * Intel PMCs cannot be accessed sanely above 32-bit width,
3597 * so we install an artificial 1<<31 period regardless of
3598 * the generic event period:
3600 .max_period
= (1ULL<<31) - 1,
3601 .get_event_constraints
= intel_get_event_constraints
,
3602 .put_event_constraints
= intel_put_event_constraints
,
3603 .event_constraints
= intel_core_event_constraints
,
3604 .guest_get_msrs
= core_guest_get_msrs
,
3605 .format_attrs
= intel_arch_formats_attr
,
3606 .events_sysfs_show
= intel_event_sysfs_show
,
3609 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3610 * together with PMU version 1 and thus be using core_pmu with
3611 * shared_regs. We need following callbacks here to allocate
3614 .cpu_prepare
= intel_pmu_cpu_prepare
,
3615 .cpu_starting
= intel_pmu_cpu_starting
,
3616 .cpu_dying
= intel_pmu_cpu_dying
,
3617 .cpu_dead
= intel_pmu_cpu_dead
,
3619 .check_period
= intel_pmu_check_period
,
3622 static struct attribute
*intel_pmu_attrs
[];
3624 static __initconst
const struct x86_pmu intel_pmu
= {
3626 .handle_irq
= intel_pmu_handle_irq
,
3627 .disable_all
= intel_pmu_disable_all
,
3628 .enable_all
= intel_pmu_enable_all
,
3629 .enable
= intel_pmu_enable_event
,
3630 .disable
= intel_pmu_disable_event
,
3631 .add
= intel_pmu_add_event
,
3632 .del
= intel_pmu_del_event
,
3633 .hw_config
= intel_pmu_hw_config
,
3634 .schedule_events
= x86_schedule_events
,
3635 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
3636 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
3637 .event_map
= intel_pmu_event_map
,
3638 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
3640 .free_running_flags
= PEBS_FREERUNNING_FLAGS
,
3642 * Intel PMCs cannot be accessed sanely above 32 bit width,
3643 * so we install an artificial 1<<31 period regardless of
3644 * the generic event period:
3646 .max_period
= (1ULL << 31) - 1,
3647 .get_event_constraints
= intel_get_event_constraints
,
3648 .put_event_constraints
= intel_put_event_constraints
,
3649 .pebs_aliases
= intel_pebs_aliases_core2
,
3651 .format_attrs
= intel_arch3_formats_attr
,
3652 .events_sysfs_show
= intel_event_sysfs_show
,
3654 .attrs
= intel_pmu_attrs
,
3656 .cpu_prepare
= intel_pmu_cpu_prepare
,
3657 .cpu_starting
= intel_pmu_cpu_starting
,
3658 .cpu_dying
= intel_pmu_cpu_dying
,
3659 .cpu_dead
= intel_pmu_cpu_dead
,
3661 .guest_get_msrs
= intel_guest_get_msrs
,
3662 .sched_task
= intel_pmu_sched_task
,
3664 .check_period
= intel_pmu_check_period
,
3667 static __init
void intel_clovertown_quirk(void)
3670 * PEBS is unreliable due to:
3672 * AJ67 - PEBS may experience CPL leaks
3673 * AJ68 - PEBS PMI may be delayed by one event
3674 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3675 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3677 * AJ67 could be worked around by restricting the OS/USR flags.
3678 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3680 * AJ106 could possibly be worked around by not allowing LBR
3681 * usage from PEBS, including the fixup.
3682 * AJ68 could possibly be worked around by always programming
3683 * a pebs_event_reset[0] value and coping with the lost events.
3685 * But taken together it might just make sense to not enable PEBS on
3688 pr_warn("PEBS disabled due to CPU errata\n");
3690 x86_pmu
.pebs_constraints
= NULL
;
3693 static int intel_snb_pebs_broken(int cpu
)
3695 u32 rev
= UINT_MAX
; /* default to broken for unknown models */
3697 switch (cpu_data(cpu
).x86_model
) {
3698 case INTEL_FAM6_SANDYBRIDGE
:
3702 case INTEL_FAM6_SANDYBRIDGE_X
:
3703 switch (cpu_data(cpu
).x86_stepping
) {
3704 case 6: rev
= 0x618; break;
3705 case 7: rev
= 0x70c; break;
3709 return (cpu_data(cpu
).microcode
< rev
);
3712 static void intel_snb_check_microcode(void)
3714 int pebs_broken
= 0;
3717 for_each_online_cpu(cpu
) {
3718 if ((pebs_broken
= intel_snb_pebs_broken(cpu
)))
3722 if (pebs_broken
== x86_pmu
.pebs_broken
)
3726 * Serialized by the microcode lock..
3728 if (x86_pmu
.pebs_broken
) {
3729 pr_info("PEBS enabled due to microcode update\n");
3730 x86_pmu
.pebs_broken
= 0;
3732 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3733 x86_pmu
.pebs_broken
= 1;
3737 static bool is_lbr_from(unsigned long msr
)
3739 unsigned long lbr_from_nr
= x86_pmu
.lbr_from
+ x86_pmu
.lbr_nr
;
3741 return x86_pmu
.lbr_from
<= msr
&& msr
< lbr_from_nr
;
3745 * Under certain circumstances, access certain MSR may cause #GP.
3746 * The function tests if the input MSR can be safely accessed.
3748 static bool check_msr(unsigned long msr
, u64 mask
)
3750 u64 val_old
, val_new
, val_tmp
;
3753 * Read the current value, change it and read it back to see if it
3754 * matches, this is needed to detect certain hardware emulators
3755 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3757 if (rdmsrl_safe(msr
, &val_old
))
3761 * Only change the bits which can be updated by wrmsrl.
3763 val_tmp
= val_old
^ mask
;
3765 if (is_lbr_from(msr
))
3766 val_tmp
= lbr_from_signext_quirk_wr(val_tmp
);
3768 if (wrmsrl_safe(msr
, val_tmp
) ||
3769 rdmsrl_safe(msr
, &val_new
))
3773 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
3774 * should equal rdmsrl()'s even with the quirk.
3776 if (val_new
!= val_tmp
)
3779 if (is_lbr_from(msr
))
3780 val_old
= lbr_from_signext_quirk_wr(val_old
);
3782 /* Here it's sure that the MSR can be safely accessed.
3783 * Restore the old value and return.
3785 wrmsrl(msr
, val_old
);
3790 static __init
void intel_sandybridge_quirk(void)
3792 x86_pmu
.check_microcode
= intel_snb_check_microcode
;
3794 intel_snb_check_microcode();
3798 static const struct { int id
; char *name
; } intel_arch_events_map
[] __initconst
= {
3799 { PERF_COUNT_HW_CPU_CYCLES
, "cpu cycles" },
3800 { PERF_COUNT_HW_INSTRUCTIONS
, "instructions" },
3801 { PERF_COUNT_HW_BUS_CYCLES
, "bus cycles" },
3802 { PERF_COUNT_HW_CACHE_REFERENCES
, "cache references" },
3803 { PERF_COUNT_HW_CACHE_MISSES
, "cache misses" },
3804 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS
, "branch instructions" },
3805 { PERF_COUNT_HW_BRANCH_MISSES
, "branch misses" },
3808 static __init
void intel_arch_events_quirk(void)
3812 /* disable event that reported as not presend by cpuid */
3813 for_each_set_bit(bit
, x86_pmu
.events_mask
, ARRAY_SIZE(intel_arch_events_map
)) {
3814 intel_perfmon_event_map
[intel_arch_events_map
[bit
].id
] = 0;
3815 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3816 intel_arch_events_map
[bit
].name
);
3820 static __init
void intel_nehalem_quirk(void)
3822 union cpuid10_ebx ebx
;
3824 ebx
.full
= x86_pmu
.events_maskl
;
3825 if (ebx
.split
.no_branch_misses_retired
) {
3827 * Erratum AAJ80 detected, we work it around by using
3828 * the BR_MISP_EXEC.ANY event. This will over-count
3829 * branch-misses, but it's still much better than the
3830 * architectural event which is often completely bogus:
3832 intel_perfmon_event_map
[PERF_COUNT_HW_BRANCH_MISSES
] = 0x7f89;
3833 ebx
.split
.no_branch_misses_retired
= 0;
3834 x86_pmu
.events_maskl
= ebx
.full
;
3835 pr_info("CPU erratum AAJ80 worked around\n");
3840 * enable software workaround for errata:
3845 * Only needed when HT is enabled. However detecting
3846 * if HT is enabled is difficult (model specific). So instead,
3847 * we enable the workaround in the early boot, and verify if
3848 * it is needed in a later initcall phase once we have valid
3849 * topology information to check if HT is actually enabled
3851 static __init
void intel_ht_bug(void)
3853 x86_pmu
.flags
|= PMU_FL_EXCL_CNTRS
| PMU_FL_EXCL_ENABLED
;
3855 x86_pmu
.start_scheduling
= intel_start_scheduling
;
3856 x86_pmu
.commit_scheduling
= intel_commit_scheduling
;
3857 x86_pmu
.stop_scheduling
= intel_stop_scheduling
;
3860 EVENT_ATTR_STR(mem
-loads
, mem_ld_hsw
, "event=0xcd,umask=0x1,ldlat=3");
3861 EVENT_ATTR_STR(mem
-stores
, mem_st_hsw
, "event=0xd0,umask=0x82")
3863 /* Haswell special events */
3864 EVENT_ATTR_STR(tx
-start
, tx_start
, "event=0xc9,umask=0x1");
3865 EVENT_ATTR_STR(tx
-commit
, tx_commit
, "event=0xc9,umask=0x2");
3866 EVENT_ATTR_STR(tx
-abort
, tx_abort
, "event=0xc9,umask=0x4");
3867 EVENT_ATTR_STR(tx
-capacity
, tx_capacity
, "event=0x54,umask=0x2");
3868 EVENT_ATTR_STR(tx
-conflict
, tx_conflict
, "event=0x54,umask=0x1");
3869 EVENT_ATTR_STR(el
-start
, el_start
, "event=0xc8,umask=0x1");
3870 EVENT_ATTR_STR(el
-commit
, el_commit
, "event=0xc8,umask=0x2");
3871 EVENT_ATTR_STR(el
-abort
, el_abort
, "event=0xc8,umask=0x4");
3872 EVENT_ATTR_STR(el
-capacity
, el_capacity
, "event=0x54,umask=0x2");
3873 EVENT_ATTR_STR(el
-conflict
, el_conflict
, "event=0x54,umask=0x1");
3874 EVENT_ATTR_STR(cycles
-t
, cycles_t
, "event=0x3c,in_tx=1");
3875 EVENT_ATTR_STR(cycles
-ct
, cycles_ct
, "event=0x3c,in_tx=1,in_tx_cp=1");
3877 static struct attribute
*hsw_events_attrs
[] = {
3878 EVENT_PTR(mem_ld_hsw
),
3879 EVENT_PTR(mem_st_hsw
),
3880 EVENT_PTR(td_slots_issued
),
3881 EVENT_PTR(td_slots_retired
),
3882 EVENT_PTR(td_fetch_bubbles
),
3883 EVENT_PTR(td_total_slots
),
3884 EVENT_PTR(td_total_slots_scale
),
3885 EVENT_PTR(td_recovery_bubbles
),
3886 EVENT_PTR(td_recovery_bubbles_scale
),
3890 static struct attribute
*hsw_tsx_events_attrs
[] = {
3891 EVENT_PTR(tx_start
),
3892 EVENT_PTR(tx_commit
),
3893 EVENT_PTR(tx_abort
),
3894 EVENT_PTR(tx_capacity
),
3895 EVENT_PTR(tx_conflict
),
3896 EVENT_PTR(el_start
),
3897 EVENT_PTR(el_commit
),
3898 EVENT_PTR(el_abort
),
3899 EVENT_PTR(el_capacity
),
3900 EVENT_PTR(el_conflict
),
3901 EVENT_PTR(cycles_t
),
3902 EVENT_PTR(cycles_ct
),
3906 static __init
struct attribute
**get_hsw_events_attrs(void)
3908 return boot_cpu_has(X86_FEATURE_RTM
) ?
3909 merge_attr(hsw_events_attrs
, hsw_tsx_events_attrs
) :
3913 static ssize_t
freeze_on_smi_show(struct device
*cdev
,
3914 struct device_attribute
*attr
,
3917 return sprintf(buf
, "%lu\n", x86_pmu
.attr_freeze_on_smi
);
3920 static DEFINE_MUTEX(freeze_on_smi_mutex
);
3922 static ssize_t
freeze_on_smi_store(struct device
*cdev
,
3923 struct device_attribute
*attr
,
3924 const char *buf
, size_t count
)
3929 ret
= kstrtoul(buf
, 0, &val
);
3936 mutex_lock(&freeze_on_smi_mutex
);
3938 if (x86_pmu
.attr_freeze_on_smi
== val
)
3941 x86_pmu
.attr_freeze_on_smi
= val
;
3944 on_each_cpu(flip_smm_bit
, &val
, 1);
3947 mutex_unlock(&freeze_on_smi_mutex
);
3952 static DEVICE_ATTR_RW(freeze_on_smi
);
3954 static ssize_t
branches_show(struct device
*cdev
,
3955 struct device_attribute
*attr
,
3958 return snprintf(buf
, PAGE_SIZE
, "%d\n", x86_pmu
.lbr_nr
);
3961 static DEVICE_ATTR_RO(branches
);
3963 static struct attribute
*lbr_attrs
[] = {
3964 &dev_attr_branches
.attr
,
3968 static char pmu_name_str
[30];
3970 static ssize_t
pmu_name_show(struct device
*cdev
,
3971 struct device_attribute
*attr
,
3974 return snprintf(buf
, PAGE_SIZE
, "%s\n", pmu_name_str
);
3977 static DEVICE_ATTR_RO(pmu_name
);
3979 static struct attribute
*intel_pmu_caps_attrs
[] = {
3980 &dev_attr_pmu_name
.attr
,
3984 static DEVICE_BOOL_ATTR(allow_tsx_force_abort
, 0644, allow_tsx_force_abort
);
3986 static struct attribute
*intel_pmu_attrs
[] = {
3987 &dev_attr_freeze_on_smi
.attr
,
3988 NULL
, /* &dev_attr_allow_tsx_force_abort.attr.attr */
3992 __init
int intel_pmu_init(void)
3994 struct attribute
**extra_attr
= NULL
;
3995 struct attribute
**to_free
= NULL
;
3996 union cpuid10_edx edx
;
3997 union cpuid10_eax eax
;
3998 union cpuid10_ebx ebx
;
3999 struct event_constraint
*c
;
4000 unsigned int unused
;
4001 struct extra_reg
*er
;
4005 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
)) {
4006 switch (boot_cpu_data
.x86
) {
4008 return p6_pmu_init();
4010 return knc_pmu_init();
4012 return p4_pmu_init();
4018 * Check whether the Architectural PerfMon supports
4019 * Branch Misses Retired hw_event or not.
4021 cpuid(10, &eax
.full
, &ebx
.full
, &unused
, &edx
.full
);
4022 if (eax
.split
.mask_length
< ARCH_PERFMON_EVENTS_COUNT
)
4025 version
= eax
.split
.version_id
;
4029 x86_pmu
= intel_pmu
;
4031 x86_pmu
.version
= version
;
4032 x86_pmu
.num_counters
= eax
.split
.num_counters
;
4033 x86_pmu
.cntval_bits
= eax
.split
.bit_width
;
4034 x86_pmu
.cntval_mask
= (1ULL << eax
.split
.bit_width
) - 1;
4036 x86_pmu
.events_maskl
= ebx
.full
;
4037 x86_pmu
.events_mask_len
= eax
.split
.mask_length
;
4039 x86_pmu
.max_pebs_events
= min_t(unsigned, MAX_PEBS_EVENTS
, x86_pmu
.num_counters
);
4042 * Quirk: v2 perfmon does not report fixed-purpose events, so
4043 * assume at least 3 events, when not running in a hypervisor:
4046 int assume
= 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR
);
4048 x86_pmu
.num_counters_fixed
=
4049 max((int)edx
.split
.num_counters_fixed
, assume
);
4052 if (boot_cpu_has(X86_FEATURE_PDCM
)) {
4055 rdmsrl(MSR_IA32_PERF_CAPABILITIES
, capabilities
);
4056 x86_pmu
.intel_cap
.capabilities
= capabilities
;
4061 x86_add_quirk(intel_arch_events_quirk
); /* Install first, so it runs last */
4064 * Install the hw-cache-events table:
4066 switch (boot_cpu_data
.x86_model
) {
4067 case INTEL_FAM6_CORE_YONAH
:
4068 pr_cont("Core events, ");
4072 case INTEL_FAM6_CORE2_MEROM
:
4073 x86_add_quirk(intel_clovertown_quirk
);
4074 case INTEL_FAM6_CORE2_MEROM_L
:
4075 case INTEL_FAM6_CORE2_PENRYN
:
4076 case INTEL_FAM6_CORE2_DUNNINGTON
:
4077 memcpy(hw_cache_event_ids
, core2_hw_cache_event_ids
,
4078 sizeof(hw_cache_event_ids
));
4080 intel_pmu_lbr_init_core();
4082 x86_pmu
.event_constraints
= intel_core2_event_constraints
;
4083 x86_pmu
.pebs_constraints
= intel_core2_pebs_event_constraints
;
4084 pr_cont("Core2 events, ");
4088 case INTEL_FAM6_NEHALEM
:
4089 case INTEL_FAM6_NEHALEM_EP
:
4090 case INTEL_FAM6_NEHALEM_EX
:
4091 memcpy(hw_cache_event_ids
, nehalem_hw_cache_event_ids
,
4092 sizeof(hw_cache_event_ids
));
4093 memcpy(hw_cache_extra_regs
, nehalem_hw_cache_extra_regs
,
4094 sizeof(hw_cache_extra_regs
));
4096 intel_pmu_lbr_init_nhm();
4098 x86_pmu
.event_constraints
= intel_nehalem_event_constraints
;
4099 x86_pmu
.pebs_constraints
= intel_nehalem_pebs_event_constraints
;
4100 x86_pmu
.enable_all
= intel_pmu_nhm_enable_all
;
4101 x86_pmu
.extra_regs
= intel_nehalem_extra_regs
;
4102 x86_pmu
.limit_period
= nhm_limit_period
;
4104 x86_pmu
.cpu_events
= nhm_events_attrs
;
4106 /* UOPS_ISSUED.STALLED_CYCLES */
4107 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
] =
4108 X86_CONFIG(.event
=0x0e, .umask
=0x01, .inv
=1, .cmask
=1);
4109 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
4110 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND
] =
4111 X86_CONFIG(.event
=0xb1, .umask
=0x3f, .inv
=1, .cmask
=1);
4113 intel_pmu_pebs_data_source_nhm();
4114 x86_add_quirk(intel_nehalem_quirk
);
4115 x86_pmu
.pebs_no_tlb
= 1;
4116 extra_attr
= nhm_format_attr
;
4118 pr_cont("Nehalem events, ");
4122 case INTEL_FAM6_ATOM_BONNELL
:
4123 case INTEL_FAM6_ATOM_BONNELL_MID
:
4124 case INTEL_FAM6_ATOM_SALTWELL
:
4125 case INTEL_FAM6_ATOM_SALTWELL_MID
:
4126 case INTEL_FAM6_ATOM_SALTWELL_TABLET
:
4127 memcpy(hw_cache_event_ids
, atom_hw_cache_event_ids
,
4128 sizeof(hw_cache_event_ids
));
4130 intel_pmu_lbr_init_atom();
4132 x86_pmu
.event_constraints
= intel_gen_event_constraints
;
4133 x86_pmu
.pebs_constraints
= intel_atom_pebs_event_constraints
;
4134 x86_pmu
.pebs_aliases
= intel_pebs_aliases_core2
;
4135 pr_cont("Atom events, ");
4139 case INTEL_FAM6_ATOM_SILVERMONT
:
4140 case INTEL_FAM6_ATOM_SILVERMONT_X
:
4141 case INTEL_FAM6_ATOM_SILVERMONT_MID
:
4142 case INTEL_FAM6_ATOM_AIRMONT
:
4143 case INTEL_FAM6_ATOM_AIRMONT_MID
:
4144 memcpy(hw_cache_event_ids
, slm_hw_cache_event_ids
,
4145 sizeof(hw_cache_event_ids
));
4146 memcpy(hw_cache_extra_regs
, slm_hw_cache_extra_regs
,
4147 sizeof(hw_cache_extra_regs
));
4149 intel_pmu_lbr_init_slm();
4151 x86_pmu
.event_constraints
= intel_slm_event_constraints
;
4152 x86_pmu
.pebs_constraints
= intel_slm_pebs_event_constraints
;
4153 x86_pmu
.extra_regs
= intel_slm_extra_regs
;
4154 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
4155 x86_pmu
.cpu_events
= slm_events_attrs
;
4156 extra_attr
= slm_format_attr
;
4157 pr_cont("Silvermont events, ");
4158 name
= "silvermont";
4161 case INTEL_FAM6_ATOM_GOLDMONT
:
4162 case INTEL_FAM6_ATOM_GOLDMONT_X
:
4163 memcpy(hw_cache_event_ids
, glm_hw_cache_event_ids
,
4164 sizeof(hw_cache_event_ids
));
4165 memcpy(hw_cache_extra_regs
, glm_hw_cache_extra_regs
,
4166 sizeof(hw_cache_extra_regs
));
4168 intel_pmu_lbr_init_skl();
4170 x86_pmu
.event_constraints
= intel_slm_event_constraints
;
4171 x86_pmu
.pebs_constraints
= intel_glm_pebs_event_constraints
;
4172 x86_pmu
.extra_regs
= intel_glm_extra_regs
;
4174 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4175 * for precise cycles.
4176 * :pp is identical to :ppp
4178 x86_pmu
.pebs_aliases
= NULL
;
4179 x86_pmu
.pebs_prec_dist
= true;
4180 x86_pmu
.lbr_pt_coexist
= true;
4181 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
4182 x86_pmu
.cpu_events
= glm_events_attrs
;
4183 extra_attr
= slm_format_attr
;
4184 pr_cont("Goldmont events, ");
4188 case INTEL_FAM6_ATOM_GOLDMONT_PLUS
:
4189 memcpy(hw_cache_event_ids
, glp_hw_cache_event_ids
,
4190 sizeof(hw_cache_event_ids
));
4191 memcpy(hw_cache_extra_regs
, glp_hw_cache_extra_regs
,
4192 sizeof(hw_cache_extra_regs
));
4194 intel_pmu_lbr_init_skl();
4196 x86_pmu
.event_constraints
= intel_slm_event_constraints
;
4197 x86_pmu
.pebs_constraints
= intel_glp_pebs_event_constraints
;
4198 x86_pmu
.extra_regs
= intel_glm_extra_regs
;
4200 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4201 * for precise cycles.
4203 x86_pmu
.pebs_aliases
= NULL
;
4204 x86_pmu
.pebs_prec_dist
= true;
4205 x86_pmu
.lbr_pt_coexist
= true;
4206 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
4207 x86_pmu
.get_event_constraints
= glp_get_event_constraints
;
4208 x86_pmu
.cpu_events
= glm_events_attrs
;
4209 /* Goldmont Plus has 4-wide pipeline */
4210 event_attr_td_total_slots_scale_glm
.event_str
= "4";
4211 extra_attr
= slm_format_attr
;
4212 pr_cont("Goldmont plus events, ");
4213 name
= "goldmont_plus";
4216 case INTEL_FAM6_WESTMERE
:
4217 case INTEL_FAM6_WESTMERE_EP
:
4218 case INTEL_FAM6_WESTMERE_EX
:
4219 memcpy(hw_cache_event_ids
, westmere_hw_cache_event_ids
,
4220 sizeof(hw_cache_event_ids
));
4221 memcpy(hw_cache_extra_regs
, nehalem_hw_cache_extra_regs
,
4222 sizeof(hw_cache_extra_regs
));
4224 intel_pmu_lbr_init_nhm();
4226 x86_pmu
.event_constraints
= intel_westmere_event_constraints
;
4227 x86_pmu
.enable_all
= intel_pmu_nhm_enable_all
;
4228 x86_pmu
.pebs_constraints
= intel_westmere_pebs_event_constraints
;
4229 x86_pmu
.extra_regs
= intel_westmere_extra_regs
;
4230 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
4232 x86_pmu
.cpu_events
= nhm_events_attrs
;
4234 /* UOPS_ISSUED.STALLED_CYCLES */
4235 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
] =
4236 X86_CONFIG(.event
=0x0e, .umask
=0x01, .inv
=1, .cmask
=1);
4237 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
4238 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND
] =
4239 X86_CONFIG(.event
=0xb1, .umask
=0x3f, .inv
=1, .cmask
=1);
4241 intel_pmu_pebs_data_source_nhm();
4242 extra_attr
= nhm_format_attr
;
4243 pr_cont("Westmere events, ");
4247 case INTEL_FAM6_SANDYBRIDGE
:
4248 case INTEL_FAM6_SANDYBRIDGE_X
:
4249 x86_add_quirk(intel_sandybridge_quirk
);
4250 x86_add_quirk(intel_ht_bug
);
4251 memcpy(hw_cache_event_ids
, snb_hw_cache_event_ids
,
4252 sizeof(hw_cache_event_ids
));
4253 memcpy(hw_cache_extra_regs
, snb_hw_cache_extra_regs
,
4254 sizeof(hw_cache_extra_regs
));
4256 intel_pmu_lbr_init_snb();
4258 x86_pmu
.event_constraints
= intel_snb_event_constraints
;
4259 x86_pmu
.pebs_constraints
= intel_snb_pebs_event_constraints
;
4260 x86_pmu
.pebs_aliases
= intel_pebs_aliases_snb
;
4261 if (boot_cpu_data
.x86_model
== INTEL_FAM6_SANDYBRIDGE_X
)
4262 x86_pmu
.extra_regs
= intel_snbep_extra_regs
;
4264 x86_pmu
.extra_regs
= intel_snb_extra_regs
;
4267 /* all extra regs are per-cpu when HT is on */
4268 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
4269 x86_pmu
.flags
|= PMU_FL_NO_HT_SHARING
;
4271 x86_pmu
.cpu_events
= snb_events_attrs
;
4273 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
4274 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
] =
4275 X86_CONFIG(.event
=0x0e, .umask
=0x01, .inv
=1, .cmask
=1);
4276 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
4277 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND
] =
4278 X86_CONFIG(.event
=0xb1, .umask
=0x01, .inv
=1, .cmask
=1);
4280 extra_attr
= nhm_format_attr
;
4282 pr_cont("SandyBridge events, ");
4283 name
= "sandybridge";
4286 case INTEL_FAM6_IVYBRIDGE
:
4287 case INTEL_FAM6_IVYBRIDGE_X
:
4288 x86_add_quirk(intel_ht_bug
);
4289 memcpy(hw_cache_event_ids
, snb_hw_cache_event_ids
,
4290 sizeof(hw_cache_event_ids
));
4291 /* dTLB-load-misses on IVB is different than SNB */
4292 hw_cache_event_ids
[C(DTLB
)][C(OP_READ
)][C(RESULT_MISS
)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
4294 memcpy(hw_cache_extra_regs
, snb_hw_cache_extra_regs
,
4295 sizeof(hw_cache_extra_regs
));
4297 intel_pmu_lbr_init_snb();
4299 x86_pmu
.event_constraints
= intel_ivb_event_constraints
;
4300 x86_pmu
.pebs_constraints
= intel_ivb_pebs_event_constraints
;
4301 x86_pmu
.pebs_aliases
= intel_pebs_aliases_ivb
;
4302 x86_pmu
.pebs_prec_dist
= true;
4303 if (boot_cpu_data
.x86_model
== INTEL_FAM6_IVYBRIDGE_X
)
4304 x86_pmu
.extra_regs
= intel_snbep_extra_regs
;
4306 x86_pmu
.extra_regs
= intel_snb_extra_regs
;
4307 /* all extra regs are per-cpu when HT is on */
4308 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
4309 x86_pmu
.flags
|= PMU_FL_NO_HT_SHARING
;
4311 x86_pmu
.cpu_events
= snb_events_attrs
;
4313 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
4314 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
] =
4315 X86_CONFIG(.event
=0x0e, .umask
=0x01, .inv
=1, .cmask
=1);
4317 extra_attr
= nhm_format_attr
;
4319 pr_cont("IvyBridge events, ");
4324 case INTEL_FAM6_HASWELL_CORE
:
4325 case INTEL_FAM6_HASWELL_X
:
4326 case INTEL_FAM6_HASWELL_ULT
:
4327 case INTEL_FAM6_HASWELL_GT3E
:
4328 x86_add_quirk(intel_ht_bug
);
4329 x86_pmu
.late_ack
= true;
4330 memcpy(hw_cache_event_ids
, hsw_hw_cache_event_ids
, sizeof(hw_cache_event_ids
));
4331 memcpy(hw_cache_extra_regs
, hsw_hw_cache_extra_regs
, sizeof(hw_cache_extra_regs
));
4333 intel_pmu_lbr_init_hsw();
4335 x86_pmu
.event_constraints
= intel_hsw_event_constraints
;
4336 x86_pmu
.pebs_constraints
= intel_hsw_pebs_event_constraints
;
4337 x86_pmu
.extra_regs
= intel_snbep_extra_regs
;
4338 x86_pmu
.pebs_aliases
= intel_pebs_aliases_ivb
;
4339 x86_pmu
.pebs_prec_dist
= true;
4340 /* all extra regs are per-cpu when HT is on */
4341 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
4342 x86_pmu
.flags
|= PMU_FL_NO_HT_SHARING
;
4344 x86_pmu
.hw_config
= hsw_hw_config
;
4345 x86_pmu
.get_event_constraints
= hsw_get_event_constraints
;
4346 x86_pmu
.cpu_events
= get_hsw_events_attrs();
4347 x86_pmu
.lbr_double_abort
= true;
4348 extra_attr
= boot_cpu_has(X86_FEATURE_RTM
) ?
4349 hsw_format_attr
: nhm_format_attr
;
4350 pr_cont("Haswell events, ");
4354 case INTEL_FAM6_BROADWELL_CORE
:
4355 case INTEL_FAM6_BROADWELL_XEON_D
:
4356 case INTEL_FAM6_BROADWELL_GT3E
:
4357 case INTEL_FAM6_BROADWELL_X
:
4358 x86_pmu
.late_ack
= true;
4359 memcpy(hw_cache_event_ids
, hsw_hw_cache_event_ids
, sizeof(hw_cache_event_ids
));
4360 memcpy(hw_cache_extra_regs
, hsw_hw_cache_extra_regs
, sizeof(hw_cache_extra_regs
));
4362 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
4363 hw_cache_extra_regs
[C(LL
)][C(OP_READ
)][C(RESULT_MISS
)] = HSW_DEMAND_READ
|
4364 BDW_L3_MISS
|HSW_SNOOP_DRAM
;
4365 hw_cache_extra_regs
[C(LL
)][C(OP_WRITE
)][C(RESULT_MISS
)] = HSW_DEMAND_WRITE
|BDW_L3_MISS
|
4367 hw_cache_extra_regs
[C(NODE
)][C(OP_READ
)][C(RESULT_ACCESS
)] = HSW_DEMAND_READ
|
4368 BDW_L3_MISS_LOCAL
|HSW_SNOOP_DRAM
;
4369 hw_cache_extra_regs
[C(NODE
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = HSW_DEMAND_WRITE
|
4370 BDW_L3_MISS_LOCAL
|HSW_SNOOP_DRAM
;
4372 intel_pmu_lbr_init_hsw();
4374 x86_pmu
.event_constraints
= intel_bdw_event_constraints
;
4375 x86_pmu
.pebs_constraints
= intel_bdw_pebs_event_constraints
;
4376 x86_pmu
.extra_regs
= intel_snbep_extra_regs
;
4377 x86_pmu
.pebs_aliases
= intel_pebs_aliases_ivb
;
4378 x86_pmu
.pebs_prec_dist
= true;
4379 /* all extra regs are per-cpu when HT is on */
4380 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
4381 x86_pmu
.flags
|= PMU_FL_NO_HT_SHARING
;
4383 x86_pmu
.hw_config
= hsw_hw_config
;
4384 x86_pmu
.get_event_constraints
= hsw_get_event_constraints
;
4385 x86_pmu
.cpu_events
= get_hsw_events_attrs();
4386 x86_pmu
.limit_period
= bdw_limit_period
;
4387 extra_attr
= boot_cpu_has(X86_FEATURE_RTM
) ?
4388 hsw_format_attr
: nhm_format_attr
;
4389 pr_cont("Broadwell events, ");
4393 case INTEL_FAM6_XEON_PHI_KNL
:
4394 case INTEL_FAM6_XEON_PHI_KNM
:
4395 memcpy(hw_cache_event_ids
,
4396 slm_hw_cache_event_ids
, sizeof(hw_cache_event_ids
));
4397 memcpy(hw_cache_extra_regs
,
4398 knl_hw_cache_extra_regs
, sizeof(hw_cache_extra_regs
));
4399 intel_pmu_lbr_init_knl();
4401 x86_pmu
.event_constraints
= intel_slm_event_constraints
;
4402 x86_pmu
.pebs_constraints
= intel_slm_pebs_event_constraints
;
4403 x86_pmu
.extra_regs
= intel_knl_extra_regs
;
4405 /* all extra regs are per-cpu when HT is on */
4406 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
4407 x86_pmu
.flags
|= PMU_FL_NO_HT_SHARING
;
4408 extra_attr
= slm_format_attr
;
4409 pr_cont("Knights Landing/Mill events, ");
4410 name
= "knights-landing";
4413 case INTEL_FAM6_SKYLAKE_MOBILE
:
4414 case INTEL_FAM6_SKYLAKE_DESKTOP
:
4415 case INTEL_FAM6_SKYLAKE_X
:
4416 case INTEL_FAM6_KABYLAKE_MOBILE
:
4417 case INTEL_FAM6_KABYLAKE_DESKTOP
:
4418 x86_pmu
.late_ack
= true;
4419 memcpy(hw_cache_event_ids
, skl_hw_cache_event_ids
, sizeof(hw_cache_event_ids
));
4420 memcpy(hw_cache_extra_regs
, skl_hw_cache_extra_regs
, sizeof(hw_cache_extra_regs
));
4421 intel_pmu_lbr_init_skl();
4423 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
4424 event_attr_td_recovery_bubbles
.event_str_noht
=
4425 "event=0xd,umask=0x1,cmask=1";
4426 event_attr_td_recovery_bubbles
.event_str_ht
=
4427 "event=0xd,umask=0x1,cmask=1,any=1";
4429 x86_pmu
.event_constraints
= intel_skl_event_constraints
;
4430 x86_pmu
.pebs_constraints
= intel_skl_pebs_event_constraints
;
4431 x86_pmu
.extra_regs
= intel_skl_extra_regs
;
4432 x86_pmu
.pebs_aliases
= intel_pebs_aliases_skl
;
4433 x86_pmu
.pebs_prec_dist
= true;
4434 /* all extra regs are per-cpu when HT is on */
4435 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
4436 x86_pmu
.flags
|= PMU_FL_NO_HT_SHARING
;
4438 x86_pmu
.hw_config
= hsw_hw_config
;
4439 x86_pmu
.get_event_constraints
= hsw_get_event_constraints
;
4440 extra_attr
= boot_cpu_has(X86_FEATURE_RTM
) ?
4441 hsw_format_attr
: nhm_format_attr
;
4442 extra_attr
= merge_attr(extra_attr
, skl_format_attr
);
4443 to_free
= extra_attr
;
4444 x86_pmu
.cpu_events
= get_hsw_events_attrs();
4445 intel_pmu_pebs_data_source_skl(
4446 boot_cpu_data
.x86_model
== INTEL_FAM6_SKYLAKE_X
);
4448 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT
)) {
4449 x86_pmu
.flags
|= PMU_FL_TFA
;
4450 x86_pmu
.get_event_constraints
= tfa_get_event_constraints
;
4451 x86_pmu
.enable_all
= intel_tfa_pmu_enable_all
;
4452 x86_pmu
.commit_scheduling
= intel_tfa_commit_scheduling
;
4453 intel_pmu_attrs
[1] = &dev_attr_allow_tsx_force_abort
.attr
.attr
;
4456 pr_cont("Skylake events, ");
4461 switch (x86_pmu
.version
) {
4463 x86_pmu
.event_constraints
= intel_v1_event_constraints
;
4464 pr_cont("generic architected perfmon v1, ");
4465 name
= "generic_arch_v1";
4469 * default constraints for v2 and up
4471 x86_pmu
.event_constraints
= intel_gen_event_constraints
;
4472 pr_cont("generic architected perfmon, ");
4473 name
= "generic_arch_v2+";
4478 snprintf(pmu_name_str
, sizeof pmu_name_str
, "%s", name
);
4480 if (version
>= 2 && extra_attr
) {
4481 x86_pmu
.format_attrs
= merge_attr(intel_arch3_formats_attr
,
4483 WARN_ON(!x86_pmu
.format_attrs
);
4486 if (x86_pmu
.num_counters
> INTEL_PMC_MAX_GENERIC
) {
4487 WARN(1, KERN_ERR
"hw perf events %d > max(%d), clipping!",
4488 x86_pmu
.num_counters
, INTEL_PMC_MAX_GENERIC
);
4489 x86_pmu
.num_counters
= INTEL_PMC_MAX_GENERIC
;
4491 x86_pmu
.intel_ctrl
= (1ULL << x86_pmu
.num_counters
) - 1;
4493 if (x86_pmu
.num_counters_fixed
> INTEL_PMC_MAX_FIXED
) {
4494 WARN(1, KERN_ERR
"hw perf events fixed %d > max(%d), clipping!",
4495 x86_pmu
.num_counters_fixed
, INTEL_PMC_MAX_FIXED
);
4496 x86_pmu
.num_counters_fixed
= INTEL_PMC_MAX_FIXED
;
4499 x86_pmu
.intel_ctrl
|=
4500 ((1LL << x86_pmu
.num_counters_fixed
)-1) << INTEL_PMC_IDX_FIXED
;
4502 if (x86_pmu
.event_constraints
) {
4504 * event on fixed counter2 (REF_CYCLES) only works on this
4505 * counter, so do not extend mask to generic counters
4507 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
4508 if (c
->cmask
== FIXED_EVENT_FLAGS
4509 && c
->idxmsk64
!= INTEL_PMC_MSK_FIXED_REF_CYCLES
) {
4510 c
->idxmsk64
|= (1ULL << x86_pmu
.num_counters
) - 1;
4513 ~(~0ULL << (INTEL_PMC_IDX_FIXED
+ x86_pmu
.num_counters_fixed
));
4514 c
->weight
= hweight64(c
->idxmsk64
);
4519 * Access LBR MSR may cause #GP under certain circumstances.
4520 * E.g. KVM doesn't support LBR MSR
4521 * Check all LBT MSR here.
4522 * Disable LBR access if any LBR MSRs can not be accessed.
4524 if (x86_pmu
.lbr_nr
&& !check_msr(x86_pmu
.lbr_tos
, 0x3UL
))
4526 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
4527 if (!(check_msr(x86_pmu
.lbr_from
+ i
, 0xffffUL
) &&
4528 check_msr(x86_pmu
.lbr_to
+ i
, 0xffffUL
)))
4532 x86_pmu
.caps_attrs
= intel_pmu_caps_attrs
;
4534 if (x86_pmu
.lbr_nr
) {
4535 x86_pmu
.caps_attrs
= merge_attr(x86_pmu
.caps_attrs
, lbr_attrs
);
4536 pr_cont("%d-deep LBR, ", x86_pmu
.lbr_nr
);
4540 * Access extra MSR may cause #GP under certain circumstances.
4541 * E.g. KVM doesn't support offcore event
4542 * Check all extra_regs here.
4544 if (x86_pmu
.extra_regs
) {
4545 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
4546 er
->extra_msr_access
= check_msr(er
->msr
, 0x11UL
);
4547 /* Disable LBR select mapping */
4548 if ((er
->idx
== EXTRA_REG_LBR
) && !er
->extra_msr_access
)
4549 x86_pmu
.lbr_sel_map
= NULL
;
4553 /* Support full width counters using alternative MSR range */
4554 if (x86_pmu
.intel_cap
.full_width_write
) {
4555 x86_pmu
.max_period
= x86_pmu
.cntval_mask
>> 1;
4556 x86_pmu
.perfctr
= MSR_IA32_PMC0
;
4557 pr_cont("full-width counters, ");
4565 * HT bug: phase 2 init
4566 * Called once we have valid topology information to check
4567 * whether or not HT is enabled
4568 * If HT is off, then we disable the workaround
4570 static __init
int fixup_ht_bug(void)
4574 * problem not present on this CPU model, nothing to do
4576 if (!(x86_pmu
.flags
& PMU_FL_EXCL_ENABLED
))
4579 if (topology_max_smt_threads() > 1) {
4580 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
4586 hardlockup_detector_perf_stop();
4588 x86_pmu
.flags
&= ~(PMU_FL_EXCL_CNTRS
| PMU_FL_EXCL_ENABLED
);
4590 x86_pmu
.start_scheduling
= NULL
;
4591 x86_pmu
.commit_scheduling
= NULL
;
4592 x86_pmu
.stop_scheduling
= NULL
;
4594 hardlockup_detector_perf_restart();
4596 for_each_online_cpu(c
)
4597 free_excl_cntrs(&per_cpu(cpu_hw_events
, c
));
4600 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
4603 subsys_initcall(fixup_ht_bug
)