arch/x86/include/asm/microcode.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_MICROCODE_H
   3 #define _ASM_X86_MICROCODE_H
   4
   5 #include <asm/cpu.h>
   6 #include <linux/earlycpio.h>
   7 #include <linux/initrd.h>
   8
   9 #define native_rdmsr(msr, val1, val2)                   \
  10 do {                                                    \
  11         u64 __val = __rdmsr((msr));                     \
  12         (void)((val1) = (u32)__val);                    \
  13         (void)((val2) = (u32)(__val >> 32));            \
  14 } while (0)
  15
  16 #define native_wrmsr(msr, low, high)                    \
  17         __wrmsr(msr, low, high)
  18
  19 #define native_wrmsrl(msr, val)                         \
  20         __wrmsr((msr), (u32)((u64)(val)),               \
  21                        (u32)((u64)(val) >> 32))
  22
  23 struct ucode_patch {
  24         struct list_head plist;
  25         void *data;             /* Intel uses only this one */
  26         u32 patch_id;
  27         u16 equiv_cpu;
  28 };
  29
  30 extern struct list_head microcode_cache;
  31
  32 struct cpu_signature {
  33         unsigned int sig;
  34         unsigned int pf;
  35         unsigned int rev;
  36 };
  37
  38 struct device;
  39
  40 enum ucode_state {
  41         UCODE_OK        = 0,
  42         UCODE_UPDATED,
  43         UCODE_NFOUND,
  44         UCODE_ERROR,
  45 };
  46
  47 struct microcode_ops {
  48         enum ucode_state (*request_microcode_user) (int cpu,
  49                                 const void __user *buf, size_t size);
  50
  51         enum ucode_state (*request_microcode_fw) (int cpu, struct device *,
  52                                                   bool refresh_fw);
  53
  54         void (*microcode_fini_cpu) (int cpu);
  55
  56         /*
  57          * The generic 'microcode_core' part guarantees that
  58          * the callbacks below run on a target cpu when they
  59          * are being called.
  60          * See also the "Synchronization" section in microcode_core.c.
  61          */
  62         enum ucode_state (*apply_microcode) (int cpu);
  63         int (*collect_cpu_info) (int cpu, struct cpu_signature *csig);
  64 };
  65
  66 struct ucode_cpu_info {
  67         struct cpu_signature    cpu_sig;
  68         int                     valid;
  69         void                    *mc;
  70 };
  71 extern struct ucode_cpu_info ucode_cpu_info[];
  72 struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa);
  73
  74 #ifdef CONFIG_MICROCODE_INTEL
  75 extern struct microcode_ops * __init init_intel_microcode(void);
  76 #else
  77 static inline struct microcode_ops * __init init_intel_microcode(void)
  78 {
  79         return NULL;
  80 }
  81 #endif /* CONFIG_MICROCODE_INTEL */
  82
  83 #ifdef CONFIG_MICROCODE_AMD
  84 extern struct microcode_ops * __init init_amd_microcode(void);
  85 extern void __exit exit_amd_microcode(void);
  86 #else
  87 static inline struct microcode_ops * __init init_amd_microcode(void)
  88 {
  89         return NULL;
  90 }
  91 static inline void __exit exit_amd_microcode(void) {}
  92 #endif
  93
  94 #define MAX_UCODE_COUNT 128
  95
  96 #define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
  97 #define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u')
  98 #define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I')
  99 #define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l')
 100 #define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
 101 #define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
 102 #define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')
 103
 104 #define CPUID_IS(a, b, c, ebx, ecx, edx)        \
 105                 (!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c))))
 106
 107 /*
 108  * In early loading microcode phase on BSP, boot_cpu_data is not set up yet.
 109  * x86_cpuid_vendor() gets vendor id for BSP.
 110  *
 111  * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify
 112  * coding, we still use x86_cpuid_vendor() to get vendor id for AP.
 113  *
 114  * x86_cpuid_vendor() gets vendor information directly from CPUID.
 115  */
 116 static inline int x86_cpuid_vendor(void)
 117 {
 118         u32 eax = 0x00000000;
 119         u32 ebx, ecx = 0, edx;
 120
 121         native_cpuid(&eax, &ebx, &ecx, &edx);
 122
 123         if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx))
 124                 return X86_VENDOR_INTEL;
 125
 126         if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx))
 127                 return X86_VENDOR_AMD;
 128
 129         return X86_VENDOR_UNKNOWN;
 130 }
 131
 132 static inline unsigned int x86_cpuid_family(void)
 133 {
 134         u32 eax = 0x00000001;
 135         u32 ebx, ecx = 0, edx;
 136
 137         native_cpuid(&eax, &ebx, &ecx, &edx);
 138
 139         return x86_family(eax);
 140 }
 141
 142 #ifdef CONFIG_MICROCODE
 143 int __init microcode_init(void);
 144 extern void __init load_ucode_bsp(void);
 145 extern void load_ucode_ap(void);
 146 void reload_early_microcode(void);
 147 extern bool get_builtin_firmware(struct cpio_data *cd, const char *name);
 148 extern bool initrd_gone;
 149 #else
 150 static inline int __init microcode_init(void)                   { return 0; };
 151 static inline void __init load_ucode_bsp(void)                  { }
 152 static inline void load_ucode_ap(void)                          { }
 153 static inline void reload_early_microcode(void)                 { }
 154 static inline bool
 155 get_builtin_firmware(struct cpio_data *cd, const char *name)    { return false; }
 156 #endif
 157
 158 #endif /* _ASM_X86_MICROCODE_H */