arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9 struct vm86;
  10
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <uapi/asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeatures.h>
  17 #include <asm/page.h>
  18 #include <asm/pgtable_types.h>
  19 #include <asm/percpu.h>
  20 #include <asm/msr.h>
  21 #include <asm/desc_defs.h>
  22 #include <asm/nops.h>
  23 #include <asm/special_insns.h>
  24 #include <asm/fpu/types.h>
  25
  26 #include <linux/personality.h>
  27 #include <linux/cache.h>
  28 #include <linux/threads.h>
  29 #include <linux/math64.h>
  30 #include <linux/err.h>
  31 #include <linux/irqflags.h>
  32
  33 /*
  34  * We handle most unaligned accesses in hardware.  On the other hand
  35  * unaligned DMA can be quite expensive on some Nehalem processors.
  36  *
  37  * Based on this we disable the IP header alignment in network drivers.
  38  */
  39 #define NET_IP_ALIGN    0
  40
  41 #define HBP_NUM 4
  42 /*
  43  * Default implementation of macro that returns current
  44  * instruction pointer ("program counter").
  45  */
  46 static inline void *current_text_addr(void)
  47 {
  48         void *pc;
  49
  50         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  51
  52         return pc;
  53 }
  54
  55 /*
  56  * These alignment constraints are for performance in the vSMP case,
  57  * but in the task_struct case we must also meet hardware imposed
  58  * alignment requirements of the FPU state:
  59  */
  60 #ifdef CONFIG_X86_VSMP
  61 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  62 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  63 #else
  64 # define ARCH_MIN_TASKALIGN             __alignof__(union fpregs_state)
  65 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  66 #endif
  67
  68 enum tlb_infos {
  69         ENTRIES,
  70         NR_INFO
  71 };
  72
  73 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
  74 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
  75 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
  76 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
  77 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
  78 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
  79 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
  80
  81 /*
  82  *  CPU type and hardware bug flags. Kept separately for each CPU.
  83  *  Members of this structure are referenced in head.S, so think twice
  84  *  before touching them. [mj]
  85  */
  86
  87 struct cpuinfo_x86 {
  88         __u8                    x86;            /* CPU family */
  89         __u8                    x86_vendor;     /* CPU vendor */
  90         __u8                    x86_model;
  91         __u8                    x86_mask;
  92 #ifdef CONFIG_X86_32
  93         char                    wp_works_ok;    /* It doesn't on 386's */
  94
  95         /* Problems on some 486Dx4's and old 386's: */
  96         char                    rfu;
  97         char                    pad0;
  98         char                    pad1;
  99 #else
 100         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
 101         int                     x86_tlbsize;
 102 #endif
 103         __u8                    x86_virt_bits;
 104         __u8                    x86_phys_bits;
 105         /* CPUID returned core id bits: */
 106         __u8                    x86_coreid_bits;
 107         /* Max extended CPUID function supported: */
 108         __u32                   extended_cpuid_level;
 109         /* Maximum supported CPUID level, -1=no CPUID: */
 110         int                     cpuid_level;
 111         __u32                   x86_capability[NCAPINTS + NBUGINTS];
 112         char                    x86_vendor_id[16];
 113         char                    x86_model_id[64];
 114         /* in KB - valid for CPUS which support this call: */
 115         int                     x86_cache_size;
 116         int                     x86_cache_alignment;    /* In bytes */
 117         /* Cache QoS architectural values: */
 118         int                     x86_cache_max_rmid;     /* max index */
 119         int                     x86_cache_occ_scale;    /* scale to bytes */
 120         int                     x86_power;
 121         unsigned long           loops_per_jiffy;
 122         /* cpuid returned max cores value: */
 123         u16                      x86_max_cores;
 124         u16                     apicid;
 125         u16                     initial_apicid;
 126         u16                     x86_clflush_size;
 127         /* number of cores as seen by the OS: */
 128         u16                     booted_cores;
 129         /* Physical processor id: */
 130         u16                     phys_proc_id;
 131         /* Logical processor id: */
 132         u16                     logical_proc_id;
 133         /* Core id: */
 134         u16                     cpu_core_id;
 135         /* Index into per_cpu list: */
 136         u16                     cpu_index;
 137         u32                     microcode;
 138 };
 139
 140 struct cpuid_regs {
 141         u32 eax, ebx, ecx, edx;
 142 };
 143
 144 enum cpuid_regs_idx {
 145         CPUID_EAX = 0,
 146         CPUID_EBX,
 147         CPUID_ECX,
 148         CPUID_EDX,
 149 };
 150
 151 #define X86_VENDOR_INTEL        0
 152 #define X86_VENDOR_CYRIX        1
 153 #define X86_VENDOR_AMD          2
 154 #define X86_VENDOR_UMC          3
 155 #define X86_VENDOR_CENTAUR      5
 156 #define X86_VENDOR_TRANSMETA    7
 157 #define X86_VENDOR_NSC          8
 158 #define X86_VENDOR_NUM          9
 159
 160 #define X86_VENDOR_UNKNOWN      0xff
 161
 162 /*
 163  * capabilities of CPUs
 164  */
 165 extern struct cpuinfo_x86       boot_cpu_data;
 166 extern struct cpuinfo_x86       new_cpu_data;
 167
 168 extern struct tss_struct        doublefault_tss;
 169 extern __u32                    cpu_caps_cleared[NCAPINTS];
 170 extern __u32                    cpu_caps_set[NCAPINTS];
 171
 172 #ifdef CONFIG_SMP
 173 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
 174 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 175 #else
 176 #define cpu_info                boot_cpu_data
 177 #define cpu_data(cpu)           boot_cpu_data
 178 #endif
 179
 180 extern const struct seq_operations cpuinfo_op;
 181
 182 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 183
 184 extern void cpu_detect(struct cpuinfo_x86 *c);
 185
 186 extern void early_cpu_init(void);
 187 extern void identify_boot_cpu(void);
 188 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 189 extern void print_cpu_info(struct cpuinfo_x86 *);
 190 void print_cpu_msr(struct cpuinfo_x86 *);
 191 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 192 extern u32 get_scattered_cpuid_leaf(unsigned int level,
 193                                     unsigned int sub_leaf,
 194                                     enum cpuid_regs_idx reg);
 195 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 196 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
 197
 198 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 199 extern void detect_ht(struct cpuinfo_x86 *c);
 200
 201 #ifdef CONFIG_X86_32
 202 extern int have_cpuid_p(void);
 203 #else
 204 static inline int have_cpuid_p(void)
 205 {
 206         return 1;
 207 }
 208 #endif
 209 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 210                                 unsigned int *ecx, unsigned int *edx)
 211 {
 212         /* ecx is often an input as well as an output. */
 213         asm volatile("cpuid"
 214             : "=a" (*eax),
 215               "=b" (*ebx),
 216               "=c" (*ecx),
 217               "=d" (*edx)
 218             : "0" (*eax), "2" (*ecx)
 219             : "memory");
 220 }
 221
 222 #define native_cpuid_reg(reg)                                   \
 223 static inline unsigned int native_cpuid_##reg(unsigned int op)  \
 224 {                                                               \
 225         unsigned int eax = op, ebx, ecx = 0, edx;               \
 226                                                                 \
 227         native_cpuid(&eax, &ebx, &ecx, &edx);                   \
 228                                                                 \
 229         return reg;                                             \
 230 }
 231
 232 /*
 233  * Native CPUID functions returning a single datum.
 234  */
 235 native_cpuid_reg(eax)
 236 native_cpuid_reg(ebx)
 237 native_cpuid_reg(ecx)
 238 native_cpuid_reg(edx)
 239
 240 static inline void load_cr3(pgd_t *pgdir)
 241 {
 242         write_cr3(__pa(pgdir));
 243 }
 244
 245 #ifdef CONFIG_X86_32
 246 /* This is the TSS defined by the hardware. */
 247 struct x86_hw_tss {
 248         unsigned short          back_link, __blh;
 249         unsigned long           sp0;
 250         unsigned short          ss0, __ss0h;
 251         unsigned long           sp1;
 252
 253         /*
 254          * We don't use ring 1, so ss1 is a convenient scratch space in
 255          * the same cacheline as sp0.  We use ss1 to cache the value in
 256          * MSR_IA32_SYSENTER_CS.  When we context switch
 257          * MSR_IA32_SYSENTER_CS, we first check if the new value being
 258          * written matches ss1, and, if it's not, then we wrmsr the new
 259          * value and update ss1.
 260          *
 261          * The only reason we context switch MSR_IA32_SYSENTER_CS is
 262          * that we set it to zero in vm86 tasks to avoid corrupting the
 263          * stack if we were to go through the sysenter path from vm86
 264          * mode.
 265          */
 266         unsigned short          ss1;    /* MSR_IA32_SYSENTER_CS */
 267
 268         unsigned short          __ss1h;
 269         unsigned long           sp2;
 270         unsigned short          ss2, __ss2h;
 271         unsigned long           __cr3;
 272         unsigned long           ip;
 273         unsigned long           flags;
 274         unsigned long           ax;
 275         unsigned long           cx;
 276         unsigned long           dx;
 277         unsigned long           bx;
 278         unsigned long           sp;
 279         unsigned long           bp;
 280         unsigned long           si;
 281         unsigned long           di;
 282         unsigned short          es, __esh;
 283         unsigned short          cs, __csh;
 284         unsigned short          ss, __ssh;
 285         unsigned short          ds, __dsh;
 286         unsigned short          fs, __fsh;
 287         unsigned short          gs, __gsh;
 288         unsigned short          ldt, __ldth;
 289         unsigned short          trace;
 290         unsigned short          io_bitmap_base;
 291
 292 } __attribute__((packed));
 293 #else
 294 struct x86_hw_tss {
 295         u32                     reserved1;
 296         u64                     sp0;
 297         u64                     sp1;
 298         u64                     sp2;
 299         u64                     reserved2;
 300         u64                     ist[7];
 301         u32                     reserved3;
 302         u32                     reserved4;
 303         u16                     reserved5;
 304         u16                     io_bitmap_base;
 305
 306 } __attribute__((packed)) ____cacheline_aligned;
 307 #endif
 308
 309 /*
 310  * IO-bitmap sizes:
 311  */
 312 #define IO_BITMAP_BITS                  65536
 313 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 314 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 315 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 316 #define INVALID_IO_BITMAP_OFFSET        0x8000
 317
 318 struct tss_struct {
 319         /*
 320          * The hardware state:
 321          */
 322         struct x86_hw_tss       x86_tss;
 323
 324         /*
 325          * The extra 1 is there because the CPU will access an
 326          * additional byte beyond the end of the IO permission
 327          * bitmap. The extra byte must be all 1 bits, and must
 328          * be within the limit.
 329          */
 330         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 331
 332 #ifdef CONFIG_X86_32
 333         /*
 334          * Space for the temporary SYSENTER stack.
 335          */
 336         unsigned long           SYSENTER_stack_canary;
 337         unsigned long           SYSENTER_stack[64];
 338 #endif
 339
 340 } ____cacheline_aligned;
 341
 342 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss);
 343
 344 #ifdef CONFIG_X86_32
 345 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
 346 #endif
 347
 348 /*
 349  * Save the original ist values for checking stack pointers during debugging
 350  */
 351 struct orig_ist {
 352         unsigned long           ist[7];
 353 };
 354
 355 #ifdef CONFIG_X86_64
 356 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 357
 358 union irq_stack_union {
 359         char irq_stack[IRQ_STACK_SIZE];
 360         /*
 361          * GCC hardcodes the stack canary as %gs:40.  Since the
 362          * irq_stack is the object at %gs:0, we reserve the bottom
 363          * 48 bytes of the irq stack for the canary.
 364          */
 365         struct {
 366                 char gs_base[40];
 367                 unsigned long stack_canary;
 368         };
 369 };
 370
 371 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
 372 DECLARE_INIT_PER_CPU(irq_stack_union);
 373
 374 DECLARE_PER_CPU(char *, irq_stack_ptr);
 375 DECLARE_PER_CPU(unsigned int, irq_count);
 376 extern asmlinkage void ignore_sysret(void);
 377 #else   /* X86_64 */
 378 #ifdef CONFIG_CC_STACKPROTECTOR
 379 /*
 380  * Make sure stack canary segment base is cached-aligned:
 381  *   "For Intel Atom processors, avoid non zero segment base address
 382  *    that is not aligned to cache line boundary at all cost."
 383  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 384  */
 385 struct stack_canary {
 386         char __pad[20];         /* canary at %gs:20 */
 387         unsigned long canary;
 388 };
 389 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 390 #endif
 391 /*
 392  * per-CPU IRQ handling stacks
 393  */
 394 struct irq_stack {
 395         u32                     stack[THREAD_SIZE/sizeof(u32)];
 396 } __aligned(THREAD_SIZE);
 397
 398 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
 399 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
 400 #endif  /* X86_64 */
 401
 402 extern unsigned int fpu_kernel_xstate_size;
 403 extern unsigned int fpu_user_xstate_size;
 404
 405 struct perf_event;
 406
 407 typedef struct {
 408         unsigned long           seg;
 409 } mm_segment_t;
 410
 411 struct thread_struct {
 412         /* Cached TLS descriptors: */
 413         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 414         unsigned long           sp0;
 415         unsigned long           sp;
 416 #ifdef CONFIG_X86_32
 417         unsigned long           sysenter_cs;
 418 #else
 419         unsigned short          es;
 420         unsigned short          ds;
 421         unsigned short          fsindex;
 422         unsigned short          gsindex;
 423 #endif
 424
 425         u32                     status;         /* thread synchronous flags */
 426
 427 #ifdef CONFIG_X86_64
 428         unsigned long           fsbase;
 429         unsigned long           gsbase;
 430 #else
 431         /*
 432          * XXX: this could presumably be unsigned short.  Alternatively,
 433          * 32-bit kernels could be taught to use fsindex instead.
 434          */
 435         unsigned long fs;
 436         unsigned long gs;
 437 #endif
 438
 439         /* Save middle states of ptrace breakpoints */
 440         struct perf_event       *ptrace_bps[HBP_NUM];
 441         /* Debug status used for traps, single steps, etc... */
 442         unsigned long           debugreg6;
 443         /* Keep track of the exact dr7 value set by the user */
 444         unsigned long           ptrace_dr7;
 445         /* Fault info: */
 446         unsigned long           cr2;
 447         unsigned long           trap_nr;
 448         unsigned long           error_code;
 449 #ifdef CONFIG_VM86
 450         /* Virtual 86 mode info */
 451         struct vm86             *vm86;
 452 #endif
 453         /* IO permissions: */
 454         unsigned long           *io_bitmap_ptr;
 455         unsigned long           iopl;
 456         /* Max allowed port in the bitmap, in bytes: */
 457         unsigned                io_bitmap_max;
 458
 459         mm_segment_t            addr_limit;
 460
 461         unsigned int            sig_on_uaccess_err:1;
 462         unsigned int            uaccess_err:1;  /* uaccess failed */
 463
 464         /* Floating point and extended processor state */
 465         struct fpu              fpu;
 466         /*
 467          * WARNING: 'fpu' is dynamically-sized.  It *MUST* be at
 468          * the end.
 469          */
 470 };
 471
 472 /*
 473  * Thread-synchronous status.
 474  *
 475  * This is different from the flags in that nobody else
 476  * ever touches our thread-synchronous status, so we don't
 477  * have to worry about atomic accesses.
 478  */
 479 #define TS_COMPAT               0x0002  /* 32bit syscall active (64BIT)*/
 480
 481 /*
 482  * Set IOPL bits in EFLAGS from given mask
 483  */
 484 static inline void native_set_iopl_mask(unsigned mask)
 485 {
 486 #ifdef CONFIG_X86_32
 487         unsigned int reg;
 488
 489         asm volatile ("pushfl;"
 490                       "popl %0;"
 491                       "andl %1, %0;"
 492                       "orl %2, %0;"
 493                       "pushl %0;"
 494                       "popfl"
 495                       : "=&r" (reg)
 496                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 497 #endif
 498 }
 499
 500 static inline void
 501 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 502 {
 503         tss->x86_tss.sp0 = thread->sp0;
 504 #ifdef CONFIG_X86_32
 505         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 506         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 507                 tss->x86_tss.ss1 = thread->sysenter_cs;
 508                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 509         }
 510 #endif
 511 }
 512
 513 static inline void native_swapgs(void)
 514 {
 515 #ifdef CONFIG_X86_64
 516         asm volatile("swapgs" ::: "memory");
 517 #endif
 518 }
 519
 520 static inline unsigned long current_top_of_stack(void)
 521 {
 522 #ifdef CONFIG_X86_64
 523         return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
 524 #else
 525         /* sp0 on x86_32 is special in and around vm86 mode. */
 526         return this_cpu_read_stable(cpu_current_top_of_stack);
 527 #endif
 528 }
 529
 530 #ifdef CONFIG_PARAVIRT
 531 #include <asm/paravirt.h>
 532 #else
 533 #define __cpuid                 native_cpuid
 534
 535 static inline void load_sp0(struct tss_struct *tss,
 536                             struct thread_struct *thread)
 537 {
 538         native_load_sp0(tss, thread);
 539 }
 540
 541 #define set_iopl_mask native_set_iopl_mask
 542 #endif /* CONFIG_PARAVIRT */
 543
 544 /* Free all resources held by a thread. */
 545 extern void release_thread(struct task_struct *);
 546
 547 unsigned long get_wchan(struct task_struct *p);
 548
 549 /*
 550  * Generic CPUID function
 551  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 552  * resulting in stale register contents being returned.
 553  */
 554 static inline void cpuid(unsigned int op,
 555                          unsigned int *eax, unsigned int *ebx,
 556                          unsigned int *ecx, unsigned int *edx)
 557 {
 558         *eax = op;
 559         *ecx = 0;
 560         __cpuid(eax, ebx, ecx, edx);
 561 }
 562
 563 /* Some CPUID calls want 'count' to be placed in ecx */
 564 static inline void cpuid_count(unsigned int op, int count,
 565                                unsigned int *eax, unsigned int *ebx,
 566                                unsigned int *ecx, unsigned int *edx)
 567 {
 568         *eax = op;
 569         *ecx = count;
 570         __cpuid(eax, ebx, ecx, edx);
 571 }
 572
 573 /*
 574  * CPUID functions returning a single datum
 575  */
 576 static inline unsigned int cpuid_eax(unsigned int op)
 577 {
 578         unsigned int eax, ebx, ecx, edx;
 579
 580         cpuid(op, &eax, &ebx, &ecx, &edx);
 581
 582         return eax;
 583 }
 584
 585 static inline unsigned int cpuid_ebx(unsigned int op)
 586 {
 587         unsigned int eax, ebx, ecx, edx;
 588
 589         cpuid(op, &eax, &ebx, &ecx, &edx);
 590
 591         return ebx;
 592 }
 593
 594 static inline unsigned int cpuid_ecx(unsigned int op)
 595 {
 596         unsigned int eax, ebx, ecx, edx;
 597
 598         cpuid(op, &eax, &ebx, &ecx, &edx);
 599
 600         return ecx;
 601 }
 602
 603 static inline unsigned int cpuid_edx(unsigned int op)
 604 {
 605         unsigned int eax, ebx, ecx, edx;
 606
 607         cpuid(op, &eax, &ebx, &ecx, &edx);
 608
 609         return edx;
 610 }
 611
 612 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 613 static __always_inline void rep_nop(void)
 614 {
 615         asm volatile("rep; nop" ::: "memory");
 616 }
 617
 618 static __always_inline void cpu_relax(void)
 619 {
 620         rep_nop();
 621 }
 622
 623 /*
 624  * This function forces the icache and prefetched instruction stream to
 625  * catch up with reality in two very specific cases:
 626  *
 627  *  a) Text was modified using one virtual address and is about to be executed
 628  *     from the same physical page at a different virtual address.
 629  *
 630  *  b) Text was modified on a different CPU, may subsequently be
 631  *     executed on this CPU, and you want to make sure the new version
 632  *     gets executed.  This generally means you're calling this in a IPI.
 633  *
 634  * If you're calling this for a different reason, you're probably doing
 635  * it wrong.
 636  */
 637 static inline void sync_core(void)
 638 {
 639         /*
 640          * There are quite a few ways to do this.  IRET-to-self is nice
 641          * because it works on every CPU, at any CPL (so it's compatible
 642          * with paravirtualization), and it never exits to a hypervisor.
 643          * The only down sides are that it's a bit slow (it seems to be
 644          * a bit more than 2x slower than the fastest options) and that
 645          * it unmasks NMIs.  The "push %cs" is needed because, in
 646          * paravirtual environments, __KERNEL_CS may not be a valid CS
 647          * value when we do IRET directly.
 648          *
 649          * In case NMI unmasking or performance ever becomes a problem,
 650          * the next best option appears to be MOV-to-CR2 and an
 651          * unconditional jump.  That sequence also works on all CPUs,
 652          * but it will fault at CPL3 (i.e. Xen PV and lguest).
 653          *
 654          * CPUID is the conventional way, but it's nasty: it doesn't
 655          * exist on some 486-like CPUs, and it usually exits to a
 656          * hypervisor.
 657          *
 658          * Like all of Linux's memory ordering operations, this is a
 659          * compiler barrier as well.
 660          */
 661         register void *__sp asm(_ASM_SP);
 662
 663 #ifdef CONFIG_X86_32
 664         asm volatile (
 665                 "pushfl\n\t"
 666                 "pushl %%cs\n\t"
 667                 "pushl $1f\n\t"
 668                 "iret\n\t"
 669                 "1:"
 670                 : "+r" (__sp) : : "memory");
 671 #else
 672         unsigned int tmp;
 673
 674         asm volatile (
 675                 "mov %%ss, %0\n\t"
 676                 "pushq %q0\n\t"
 677                 "pushq %%rsp\n\t"
 678                 "addq $8, (%%rsp)\n\t"
 679                 "pushfq\n\t"
 680                 "mov %%cs, %0\n\t"
 681                 "pushq %q0\n\t"
 682                 "pushq $1f\n\t"
 683                 "iretq\n\t"
 684                 "1:"
 685                 : "=&r" (tmp), "+r" (__sp) : : "cc", "memory");
 686 #endif
 687 }
 688
 689 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 690 extern void amd_e400_c1e_apic_setup(void);
 691
 692 extern unsigned long            boot_option_idle_override;
 693
 694 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
 695                          IDLE_POLL};
 696
 697 extern void enable_sep_cpu(void);
 698 extern int sysenter_setup(void);
 699
 700 extern void early_trap_init(void);
 701 void early_trap_pf_init(void);
 702
 703 /* Defined in head.S */
 704 extern struct desc_ptr          early_gdt_descr;
 705
 706 extern void cpu_set_gdt(int);
 707 extern void switch_to_new_gdt(int);
 708 extern void load_percpu_segment(int);
 709 extern void cpu_init(void);
 710
 711 static inline unsigned long get_debugctlmsr(void)
 712 {
 713         unsigned long debugctlmsr = 0;
 714
 715 #ifndef CONFIG_X86_DEBUGCTLMSR
 716         if (boot_cpu_data.x86 < 6)
 717                 return 0;
 718 #endif
 719         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 720
 721         return debugctlmsr;
 722 }
 723
 724 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 725 {
 726 #ifndef CONFIG_X86_DEBUGCTLMSR
 727         if (boot_cpu_data.x86 < 6)
 728                 return;
 729 #endif
 730         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 731 }
 732
 733 extern void set_task_blockstep(struct task_struct *task, bool on);
 734
 735 /* Boot loader type from the setup header: */
 736 extern int                      bootloader_type;
 737 extern int                      bootloader_version;
 738
 739 extern char                     ignore_fpu_irq;
 740
 741 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 742 #define ARCH_HAS_PREFETCHW
 743 #define ARCH_HAS_SPINLOCK_PREFETCH
 744
 745 #ifdef CONFIG_X86_32
 746 # define BASE_PREFETCH          ""
 747 # define ARCH_HAS_PREFETCH
 748 #else
 749 # define BASE_PREFETCH          "prefetcht0 %P1"
 750 #endif
 751
 752 /*
 753  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 754  *
 755  * It's not worth to care about 3dnow prefetches for the K6
 756  * because they are microcoded there and very slow.
 757  */
 758 static inline void prefetch(const void *x)
 759 {
 760         alternative_input(BASE_PREFETCH, "prefetchnta %P1",
 761                           X86_FEATURE_XMM,
 762                           "m" (*(const char *)x));
 763 }
 764
 765 /*
 766  * 3dnow prefetch to get an exclusive cache line.
 767  * Useful for spinlocks to avoid one state transition in the
 768  * cache coherency protocol:
 769  */
 770 static inline void prefetchw(const void *x)
 771 {
 772         alternative_input(BASE_PREFETCH, "prefetchw %P1",
 773                           X86_FEATURE_3DNOWPREFETCH,
 774                           "m" (*(const char *)x));
 775 }
 776
 777 static inline void spin_lock_prefetch(const void *x)
 778 {
 779         prefetchw(x);
 780 }
 781
 782 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
 783                            TOP_OF_KERNEL_STACK_PADDING)
 784
 785 #ifdef CONFIG_X86_32
 786 /*
 787  * User space process size: 3GB (default).
 788  */
 789 #define TASK_SIZE               PAGE_OFFSET
 790 #define TASK_SIZE_MAX           TASK_SIZE
 791 #define STACK_TOP               TASK_SIZE
 792 #define STACK_TOP_MAX           STACK_TOP
 793
 794 #define INIT_THREAD  {                                                    \
 795         .sp0                    = TOP_OF_INIT_STACK,                      \
 796         .sysenter_cs            = __KERNEL_CS,                            \
 797         .io_bitmap_ptr          = NULL,                                   \
 798         .addr_limit             = KERNEL_DS,                              \
 799 }
 800
 801 /*
 802  * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack.
 803  * This is necessary to guarantee that the entire "struct pt_regs"
 804  * is accessible even if the CPU haven't stored the SS/ESP registers
 805  * on the stack (interrupt gate does not save these registers
 806  * when switching to the same priv ring).
 807  * Therefore beware: accessing the ss/esp fields of the
 808  * "struct pt_regs" is possible, but they may contain the
 809  * completely wrong values.
 810  */
 811 #define task_pt_regs(task) \
 812 ({                                                                      \
 813         unsigned long __ptr = (unsigned long)task_stack_page(task);     \
 814         __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;             \
 815         ((struct pt_regs *)__ptr) - 1;                                  \
 816 })
 817
 818 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 819
 820 #else
 821 /*
 822  * User space process size. 47bits minus one guard page.  The guard
 823  * page is necessary on Intel CPUs: if a SYSCALL instruction is at
 824  * the highest possible canonical userspace address, then that
 825  * syscall will enter the kernel with a non-canonical return
 826  * address, and SYSRET will explode dangerously.  We avoid this
 827  * particular problem by preventing anything from being mapped
 828  * at the maximum canonical address.
 829  */
 830 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
 831
 832 /* This decides where the kernel will search for a free chunk of vm
 833  * space during mmap's.
 834  */
 835 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 836                                         0xc0000000 : 0xFFFFe000)
 837
 838 #define TASK_SIZE               (test_thread_flag(TIF_ADDR32) ? \
 839                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 840 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
 841                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 842
 843 #define STACK_TOP               TASK_SIZE
 844 #define STACK_TOP_MAX           TASK_SIZE_MAX
 845
 846 #define INIT_THREAD  {                                          \
 847         .sp0                    = TOP_OF_INIT_STACK,            \
 848         .addr_limit             = KERNEL_DS,                    \
 849 }
 850
 851 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 852 extern unsigned long KSTK_ESP(struct task_struct *task);
 853
 854 #endif /* CONFIG_X86_64 */
 855
 856 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 857
 858 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 859                                                unsigned long new_sp);
 860
 861 /*
 862  * This decides where the kernel will search for a free chunk of vm
 863  * space during mmap's.
 864  */
 865 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 866
 867 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 868
 869 /* Get/set a process' ability to use the timestamp counter instruction */
 870 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 871 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 872
 873 extern int get_tsc_mode(unsigned long adr);
 874 extern int set_tsc_mode(unsigned int val);
 875
 876 /* Register/unregister a process' MPX related resource */
 877 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
 878 #define MPX_DISABLE_MANAGEMENT()        mpx_disable_management()
 879
 880 #ifdef CONFIG_X86_INTEL_MPX
 881 extern int mpx_enable_management(void);
 882 extern int mpx_disable_management(void);
 883 #else
 884 static inline int mpx_enable_management(void)
 885 {
 886         return -EINVAL;
 887 }
 888 static inline int mpx_disable_management(void)
 889 {
 890         return -EINVAL;
 891 }
 892 #endif /* CONFIG_X86_INTEL_MPX */
 893
 894 extern u16 amd_get_nb_id(int cpu);
 895 extern u32 amd_get_nodes_per_socket(void);
 896
 897 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
 898 {
 899         uint32_t base, eax, signature[3];
 900
 901         for (base = 0x40000000; base < 0x40010000; base += 0x100) {
 902                 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
 903
 904                 if (!memcmp(sig, signature, 12) &&
 905                     (leaves == 0 || ((eax - base) >= leaves)))
 906                         return base;
 907         }
 908
 909         return 0;
 910 }
 911
 912 extern unsigned long arch_align_stack(unsigned long sp);
 913 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 914
 915 void default_idle(void);
 916 #ifdef  CONFIG_XEN
 917 bool xen_set_default_idle(void);
 918 #else
 919 #define xen_set_default_idle 0
 920 #endif
 921
 922 void stop_this_cpu(void *dummy);
 923 void df_debug(struct pt_regs *regs, long error_code);
 924 #endif /* _ASM_X86_PROCESSOR_H */