1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PROCESSOR_H
3 #define _ASM_X86_PROCESSOR_H
5 #include <asm/processor-flags.h>
7 /* Forward declaration, a strange C thing */
12 #include <asm/math_emu.h>
13 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <uapi/asm/sigcontext.h>
16 #include <asm/current.h>
17 #include <asm/cpufeatures.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
22 #include <asm/desc_defs.h>
24 #include <asm/special_insns.h>
25 #include <asm/fpu/types.h>
26 #include <asm/unwind_hints.h>
28 #include <linux/personality.h>
29 #include <linux/cache.h>
30 #include <linux/threads.h>
31 #include <linux/math64.h>
32 #include <linux/err.h>
33 #include <linux/irqflags.h>
34 #include <linux/mem_encrypt.h>
37 * We handle most unaligned accesses in hardware. On the other hand
38 * unaligned DMA can be quite expensive on some Nehalem processors.
40 * Based on this we disable the IP header alignment in network drivers.
42 #define NET_IP_ALIGN 0
46 * Default implementation of macro that returns current
47 * instruction pointer ("program counter").
49 static inline void *current_text_addr(void)
53 asm volatile("mov $1f, %0; 1:":"=r" (pc
));
59 * These alignment constraints are for performance in the vSMP case,
60 * but in the task_struct case we must also meet hardware imposed
61 * alignment requirements of the FPU state:
63 #ifdef CONFIG_X86_VSMP
64 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
65 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
67 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
68 # define ARCH_MIN_MMSTRUCT_ALIGN 0
76 extern u16 __read_mostly tlb_lli_4k
[NR_INFO
];
77 extern u16 __read_mostly tlb_lli_2m
[NR_INFO
];
78 extern u16 __read_mostly tlb_lli_4m
[NR_INFO
];
79 extern u16 __read_mostly tlb_lld_4k
[NR_INFO
];
80 extern u16 __read_mostly tlb_lld_2m
[NR_INFO
];
81 extern u16 __read_mostly tlb_lld_4m
[NR_INFO
];
82 extern u16 __read_mostly tlb_lld_1g
[NR_INFO
];
85 * CPU type and hardware bug flags. Kept separately for each CPU.
86 * Members of this structure are referenced in head_32.S, so think twice
87 * before touching them. [mj]
91 __u8 x86
; /* CPU family */
92 __u8 x86_vendor
; /* CPU vendor */
96 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
101 /* CPUID returned core id bits: */
102 __u8 x86_coreid_bits
;
104 /* Max extended CPUID function supported: */
105 __u32 extended_cpuid_level
;
106 /* Maximum supported CPUID level, -1=no CPUID: */
108 __u32 x86_capability
[NCAPINTS
+ NBUGINTS
];
109 char x86_vendor_id
[16];
110 char x86_model_id
[64];
111 /* in KB - valid for CPUS which support this call: */
113 int x86_cache_alignment
; /* In bytes */
114 /* Cache QoS architectural values: */
115 int x86_cache_max_rmid
; /* max index */
116 int x86_cache_occ_scale
; /* scale to bytes */
118 unsigned long loops_per_jiffy
;
119 /* cpuid returned max cores value: */
123 u16 x86_clflush_size
;
124 /* number of cores as seen by the OS: */
126 /* Physical processor id: */
128 /* Logical processor id: */
132 /* Index into per_cpu list: */
135 unsigned initialized
: 1;
136 } __randomize_layout
;
139 u32 eax
, ebx
, ecx
, edx
;
142 enum cpuid_regs_idx
{
149 #define X86_VENDOR_INTEL 0
150 #define X86_VENDOR_CYRIX 1
151 #define X86_VENDOR_AMD 2
152 #define X86_VENDOR_UMC 3
153 #define X86_VENDOR_CENTAUR 5
154 #define X86_VENDOR_TRANSMETA 7
155 #define X86_VENDOR_NSC 8
156 #define X86_VENDOR_NUM 9
158 #define X86_VENDOR_UNKNOWN 0xff
161 * capabilities of CPUs
163 extern struct cpuinfo_x86 boot_cpu_data
;
164 extern struct cpuinfo_x86 new_cpu_data
;
166 extern struct tss_struct doublefault_tss
;
167 extern __u32 cpu_caps_cleared
[NCAPINTS
];
168 extern __u32 cpu_caps_set
[NCAPINTS
];
171 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
172 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
174 #define cpu_info boot_cpu_data
175 #define cpu_data(cpu) boot_cpu_data
178 extern const struct seq_operations cpuinfo_op
;
180 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
182 extern void cpu_detect(struct cpuinfo_x86
*c
);
184 extern void early_cpu_init(void);
185 extern void identify_boot_cpu(void);
186 extern void identify_secondary_cpu(struct cpuinfo_x86
*);
187 extern void print_cpu_info(struct cpuinfo_x86
*);
188 void print_cpu_msr(struct cpuinfo_x86
*);
189 extern void init_scattered_cpuid_features(struct cpuinfo_x86
*c
);
190 extern u32
get_scattered_cpuid_leaf(unsigned int level
,
191 unsigned int sub_leaf
,
192 enum cpuid_regs_idx reg
);
193 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86
*c
);
194 extern void init_amd_cacheinfo(struct cpuinfo_x86
*c
);
196 extern void detect_extended_topology(struct cpuinfo_x86
*c
);
197 extern void detect_ht(struct cpuinfo_x86
*c
);
200 extern int have_cpuid_p(void);
202 static inline int have_cpuid_p(void)
207 static inline void native_cpuid(unsigned int *eax
, unsigned int *ebx
,
208 unsigned int *ecx
, unsigned int *edx
)
210 /* ecx is often an input as well as an output. */
216 : "0" (*eax
), "2" (*ecx
)
220 #define native_cpuid_reg(reg) \
221 static inline unsigned int native_cpuid_##reg(unsigned int op) \
223 unsigned int eax = op, ebx, ecx = 0, edx; \
225 native_cpuid(&eax, &ebx, &ecx, &edx); \
231 * Native CPUID functions returning a single datum.
233 native_cpuid_reg(eax
)
234 native_cpuid_reg(ebx
)
235 native_cpuid_reg(ecx
)
236 native_cpuid_reg(edx
)
239 * Friendlier CR3 helpers.
241 static inline unsigned long read_cr3_pa(void)
243 return __read_cr3() & CR3_ADDR_MASK
;
246 static inline unsigned long native_read_cr3_pa(void)
248 return __native_read_cr3() & CR3_ADDR_MASK
;
251 static inline void load_cr3(pgd_t
*pgdir
)
253 write_cr3(__sme_pa(pgdir
));
257 /* This is the TSS defined by the hardware. */
259 unsigned short back_link
, __blh
;
261 unsigned short ss0
, __ss0h
;
265 * We don't use ring 1, so ss1 is a convenient scratch space in
266 * the same cacheline as sp0. We use ss1 to cache the value in
267 * MSR_IA32_SYSENTER_CS. When we context switch
268 * MSR_IA32_SYSENTER_CS, we first check if the new value being
269 * written matches ss1, and, if it's not, then we wrmsr the new
270 * value and update ss1.
272 * The only reason we context switch MSR_IA32_SYSENTER_CS is
273 * that we set it to zero in vm86 tasks to avoid corrupting the
274 * stack if we were to go through the sysenter path from vm86
277 unsigned short ss1
; /* MSR_IA32_SYSENTER_CS */
279 unsigned short __ss1h
;
281 unsigned short ss2
, __ss2h
;
293 unsigned short es
, __esh
;
294 unsigned short cs
, __csh
;
295 unsigned short ss
, __ssh
;
296 unsigned short ds
, __dsh
;
297 unsigned short fs
, __fsh
;
298 unsigned short gs
, __gsh
;
299 unsigned short ldt
, __ldth
;
300 unsigned short trace
;
301 unsigned short io_bitmap_base
;
303 } __attribute__((packed
));
317 } __attribute__((packed
));
323 #define IO_BITMAP_BITS 65536
324 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
325 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
326 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
327 #define INVALID_IO_BITMAP_OFFSET 0x8000
331 * The hardware state:
333 struct x86_hw_tss x86_tss
;
336 * The extra 1 is there because the CPU will access an
337 * additional byte beyond the end of the IO permission
338 * bitmap. The extra byte must be all 1 bits, and must
339 * be within the limit.
341 unsigned long io_bitmap
[IO_BITMAP_LONGS
+ 1];
345 * Space for the temporary SYSENTER stack.
347 unsigned long SYSENTER_stack_canary
;
348 unsigned long SYSENTER_stack
[64];
351 } ____cacheline_aligned
;
353 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct
, cpu_tss
);
356 * sizeof(unsigned long) coming from an extra "long" at the end
359 * -1? seg base+limit should be pointing to the address of the
362 #define __KERNEL_TSS_LIMIT \
363 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
366 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack
);
370 * Save the original ist values for checking stack pointers during debugging
373 unsigned long ist
[7];
377 DECLARE_PER_CPU(struct orig_ist
, orig_ist
);
379 union irq_stack_union
{
380 char irq_stack
[IRQ_STACK_SIZE
];
382 * GCC hardcodes the stack canary as %gs:40. Since the
383 * irq_stack is the object at %gs:0, we reserve the bottom
384 * 48 bytes of the irq stack for the canary.
388 unsigned long stack_canary
;
392 DECLARE_PER_CPU_FIRST(union irq_stack_union
, irq_stack_union
) __visible
;
393 DECLARE_INIT_PER_CPU(irq_stack_union
);
395 DECLARE_PER_CPU(char *, irq_stack_ptr
);
396 DECLARE_PER_CPU(unsigned int, irq_count
);
397 extern asmlinkage
void ignore_sysret(void);
399 #ifdef CONFIG_CC_STACKPROTECTOR
401 * Make sure stack canary segment base is cached-aligned:
402 * "For Intel Atom processors, avoid non zero segment base address
403 * that is not aligned to cache line boundary at all cost."
404 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
406 struct stack_canary
{
407 char __pad
[20]; /* canary at %gs:20 */
408 unsigned long canary
;
410 DECLARE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
413 * per-CPU IRQ handling stacks
416 u32 stack
[THREAD_SIZE
/sizeof(u32
)];
417 } __aligned(THREAD_SIZE
);
419 DECLARE_PER_CPU(struct irq_stack
*, hardirq_stack
);
420 DECLARE_PER_CPU(struct irq_stack
*, softirq_stack
);
423 extern unsigned int fpu_kernel_xstate_size
;
424 extern unsigned int fpu_user_xstate_size
;
432 struct thread_struct
{
433 /* Cached TLS descriptors: */
434 struct desc_struct tls_array
[GDT_ENTRY_TLS_ENTRIES
];
440 unsigned long sysenter_cs
;
444 unsigned short fsindex
;
445 unsigned short gsindex
;
448 u32 status
; /* thread synchronous flags */
451 unsigned long fsbase
;
452 unsigned long gsbase
;
455 * XXX: this could presumably be unsigned short. Alternatively,
456 * 32-bit kernels could be taught to use fsindex instead.
462 /* Save middle states of ptrace breakpoints */
463 struct perf_event
*ptrace_bps
[HBP_NUM
];
464 /* Debug status used for traps, single steps, etc... */
465 unsigned long debugreg6
;
466 /* Keep track of the exact dr7 value set by the user */
467 unsigned long ptrace_dr7
;
470 unsigned long trap_nr
;
471 unsigned long error_code
;
473 /* Virtual 86 mode info */
476 /* IO permissions: */
477 unsigned long *io_bitmap_ptr
;
479 /* Max allowed port in the bitmap, in bytes: */
480 unsigned io_bitmap_max
;
482 mm_segment_t addr_limit
;
484 unsigned int sig_on_uaccess_err
:1;
485 unsigned int uaccess_err
:1; /* uaccess failed */
487 /* Floating point and extended processor state */
490 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
496 * Thread-synchronous status.
498 * This is different from the flags in that nobody else
499 * ever touches our thread-synchronous status, so we don't
500 * have to worry about atomic accesses.
502 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
505 * Set IOPL bits in EFLAGS from given mask
507 static inline void native_set_iopl_mask(unsigned mask
)
512 asm volatile ("pushfl;"
519 : "i" (~X86_EFLAGS_IOPL
), "r" (mask
));
524 native_load_sp0(unsigned long sp0
)
526 this_cpu_write(cpu_tss
.x86_tss
.sp0
, sp0
);
529 static inline void native_swapgs(void)
532 asm volatile("swapgs" ::: "memory");
536 static inline unsigned long current_top_of_stack(void)
539 return this_cpu_read_stable(cpu_tss
.x86_tss
.sp0
);
541 /* sp0 on x86_32 is special in and around vm86 mode. */
542 return this_cpu_read_stable(cpu_current_top_of_stack
);
546 static inline bool on_thread_stack(void)
548 return (unsigned long)(current_top_of_stack() -
549 current_stack_pointer
) < THREAD_SIZE
;
552 #ifdef CONFIG_PARAVIRT
553 #include <asm/paravirt.h>
555 #define __cpuid native_cpuid
557 static inline void load_sp0(unsigned long sp0
)
559 native_load_sp0(sp0
);
562 #define set_iopl_mask native_set_iopl_mask
563 #endif /* CONFIG_PARAVIRT */
565 /* Free all resources held by a thread. */
566 extern void release_thread(struct task_struct
*);
568 unsigned long get_wchan(struct task_struct
*p
);
571 * Generic CPUID function
572 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
573 * resulting in stale register contents being returned.
575 static inline void cpuid(unsigned int op
,
576 unsigned int *eax
, unsigned int *ebx
,
577 unsigned int *ecx
, unsigned int *edx
)
581 __cpuid(eax
, ebx
, ecx
, edx
);
584 /* Some CPUID calls want 'count' to be placed in ecx */
585 static inline void cpuid_count(unsigned int op
, int count
,
586 unsigned int *eax
, unsigned int *ebx
,
587 unsigned int *ecx
, unsigned int *edx
)
591 __cpuid(eax
, ebx
, ecx
, edx
);
595 * CPUID functions returning a single datum
597 static inline unsigned int cpuid_eax(unsigned int op
)
599 unsigned int eax
, ebx
, ecx
, edx
;
601 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
606 static inline unsigned int cpuid_ebx(unsigned int op
)
608 unsigned int eax
, ebx
, ecx
, edx
;
610 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
615 static inline unsigned int cpuid_ecx(unsigned int op
)
617 unsigned int eax
, ebx
, ecx
, edx
;
619 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
624 static inline unsigned int cpuid_edx(unsigned int op
)
626 unsigned int eax
, ebx
, ecx
, edx
;
628 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
633 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
634 static __always_inline
void rep_nop(void)
636 asm volatile("rep; nop" ::: "memory");
639 static __always_inline
void cpu_relax(void)
645 * This function forces the icache and prefetched instruction stream to
646 * catch up with reality in two very specific cases:
648 * a) Text was modified using one virtual address and is about to be executed
649 * from the same physical page at a different virtual address.
651 * b) Text was modified on a different CPU, may subsequently be
652 * executed on this CPU, and you want to make sure the new version
653 * gets executed. This generally means you're calling this in a IPI.
655 * If you're calling this for a different reason, you're probably doing
658 static inline void sync_core(void)
661 * There are quite a few ways to do this. IRET-to-self is nice
662 * because it works on every CPU, at any CPL (so it's compatible
663 * with paravirtualization), and it never exits to a hypervisor.
664 * The only down sides are that it's a bit slow (it seems to be
665 * a bit more than 2x slower than the fastest options) and that
666 * it unmasks NMIs. The "push %cs" is needed because, in
667 * paravirtual environments, __KERNEL_CS may not be a valid CS
668 * value when we do IRET directly.
670 * In case NMI unmasking or performance ever becomes a problem,
671 * the next best option appears to be MOV-to-CR2 and an
672 * unconditional jump. That sequence also works on all CPUs,
673 * but it will fault at CPL3 (i.e. Xen PV).
675 * CPUID is the conventional way, but it's nasty: it doesn't
676 * exist on some 486-like CPUs, and it usually exits to a
679 * Like all of Linux's memory ordering operations, this is a
680 * compiler barrier as well.
689 : ASM_CALL_CONSTRAINT
: : "memory");
698 "addq $8, (%%rsp)\n\t"
706 : "=&r" (tmp
), ASM_CALL_CONSTRAINT
: : "cc", "memory");
710 extern void select_idle_routine(const struct cpuinfo_x86
*c
);
711 extern void amd_e400_c1e_apic_setup(void);
713 extern unsigned long boot_option_idle_override
;
715 enum idle_boot_override
{IDLE_NO_OVERRIDE
=0, IDLE_HALT
, IDLE_NOMWAIT
,
718 extern void enable_sep_cpu(void);
719 extern int sysenter_setup(void);
721 extern void early_trap_init(void);
722 void early_trap_pf_init(void);
724 /* Defined in head.S */
725 extern struct desc_ptr early_gdt_descr
;
727 extern void cpu_set_gdt(int);
728 extern void switch_to_new_gdt(int);
729 extern void load_direct_gdt(int);
730 extern void load_fixmap_gdt(int);
731 extern void load_percpu_segment(int);
732 extern void cpu_init(void);
734 static inline unsigned long get_debugctlmsr(void)
736 unsigned long debugctlmsr
= 0;
738 #ifndef CONFIG_X86_DEBUGCTLMSR
739 if (boot_cpu_data
.x86
< 6)
742 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctlmsr
);
747 static inline void update_debugctlmsr(unsigned long debugctlmsr
)
749 #ifndef CONFIG_X86_DEBUGCTLMSR
750 if (boot_cpu_data
.x86
< 6)
753 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctlmsr
);
756 extern void set_task_blockstep(struct task_struct
*task
, bool on
);
758 /* Boot loader type from the setup header: */
759 extern int bootloader_type
;
760 extern int bootloader_version
;
762 extern char ignore_fpu_irq
;
764 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
765 #define ARCH_HAS_PREFETCHW
766 #define ARCH_HAS_SPINLOCK_PREFETCH
769 # define BASE_PREFETCH ""
770 # define ARCH_HAS_PREFETCH
772 # define BASE_PREFETCH "prefetcht0 %P1"
776 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
778 * It's not worth to care about 3dnow prefetches for the K6
779 * because they are microcoded there and very slow.
781 static inline void prefetch(const void *x
)
783 alternative_input(BASE_PREFETCH
, "prefetchnta %P1",
785 "m" (*(const char *)x
));
789 * 3dnow prefetch to get an exclusive cache line.
790 * Useful for spinlocks to avoid one state transition in the
791 * cache coherency protocol:
793 static inline void prefetchw(const void *x
)
795 alternative_input(BASE_PREFETCH
, "prefetchw %P1",
796 X86_FEATURE_3DNOWPREFETCH
,
797 "m" (*(const char *)x
));
800 static inline void spin_lock_prefetch(const void *x
)
805 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
806 TOP_OF_KERNEL_STACK_PADDING)
808 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
810 #define task_pt_regs(task) \
812 unsigned long __ptr = (unsigned long)task_stack_page(task); \
813 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
814 ((struct pt_regs *)__ptr) - 1; \
819 * User space process size: 3GB (default).
821 #define IA32_PAGE_OFFSET PAGE_OFFSET
822 #define TASK_SIZE PAGE_OFFSET
823 #define TASK_SIZE_LOW TASK_SIZE
824 #define TASK_SIZE_MAX TASK_SIZE
825 #define DEFAULT_MAP_WINDOW TASK_SIZE
826 #define STACK_TOP TASK_SIZE
827 #define STACK_TOP_MAX STACK_TOP
829 #define INIT_THREAD { \
830 .sp0 = TOP_OF_INIT_STACK, \
831 .sysenter_cs = __KERNEL_CS, \
832 .io_bitmap_ptr = NULL, \
833 .addr_limit = KERNEL_DS, \
836 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
840 * User space process size. 47bits minus one guard page. The guard
841 * page is necessary on Intel CPUs: if a SYSCALL instruction is at
842 * the highest possible canonical userspace address, then that
843 * syscall will enter the kernel with a non-canonical return
844 * address, and SYSRET will explode dangerously. We avoid this
845 * particular problem by preventing anything from being mapped
846 * at the maximum canonical address.
848 #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
850 #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE)
852 /* This decides where the kernel will search for a free chunk of vm
853 * space during mmap's.
855 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
856 0xc0000000 : 0xFFFFe000)
858 #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \
859 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
860 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
861 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
862 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
863 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
865 #define STACK_TOP TASK_SIZE_LOW
866 #define STACK_TOP_MAX TASK_SIZE_MAX
868 #define INIT_THREAD { \
869 .addr_limit = KERNEL_DS, \
872 extern unsigned long KSTK_ESP(struct task_struct
*task
);
874 #endif /* CONFIG_X86_64 */
876 extern void start_thread(struct pt_regs
*regs
, unsigned long new_ip
,
877 unsigned long new_sp
);
880 * This decides where the kernel will search for a free chunk of vm
881 * space during mmap's.
883 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
884 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
886 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
888 /* Get/set a process' ability to use the timestamp counter instruction */
889 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
890 #define SET_TSC_CTL(val) set_tsc_mode((val))
892 extern int get_tsc_mode(unsigned long adr
);
893 extern int set_tsc_mode(unsigned int val
);
895 DECLARE_PER_CPU(u64
, msr_misc_features_shadow
);
897 /* Register/unregister a process' MPX related resource */
898 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
899 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
901 #ifdef CONFIG_X86_INTEL_MPX
902 extern int mpx_enable_management(void);
903 extern int mpx_disable_management(void);
905 static inline int mpx_enable_management(void)
909 static inline int mpx_disable_management(void)
913 #endif /* CONFIG_X86_INTEL_MPX */
915 #ifdef CONFIG_CPU_SUP_AMD
916 extern u16
amd_get_nb_id(int cpu
);
917 extern u32
amd_get_nodes_per_socket(void);
919 static inline u16
amd_get_nb_id(int cpu
) { return 0; }
920 static inline u32
amd_get_nodes_per_socket(void) { return 0; }
923 static inline uint32_t hypervisor_cpuid_base(const char *sig
, uint32_t leaves
)
925 uint32_t base
, eax
, signature
[3];
927 for (base
= 0x40000000; base
< 0x40010000; base
+= 0x100) {
928 cpuid(base
, &eax
, &signature
[0], &signature
[1], &signature
[2]);
930 if (!memcmp(sig
, signature
, 12) &&
931 (leaves
== 0 || ((eax
- base
) >= leaves
)))
938 extern unsigned long arch_align_stack(unsigned long sp
);
939 extern void free_init_pages(char *what
, unsigned long begin
, unsigned long end
);
941 void default_idle(void);
943 bool xen_set_default_idle(void);
945 #define xen_set_default_idle 0
948 void stop_this_cpu(void *dummy
);
949 void df_debug(struct pt_regs
*regs
, long error_code
);
950 #endif /* _ASM_X86_PROCESSOR_H */