2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
48 #include <asm/io_apic.h>
57 #include <asm/hypervisor.h>
59 unsigned int num_processors
;
61 unsigned disabled_cpus
;
63 /* Processor that is doing the boot up */
64 unsigned int boot_cpu_physical_apicid
= -1U;
65 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid
);
68 * The highest APIC ID seen during enumeration.
70 static unsigned int max_physical_apicid
;
73 * Bitmask of physically existing CPUs:
75 physid_mask_t phys_cpu_present_map
;
78 * Processor to be disabled specified by kernel parameter
79 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
80 * avoid undefined behaviour caused by sending INIT from AP to BSP.
82 static unsigned int disabled_cpu_apicid __read_mostly
= BAD_APICID
;
85 * Map cpu index to physical APIC ID
87 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16
, x86_cpu_to_apicid
, BAD_APICID
);
88 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
89 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
90 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
95 * On x86_32, the mapping between cpu and logical apicid may vary
96 * depending on apic in use. The following early percpu variable is
97 * used for the mapping. This is where the behaviors of x86_64 and 32
98 * actually diverge. Let's keep it ugly for now.
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid
, BAD_APICID
);
102 /* Local APIC was disabled by the BIOS and enabled by the kernel */
103 static int enabled_via_apicbase
;
106 * Handle interrupt mode configuration register (IMCR).
107 * This register controls whether the interrupt signals
108 * that reach the BSP come from the master PIC or from the
109 * local APIC. Before entering Symmetric I/O Mode, either
110 * the BIOS or the operating system must switch out of
111 * PIC Mode by changing the IMCR.
113 static inline void imcr_pic_to_apic(void)
115 /* select IMCR register */
117 /* NMI and 8259 INTR go through APIC */
121 static inline void imcr_apic_to_pic(void)
123 /* select IMCR register */
125 /* NMI and 8259 INTR go directly to BSP */
131 * Knob to control our willingness to enable the local APIC.
135 static int force_enable_local_apic __initdata
;
137 /* Control whether x2APIC mode is enabled or not */
138 static bool nox2apic __initdata
;
141 * APIC command line parameters
143 static int __init
parse_lapic(char *arg
)
145 if (config_enabled(CONFIG_X86_32
) && !arg
)
146 force_enable_local_apic
= 1;
147 else if (arg
&& !strncmp(arg
, "notscdeadline", 13))
148 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER
);
151 early_param("lapic", parse_lapic
);
154 static int apic_calibrate_pmtmr __initdata
;
155 static __init
int setup_apicpmtimer(char *s
)
157 apic_calibrate_pmtmr
= 1;
161 __setup("apicpmtimer", setup_apicpmtimer
);
165 #ifdef CONFIG_X86_X2APIC
166 /* x2apic enabled before OS handover */
167 int x2apic_preenabled
;
168 static int x2apic_disabled
;
169 static int __init
setup_nox2apic(char *str
)
171 if (x2apic_enabled()) {
172 int apicid
= native_apic_msr_read(APIC_ID
);
175 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
180 pr_warning("x2apic already enabled. will disable it\n");
182 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
188 early_param("nox2apic", setup_nox2apic
);
191 unsigned long mp_lapic_addr
;
193 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
194 static int disable_apic_timer __initdata
;
195 /* Local APIC timer works in C2 */
196 int local_apic_timer_c2_ok
;
197 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
199 int first_system_vector
= 0xfe;
202 * Debug level, exported for io_apic.c
204 unsigned int apic_verbosity
;
208 /* Have we found an MP table */
209 int smp_found_config
;
211 static struct resource lapic_resource
= {
212 .name
= "Local APIC",
213 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
216 unsigned int lapic_timer_frequency
= 0;
218 static void apic_pm_activate(void);
220 static unsigned long apic_phys
;
223 * Get the LAPIC version
225 static inline int lapic_get_version(void)
227 return GET_APIC_VERSION(apic_read(APIC_LVR
));
231 * Check, if the APIC is integrated or a separate chip
233 static inline int lapic_is_integrated(void)
238 return APIC_INTEGRATED(lapic_get_version());
243 * Check, whether this is a modern or a first generation APIC
245 static int modern_apic(void)
247 /* AMD systems use old APIC versions, so check the CPU */
248 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
249 boot_cpu_data
.x86
>= 0xf)
251 return lapic_get_version() >= 0x14;
255 * right after this call apic become NOOP driven
256 * so apic->write/read doesn't do anything
258 static void __init
apic_disable(void)
260 pr_info("APIC: switched to apic NOOP\n");
264 void native_apic_wait_icr_idle(void)
266 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
270 u32
native_safe_apic_wait_icr_idle(void)
277 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
280 inc_irq_stat(icr_read_retry_count
);
282 } while (timeout
++ < 1000);
287 void native_apic_icr_write(u32 low
, u32 id
)
291 local_irq_save(flags
);
292 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
293 apic_write(APIC_ICR
, low
);
294 local_irq_restore(flags
);
297 u64
native_apic_icr_read(void)
301 icr2
= apic_read(APIC_ICR2
);
302 icr1
= apic_read(APIC_ICR
);
304 return icr1
| ((u64
)icr2
<< 32);
309 * get_physical_broadcast - Get number of physical broadcast IDs
311 int get_physical_broadcast(void)
313 return modern_apic() ? 0xff : 0xf;
318 * lapic_get_maxlvt - get the maximum number of local vector table entries
320 int lapic_get_maxlvt(void)
324 v
= apic_read(APIC_LVR
);
326 * - we always have APIC integrated on 64bit mode
327 * - 82489DXs do not report # of LVT entries
329 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
337 #define APIC_DIVISOR 16
338 #define TSC_DIVISOR 32
341 * This function sets up the local APIC timer, with a timeout of
342 * 'clocks' APIC bus clock. During calibration we actually call
343 * this function twice on the boot CPU, once with a bogus timeout
344 * value, second time for real. The other (noncalibrating) CPUs
345 * call this function only once, with the real, calibrated value.
347 * We do reads before writes even if unnecessary, to get around the
348 * P5 APIC double write bug.
350 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
352 unsigned int lvtt_value
, tmp_value
;
354 lvtt_value
= LOCAL_TIMER_VECTOR
;
356 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
357 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
))
358 lvtt_value
|= APIC_LVT_TIMER_TSCDEADLINE
;
360 if (!lapic_is_integrated())
361 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
364 lvtt_value
|= APIC_LVT_MASKED
;
366 apic_write(APIC_LVTT
, lvtt_value
);
368 if (lvtt_value
& APIC_LVT_TIMER_TSCDEADLINE
) {
369 printk_once(KERN_DEBUG
"TSC deadline timer enabled\n");
376 tmp_value
= apic_read(APIC_TDCR
);
377 apic_write(APIC_TDCR
,
378 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
382 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
386 * Setup extended LVT, AMD specific
388 * Software should use the LVT offsets the BIOS provides. The offsets
389 * are determined by the subsystems using it like those for MCE
390 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
391 * are supported. Beginning with family 10h at least 4 offsets are
394 * Since the offsets must be consistent for all cores, we keep track
395 * of the LVT offsets in software and reserve the offset for the same
396 * vector also to be used on other cores. An offset is freed by
397 * setting the entry to APIC_EILVT_MASKED.
399 * If the BIOS is right, there should be no conflicts. Otherwise a
400 * "[Firmware Bug]: ..." error message is generated. However, if
401 * software does not properly determines the offsets, it is not
402 * necessarily a BIOS bug.
405 static atomic_t eilvt_offsets
[APIC_EILVT_NR_MAX
];
407 static inline int eilvt_entry_is_changeable(unsigned int old
, unsigned int new)
409 return (old
& APIC_EILVT_MASKED
)
410 || (new == APIC_EILVT_MASKED
)
411 || ((new & ~APIC_EILVT_MASKED
) == old
);
414 static unsigned int reserve_eilvt_offset(int offset
, unsigned int new)
416 unsigned int rsvd
, vector
;
418 if (offset
>= APIC_EILVT_NR_MAX
)
421 rsvd
= atomic_read(&eilvt_offsets
[offset
]);
423 vector
= rsvd
& ~APIC_EILVT_MASKED
; /* 0: unassigned */
424 if (vector
&& !eilvt_entry_is_changeable(vector
, new))
425 /* may not change if vectors are different */
427 rsvd
= atomic_cmpxchg(&eilvt_offsets
[offset
], rsvd
, new);
428 } while (rsvd
!= new);
430 rsvd
&= ~APIC_EILVT_MASKED
;
431 if (rsvd
&& rsvd
!= vector
)
432 pr_info("LVT offset %d assigned for vector 0x%02x\n",
439 * If mask=1, the LVT entry does not generate interrupts while mask=0
440 * enables the vector. See also the BKDGs. Must be called with
441 * preemption disabled.
444 int setup_APIC_eilvt(u8 offset
, u8 vector
, u8 msg_type
, u8 mask
)
446 unsigned long reg
= APIC_EILVTn(offset
);
447 unsigned int new, old
, reserved
;
449 new = (mask
<< 16) | (msg_type
<< 8) | vector
;
450 old
= apic_read(reg
);
451 reserved
= reserve_eilvt_offset(offset
, new);
453 if (reserved
!= new) {
454 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
455 "vector 0x%x, but the register is already in use for "
456 "vector 0x%x on another cpu\n",
457 smp_processor_id(), reg
, offset
, new, reserved
);
461 if (!eilvt_entry_is_changeable(old
, new)) {
462 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
463 "vector 0x%x, but the register is already in use for "
464 "vector 0x%x on this cpu\n",
465 smp_processor_id(), reg
, offset
, new, old
);
469 apic_write(reg
, new);
473 EXPORT_SYMBOL_GPL(setup_APIC_eilvt
);
476 * Program the next event, relative to now
478 static int lapic_next_event(unsigned long delta
,
479 struct clock_event_device
*evt
)
481 apic_write(APIC_TMICT
, delta
);
485 static int lapic_next_deadline(unsigned long delta
,
486 struct clock_event_device
*evt
)
491 wrmsrl(MSR_IA32_TSC_DEADLINE
, tsc
+ (((u64
) delta
) * TSC_DIVISOR
));
496 * Setup the lapic timer in periodic or oneshot mode
498 static void lapic_timer_setup(enum clock_event_mode mode
,
499 struct clock_event_device
*evt
)
504 /* Lapic used as dummy for broadcast ? */
505 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
508 local_irq_save(flags
);
511 case CLOCK_EVT_MODE_PERIODIC
:
512 case CLOCK_EVT_MODE_ONESHOT
:
513 __setup_APIC_LVTT(lapic_timer_frequency
,
514 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
516 case CLOCK_EVT_MODE_UNUSED
:
517 case CLOCK_EVT_MODE_SHUTDOWN
:
518 v
= apic_read(APIC_LVTT
);
519 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
520 apic_write(APIC_LVTT
, v
);
521 apic_write(APIC_TMICT
, 0);
523 case CLOCK_EVT_MODE_RESUME
:
524 /* Nothing to do here */
528 local_irq_restore(flags
);
532 * Local APIC timer broadcast function
534 static void lapic_timer_broadcast(const struct cpumask
*mask
)
537 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
543 * The local apic timer can be used for any function which is CPU local.
545 static struct clock_event_device lapic_clockevent
= {
547 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
548 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
550 .set_mode
= lapic_timer_setup
,
551 .set_next_event
= lapic_next_event
,
552 .broadcast
= lapic_timer_broadcast
,
556 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
559 * Setup the local APIC timer for this CPU. Copy the initialized values
560 * of the boot CPU and register the clock event in the framework.
562 static void setup_APIC_timer(void)
564 struct clock_event_device
*levt
= this_cpu_ptr(&lapic_events
);
566 if (this_cpu_has(X86_FEATURE_ARAT
)) {
567 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
568 /* Make LAPIC timer preferrable over percpu HPET */
569 lapic_clockevent
.rating
= 150;
572 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
573 levt
->cpumask
= cpumask_of(smp_processor_id());
575 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
)) {
576 levt
->features
&= ~(CLOCK_EVT_FEAT_PERIODIC
|
577 CLOCK_EVT_FEAT_DUMMY
);
578 levt
->set_next_event
= lapic_next_deadline
;
579 clockevents_config_and_register(levt
,
580 (tsc_khz
/ TSC_DIVISOR
) * 1000,
583 clockevents_register_device(levt
);
587 * In this functions we calibrate APIC bus clocks to the external timer.
589 * We want to do the calibration only once since we want to have local timer
590 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
593 * This was previously done by reading the PIT/HPET and waiting for a wrap
594 * around to find out, that a tick has elapsed. I have a box, where the PIT
595 * readout is broken, so it never gets out of the wait loop again. This was
596 * also reported by others.
598 * Monitoring the jiffies value is inaccurate and the clockevents
599 * infrastructure allows us to do a simple substitution of the interrupt
602 * The calibration routine also uses the pm_timer when possible, as the PIT
603 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
604 * back to normal later in the boot process).
607 #define LAPIC_CAL_LOOPS (HZ/10)
609 static __initdata
int lapic_cal_loops
= -1;
610 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
611 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
612 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
613 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
616 * Temporary interrupt handler.
618 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
620 unsigned long long tsc
= 0;
621 long tapic
= apic_read(APIC_TMCCT
);
622 unsigned long pm
= acpi_pm_read_early();
627 switch (lapic_cal_loops
++) {
629 lapic_cal_t1
= tapic
;
630 lapic_cal_tsc1
= tsc
;
632 lapic_cal_j1
= jiffies
;
635 case LAPIC_CAL_LOOPS
:
636 lapic_cal_t2
= tapic
;
637 lapic_cal_tsc2
= tsc
;
638 if (pm
< lapic_cal_pm1
)
639 pm
+= ACPI_PM_OVRRUN
;
641 lapic_cal_j2
= jiffies
;
647 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
649 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
650 const long pm_thresh
= pm_100ms
/ 100;
654 #ifndef CONFIG_X86_PM_TIMER
658 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
660 /* Check, if the PM timer is available */
664 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
666 if (deltapm
> (pm_100ms
- pm_thresh
) &&
667 deltapm
< (pm_100ms
+ pm_thresh
)) {
668 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
672 res
= (((u64
)deltapm
) * mult
) >> 22;
673 do_div(res
, 1000000);
674 pr_warning("APIC calibration not consistent "
675 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
677 /* Correct the lapic counter value */
678 res
= (((u64
)(*delta
)) * pm_100ms
);
679 do_div(res
, deltapm
);
680 pr_info("APIC delta adjusted to PM-Timer: "
681 "%lu (%ld)\n", (unsigned long)res
, *delta
);
684 /* Correct the tsc counter value */
686 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
687 do_div(res
, deltapm
);
688 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
689 "PM-Timer: %lu (%ld)\n",
690 (unsigned long)res
, *deltatsc
);
691 *deltatsc
= (long)res
;
697 static int __init
calibrate_APIC_clock(void)
699 struct clock_event_device
*levt
= this_cpu_ptr(&lapic_events
);
700 void (*real_handler
)(struct clock_event_device
*dev
);
701 unsigned long deltaj
;
702 long delta
, deltatsc
;
703 int pm_referenced
= 0;
706 * check if lapic timer has already been calibrated by platform
707 * specific routine, such as tsc calibration code. if so, we just fill
708 * in the clockevent structure and return.
711 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
)) {
713 } else if (lapic_timer_frequency
) {
714 apic_printk(APIC_VERBOSE
, "lapic timer already calibrated %d\n",
715 lapic_timer_frequency
);
716 lapic_clockevent
.mult
= div_sc(lapic_timer_frequency
/APIC_DIVISOR
,
717 TICK_NSEC
, lapic_clockevent
.shift
);
718 lapic_clockevent
.max_delta_ns
=
719 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
720 lapic_clockevent
.min_delta_ns
=
721 clockevent_delta2ns(0xF, &lapic_clockevent
);
722 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
726 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
727 "calibrating APIC timer ...\n");
731 /* Replace the global interrupt handler */
732 real_handler
= global_clock_event
->event_handler
;
733 global_clock_event
->event_handler
= lapic_cal_handler
;
736 * Setup the APIC counter to maximum. There is no way the lapic
737 * can underflow in the 100ms detection time frame
739 __setup_APIC_LVTT(0xffffffff, 0, 0);
741 /* Let the interrupts run */
744 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
749 /* Restore the real event handler */
750 global_clock_event
->event_handler
= real_handler
;
752 /* Build delta t1-t2 as apic timer counts down */
753 delta
= lapic_cal_t1
- lapic_cal_t2
;
754 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
756 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
758 /* we trust the PM based calibration if possible */
759 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
762 /* Calculate the scaled math multiplication factor */
763 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
764 lapic_clockevent
.shift
);
765 lapic_clockevent
.max_delta_ns
=
766 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent
);
767 lapic_clockevent
.min_delta_ns
=
768 clockevent_delta2ns(0xF, &lapic_clockevent
);
770 lapic_timer_frequency
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
772 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
773 apic_printk(APIC_VERBOSE
, "..... mult: %u\n", lapic_clockevent
.mult
);
774 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
775 lapic_timer_frequency
);
778 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
780 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
781 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
784 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
786 lapic_timer_frequency
/ (1000000 / HZ
),
787 lapic_timer_frequency
% (1000000 / HZ
));
790 * Do a sanity check on the APIC calibration result
792 if (lapic_timer_frequency
< (1000000 / HZ
)) {
794 pr_warning("APIC frequency too slow, disabling apic timer\n");
798 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
801 * PM timer calibration failed or not turned on
802 * so lets try APIC timer based calibration
804 if (!pm_referenced
) {
805 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
808 * Setup the apic timer manually
810 levt
->event_handler
= lapic_cal_handler
;
811 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
812 lapic_cal_loops
= -1;
814 /* Let the interrupts run */
817 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
820 /* Stop the lapic timer */
821 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
824 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
825 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
827 /* Check, if the jiffies result is consistent */
828 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
829 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
831 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
835 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
836 pr_warning("APIC timer disabled due to verification failure\n");
844 * Setup the boot APIC
846 * Calibrate and verify the result.
848 void __init
setup_boot_APIC_clock(void)
851 * The local apic timer can be disabled via the kernel
852 * commandline or from the CPU detection code. Register the lapic
853 * timer as a dummy clock event source on SMP systems, so the
854 * broadcast mechanism is used. On UP systems simply ignore it.
856 if (disable_apic_timer
) {
857 pr_info("Disabling APIC timer\n");
858 /* No broadcast on UP ! */
859 if (num_possible_cpus() > 1) {
860 lapic_clockevent
.mult
= 1;
866 if (calibrate_APIC_clock()) {
867 /* No broadcast on UP ! */
868 if (num_possible_cpus() > 1)
874 * If nmi_watchdog is set to IO_APIC, we need the
875 * PIT/HPET going. Otherwise register lapic as a dummy
878 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
880 /* Setup the lapic or request the broadcast */
884 void setup_secondary_APIC_clock(void)
890 * The guts of the apic timer interrupt
892 static void local_apic_timer_interrupt(void)
894 int cpu
= smp_processor_id();
895 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
898 * Normally we should not be here till LAPIC has been initialized but
899 * in some cases like kdump, its possible that there is a pending LAPIC
900 * timer interrupt from previous kernel's context and is delivered in
901 * new kernel the moment interrupts are enabled.
903 * Interrupts are enabled early and LAPIC is setup much later, hence
904 * its possible that when we get here evt->event_handler is NULL.
905 * Check for event_handler being NULL and discard the interrupt as
908 if (!evt
->event_handler
) {
909 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
911 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
916 * the NMI deadlock-detector uses this.
918 inc_irq_stat(apic_timer_irqs
);
920 evt
->event_handler(evt
);
924 * Local APIC timer interrupt. This is the most natural way for doing
925 * local interrupts, but local timer interrupts can be emulated by
926 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
928 * [ if a single-CPU system runs an SMP kernel then we call the local
929 * interrupt as well. Thus we cannot inline the local irq ... ]
931 __visible
void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
933 struct pt_regs
*old_regs
= set_irq_regs(regs
);
936 * NOTE! We'd better ACK the irq immediately,
937 * because timer handling can be slow.
939 * update_process_times() expects us to have done irq_enter().
940 * Besides, if we don't timer interrupts ignore the global
941 * interrupt lock, which is the WrongThing (tm) to do.
944 local_apic_timer_interrupt();
947 set_irq_regs(old_regs
);
950 __visible
void __irq_entry
smp_trace_apic_timer_interrupt(struct pt_regs
*regs
)
952 struct pt_regs
*old_regs
= set_irq_regs(regs
);
955 * NOTE! We'd better ACK the irq immediately,
956 * because timer handling can be slow.
958 * update_process_times() expects us to have done irq_enter().
959 * Besides, if we don't timer interrupts ignore the global
960 * interrupt lock, which is the WrongThing (tm) to do.
963 trace_local_timer_entry(LOCAL_TIMER_VECTOR
);
964 local_apic_timer_interrupt();
965 trace_local_timer_exit(LOCAL_TIMER_VECTOR
);
968 set_irq_regs(old_regs
);
971 int setup_profiling_timer(unsigned int multiplier
)
977 * Local APIC start and shutdown
981 * clear_local_APIC - shutdown the local APIC
983 * This is called, when a CPU is disabled and before rebooting, so the state of
984 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
985 * leftovers during boot.
987 void clear_local_APIC(void)
992 /* APIC hasn't been mapped yet */
993 if (!x2apic_mode
&& !apic_phys
)
996 maxlvt
= lapic_get_maxlvt();
998 * Masking an LVT entry can trigger a local APIC error
999 * if the vector is zero. Mask LVTERR first to prevent this.
1002 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
1003 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
1006 * Careful: we have to set masks only first to deassert
1007 * any level-triggered sources.
1009 v
= apic_read(APIC_LVTT
);
1010 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
1011 v
= apic_read(APIC_LVT0
);
1012 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1013 v
= apic_read(APIC_LVT1
);
1014 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
1016 v
= apic_read(APIC_LVTPC
);
1017 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
1020 /* lets not touch this if we didn't frob it */
1021 #ifdef CONFIG_X86_THERMAL_VECTOR
1023 v
= apic_read(APIC_LVTTHMR
);
1024 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
1027 #ifdef CONFIG_X86_MCE_INTEL
1029 v
= apic_read(APIC_LVTCMCI
);
1030 if (!(v
& APIC_LVT_MASKED
))
1031 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
1036 * Clean APIC state for other OSs:
1038 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
1039 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1040 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
1042 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
1044 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
1046 /* Integrated APIC (!82489DX) ? */
1047 if (lapic_is_integrated()) {
1049 /* Clear ESR due to Pentium errata 3AP and 11AP */
1050 apic_write(APIC_ESR
, 0);
1051 apic_read(APIC_ESR
);
1056 * disable_local_APIC - clear and disable the local APIC
1058 void disable_local_APIC(void)
1062 /* APIC hasn't been mapped yet */
1063 if (!x2apic_mode
&& !apic_phys
)
1069 * Disable APIC (implies clearing of registers
1072 value
= apic_read(APIC_SPIV
);
1073 value
&= ~APIC_SPIV_APIC_ENABLED
;
1074 apic_write(APIC_SPIV
, value
);
1076 #ifdef CONFIG_X86_32
1078 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1079 * restore the disabled state.
1081 if (enabled_via_apicbase
) {
1084 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1085 l
&= ~MSR_IA32_APICBASE_ENABLE
;
1086 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1092 * If Linux enabled the LAPIC against the BIOS default disable it down before
1093 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1094 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1095 * for the case where Linux didn't enable the LAPIC.
1097 void lapic_shutdown(void)
1099 unsigned long flags
;
1101 if (!cpu_has_apic
&& !apic_from_smp_config())
1104 local_irq_save(flags
);
1106 #ifdef CONFIG_X86_32
1107 if (!enabled_via_apicbase
)
1111 disable_local_APIC();
1114 local_irq_restore(flags
);
1118 * This is to verify that we're looking at a real local APIC.
1119 * Check these against your board if the CPUs aren't getting
1120 * started for no apparent reason.
1122 int __init
verify_local_APIC(void)
1124 unsigned int reg0
, reg1
;
1127 * The version register is read-only in a real APIC.
1129 reg0
= apic_read(APIC_LVR
);
1130 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
1131 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
1132 reg1
= apic_read(APIC_LVR
);
1133 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
1136 * The two version reads above should print the same
1137 * numbers. If the second one is different, then we
1138 * poke at a non-APIC.
1144 * Check if the version looks reasonably.
1146 reg1
= GET_APIC_VERSION(reg0
);
1147 if (reg1
== 0x00 || reg1
== 0xff)
1149 reg1
= lapic_get_maxlvt();
1150 if (reg1
< 0x02 || reg1
== 0xff)
1154 * The ID register is read/write in a real APIC.
1156 reg0
= apic_read(APIC_ID
);
1157 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1158 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1159 reg1
= apic_read(APIC_ID
);
1160 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1161 apic_write(APIC_ID
, reg0
);
1162 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1166 * The next two are just to see if we have sane values.
1167 * They're only really relevant if we're in Virtual Wire
1168 * compatibility mode, but most boxes are anymore.
1170 reg0
= apic_read(APIC_LVT0
);
1171 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1172 reg1
= apic_read(APIC_LVT1
);
1173 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1179 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1181 void __init
sync_Arb_IDs(void)
1184 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1187 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1193 apic_wait_icr_idle();
1195 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1196 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1197 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1201 * An initial setup of the virtual wire mode.
1203 void __init
init_bsp_APIC(void)
1208 * Don't do the setup now if we have a SMP BIOS as the
1209 * through-I/O-APIC virtual wire mode might be active.
1211 if (smp_found_config
|| !cpu_has_apic
)
1215 * Do not trust the local APIC being empty at bootup.
1222 value
= apic_read(APIC_SPIV
);
1223 value
&= ~APIC_VECTOR_MASK
;
1224 value
|= APIC_SPIV_APIC_ENABLED
;
1226 #ifdef CONFIG_X86_32
1227 /* This bit is reserved on P4/Xeon and should be cleared */
1228 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1229 (boot_cpu_data
.x86
== 15))
1230 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1233 value
|= APIC_SPIV_FOCUS_DISABLED
;
1234 value
|= SPURIOUS_APIC_VECTOR
;
1235 apic_write(APIC_SPIV
, value
);
1238 * Set up the virtual wire mode.
1240 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1241 value
= APIC_DM_NMI
;
1242 if (!lapic_is_integrated()) /* 82489DX */
1243 value
|= APIC_LVT_LEVEL_TRIGGER
;
1244 apic_write(APIC_LVT1
, value
);
1247 static void lapic_setup_esr(void)
1249 unsigned int oldvalue
, value
, maxlvt
;
1251 if (!lapic_is_integrated()) {
1252 pr_info("No ESR for 82489DX.\n");
1256 if (apic
->disable_esr
) {
1258 * Something untraceable is creating bad interrupts on
1259 * secondary quads ... for the moment, just leave the
1260 * ESR disabled - we can't do anything useful with the
1261 * errors anyway - mbligh
1263 pr_info("Leaving ESR disabled.\n");
1267 maxlvt
= lapic_get_maxlvt();
1268 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1269 apic_write(APIC_ESR
, 0);
1270 oldvalue
= apic_read(APIC_ESR
);
1272 /* enables sending errors */
1273 value
= ERROR_APIC_VECTOR
;
1274 apic_write(APIC_LVTERR
, value
);
1277 * spec says clear errors after enabling vector.
1280 apic_write(APIC_ESR
, 0);
1281 value
= apic_read(APIC_ESR
);
1282 if (value
!= oldvalue
)
1283 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1284 "vector: 0x%08x after: 0x%08x\n",
1289 * setup_local_APIC - setup the local APIC
1291 * Used to setup local APIC while initializing BSP or bringin up APs.
1292 * Always called with preemption disabled.
1294 void setup_local_APIC(void)
1296 int cpu
= smp_processor_id();
1297 unsigned int value
, queued
;
1298 int i
, j
, acked
= 0;
1299 unsigned long long tsc
= 0, ntsc
;
1300 long long max_loops
= cpu_khz
;
1306 disable_ioapic_support();
1310 #ifdef CONFIG_X86_32
1311 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1312 if (lapic_is_integrated() && apic
->disable_esr
) {
1313 apic_write(APIC_ESR
, 0);
1314 apic_write(APIC_ESR
, 0);
1315 apic_write(APIC_ESR
, 0);
1316 apic_write(APIC_ESR
, 0);
1319 perf_events_lapic_init();
1322 * Double-check whether this APIC is really registered.
1323 * This is meaningless in clustered apic mode, so we skip it.
1325 BUG_ON(!apic
->apic_id_registered());
1328 * Intel recommends to set DFR, LDR and TPR before enabling
1329 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1330 * document number 292116). So here it goes...
1332 apic
->init_apic_ldr();
1334 #ifdef CONFIG_X86_32
1336 * APIC LDR is initialized. If logical_apicid mapping was
1337 * initialized during get_smp_config(), make sure it matches the
1340 i
= early_per_cpu(x86_cpu_to_logical_apicid
, cpu
);
1341 WARN_ON(i
!= BAD_APICID
&& i
!= logical_smp_processor_id());
1342 /* always use the value from LDR */
1343 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
1344 logical_smp_processor_id();
1348 * Set Task Priority to 'accept all'. We never change this
1351 value
= apic_read(APIC_TASKPRI
);
1352 value
&= ~APIC_TPRI_MASK
;
1353 apic_write(APIC_TASKPRI
, value
);
1356 * After a crash, we no longer service the interrupts and a pending
1357 * interrupt from previous kernel might still have ISR bit set.
1359 * Most probably by now CPU has serviced that pending interrupt and
1360 * it might not have done the ack_APIC_irq() because it thought,
1361 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1362 * does not clear the ISR bit and cpu thinks it has already serivced
1363 * the interrupt. Hence a vector might get locked. It was noticed
1364 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1368 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--)
1369 queued
|= apic_read(APIC_IRR
+ i
*0x10);
1371 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1372 value
= apic_read(APIC_ISR
+ i
*0x10);
1373 for (j
= 31; j
>= 0; j
--) {
1374 if (value
& (1<<j
)) {
1381 printk(KERN_ERR
"LAPIC pending interrupts after %d EOI\n",
1388 max_loops
= (cpu_khz
<< 10) - (ntsc
- tsc
);
1392 } while (queued
&& max_loops
> 0);
1393 WARN_ON(max_loops
<= 0);
1396 * Now that we are all set up, enable the APIC
1398 value
= apic_read(APIC_SPIV
);
1399 value
&= ~APIC_VECTOR_MASK
;
1403 value
|= APIC_SPIV_APIC_ENABLED
;
1405 #ifdef CONFIG_X86_32
1407 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1408 * certain networking cards. If high frequency interrupts are
1409 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1410 * entry is masked/unmasked at a high rate as well then sooner or
1411 * later IOAPIC line gets 'stuck', no more interrupts are received
1412 * from the device. If focus CPU is disabled then the hang goes
1415 * [ This bug can be reproduced easily with a level-triggered
1416 * PCI Ne2000 networking cards and PII/PIII processors, dual
1420 * Actually disabling the focus CPU check just makes the hang less
1421 * frequent as it makes the interrupt distributon model be more
1422 * like LRU than MRU (the short-term load is more even across CPUs).
1423 * See also the comment in end_level_ioapic_irq(). --macro
1427 * - enable focus processor (bit==0)
1428 * - 64bit mode always use processor focus
1429 * so no need to set it
1431 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1435 * Set spurious IRQ vector
1437 value
|= SPURIOUS_APIC_VECTOR
;
1438 apic_write(APIC_SPIV
, value
);
1441 * Set up LVT0, LVT1:
1443 * set up through-local-APIC on the BP's LINT0. This is not
1444 * strictly necessary in pure symmetric-IO mode, but sometimes
1445 * we delegate interrupts to the 8259A.
1448 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1450 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1451 if (!cpu
&& (pic_mode
|| !value
)) {
1452 value
= APIC_DM_EXTINT
;
1453 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", cpu
);
1455 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1456 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", cpu
);
1458 apic_write(APIC_LVT0
, value
);
1461 * only the BP should see the LINT1 NMI signal, obviously.
1464 value
= APIC_DM_NMI
;
1466 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1467 if (!lapic_is_integrated()) /* 82489DX */
1468 value
|= APIC_LVT_LEVEL_TRIGGER
;
1469 apic_write(APIC_LVT1
, value
);
1471 #ifdef CONFIG_X86_MCE_INTEL
1472 /* Recheck CMCI information after local APIC is up on CPU #0 */
1478 void end_local_APIC_setup(void)
1482 #ifdef CONFIG_X86_32
1485 /* Disable the local apic timer */
1486 value
= apic_read(APIC_LVTT
);
1487 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1488 apic_write(APIC_LVTT
, value
);
1495 void __init
bsp_end_local_APIC_setup(void)
1497 end_local_APIC_setup();
1500 * Now that local APIC setup is completed for BP, configure the fault
1501 * handling for interrupt remapping.
1503 irq_remap_enable_fault_handling();
1507 #ifdef CONFIG_X86_X2APIC
1509 * Need to disable xapic and x2apic at the same time and then enable xapic mode
1511 static inline void __disable_x2apic(u64 msr
)
1513 wrmsrl(MSR_IA32_APICBASE
,
1514 msr
& ~(X2APIC_ENABLE
| XAPIC_ENABLE
));
1515 wrmsrl(MSR_IA32_APICBASE
, msr
& ~X2APIC_ENABLE
);
1518 static __init
void disable_x2apic(void)
1522 if (!cpu_has_x2apic
)
1525 rdmsrl(MSR_IA32_APICBASE
, msr
);
1526 if (msr
& X2APIC_ENABLE
) {
1527 u32 x2apic_id
= read_apic_id();
1529 if (x2apic_id
>= 255)
1530 panic("Cannot disable x2apic, id: %08x\n", x2apic_id
);
1532 pr_info("Disabling x2apic\n");
1533 __disable_x2apic(msr
);
1536 clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC
);
1537 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
1540 x2apic_disabled
= 1;
1543 register_lapic_address(mp_lapic_addr
);
1547 void check_x2apic(void)
1549 if (x2apic_enabled()) {
1550 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1551 x2apic_preenabled
= x2apic_mode
= 1;
1555 void enable_x2apic(void)
1559 rdmsrl(MSR_IA32_APICBASE
, msr
);
1560 if (x2apic_disabled
) {
1561 __disable_x2apic(msr
);
1568 if (!(msr
& X2APIC_ENABLE
)) {
1569 printk_once(KERN_INFO
"Enabling x2apic\n");
1570 wrmsrl(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
);
1573 #endif /* CONFIG_X86_X2APIC */
1575 int __init
enable_IR(void)
1577 #ifdef CONFIG_IRQ_REMAP
1578 if (!irq_remapping_supported()) {
1579 pr_debug("intr-remapping not supported\n");
1583 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1584 pr_info("Skipped enabling intr-remap because of skipping "
1589 return irq_remapping_enable();
1594 void __init
enable_IR_x2apic(void)
1596 unsigned long flags
;
1597 int ret
, x2apic_enabled
= 0;
1598 int hardware_init_ret
;
1600 /* Make sure irq_remap_ops are initialized */
1601 setup_irq_remapping_ops();
1603 hardware_init_ret
= irq_remapping_prepare();
1604 if (hardware_init_ret
&& !x2apic_supported())
1607 ret
= save_ioapic_entries();
1609 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1613 local_irq_save(flags
);
1614 legacy_pic
->mask_all();
1615 mask_ioapic_entries();
1617 if (x2apic_preenabled
&& nox2apic
)
1620 if (hardware_init_ret
)
1625 if (!x2apic_supported())
1629 /* IR is required if there is APIC ID > 255 even when running
1632 if (max_physical_apicid
> 255 ||
1633 !hypervisor_x2apic_available()) {
1634 if (x2apic_preenabled
)
1639 * without IR all CPUs can be addressed by IOAPIC/MSI
1640 * only in physical mode
1642 x2apic_force_phys();
1645 if (ret
== IRQ_REMAP_XAPIC_MODE
) {
1646 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
1652 if (x2apic_supported() && !x2apic_mode
) {
1655 pr_info("Enabled x2apic\n");
1659 if (ret
< 0) /* IR enabling failed */
1660 restore_ioapic_entries();
1661 legacy_pic
->restore_mask();
1662 local_irq_restore(flags
);
1665 #ifdef CONFIG_X86_64
1667 * Detect and enable local APICs on non-SMP boards.
1668 * Original code written by Keir Fraser.
1669 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1670 * not correctly set up (usually the APIC timer won't work etc.)
1672 static int __init
detect_init_APIC(void)
1674 if (!cpu_has_apic
) {
1675 pr_info("No local APIC present\n");
1679 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1684 static int __init
apic_verify(void)
1689 * The APIC feature bit should now be enabled
1692 features
= cpuid_edx(1);
1693 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1694 pr_warning("Could not enable APIC!\n");
1697 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1698 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1700 /* The BIOS may have set up the APIC at some other address */
1701 if (boot_cpu_data
.x86
>= 6) {
1702 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1703 if (l
& MSR_IA32_APICBASE_ENABLE
)
1704 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1707 pr_info("Found and enabled local APIC!\n");
1711 int __init
apic_force_enable(unsigned long addr
)
1719 * Some BIOSes disable the local APIC in the APIC_BASE
1720 * MSR. This can only be done in software for Intel P6 or later
1721 * and AMD K7 (Model > 1) or later.
1723 if (boot_cpu_data
.x86
>= 6) {
1724 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1725 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1726 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1727 l
&= ~MSR_IA32_APICBASE_BASE
;
1728 l
|= MSR_IA32_APICBASE_ENABLE
| addr
;
1729 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1730 enabled_via_apicbase
= 1;
1733 return apic_verify();
1737 * Detect and initialize APIC
1739 static int __init
detect_init_APIC(void)
1741 /* Disabled by kernel option? */
1745 switch (boot_cpu_data
.x86_vendor
) {
1746 case X86_VENDOR_AMD
:
1747 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1748 (boot_cpu_data
.x86
>= 15))
1751 case X86_VENDOR_INTEL
:
1752 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1753 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1760 if (!cpu_has_apic
) {
1762 * Over-ride BIOS and try to enable the local APIC only if
1763 * "lapic" specified.
1765 if (!force_enable_local_apic
) {
1766 pr_info("Local APIC disabled by BIOS -- "
1767 "you can enable it with \"lapic\"\n");
1770 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE
))
1782 pr_info("No local APIC present or hardware disabled\n");
1788 * init_apic_mappings - initialize APIC mappings
1790 void __init
init_apic_mappings(void)
1792 unsigned int new_apicid
;
1795 boot_cpu_physical_apicid
= read_apic_id();
1799 /* If no local APIC can be found return early */
1800 if (!smp_found_config
&& detect_init_APIC()) {
1801 /* lets NOP'ify apic operations */
1802 pr_info("APIC: disable apic facility\n");
1805 apic_phys
= mp_lapic_addr
;
1808 * acpi lapic path already maps that address in
1809 * acpi_register_lapic_address()
1811 if (!acpi_lapic
&& !smp_found_config
)
1812 register_lapic_address(apic_phys
);
1816 * Fetch the APIC ID of the BSP in case we have a
1817 * default configuration (or the MP table is broken).
1819 new_apicid
= read_apic_id();
1820 if (boot_cpu_physical_apicid
!= new_apicid
) {
1821 boot_cpu_physical_apicid
= new_apicid
;
1823 * yeah -- we lie about apic_version
1824 * in case if apic was disabled via boot option
1825 * but it's not a problem for SMP compiled kernel
1826 * since smp_sanity_check is prepared for such a case
1827 * and disable smp mode
1829 apic_version
[new_apicid
] =
1830 GET_APIC_VERSION(apic_read(APIC_LVR
));
1834 void __init
register_lapic_address(unsigned long address
)
1836 mp_lapic_addr
= address
;
1839 set_fixmap_nocache(FIX_APIC_BASE
, address
);
1840 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1841 APIC_BASE
, mp_lapic_addr
);
1843 if (boot_cpu_physical_apicid
== -1U) {
1844 boot_cpu_physical_apicid
= read_apic_id();
1845 apic_version
[boot_cpu_physical_apicid
] =
1846 GET_APIC_VERSION(apic_read(APIC_LVR
));
1851 * This initializes the IO-APIC and APIC hardware if this is
1854 int apic_version
[MAX_LOCAL_APIC
];
1856 int __init
APIC_init_uniprocessor(void)
1859 pr_info("Apic disabled\n");
1862 #ifdef CONFIG_X86_64
1863 if (!cpu_has_apic
) {
1865 pr_info("Apic disabled by BIOS\n");
1869 if (!smp_found_config
&& !cpu_has_apic
)
1873 * Complain if the BIOS pretends there is one.
1875 if (!cpu_has_apic
&&
1876 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1877 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1878 boot_cpu_physical_apicid
);
1883 default_setup_apic_routing();
1885 verify_local_APIC();
1888 #ifdef CONFIG_X86_64
1889 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1892 * Hack: In case of kdump, after a crash, kernel might be booting
1893 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1894 * might be zero if read from MP tables. Get it from LAPIC.
1896 # ifdef CONFIG_CRASH_DUMP
1897 boot_cpu_physical_apicid
= read_apic_id();
1900 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1903 #ifdef CONFIG_X86_IO_APIC
1905 * Now enable IO-APICs, actually call clear_IO_APIC
1906 * We need clear_IO_APIC before enabling error vector
1908 if (!skip_ioapic_setup
&& nr_ioapics
)
1912 bsp_end_local_APIC_setup();
1914 #ifdef CONFIG_X86_IO_APIC
1915 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1922 x86_init
.timers
.setup_percpu_clockev();
1927 * Local APIC interrupts
1931 * This interrupt should _never_ happen with our APIC/SMP architecture
1933 static inline void __smp_spurious_interrupt(void)
1938 * Check if this really is a spurious interrupt and ACK it
1939 * if it is a vectored one. Just in case...
1940 * Spurious interrupts should not be ACKed.
1942 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1943 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1946 inc_irq_stat(irq_spurious_count
);
1948 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1949 pr_info("spurious APIC interrupt on CPU#%d, "
1950 "should never happen.\n", smp_processor_id());
1953 __visible
void smp_spurious_interrupt(struct pt_regs
*regs
)
1956 __smp_spurious_interrupt();
1960 __visible
void smp_trace_spurious_interrupt(struct pt_regs
*regs
)
1963 trace_spurious_apic_entry(SPURIOUS_APIC_VECTOR
);
1964 __smp_spurious_interrupt();
1965 trace_spurious_apic_exit(SPURIOUS_APIC_VECTOR
);
1970 * This interrupt should never happen with our APIC/SMP architecture
1972 static inline void __smp_error_interrupt(struct pt_regs
*regs
)
1976 static const char * const error_interrupt_reason
[] = {
1977 "Send CS error", /* APIC Error Bit 0 */
1978 "Receive CS error", /* APIC Error Bit 1 */
1979 "Send accept error", /* APIC Error Bit 2 */
1980 "Receive accept error", /* APIC Error Bit 3 */
1981 "Redirectable IPI", /* APIC Error Bit 4 */
1982 "Send illegal vector", /* APIC Error Bit 5 */
1983 "Received illegal vector", /* APIC Error Bit 6 */
1984 "Illegal register address", /* APIC Error Bit 7 */
1987 /* First tickle the hardware, only then report what went on. -- REW */
1988 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1989 apic_write(APIC_ESR
, 0);
1990 v
= apic_read(APIC_ESR
);
1992 atomic_inc(&irq_err_count
);
1994 apic_printk(APIC_DEBUG
, KERN_DEBUG
"APIC error on CPU%d: %02x",
1995 smp_processor_id(), v
);
2000 apic_printk(APIC_DEBUG
, KERN_CONT
" : %s", error_interrupt_reason
[i
]);
2005 apic_printk(APIC_DEBUG
, KERN_CONT
"\n");
2009 __visible
void smp_error_interrupt(struct pt_regs
*regs
)
2012 __smp_error_interrupt(regs
);
2016 __visible
void smp_trace_error_interrupt(struct pt_regs
*regs
)
2019 trace_error_apic_entry(ERROR_APIC_VECTOR
);
2020 __smp_error_interrupt(regs
);
2021 trace_error_apic_exit(ERROR_APIC_VECTOR
);
2026 * connect_bsp_APIC - attach the APIC to the interrupt system
2028 void __init
connect_bsp_APIC(void)
2030 #ifdef CONFIG_X86_32
2033 * Do not trust the local APIC being empty at bootup.
2037 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2038 * local APIC to INT and NMI lines.
2040 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
2041 "enabling APIC mode.\n");
2048 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2049 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2051 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2054 void disconnect_bsp_APIC(int virt_wire_setup
)
2058 #ifdef CONFIG_X86_32
2061 * Put the board back into PIC mode (has an effect only on
2062 * certain older boards). Note that APIC interrupts, including
2063 * IPIs, won't work beyond this point! The only exception are
2066 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
2067 "entering PIC mode.\n");
2073 /* Go back to Virtual Wire compatibility mode */
2075 /* For the spurious interrupt use vector F, and enable it */
2076 value
= apic_read(APIC_SPIV
);
2077 value
&= ~APIC_VECTOR_MASK
;
2078 value
|= APIC_SPIV_APIC_ENABLED
;
2080 apic_write(APIC_SPIV
, value
);
2082 if (!virt_wire_setup
) {
2084 * For LVT0 make it edge triggered, active high,
2085 * external and enabled
2087 value
= apic_read(APIC_LVT0
);
2088 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
2089 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
2090 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
2091 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
2092 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
2093 apic_write(APIC_LVT0
, value
);
2096 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
2100 * For LVT1 make it edge triggered, active high,
2103 value
= apic_read(APIC_LVT1
);
2104 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
2105 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
2106 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
2107 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
2108 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
2109 apic_write(APIC_LVT1
, value
);
2112 int generic_processor_info(int apicid
, int version
)
2114 int cpu
, max
= nr_cpu_ids
;
2115 bool boot_cpu_detected
= physid_isset(boot_cpu_physical_apicid
,
2116 phys_cpu_present_map
);
2119 * boot_cpu_physical_apicid is designed to have the apicid
2120 * returned by read_apic_id(), i.e, the apicid of the
2121 * currently booting-up processor. However, on some platforms,
2122 * it is temporarily modified by the apicid reported as BSP
2123 * through MP table. Concretely:
2125 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2126 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2128 * This function is executed with the modified
2129 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2130 * parameter doesn't work to disable APs on kdump 2nd kernel.
2132 * Since fixing handling of boot_cpu_physical_apicid requires
2133 * another discussion and tests on each platform, we leave it
2134 * for now and here we use read_apic_id() directly in this
2135 * function, generic_processor_info().
2137 if (disabled_cpu_apicid
!= BAD_APICID
&&
2138 disabled_cpu_apicid
!= read_apic_id() &&
2139 disabled_cpu_apicid
== apicid
) {
2140 int thiscpu
= num_processors
+ disabled_cpus
;
2142 pr_warning("APIC: Disabling requested cpu."
2143 " Processor %d/0x%x ignored.\n",
2151 * If boot cpu has not been detected yet, then only allow upto
2152 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2154 if (!boot_cpu_detected
&& num_processors
>= nr_cpu_ids
- 1 &&
2155 apicid
!= boot_cpu_physical_apicid
) {
2156 int thiscpu
= max
+ disabled_cpus
- 1;
2159 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
2160 " reached. Keeping one slot for boot cpu."
2161 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
2167 if (num_processors
>= nr_cpu_ids
) {
2168 int thiscpu
= max
+ disabled_cpus
;
2171 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
2172 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
2179 if (apicid
== boot_cpu_physical_apicid
) {
2181 * x86_bios_cpu_apicid is required to have processors listed
2182 * in same order as logical cpu numbers. Hence the first
2183 * entry is BSP, and so on.
2184 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2189 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
2194 if (version
== 0x0) {
2195 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2199 apic_version
[apicid
] = version
;
2201 if (version
!= apic_version
[boot_cpu_physical_apicid
]) {
2202 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2203 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
2206 physid_set(apicid
, phys_cpu_present_map
);
2207 if (apicid
> max_physical_apicid
)
2208 max_physical_apicid
= apicid
;
2210 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2211 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
2212 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
2214 #ifdef CONFIG_X86_32
2215 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
2216 apic
->x86_32_early_logical_apicid(cpu
);
2218 set_cpu_possible(cpu
, true);
2219 set_cpu_present(cpu
, true);
2224 int hard_smp_processor_id(void)
2226 return read_apic_id();
2229 void default_init_apic_ldr(void)
2233 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
2234 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
2235 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2236 apic_write(APIC_LDR
, val
);
2239 int default_cpu_mask_to_apicid_and(const struct cpumask
*cpumask
,
2240 const struct cpumask
*andmask
,
2241 unsigned int *apicid
)
2245 for_each_cpu_and(cpu
, cpumask
, andmask
) {
2246 if (cpumask_test_cpu(cpu
, cpu_online_mask
))
2250 if (likely(cpu
< nr_cpu_ids
)) {
2251 *apicid
= per_cpu(x86_cpu_to_apicid
, cpu
);
2259 * Override the generic EOI implementation with an optimized version.
2260 * Only called during early boot when only one CPU is active and with
2261 * interrupts disabled, so we know this does not race with actual APIC driver
2264 void __init
apic_set_eoi_write(void (*eoi_write
)(u32 reg
, u32 v
))
2268 for (drv
= __apicdrivers
; drv
< __apicdrivers_end
; drv
++) {
2269 /* Should happen once for each apic */
2270 WARN_ON((*drv
)->eoi_write
== eoi_write
);
2271 (*drv
)->eoi_write
= eoi_write
;
2282 * 'active' is true if the local APIC was enabled by us and
2283 * not the BIOS; this signifies that we are also responsible
2284 * for disabling it before entering apm/acpi suspend
2287 /* r/w apic fields */
2288 unsigned int apic_id
;
2289 unsigned int apic_taskpri
;
2290 unsigned int apic_ldr
;
2291 unsigned int apic_dfr
;
2292 unsigned int apic_spiv
;
2293 unsigned int apic_lvtt
;
2294 unsigned int apic_lvtpc
;
2295 unsigned int apic_lvt0
;
2296 unsigned int apic_lvt1
;
2297 unsigned int apic_lvterr
;
2298 unsigned int apic_tmict
;
2299 unsigned int apic_tdcr
;
2300 unsigned int apic_thmr
;
2303 static int lapic_suspend(void)
2305 unsigned long flags
;
2308 if (!apic_pm_state
.active
)
2311 maxlvt
= lapic_get_maxlvt();
2313 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
2314 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
2315 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
2316 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
2317 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
2318 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2320 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2321 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2322 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2323 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2324 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2325 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2326 #ifdef CONFIG_X86_THERMAL_VECTOR
2328 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2331 local_irq_save(flags
);
2332 disable_local_APIC();
2334 irq_remapping_disable();
2336 local_irq_restore(flags
);
2340 static void lapic_resume(void)
2343 unsigned long flags
;
2346 if (!apic_pm_state
.active
)
2349 local_irq_save(flags
);
2352 * IO-APIC and PIC have their own resume routines.
2353 * We just mask them here to make sure the interrupt
2354 * subsystem is completely quiet while we enable x2apic
2355 * and interrupt-remapping.
2357 mask_ioapic_entries();
2358 legacy_pic
->mask_all();
2364 * Make sure the APICBASE points to the right address
2366 * FIXME! This will be wrong if we ever support suspend on
2367 * SMP! We'll need to do this as part of the CPU restore!
2369 if (boot_cpu_data
.x86
>= 6) {
2370 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2371 l
&= ~MSR_IA32_APICBASE_BASE
;
2372 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2373 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2377 maxlvt
= lapic_get_maxlvt();
2378 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2379 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2380 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2381 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2382 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2383 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2384 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2385 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2386 #if defined(CONFIG_X86_MCE_INTEL)
2388 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2391 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2392 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2393 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2394 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2395 apic_write(APIC_ESR
, 0);
2396 apic_read(APIC_ESR
);
2397 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2398 apic_write(APIC_ESR
, 0);
2399 apic_read(APIC_ESR
);
2401 irq_remapping_reenable(x2apic_mode
);
2403 local_irq_restore(flags
);
2407 * This device has no shutdown method - fully functioning local APICs
2408 * are needed on every CPU up until machine_halt/restart/poweroff.
2411 static struct syscore_ops lapic_syscore_ops
= {
2412 .resume
= lapic_resume
,
2413 .suspend
= lapic_suspend
,
2416 static void apic_pm_activate(void)
2418 apic_pm_state
.active
= 1;
2421 static int __init
init_lapic_sysfs(void)
2423 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2425 register_syscore_ops(&lapic_syscore_ops
);
2430 /* local apic needs to resume before other devices access its registers. */
2431 core_initcall(init_lapic_sysfs
);
2433 #else /* CONFIG_PM */
2435 static void apic_pm_activate(void) { }
2437 #endif /* CONFIG_PM */
2439 #ifdef CONFIG_X86_64
2441 static int multi_checked
;
2444 static int set_multi(const struct dmi_system_id
*d
)
2448 pr_info("APIC: %s detected, Multi Chassis\n", d
->ident
);
2453 static const struct dmi_system_id multi_dmi_table
[] = {
2455 .callback
= set_multi
,
2456 .ident
= "IBM System Summit2",
2458 DMI_MATCH(DMI_SYS_VENDOR
, "IBM"),
2459 DMI_MATCH(DMI_PRODUCT_NAME
, "Summit2"),
2465 static void dmi_check_multi(void)
2470 dmi_check_system(multi_dmi_table
);
2475 * apic_is_clustered_box() -- Check if we can expect good TSC
2477 * Thus far, the major user of this is IBM's Summit2 series:
2478 * Clustered boxes may have unsynced TSC problems if they are
2480 * Use DMI to check them
2482 int apic_is_clustered_box(void)
2490 * APIC command line parameters
2492 static int __init
setup_disableapic(char *arg
)
2495 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2498 early_param("disableapic", setup_disableapic
);
2500 /* same as disableapic, for compatibility */
2501 static int __init
setup_nolapic(char *arg
)
2503 return setup_disableapic(arg
);
2505 early_param("nolapic", setup_nolapic
);
2507 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2509 local_apic_timer_c2_ok
= 1;
2512 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2514 static int __init
parse_disable_apic_timer(char *arg
)
2516 disable_apic_timer
= 1;
2519 early_param("noapictimer", parse_disable_apic_timer
);
2521 static int __init
parse_nolapic_timer(char *arg
)
2523 disable_apic_timer
= 1;
2526 early_param("nolapic_timer", parse_nolapic_timer
);
2528 static int __init
apic_set_verbosity(char *arg
)
2531 #ifdef CONFIG_X86_64
2532 skip_ioapic_setup
= 0;
2538 if (strcmp("debug", arg
) == 0)
2539 apic_verbosity
= APIC_DEBUG
;
2540 else if (strcmp("verbose", arg
) == 0)
2541 apic_verbosity
= APIC_VERBOSE
;
2543 pr_warning("APIC Verbosity level %s not recognised"
2544 " use apic=verbose or apic=debug\n", arg
);
2550 early_param("apic", apic_set_verbosity
);
2552 static int __init
lapic_insert_resource(void)
2557 /* Put local APIC into the resource map. */
2558 lapic_resource
.start
= apic_phys
;
2559 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2560 insert_resource(&iomem_resource
, &lapic_resource
);
2566 * need call insert after e820_reserve_resources()
2567 * that is using request_resource
2569 late_initcall(lapic_insert_resource
);
2571 static int __init
apic_set_disabled_cpu_apicid(char *arg
)
2573 if (!arg
|| !get_option(&arg
, &disabled_cpu_apicid
))
2578 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid
);