2 * Pentium 4/Xeon CPU on demand clock modulation/speed scaling
3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
4 * (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
5 * (C) 2002 Arjan van de Ven <arjanv@redhat.com>
6 * (C) 2002 Tora T. Engstad
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 * The author(s) of this software shall not be held liable for damages
15 * of any nature resulting due to the use of this software. This
16 * software is provided AS-IS with no warranties.
18 * Date Errata Description
19 * 20020525 N44, O17 12.5% or 25% DC causes lockup
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/smp.h>
27 #include <linux/cpufreq.h>
28 #include <linux/cpumask.h>
29 #include <linux/timex.h>
31 #include <asm/processor.h>
33 #include <asm/timer.h>
35 #include "speedstep-lib.h"
37 #define PFX "p4-clockmod: "
38 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
42 * Duty Cycle (3bits), note DC_DISABLE is not specified in
43 * intel docs i just use it to mean disable
46 DC_RESV
, DC_DFLT
, DC_25PT
, DC_38PT
, DC_50PT
,
47 DC_64PT
, DC_75PT
, DC_88PT
, DC_DISABLE
53 static int has_N44_O17_errata
[NR_CPUS
];
54 static unsigned int stock_freq
;
55 static struct cpufreq_driver p4clockmod_driver
;
56 static unsigned int cpufreq_p4_get(unsigned int cpu
);
58 static int cpufreq_p4_setdc(unsigned int cpu
, unsigned int newstate
)
62 if (!cpu_online(cpu
) ||
63 (newstate
> DC_DISABLE
) || (newstate
== DC_RESV
))
66 rdmsr_on_cpu(cpu
, MSR_IA32_THERM_STATUS
, &l
, &h
);
69 dprintk("CPU#%d currently thermal throttled\n", cpu
);
71 if (has_N44_O17_errata
[cpu
] &&
72 (newstate
== DC_25PT
|| newstate
== DC_DFLT
))
75 rdmsr_on_cpu(cpu
, MSR_IA32_THERM_CONTROL
, &l
, &h
);
76 if (newstate
== DC_DISABLE
) {
77 dprintk("CPU#%d disabling modulation\n", cpu
);
78 wrmsr_on_cpu(cpu
, MSR_IA32_THERM_CONTROL
, l
& ~(1<<4), h
);
80 dprintk("CPU#%d setting duty cycle to %d%%\n",
81 cpu
, ((125 * newstate
) / 10));
82 /* bits 63 - 5 : reserved
83 * bit 4 : enable/disable
84 * bits 3-1 : duty cycle
88 l
= l
| (1<<4) | ((newstate
& 0x7)<<1);
89 wrmsr_on_cpu(cpu
, MSR_IA32_THERM_CONTROL
, l
, h
);
96 static struct cpufreq_frequency_table p4clockmod_table
[] = {
97 {DC_RESV
, CPUFREQ_ENTRY_INVALID
},
106 {DC_RESV
, CPUFREQ_TABLE_END
},
110 static int cpufreq_p4_target(struct cpufreq_policy
*policy
,
111 unsigned int target_freq
,
112 unsigned int relation
)
114 unsigned int newstate
= DC_RESV
;
115 struct cpufreq_freqs freqs
;
118 if (cpufreq_frequency_table_target(policy
, &p4clockmod_table
[0],
119 target_freq
, relation
, &newstate
))
122 freqs
.old
= cpufreq_p4_get(policy
->cpu
);
123 freqs
.new = stock_freq
* p4clockmod_table
[newstate
].index
/ 8;
125 if (freqs
.new == freqs
.old
)
129 for_each_cpu(i
, policy
->cpus
) {
131 cpufreq_notify_transition(&freqs
, CPUFREQ_PRECHANGE
);
134 /* run on each logical CPU,
135 * see section 13.15.3 of IA32 Intel Architecture Software
136 * Developer's Manual, Volume 3
138 for_each_cpu(i
, policy
->cpus
)
139 cpufreq_p4_setdc(i
, p4clockmod_table
[newstate
].index
);
142 for_each_cpu(i
, policy
->cpus
) {
144 cpufreq_notify_transition(&freqs
, CPUFREQ_POSTCHANGE
);
151 static int cpufreq_p4_verify(struct cpufreq_policy
*policy
)
153 return cpufreq_frequency_table_verify(policy
, &p4clockmod_table
[0]);
157 static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86
*c
)
159 if (c
->x86
== 0x06) {
160 if (cpu_has(c
, X86_FEATURE_EST
))
161 printk(KERN_WARNING PFX
"Warning: EST-capable CPU "
162 "detected. The acpi-cpufreq module offers "
163 "voltage scaling in addition of frequency "
164 "scaling. You should use that instead of "
165 "p4-clockmod, if possible.\n");
166 switch (c
->x86_model
) {
167 case 0x0E: /* Core */
168 case 0x0F: /* Core Duo */
169 case 0x16: /* Celeron Core */
170 case 0x1C: /* Atom */
171 p4clockmod_driver
.flags
|= CPUFREQ_CONST_LOOPS
;
172 return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE
);
173 case 0x0D: /* Pentium M (Dothan) */
174 p4clockmod_driver
.flags
|= CPUFREQ_CONST_LOOPS
;
176 case 0x09: /* Pentium M (Banias) */
177 return speedstep_get_frequency(SPEEDSTEP_CPU_PM
);
182 if (!cpu_has(c
, X86_FEATURE_EST
))
183 printk(KERN_WARNING PFX
"Unknown CPU. "
184 "Please send an e-mail to "
185 "<cpufreq@vger.kernel.org>\n");
189 /* on P-4s, the TSC runs with constant frequency independent whether
190 * throttling is active or not. */
191 p4clockmod_driver
.flags
|= CPUFREQ_CONST_LOOPS
;
193 if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4M
) {
194 printk(KERN_WARNING PFX
"Warning: Pentium 4-M detected. "
195 "The speedstep-ich or acpi cpufreq modules offer "
196 "voltage scaling in addition of frequency scaling. "
197 "You should use either one instead of p4-clockmod, "
199 return speedstep_get_frequency(SPEEDSTEP_CPU_P4M
);
202 return speedstep_get_frequency(SPEEDSTEP_CPU_P4D
);
207 static int cpufreq_p4_cpu_init(struct cpufreq_policy
*policy
)
209 struct cpuinfo_x86
*c
= &cpu_data(policy
->cpu
);
214 cpumask_copy(policy
->cpus
, cpu_sibling_mask(policy
->cpu
));
217 /* Errata workaround */
218 cpuid
= (c
->x86
<< 8) | (c
->x86_model
<< 4) | c
->x86_mask
;
224 has_N44_O17_errata
[policy
->cpu
] = 1;
225 dprintk("has errata -- disabling low frequencies\n");
228 if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4D
&&
230 /* switch to maximum frequency and measure result */
231 cpufreq_p4_setdc(policy
->cpu
, DC_DISABLE
);
232 recalibrate_cpu_khz();
234 /* get max frequency */
235 stock_freq
= cpufreq_p4_get_frequency(c
);
240 for (i
= 1; (p4clockmod_table
[i
].frequency
!= CPUFREQ_TABLE_END
); i
++) {
241 if ((i
< 2) && (has_N44_O17_errata
[policy
->cpu
]))
242 p4clockmod_table
[i
].frequency
= CPUFREQ_ENTRY_INVALID
;
244 p4clockmod_table
[i
].frequency
= (stock_freq
* i
)/8;
246 cpufreq_frequency_table_get_attr(p4clockmod_table
, policy
->cpu
);
248 /* cpuinfo and default policy values */
250 /* the transition latency is set to be 1 higher than the maximum
251 * transition latency of the ondemand governor */
252 policy
->cpuinfo
.transition_latency
= 10000001;
253 policy
->cur
= stock_freq
;
255 return cpufreq_frequency_table_cpuinfo(policy
, &p4clockmod_table
[0]);
259 static int cpufreq_p4_cpu_exit(struct cpufreq_policy
*policy
)
261 cpufreq_frequency_table_put_attr(policy
->cpu
);
265 static unsigned int cpufreq_p4_get(unsigned int cpu
)
269 rdmsr_on_cpu(cpu
, MSR_IA32_THERM_CONTROL
, &l
, &h
);
278 return stock_freq
* l
/ 8;
283 static struct freq_attr
*p4clockmod_attr
[] = {
284 &cpufreq_freq_attr_scaling_available_freqs
,
288 static struct cpufreq_driver p4clockmod_driver
= {
289 .verify
= cpufreq_p4_verify
,
290 .target
= cpufreq_p4_target
,
291 .init
= cpufreq_p4_cpu_init
,
292 .exit
= cpufreq_p4_cpu_exit
,
293 .get
= cpufreq_p4_get
,
294 .name
= "p4-clockmod",
295 .owner
= THIS_MODULE
,
296 .attr
= p4clockmod_attr
,
300 static int __init
cpufreq_p4_init(void)
302 struct cpuinfo_x86
*c
= &cpu_data(0);
306 * THERM_CONTROL is architectural for IA32 now, so
307 * we can rely on the capability checks
309 if (c
->x86_vendor
!= X86_VENDOR_INTEL
)
312 if (!test_cpu_cap(c
, X86_FEATURE_ACPI
) ||
313 !test_cpu_cap(c
, X86_FEATURE_ACC
))
316 ret
= cpufreq_register_driver(&p4clockmod_driver
);
318 printk(KERN_INFO PFX
"P4/Xeon(TM) CPU On-Demand Clock "
319 "Modulation available\n");
325 static void __exit
cpufreq_p4_exit(void)
327 cpufreq_unregister_driver(&p4clockmod_driver
);
331 MODULE_AUTHOR("Zwane Mwaikambo <zwane@commfireservices.com>");
332 MODULE_DESCRIPTION("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
333 MODULE_LICENSE("GPL");
335 late_initcall(cpufreq_p4_init
);
336 module_exit(cpufreq_p4_exit
);