2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
71 #include <asm/fpu/internal.h>
72 #include <asm/setup.h>
73 #include <asm/uv/uv.h>
74 #include <linux/mc146818rtc.h>
75 #include <asm/i8259.h>
76 #include <asm/realmode.h>
79 /* Number of siblings per CPU package */
80 int smp_num_siblings
= 1;
81 EXPORT_SYMBOL(smp_num_siblings
);
83 /* Last level cache ID of each logical CPU */
84 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
86 /* representing HT siblings of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
90 /* representing HT and core siblings of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
92 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
96 /* Per CPU bogomips and other parameters */
97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
98 EXPORT_PER_CPU_SYMBOL(cpu_info
);
100 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
104 spin_lock_irqsave(&rtc_lock
, flags
);
105 CMOS_WRITE(0xa, 0xf);
106 spin_unlock_irqrestore(&rtc_lock
, flags
);
109 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
112 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
117 static inline void smpboot_restore_warm_reset_vector(void)
122 * Install writable page 0 entry to set BIOS data area.
127 * Paranoid: Set warm reset code and vector here back
130 spin_lock_irqsave(&rtc_lock
, flags
);
132 spin_unlock_irqrestore(&rtc_lock
, flags
);
134 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
138 * Report back to the Boot Processor during boot time or to the caller processor
141 static void smp_callin(void)
146 * If waken up by an INIT in an 82489DX configuration
147 * cpu_callout_mask guarantees we don't get here before
148 * an INIT_deassert IPI reaches our local APIC, so it is
149 * now safe to touch our local APIC.
151 cpuid
= smp_processor_id();
154 * (This works even if the APIC is not enabled.)
156 phys_id
= read_apic_id();
159 * the boot CPU has finished the init stage and is spinning
160 * on callin_map until we finish. We are free to set up this
161 * CPU, first the APIC. (this is probably redundant on most
167 * Save our processor parameters. Note: this information
168 * is needed for clock calibration.
170 smp_store_cpu_info(cpuid
);
174 * Update loops_per_jiffy in cpu_data. Previous call to
175 * smp_store_cpu_info() stored a value that is close but not as
176 * accurate as the value just calculated.
179 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
180 pr_debug("Stack at about %p\n", &cpuid
);
183 * This must be done before setting cpu_online_mask
184 * or calling notify_cpu_starting.
186 set_cpu_sibling_map(raw_smp_processor_id());
189 notify_cpu_starting(cpuid
);
192 * Allow the master to continue.
194 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
197 static int cpu0_logical_apicid
;
198 static int enable_start_cpu0
;
200 * Activate a secondary processor.
202 static void notrace
start_secondary(void *unused
)
205 * Don't put *anything* before cpu_init(), SMP booting is too
206 * fragile that we want to limit the things done here to the
207 * most necessary things.
210 x86_cpuinit
.early_percpu_clock_init();
214 enable_start_cpu0
= 0;
217 /* switch away from the initial page table */
218 load_cr3(swapper_pg_dir
);
222 /* otherwise gcc will move up smp_processor_id before the cpu_init */
225 * Check TSC synchronization with the BP:
227 check_tsc_sync_target();
230 * Lock vector_lock and initialize the vectors on this cpu
231 * before setting the cpu online. We must set it online with
232 * vector_lock held to prevent a concurrent setup/teardown
233 * from seeing a half valid vector space.
236 setup_vector_irq(smp_processor_id());
237 set_cpu_online(smp_processor_id(), true);
238 unlock_vector_lock();
239 cpu_set_state_online(smp_processor_id());
240 x86_platform
.nmi_init();
242 /* enable local interrupts */
245 /* to prevent fake stack check failure in clock setup */
246 boot_init_stack_canary();
248 x86_cpuinit
.setup_percpu_clockev();
251 cpu_startup_entry(CPUHP_ONLINE
);
254 void __init
smp_store_boot_cpu_info(void)
256 int id
= 0; /* CPU 0 */
257 struct cpuinfo_x86
*c
= &cpu_data(id
);
264 * The bootstrap kernel entry code has set these up. Save them for
267 void smp_store_cpu_info(int id
)
269 struct cpuinfo_x86
*c
= &cpu_data(id
);
274 * During boot time, CPU0 has this setup already. Save the info when
275 * bringing up AP or offlined CPU0.
277 identify_secondary_cpu(c
);
281 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
283 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
285 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
289 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
291 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
293 return !WARN_ONCE(!topology_same_node(c
, o
),
294 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
295 "[node: %d != %d]. Ignoring dependency.\n",
296 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
299 #define link_mask(mfunc, c1, c2) \
301 cpumask_set_cpu((c1), mfunc(c2)); \
302 cpumask_set_cpu((c2), mfunc(c1)); \
305 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
307 if (cpu_has_topoext
) {
308 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
310 if (c
->phys_proc_id
== o
->phys_proc_id
&&
311 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
) &&
312 c
->compute_unit_id
== o
->compute_unit_id
)
313 return topology_sane(c
, o
, "smt");
315 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
316 c
->cpu_core_id
== o
->cpu_core_id
) {
317 return topology_sane(c
, o
, "smt");
323 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
325 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
327 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
328 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
329 return topology_sane(c
, o
, "llc");
335 * Unlike the other levels, we do not enforce keeping a
336 * multicore group inside a NUMA node. If this happens, we will
337 * discard the MC level of the topology later.
339 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
341 if (c
->phys_proc_id
== o
->phys_proc_id
)
346 static struct sched_domain_topology_level numa_inside_package_topology
[] = {
347 #ifdef CONFIG_SCHED_SMT
348 { cpu_smt_mask
, cpu_smt_flags
, SD_INIT_NAME(SMT
) },
350 #ifdef CONFIG_SCHED_MC
351 { cpu_coregroup_mask
, cpu_core_flags
, SD_INIT_NAME(MC
) },
356 * set_sched_topology() sets the topology internal to a CPU. The
357 * NUMA topologies are layered on top of it to build the full
360 * If NUMA nodes are observed to occur within a CPU package, this
361 * function should be called. It forces the sched domain code to
362 * only use the SMT level for the CPU portion of the topology.
363 * This essentially falls back to relying on NUMA information
364 * from the SRAT table to describe the entire system topology
365 * (except for hyperthreads).
367 static void primarily_use_numa_for_topology(void)
369 set_sched_topology(numa_inside_package_topology
);
372 void set_cpu_sibling_map(int cpu
)
374 bool has_smt
= smp_num_siblings
> 1;
375 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
376 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
377 struct cpuinfo_x86
*o
;
380 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
383 cpumask_set_cpu(cpu
, topology_sibling_cpumask(cpu
));
384 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
385 cpumask_set_cpu(cpu
, topology_core_cpumask(cpu
));
390 for_each_cpu(i
, cpu_sibling_setup_mask
) {
393 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
394 link_mask(topology_sibling_cpumask
, cpu
, i
);
396 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
397 link_mask(cpu_llc_shared_mask
, cpu
, i
);
402 * This needs a separate iteration over the cpus because we rely on all
403 * topology_sibling_cpumask links to be set-up.
405 for_each_cpu(i
, cpu_sibling_setup_mask
) {
408 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
))) {
409 link_mask(topology_core_cpumask
, cpu
, i
);
412 * Does this new cpu bringup a new core?
415 topology_sibling_cpumask(cpu
)) == 1) {
417 * for each core in package, increment
418 * the booted_cores for this new cpu
421 topology_sibling_cpumask(i
)) == i
)
424 * increment the core count for all
425 * the other cpus in this package
428 cpu_data(i
).booted_cores
++;
429 } else if (i
!= cpu
&& !c
->booted_cores
)
430 c
->booted_cores
= cpu_data(i
).booted_cores
;
432 if (match_die(c
, o
) && !topology_same_node(c
, o
))
433 primarily_use_numa_for_topology();
437 /* maps the cpu to the sched domain representing multi-core */
438 const struct cpumask
*cpu_coregroup_mask(int cpu
)
440 return cpu_llc_shared_mask(cpu
);
443 static void impress_friends(void)
446 unsigned long bogosum
= 0;
448 * Allow the user to impress friends.
450 pr_debug("Before bogomips\n");
451 for_each_possible_cpu(cpu
)
452 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
453 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
454 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
457 (bogosum
/(5000/HZ
))%100);
459 pr_debug("Before bogocount - setting activated=1\n");
462 void __inquire_remote_apic(int apicid
)
464 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
465 const char * const names
[] = { "ID", "VERSION", "SPIV" };
469 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
471 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
472 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
477 status
= safe_apic_wait_icr_idle();
479 pr_cont("a previous APIC delivery may have failed\n");
481 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
486 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
487 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
490 case APIC_ICR_RR_VALID
:
491 status
= apic_read(APIC_RRR
);
492 pr_cont("%08x\n", status
);
501 * The Multiprocessor Specification 1.4 (1997) example code suggests
502 * that there should be a 10ms delay between the BSP asserting INIT
503 * and de-asserting INIT, when starting a remote processor.
504 * But that slows boot and resume on modern processors, which include
505 * many cores and don't require that delay.
507 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
508 * Modern processor families are quirked to remove the delay entirely.
510 #define UDELAY_10MS_DEFAULT 10000
512 static unsigned int init_udelay
= UINT_MAX
;
514 static int __init
cpu_init_udelay(char *str
)
516 get_option(&str
, &init_udelay
);
520 early_param("cpu_init_udelay", cpu_init_udelay
);
522 static void __init
smp_quirk_init_udelay(void)
524 /* if cmdline changed it from default, leave it alone */
525 if (init_udelay
!= UINT_MAX
)
528 /* if modern processor, use no delay */
529 if (((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 6)) ||
530 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && (boot_cpu_data
.x86
>= 0xF))) {
534 /* else, use legacy delay */
535 init_udelay
= UDELAY_10MS_DEFAULT
;
539 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
540 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
541 * won't ... remember to clear down the APIC, etc later.
544 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
546 unsigned long send_status
, accept_status
= 0;
550 /* Boot on the stack */
551 /* Kick the second */
552 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
554 pr_debug("Waiting for send to finish...\n");
555 send_status
= safe_apic_wait_icr_idle();
558 * Give the other CPU some time to accept the IPI.
561 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
562 maxlvt
= lapic_get_maxlvt();
563 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
564 apic_write(APIC_ESR
, 0);
565 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
567 pr_debug("NMI sent\n");
570 pr_err("APIC never delivered???\n");
572 pr_err("APIC delivery error (%lx)\n", accept_status
);
574 return (send_status
| accept_status
);
578 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
580 unsigned long send_status
= 0, accept_status
= 0;
581 int maxlvt
, num_starts
, j
;
583 maxlvt
= lapic_get_maxlvt();
586 * Be paranoid about clearing APIC errors.
588 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
589 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
590 apic_write(APIC_ESR
, 0);
594 pr_debug("Asserting INIT\n");
597 * Turn INIT on target chip
602 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
605 pr_debug("Waiting for send to finish...\n");
606 send_status
= safe_apic_wait_icr_idle();
610 pr_debug("Deasserting INIT\n");
614 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
616 pr_debug("Waiting for send to finish...\n");
617 send_status
= safe_apic_wait_icr_idle();
622 * Should we send STARTUP IPIs ?
624 * Determine this based on the APIC version.
625 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
627 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
633 * Paravirt / VMI wants a startup IPI hook here to set up the
634 * target processor state.
636 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
640 * Run STARTUP IPI loop.
642 pr_debug("#startup loops: %d\n", num_starts
);
644 for (j
= 1; j
<= num_starts
; j
++) {
645 pr_debug("Sending STARTUP #%d\n", j
);
646 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
647 apic_write(APIC_ESR
, 0);
649 pr_debug("After apic_write\n");
656 /* Boot on the stack */
657 /* Kick the second */
658 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
662 * Give the other CPU some time to accept the IPI.
664 if (init_udelay
== 0)
669 pr_debug("Startup point 1\n");
671 pr_debug("Waiting for send to finish...\n");
672 send_status
= safe_apic_wait_icr_idle();
675 * Give the other CPU some time to accept the IPI.
677 if (init_udelay
== 0)
682 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
683 apic_write(APIC_ESR
, 0);
684 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
685 if (send_status
|| accept_status
)
688 pr_debug("After Startup\n");
691 pr_err("APIC never delivered???\n");
693 pr_err("APIC delivery error (%lx)\n", accept_status
);
695 return (send_status
| accept_status
);
698 void smp_announce(void)
700 int num_nodes
= num_online_nodes();
702 printk(KERN_INFO
"x86: Booted up %d node%s, %d CPUs\n",
703 num_nodes
, (num_nodes
> 1 ? "s" : ""), num_online_cpus());
706 /* reduce the number of lines printed when booting a large cpu count system */
707 static void announce_cpu(int cpu
, int apicid
)
709 static int current_node
= -1;
710 int node
= early_cpu_to_node(cpu
);
711 static int width
, node_width
;
714 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
717 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
720 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
722 if (system_state
== SYSTEM_BOOTING
) {
723 if (node
!= current_node
) {
724 if (current_node
> (-1))
728 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
729 node_width
- num_digits(node
), " ", node
);
732 /* Add padding for the BSP */
734 pr_cont("%*s", width
+ 1, " ");
736 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
739 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
743 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
747 cpu
= smp_processor_id();
748 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
755 * Wake up AP by INIT, INIT, STARTUP sequence.
757 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
758 * boot-strap code which is not a desired behavior for waking up BSP. To
759 * void the boot-strap code, wake up CPU0 by NMI instead.
761 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
762 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
763 * We'll change this code in the future to wake up hard offlined CPU0 if
764 * real platform and request are available.
767 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
768 int *cpu0_nmi_registered
)
776 * Wake up AP by INIT, INIT, STARTUP sequence.
779 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
784 * Wake up BSP by nmi.
786 * Register a NMI handler to help wake up CPU0.
788 boot_error
= register_nmi_handler(NMI_LOCAL
,
789 wakeup_cpu0_nmi
, 0, "wake_cpu0");
792 enable_start_cpu0
= 1;
793 *cpu0_nmi_registered
= 1;
794 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
795 id
= cpu0_logical_apicid
;
798 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
807 void common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
809 /* Just in case we booted with a single CPU. */
810 alternatives_enable_smp();
812 per_cpu(current_task
, cpu
) = idle
;
815 /* Stack for startup_32 can be just as for start_secondary onwards */
817 per_cpu(cpu_current_top_of_stack
, cpu
) =
818 (unsigned long)task_stack_page(idle
) + THREAD_SIZE
;
820 clear_tsk_thread_flag(idle
, TIF_FORK
);
821 initial_gs
= per_cpu_offset(cpu
);
826 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
827 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
828 * Returns zero if CPU booted OK, else error code from
829 * ->wakeup_secondary_cpu.
831 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
833 volatile u32
*trampoline_status
=
834 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
835 /* start_ip had better be page-aligned! */
836 unsigned long start_ip
= real_mode_header
->trampoline_start
;
838 unsigned long boot_error
= 0;
839 int cpu0_nmi_registered
= 0;
840 unsigned long timeout
;
842 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
843 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
845 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
846 initial_code
= (unsigned long)start_secondary
;
847 stack_start
= idle
->thread
.sp
;
850 * Enable the espfix hack for this CPU
852 #ifdef CONFIG_X86_ESPFIX64
856 /* So we see what's up */
857 announce_cpu(cpu
, apicid
);
860 * This grunge runs the startup process for
861 * the targeted processor.
864 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
866 pr_debug("Setting warm reset code and vector.\n");
868 smpboot_setup_warm_reset_vector(start_ip
);
870 * Be paranoid about clearing APIC errors.
872 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
873 apic_write(APIC_ESR
, 0);
879 * AP might wait on cpu_callout_mask in cpu_init() with
880 * cpu_initialized_mask set if previous attempt to online
881 * it timed-out. Clear cpu_initialized_mask so that after
882 * INIT/SIPI it could start with a clean state.
884 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
888 * Wake up a CPU in difference cases:
889 * - Use the method in the APIC driver if it's defined
891 * - Use an INIT boot APIC message for APs or NMI for BSP.
893 if (apic
->wakeup_secondary_cpu
)
894 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
896 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
897 &cpu0_nmi_registered
);
901 * Wait 10s total for first sign of life from AP
904 timeout
= jiffies
+ 10*HZ
;
905 while (time_before(jiffies
, timeout
)) {
906 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
908 * Tell AP to proceed with initialization
910 cpumask_set_cpu(cpu
, cpu_callout_mask
);
920 * Wait till AP completes initial initialization
922 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
924 * Allow other tasks to run while we wait for the
925 * AP to come online. This also gives a chance
926 * for the MTRR work(triggered by the AP coming online)
927 * to be completed in the stop machine context.
933 /* mark "stuck" area as not stuck */
934 *trampoline_status
= 0;
936 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
938 * Cleanup possible dangling ends...
940 smpboot_restore_warm_reset_vector();
943 * Clean up the nmi handler. Do this after the callin and callout sync
944 * to avoid impact of possible long unregister time.
946 if (cpu0_nmi_registered
)
947 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
952 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
954 int apicid
= apic
->cpu_present_to_apicid(cpu
);
958 WARN_ON(irqs_disabled());
960 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
962 if (apicid
== BAD_APICID
||
963 !physid_isset(apicid
, phys_cpu_present_map
) ||
964 !apic
->apic_id_valid(apicid
)) {
965 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
970 * Already booted CPU?
972 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
973 pr_debug("do_boot_cpu %d Already started\n", cpu
);
978 * Save current MTRR state in case it was changed since early boot
979 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
983 /* x86 CPUs take themselves offline, so delayed offline is OK. */
984 err
= cpu_check_up_prepare(cpu
);
985 if (err
&& err
!= -EBUSY
)
988 /* the FPU context is blank, nobody can own it */
989 __cpu_disable_lazy_restore(cpu
);
991 common_cpu_up(cpu
, tidle
);
994 * We have to walk the irq descriptors to setup the vector
995 * space for the cpu which comes online. Prevent irq
996 * alloc/free across the bringup.
1000 err
= do_boot_cpu(apicid
, cpu
, tidle
);
1003 irq_unlock_sparse();
1004 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
1009 * Check TSC synchronization with the AP (keep irqs disabled
1012 local_irq_save(flags
);
1013 check_tsc_sync_source(cpu
);
1014 local_irq_restore(flags
);
1016 while (!cpu_online(cpu
)) {
1018 touch_nmi_watchdog();
1021 irq_unlock_sparse();
1027 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1029 void arch_disable_smp_support(void)
1031 disable_ioapic_support();
1035 * Fall back to non SMP mode after errors.
1037 * RED-PEN audit/test this more. I bet there is more state messed up here.
1039 static __init
void disable_smp(void)
1041 pr_info("SMP disabled\n");
1043 disable_ioapic_support();
1045 init_cpu_present(cpumask_of(0));
1046 init_cpu_possible(cpumask_of(0));
1048 if (smp_found_config
)
1049 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1051 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1052 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1053 cpumask_set_cpu(0, topology_core_cpumask(0));
1064 * Various sanity checks.
1066 static int __init
smp_sanity_check(unsigned max_cpus
)
1070 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1071 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1075 pr_warn("More than 8 CPUs detected - skipping them\n"
1076 "Use CONFIG_X86_BIGSMP\n");
1079 for_each_present_cpu(cpu
) {
1081 set_cpu_present(cpu
, false);
1086 for_each_possible_cpu(cpu
) {
1088 set_cpu_possible(cpu
, false);
1096 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1097 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1098 hard_smp_processor_id());
1100 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1104 * If we couldn't find an SMP configuration at boot time,
1105 * get out of here now!
1107 if (!smp_found_config
&& !acpi_lapic
) {
1109 pr_notice("SMP motherboard not detected\n");
1110 return SMP_NO_CONFIG
;
1114 * Should not be necessary because the MP table should list the boot
1115 * CPU too, but we do it for the sake of robustness anyway.
1117 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1118 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1119 boot_cpu_physical_apicid
);
1120 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1125 * If we couldn't find a local APIC, then get out of here now!
1127 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
1129 if (!disable_apic
) {
1130 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1131 boot_cpu_physical_apicid
);
1132 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1138 * If SMP should be disabled, then really disable it!
1141 pr_info("SMP mode deactivated\n");
1142 return SMP_FORCE_UP
;
1148 static void __init
smp_cpu_index_default(void)
1151 struct cpuinfo_x86
*c
;
1153 for_each_possible_cpu(i
) {
1155 /* mark all to hotplug */
1156 c
->cpu_index
= nr_cpu_ids
;
1161 * Prepare for SMP bootup. The MP table or ACPI has been read
1162 * earlier. Just do some sanity checking here and enable APIC mode.
1164 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1168 smp_cpu_index_default();
1171 * Setup boot CPU information
1173 smp_store_boot_cpu_info(); /* Final full version of the data */
1174 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1177 current_thread_info()->cpu
= 0; /* needed? */
1178 for_each_possible_cpu(i
) {
1179 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1180 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1181 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1183 set_cpu_sibling_map(0);
1185 switch (smp_sanity_check(max_cpus
)) {
1188 if (APIC_init_uniprocessor())
1189 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1196 apic_bsp_setup(false);
1202 default_setup_apic_routing();
1204 if (read_apic_id() != boot_cpu_physical_apicid
) {
1205 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1206 read_apic_id(), boot_cpu_physical_apicid
);
1207 /* Or can we switch back to PIC here? */
1210 cpu0_logical_apicid
= apic_bsp_setup(false);
1212 pr_info("CPU%d: ", 0);
1213 print_cpu_info(&cpu_data(0));
1218 set_mtrr_aps_delayed_init();
1220 smp_quirk_init_udelay();
1223 void arch_enable_nonboot_cpus_begin(void)
1225 set_mtrr_aps_delayed_init();
1228 void arch_enable_nonboot_cpus_end(void)
1234 * Early setup to make printk work.
1236 void __init
native_smp_prepare_boot_cpu(void)
1238 int me
= smp_processor_id();
1239 switch_to_new_gdt(me
);
1240 /* already set me in cpu_online_mask in boot_cpu_init() */
1241 cpumask_set_cpu(me
, cpu_callout_mask
);
1242 cpu_set_state_online(me
);
1245 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1247 pr_debug("Boot done\n");
1251 setup_ioapic_dest();
1255 static int __initdata setup_possible_cpus
= -1;
1256 static int __init
_setup_possible_cpus(char *str
)
1258 get_option(&str
, &setup_possible_cpus
);
1261 early_param("possible_cpus", _setup_possible_cpus
);
1265 * cpu_possible_mask should be static, it cannot change as cpu's
1266 * are onlined, or offlined. The reason is per-cpu data-structures
1267 * are allocated by some modules at init time, and dont expect to
1268 * do this dynamically on cpu arrival/departure.
1269 * cpu_present_mask on the other hand can change dynamically.
1270 * In case when cpu_hotplug is not compiled, then we resort to current
1271 * behaviour, which is cpu_possible == cpu_present.
1274 * Three ways to find out the number of additional hotplug CPUs:
1275 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1276 * - The user can overwrite it with possible_cpus=NUM
1277 * - Otherwise don't reserve additional CPUs.
1278 * We do this because additional CPUs waste a lot of memory.
1281 __init
void prefill_possible_map(void)
1285 /* no processor from mptable or madt */
1286 if (!num_processors
)
1289 i
= setup_max_cpus
?: 1;
1290 if (setup_possible_cpus
== -1) {
1291 possible
= num_processors
;
1292 #ifdef CONFIG_HOTPLUG_CPU
1294 possible
+= disabled_cpus
;
1300 possible
= setup_possible_cpus
;
1302 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1304 /* nr_cpu_ids could be reduced via nr_cpus= */
1305 if (possible
> nr_cpu_ids
) {
1306 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1307 possible
, nr_cpu_ids
);
1308 possible
= nr_cpu_ids
;
1311 #ifdef CONFIG_HOTPLUG_CPU
1312 if (!setup_max_cpus
)
1315 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1316 possible
, setup_max_cpus
);
1320 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1321 possible
, max_t(int, possible
- num_processors
, 0));
1323 for (i
= 0; i
< possible
; i
++)
1324 set_cpu_possible(i
, true);
1325 for (; i
< NR_CPUS
; i
++)
1326 set_cpu_possible(i
, false);
1328 nr_cpu_ids
= possible
;
1331 #ifdef CONFIG_HOTPLUG_CPU
1333 static void remove_siblinginfo(int cpu
)
1336 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1338 for_each_cpu(sibling
, topology_core_cpumask(cpu
)) {
1339 cpumask_clear_cpu(cpu
, topology_core_cpumask(sibling
));
1341 * last thread sibling in this cpu core going down
1343 if (cpumask_weight(topology_sibling_cpumask(cpu
)) == 1)
1344 cpu_data(sibling
).booted_cores
--;
1347 for_each_cpu(sibling
, topology_sibling_cpumask(cpu
))
1348 cpumask_clear_cpu(cpu
, topology_sibling_cpumask(sibling
));
1349 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1350 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1351 cpumask_clear(cpu_llc_shared_mask(cpu
));
1352 cpumask_clear(topology_sibling_cpumask(cpu
));
1353 cpumask_clear(topology_core_cpumask(cpu
));
1354 c
->phys_proc_id
= 0;
1356 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1359 static void remove_cpu_from_maps(int cpu
)
1361 set_cpu_online(cpu
, false);
1362 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1363 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1364 /* was set by cpu_init() */
1365 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1366 numa_remove_cpu(cpu
);
1369 void cpu_disable_common(void)
1371 int cpu
= smp_processor_id();
1373 remove_siblinginfo(cpu
);
1375 /* It's now safe to remove this processor from the online map */
1377 remove_cpu_from_maps(cpu
);
1378 unlock_vector_lock();
1382 int native_cpu_disable(void)
1386 ret
= check_irq_vectors_for_cpu_disable();
1391 cpu_disable_common();
1396 int common_cpu_die(unsigned int cpu
)
1400 /* We don't do anything here: idle task is faking death itself. */
1402 /* They ack this in play_dead() by setting CPU_DEAD */
1403 if (cpu_wait_death(cpu
, 5)) {
1404 if (system_state
== SYSTEM_RUNNING
)
1405 pr_info("CPU %u is now offline\n", cpu
);
1407 pr_err("CPU %u didn't die...\n", cpu
);
1414 void native_cpu_die(unsigned int cpu
)
1416 common_cpu_die(cpu
);
1419 void play_dead_common(void)
1422 reset_lazy_tlbstate();
1423 amd_e400_remove_cpu(raw_smp_processor_id());
1426 (void)cpu_report_death();
1429 * With physical CPU hotplug, we should halt the cpu
1431 local_irq_disable();
1434 static bool wakeup_cpu0(void)
1436 if (smp_processor_id() == 0 && enable_start_cpu0
)
1443 * We need to flush the caches before going to sleep, lest we have
1444 * dirty data in our caches when we come back up.
1446 static inline void mwait_play_dead(void)
1448 unsigned int eax
, ebx
, ecx
, edx
;
1449 unsigned int highest_cstate
= 0;
1450 unsigned int highest_subcstate
= 0;
1454 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1456 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1458 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1461 eax
= CPUID_MWAIT_LEAF
;
1463 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1466 * eax will be 0 if EDX enumeration is not valid.
1467 * Initialized below to cstate, sub_cstate value when EDX is valid.
1469 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1472 edx
>>= MWAIT_SUBSTATE_SIZE
;
1473 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1474 if (edx
& MWAIT_SUBSTATE_MASK
) {
1476 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1479 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1480 (highest_subcstate
- 1);
1484 * This should be a memory location in a cache line which is
1485 * unlikely to be touched by other processors. The actual
1486 * content is immaterial as it is not actually modified in any way.
1488 mwait_ptr
= ¤t_thread_info()->flags
;
1494 * The CLFLUSH is a workaround for erratum AAI65 for
1495 * the Xeon 7400 series. It's not clear it is actually
1496 * needed, but it should be harmless in either case.
1497 * The WBINVD is insufficient due to the spurious-wakeup
1498 * case where we return around the loop.
1503 __monitor(mwait_ptr
, 0, 0);
1507 * If NMI wants to wake up CPU0, start CPU0.
1514 static inline void hlt_play_dead(void)
1516 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1522 * If NMI wants to wake up CPU0, start CPU0.
1529 void native_play_dead(void)
1532 tboot_shutdown(TB_SHUTDOWN_WFS
);
1534 mwait_play_dead(); /* Only returns on failure */
1535 if (cpuidle_play_dead())
1539 #else /* ... !CONFIG_HOTPLUG_CPU */
1540 int native_cpu_disable(void)
1545 void native_cpu_die(unsigned int cpu
)
1547 /* We said "no" in __cpu_disable */
1551 void native_play_dead(void)