2 * Copyright (C) 2001 MandrakeSoft S.A.
7 * http://www.linux-mandrake.com/
8 * http://www.mandrakesoft.com/
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * Yunhong Jiang <yunhong.jiang@intel.com>
25 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
26 * Based on Xen 3.1 code.
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
36 #include <asm/processor.h>
38 #include <asm/current.h>
41 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
43 #define ioapic_debug(fmt, arg...)
45 static void ioapic_deliver(struct kvm_ioapic
*vioapic
, int irq
);
47 static unsigned long ioapic_read_indirect(struct kvm_ioapic
*ioapic
,
51 unsigned long result
= 0;
53 switch (ioapic
->ioregsel
) {
54 case IOAPIC_REG_VERSION
:
55 result
= ((((IOAPIC_NUM_PINS
- 1) & 0xff) << 16)
56 | (IOAPIC_VERSION_ID
& 0xff));
59 case IOAPIC_REG_APIC_ID
:
60 case IOAPIC_REG_ARB_ID
:
61 result
= ((ioapic
->id
& 0xf) << 24);
66 u32 redir_index
= (ioapic
->ioregsel
- 0x10) >> 1;
69 ASSERT(redir_index
< IOAPIC_NUM_PINS
);
71 redir_content
= ioapic
->redirtbl
[redir_index
].bits
;
72 result
= (ioapic
->ioregsel
& 0x1) ?
73 (redir_content
>> 32) & 0xffffffff :
74 redir_content
& 0xffffffff;
82 static void ioapic_service(struct kvm_ioapic
*ioapic
, unsigned int idx
)
84 union ioapic_redir_entry
*pent
;
86 pent
= &ioapic
->redirtbl
[idx
];
88 if (!pent
->fields
.mask
) {
89 ioapic_deliver(ioapic
, idx
);
90 if (pent
->fields
.trig_mode
== IOAPIC_LEVEL_TRIG
)
91 pent
->fields
.remote_irr
= 1;
93 if (!pent
->fields
.trig_mode
)
94 ioapic
->irr
&= ~(1 << idx
);
97 static void ioapic_write_indirect(struct kvm_ioapic
*ioapic
, u32 val
)
101 switch (ioapic
->ioregsel
) {
102 case IOAPIC_REG_VERSION
:
103 /* Writes are ignored. */
106 case IOAPIC_REG_APIC_ID
:
107 ioapic
->id
= (val
>> 24) & 0xf;
110 case IOAPIC_REG_ARB_ID
:
114 index
= (ioapic
->ioregsel
- 0x10) >> 1;
116 ioapic_debug("change redir index %x val %x\n", index
, val
);
117 if (index
>= IOAPIC_NUM_PINS
)
119 if (ioapic
->ioregsel
& 1) {
120 ioapic
->redirtbl
[index
].bits
&= 0xffffffff;
121 ioapic
->redirtbl
[index
].bits
|= (u64
) val
<< 32;
123 ioapic
->redirtbl
[index
].bits
&= ~0xffffffffULL
;
124 ioapic
->redirtbl
[index
].bits
|= (u32
) val
;
125 ioapic
->redirtbl
[index
].fields
.remote_irr
= 0;
127 if (ioapic
->irr
& (1 << index
))
128 ioapic_service(ioapic
, index
);
133 static void ioapic_inj_irq(struct kvm_ioapic
*ioapic
,
134 struct kvm_vcpu
*vcpu
,
135 u8 vector
, u8 trig_mode
, u8 delivery_mode
)
137 ioapic_debug("irq %d trig %d deliv %d\n", vector
, trig_mode
,
140 ASSERT((delivery_mode
== IOAPIC_FIXED
) ||
141 (delivery_mode
== IOAPIC_LOWEST_PRIORITY
));
143 kvm_apic_set_irq(vcpu
, vector
, trig_mode
);
146 static u32
ioapic_get_delivery_bitmask(struct kvm_ioapic
*ioapic
, u8 dest
,
151 struct kvm
*kvm
= ioapic
->kvm
;
152 struct kvm_vcpu
*vcpu
;
154 ioapic_debug("dest %d dest_mode %d\n", dest
, dest_mode
);
156 if (dest_mode
== 0) { /* Physical mode. */
157 if (dest
== 0xFF) { /* Broadcast. */
158 for (i
= 0; i
< KVM_MAX_VCPUS
; ++i
)
159 if (kvm
->vcpus
[i
] && kvm
->vcpus
[i
]->arch
.apic
)
163 for (i
= 0; i
< KVM_MAX_VCPUS
; ++i
) {
164 vcpu
= kvm
->vcpus
[i
];
167 if (kvm_apic_match_physical_addr(vcpu
->arch
.apic
, dest
)) {
173 } else if (dest
!= 0) /* Logical mode, MDA non-zero. */
174 for (i
= 0; i
< KVM_MAX_VCPUS
; ++i
) {
175 vcpu
= kvm
->vcpus
[i
];
178 if (vcpu
->arch
.apic
&&
179 kvm_apic_match_logical_addr(vcpu
->arch
.apic
, dest
))
180 mask
|= 1 << vcpu
->vcpu_id
;
182 ioapic_debug("mask %x\n", mask
);
186 static void ioapic_deliver(struct kvm_ioapic
*ioapic
, int irq
)
188 u8 dest
= ioapic
->redirtbl
[irq
].fields
.dest_id
;
189 u8 dest_mode
= ioapic
->redirtbl
[irq
].fields
.dest_mode
;
190 u8 delivery_mode
= ioapic
->redirtbl
[irq
].fields
.delivery_mode
;
191 u8 vector
= ioapic
->redirtbl
[irq
].fields
.vector
;
192 u8 trig_mode
= ioapic
->redirtbl
[irq
].fields
.trig_mode
;
194 struct kvm_vcpu
*vcpu
;
197 ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
198 "vector=%x trig_mode=%x\n",
199 dest
, dest_mode
, delivery_mode
, vector
, trig_mode
);
201 deliver_bitmask
= ioapic_get_delivery_bitmask(ioapic
, dest
, dest_mode
);
202 if (!deliver_bitmask
) {
203 ioapic_debug("no target on destination\n");
207 switch (delivery_mode
) {
208 case IOAPIC_LOWEST_PRIORITY
:
209 vcpu
= kvm_get_lowest_prio_vcpu(ioapic
->kvm
, vector
,
212 ioapic_inj_irq(ioapic
, vcpu
, vector
,
213 trig_mode
, delivery_mode
);
215 ioapic_debug("null lowest prio vcpu: "
216 "mask=%x vector=%x delivery_mode=%x\n",
217 deliver_bitmask
, vector
, IOAPIC_LOWEST_PRIORITY
);
220 for (vcpu_id
= 0; deliver_bitmask
!= 0; vcpu_id
++) {
221 if (!(deliver_bitmask
& (1 << vcpu_id
)))
223 deliver_bitmask
&= ~(1 << vcpu_id
);
224 vcpu
= ioapic
->kvm
->vcpus
[vcpu_id
];
226 ioapic_inj_irq(ioapic
, vcpu
, vector
,
227 trig_mode
, delivery_mode
);
234 printk(KERN_WARNING
"Unsupported delivery mode %d\n",
240 void kvm_ioapic_set_irq(struct kvm_ioapic
*ioapic
, int irq
, int level
)
242 u32 old_irr
= ioapic
->irr
;
244 union ioapic_redir_entry entry
;
246 if (irq
>= 0 && irq
< IOAPIC_NUM_PINS
) {
247 entry
= ioapic
->redirtbl
[irq
];
248 level
^= entry
.fields
.polarity
;
250 ioapic
->irr
&= ~mask
;
253 if ((!entry
.fields
.trig_mode
&& old_irr
!= ioapic
->irr
)
254 || !entry
.fields
.remote_irr
)
255 ioapic_service(ioapic
, irq
);
260 static int get_eoi_gsi(struct kvm_ioapic
*ioapic
, int vector
)
264 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++)
265 if (ioapic
->redirtbl
[i
].fields
.vector
== vector
)
270 void kvm_ioapic_update_eoi(struct kvm
*kvm
, int vector
)
272 struct kvm_ioapic
*ioapic
= kvm
->arch
.vioapic
;
273 union ioapic_redir_entry
*ent
;
276 gsi
= get_eoi_gsi(ioapic
, vector
);
278 printk(KERN_WARNING
"Can't find redir item for %d EOI\n",
283 ent
= &ioapic
->redirtbl
[gsi
];
284 ASSERT(ent
->fields
.trig_mode
== IOAPIC_LEVEL_TRIG
);
286 ent
->fields
.remote_irr
= 0;
287 if (!ent
->fields
.mask
&& (ioapic
->irr
& (1 << gsi
)))
288 ioapic_deliver(ioapic
, gsi
);
291 static int ioapic_in_range(struct kvm_io_device
*this, gpa_t addr
)
293 struct kvm_ioapic
*ioapic
= (struct kvm_ioapic
*)this->private;
295 return ((addr
>= ioapic
->base_address
&&
296 (addr
< ioapic
->base_address
+ IOAPIC_MEM_LENGTH
)));
299 static void ioapic_mmio_read(struct kvm_io_device
*this, gpa_t addr
, int len
,
302 struct kvm_ioapic
*ioapic
= (struct kvm_ioapic
*)this->private;
305 ioapic_debug("addr %lx\n", (unsigned long)addr
);
306 ASSERT(!(addr
& 0xf)); /* check alignment */
310 case IOAPIC_REG_SELECT
:
311 result
= ioapic
->ioregsel
;
314 case IOAPIC_REG_WINDOW
:
315 result
= ioapic_read_indirect(ioapic
, addr
, len
);
324 *(u64
*) val
= result
;
329 memcpy(val
, (char *)&result
, len
);
332 printk(KERN_WARNING
"ioapic: wrong length %d\n", len
);
336 static void ioapic_mmio_write(struct kvm_io_device
*this, gpa_t addr
, int len
,
339 struct kvm_ioapic
*ioapic
= (struct kvm_ioapic
*)this->private;
342 ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
343 (void*)addr
, len
, val
);
344 ASSERT(!(addr
& 0xf)); /* check alignment */
345 if (len
== 4 || len
== 8)
348 printk(KERN_WARNING
"ioapic: Unsupported size %d\n", len
);
354 case IOAPIC_REG_SELECT
:
355 ioapic
->ioregsel
= data
;
358 case IOAPIC_REG_WINDOW
:
359 ioapic_write_indirect(ioapic
, data
);
363 kvm_ioapic_update_eoi(ioapic
, data
);
372 void kvm_ioapic_reset(struct kvm_ioapic
*ioapic
)
376 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++)
377 ioapic
->redirtbl
[i
].fields
.mask
= 1;
378 ioapic
->base_address
= IOAPIC_DEFAULT_BASE_ADDRESS
;
379 ioapic
->ioregsel
= 0;
384 int kvm_ioapic_init(struct kvm
*kvm
)
386 struct kvm_ioapic
*ioapic
;
388 ioapic
= kzalloc(sizeof(struct kvm_ioapic
), GFP_KERNEL
);
391 kvm
->arch
.vioapic
= ioapic
;
392 kvm_ioapic_reset(ioapic
);
393 ioapic
->dev
.read
= ioapic_mmio_read
;
394 ioapic
->dev
.write
= ioapic_mmio_write
;
395 ioapic
->dev
.in_range
= ioapic_in_range
;
396 ioapic
->dev
.private = ioapic
;
398 kvm_io_bus_register_dev(&kvm
->mmio_bus
, &ioapic
->dev
);