2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
20 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29 #include <linux/slab.h>
33 #include <asm/virtext.h>
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
41 #define IOPM_ALLOC_ORDER 2
42 #define MSRPM_ALLOC_ORDER 1
44 #define SEG_TYPE_LDT 2
45 #define SEG_TYPE_BUSY_TSS16 3
47 #define SVM_FEATURE_NPT (1 << 0)
48 #define SVM_FEATURE_LBRV (1 << 1)
49 #define SVM_FEATURE_SVML (1 << 2)
50 #define SVM_FEATURE_NRIP (1 << 3)
51 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
53 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
57 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
59 static const u32 host_save_user_msrs
[] = {
61 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
64 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
67 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
77 /* These are the merged vectors */
80 /* gpa pointers to the real vectors */
84 /* A VMEXIT is required but not yet emulated */
87 /* cache for intercepts of the guest */
88 u16 intercept_cr_read
;
89 u16 intercept_cr_write
;
90 u16 intercept_dr_read
;
91 u16 intercept_dr_write
;
92 u32 intercept_exceptions
;
97 #define MSRPM_OFFSETS 16
98 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
101 struct kvm_vcpu vcpu
;
103 unsigned long vmcb_pa
;
104 struct svm_cpu_data
*svm_data
;
105 uint64_t asid_generation
;
106 uint64_t sysenter_esp
;
107 uint64_t sysenter_eip
;
111 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
116 struct nested_state nested
;
120 unsigned int3_injected
;
121 unsigned long int3_rip
;
124 #define MSR_INVALID 0xffffffffU
126 static struct svm_direct_access_msrs
{
127 u32 index
; /* Index of the MSR */
128 bool always
; /* True if intercept is always on */
129 } direct_access_msrs
[] = {
130 { .index
= MSR_K6_STAR
, .always
= true },
131 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
133 { .index
= MSR_GS_BASE
, .always
= true },
134 { .index
= MSR_FS_BASE
, .always
= true },
135 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
136 { .index
= MSR_LSTAR
, .always
= true },
137 { .index
= MSR_CSTAR
, .always
= true },
138 { .index
= MSR_SYSCALL_MASK
, .always
= true },
140 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
141 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
142 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
143 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
144 { .index
= MSR_INVALID
, .always
= false },
147 /* enable NPT for AMD64 and X86 with PAE */
148 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
149 static bool npt_enabled
= true;
151 static bool npt_enabled
;
155 module_param(npt
, int, S_IRUGO
);
157 static int nested
= 1;
158 module_param(nested
, int, S_IRUGO
);
160 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
161 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
163 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
164 static int nested_svm_intercept(struct vcpu_svm
*svm
);
165 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
166 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
167 bool has_error_code
, u32 error_code
);
169 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
171 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
174 static inline bool is_nested(struct vcpu_svm
*svm
)
176 return svm
->nested
.vmcb
;
179 static inline void enable_gif(struct vcpu_svm
*svm
)
181 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
184 static inline void disable_gif(struct vcpu_svm
*svm
)
186 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
189 static inline bool gif_set(struct vcpu_svm
*svm
)
191 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
194 static unsigned long iopm_base
;
196 struct kvm_ldttss_desc
{
199 unsigned base1
:8, type
:5, dpl
:2, p
:1;
200 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
203 } __attribute__((packed
));
205 struct svm_cpu_data
{
211 struct kvm_ldttss_desc
*tss_desc
;
213 struct page
*save_area
;
216 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
217 static uint32_t svm_features
;
219 struct svm_init_data
{
224 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
226 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
227 #define MSRS_RANGE_SIZE 2048
228 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
230 static u32
svm_msrpm_offset(u32 msr
)
235 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
236 if (msr
< msrpm_ranges
[i
] ||
237 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
240 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
241 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
243 /* Now we have the u8 offset - but need the u32 offset */
247 /* MSR not in any range */
251 #define MAX_INST_SIZE 15
253 static inline u32
svm_has(u32 feat
)
255 return svm_features
& feat
;
258 static inline void clgi(void)
260 asm volatile (__ex(SVM_CLGI
));
263 static inline void stgi(void)
265 asm volatile (__ex(SVM_STGI
));
268 static inline void invlpga(unsigned long addr
, u32 asid
)
270 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
273 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
275 to_svm(vcpu
)->asid_generation
--;
278 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
280 force_new_asid(vcpu
);
283 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
285 if (!npt_enabled
&& !(efer
& EFER_LMA
))
288 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
289 vcpu
->arch
.efer
= efer
;
292 static int is_external_interrupt(u32 info
)
294 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
295 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
298 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
300 struct vcpu_svm
*svm
= to_svm(vcpu
);
303 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
304 ret
|= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
308 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
310 struct vcpu_svm
*svm
= to_svm(vcpu
);
313 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
315 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
319 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
321 struct vcpu_svm
*svm
= to_svm(vcpu
);
323 if (svm
->vmcb
->control
.next_rip
!= 0)
324 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
326 if (!svm
->next_rip
) {
327 if (emulate_instruction(vcpu
, 0, 0, EMULTYPE_SKIP
) !=
329 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
332 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
333 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
334 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
336 kvm_rip_write(vcpu
, svm
->next_rip
);
337 svm_set_interrupt_shadow(vcpu
, 0);
340 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
341 bool has_error_code
, u32 error_code
,
344 struct vcpu_svm
*svm
= to_svm(vcpu
);
347 * If we are within a nested VM we'd better #VMEXIT and let the guest
348 * handle the exception
351 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
354 if (nr
== BP_VECTOR
&& !svm_has(SVM_FEATURE_NRIP
)) {
355 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
358 * For guest debugging where we have to reinject #BP if some
359 * INT3 is guest-owned:
360 * Emulate nRIP by moving RIP forward. Will fail if injection
361 * raises a fault that is not intercepted. Still better than
362 * failing in all cases.
364 skip_emulated_instruction(&svm
->vcpu
);
365 rip
= kvm_rip_read(&svm
->vcpu
);
366 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
367 svm
->int3_injected
= rip
- old_rip
;
370 svm
->vmcb
->control
.event_inj
= nr
372 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
373 | SVM_EVTINJ_TYPE_EXEPT
;
374 svm
->vmcb
->control
.event_inj_err
= error_code
;
377 static int has_svm(void)
381 if (!cpu_has_svm(&msg
)) {
382 printk(KERN_INFO
"has_svm: %s\n", msg
);
389 static void svm_hardware_disable(void *garbage
)
394 static int svm_hardware_enable(void *garbage
)
397 struct svm_cpu_data
*sd
;
399 struct desc_ptr gdt_descr
;
400 struct desc_struct
*gdt
;
401 int me
= raw_smp_processor_id();
403 rdmsrl(MSR_EFER
, efer
);
404 if (efer
& EFER_SVME
)
408 printk(KERN_ERR
"svm_hardware_enable: err EOPNOTSUPP on %d\n",
412 sd
= per_cpu(svm_data
, me
);
415 printk(KERN_ERR
"svm_hardware_enable: svm_data is NULL on %d\n",
420 sd
->asid_generation
= 1;
421 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
422 sd
->next_asid
= sd
->max_asid
+ 1;
424 native_store_gdt(&gdt_descr
);
425 gdt
= (struct desc_struct
*)gdt_descr
.address
;
426 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
428 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
430 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
435 static void svm_cpu_uninit(int cpu
)
437 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
442 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
443 __free_page(sd
->save_area
);
447 static int svm_cpu_init(int cpu
)
449 struct svm_cpu_data
*sd
;
452 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
456 sd
->save_area
= alloc_page(GFP_KERNEL
);
461 per_cpu(svm_data
, cpu
) = sd
;
471 static bool valid_msr_intercept(u32 index
)
475 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
476 if (direct_access_msrs
[i
].index
== index
)
482 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
485 u8 bit_read
, bit_write
;
490 * If this warning triggers extend the direct_access_msrs list at the
491 * beginning of the file
493 WARN_ON(!valid_msr_intercept(msr
));
495 offset
= svm_msrpm_offset(msr
);
496 bit_read
= 2 * (msr
& 0x0f);
497 bit_write
= 2 * (msr
& 0x0f) + 1;
500 BUG_ON(offset
== MSR_INVALID
);
502 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
503 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
508 static void svm_vcpu_init_msrpm(u32
*msrpm
)
512 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
514 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
515 if (!direct_access_msrs
[i
].always
)
518 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
522 static void add_msr_offset(u32 offset
)
526 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
528 /* Offset already in list? */
529 if (msrpm_offsets
[i
] == offset
)
532 /* Slot used by another offset? */
533 if (msrpm_offsets
[i
] != MSR_INVALID
)
536 /* Add offset to list */
537 msrpm_offsets
[i
] = offset
;
543 * If this BUG triggers the msrpm_offsets table has an overflow. Just
544 * increase MSRPM_OFFSETS in this case.
549 static void init_msrpm_offsets(void)
553 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
555 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
558 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
559 BUG_ON(offset
== MSR_INVALID
);
561 add_msr_offset(offset
);
565 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
567 u32
*msrpm
= svm
->msrpm
;
569 svm
->vmcb
->control
.lbr_ctl
= 1;
570 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
571 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
572 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
573 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
576 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
578 u32
*msrpm
= svm
->msrpm
;
580 svm
->vmcb
->control
.lbr_ctl
= 0;
581 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
582 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
583 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
584 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
587 static __init
int svm_hardware_setup(void)
590 struct page
*iopm_pages
;
594 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
599 iopm_va
= page_address(iopm_pages
);
600 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
601 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
603 init_msrpm_offsets();
605 if (boot_cpu_has(X86_FEATURE_NX
))
606 kvm_enable_efer_bits(EFER_NX
);
608 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
609 kvm_enable_efer_bits(EFER_FFXSR
);
612 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
613 kvm_enable_efer_bits(EFER_SVME
);
616 for_each_possible_cpu(cpu
) {
617 r
= svm_cpu_init(cpu
);
622 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
624 if (!svm_has(SVM_FEATURE_NPT
))
627 if (npt_enabled
&& !npt
) {
628 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
633 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
641 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
646 static __exit
void svm_hardware_unsetup(void)
650 for_each_possible_cpu(cpu
)
653 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
657 static void init_seg(struct vmcb_seg
*seg
)
660 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
661 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
666 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
669 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
674 static void init_vmcb(struct vcpu_svm
*svm
)
676 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
677 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
679 svm
->vcpu
.fpu_active
= 1;
681 control
->intercept_cr_read
= INTERCEPT_CR0_MASK
|
685 control
->intercept_cr_write
= INTERCEPT_CR0_MASK
|
690 control
->intercept_dr_read
= INTERCEPT_DR0_MASK
|
699 control
->intercept_dr_write
= INTERCEPT_DR0_MASK
|
708 control
->intercept_exceptions
= (1 << PF_VECTOR
) |
713 control
->intercept
= (1ULL << INTERCEPT_INTR
) |
714 (1ULL << INTERCEPT_NMI
) |
715 (1ULL << INTERCEPT_SMI
) |
716 (1ULL << INTERCEPT_SELECTIVE_CR0
) |
717 (1ULL << INTERCEPT_CPUID
) |
718 (1ULL << INTERCEPT_INVD
) |
719 (1ULL << INTERCEPT_HLT
) |
720 (1ULL << INTERCEPT_INVLPG
) |
721 (1ULL << INTERCEPT_INVLPGA
) |
722 (1ULL << INTERCEPT_IOIO_PROT
) |
723 (1ULL << INTERCEPT_MSR_PROT
) |
724 (1ULL << INTERCEPT_TASK_SWITCH
) |
725 (1ULL << INTERCEPT_SHUTDOWN
) |
726 (1ULL << INTERCEPT_VMRUN
) |
727 (1ULL << INTERCEPT_VMMCALL
) |
728 (1ULL << INTERCEPT_VMLOAD
) |
729 (1ULL << INTERCEPT_VMSAVE
) |
730 (1ULL << INTERCEPT_STGI
) |
731 (1ULL << INTERCEPT_CLGI
) |
732 (1ULL << INTERCEPT_SKINIT
) |
733 (1ULL << INTERCEPT_WBINVD
) |
734 (1ULL << INTERCEPT_MONITOR
) |
735 (1ULL << INTERCEPT_MWAIT
);
737 control
->iopm_base_pa
= iopm_base
;
738 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
739 control
->tsc_offset
= 0;
740 control
->int_ctl
= V_INTR_MASKING_MASK
;
748 save
->cs
.selector
= 0xf000;
749 /* Executable/Readable Code Segment */
750 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
751 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
752 save
->cs
.limit
= 0xffff;
754 * cs.base should really be 0xffff0000, but vmx can't handle that, so
755 * be consistent with it.
757 * Replace when we have real mode working for vmx.
759 save
->cs
.base
= 0xf0000;
761 save
->gdtr
.limit
= 0xffff;
762 save
->idtr
.limit
= 0xffff;
764 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
765 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
767 save
->efer
= EFER_SVME
;
768 save
->dr6
= 0xffff0ff0;
771 save
->rip
= 0x0000fff0;
772 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
775 * This is the guest-visible cr0 value.
776 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
778 svm
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
779 kvm_set_cr0(&svm
->vcpu
, svm
->vcpu
.arch
.cr0
);
781 save
->cr4
= X86_CR4_PAE
;
785 /* Setup VMCB for Nested Paging */
786 control
->nested_ctl
= 1;
787 control
->intercept
&= ~((1ULL << INTERCEPT_TASK_SWITCH
) |
788 (1ULL << INTERCEPT_INVLPG
));
789 control
->intercept_exceptions
&= ~(1 << PF_VECTOR
);
790 control
->intercept_cr_read
&= ~INTERCEPT_CR3_MASK
;
791 control
->intercept_cr_write
&= ~INTERCEPT_CR3_MASK
;
792 save
->g_pat
= 0x0007040600070406ULL
;
796 force_new_asid(&svm
->vcpu
);
798 svm
->nested
.vmcb
= 0;
799 svm
->vcpu
.arch
.hflags
= 0;
801 if (svm_has(SVM_FEATURE_PAUSE_FILTER
)) {
802 control
->pause_filter_count
= 3000;
803 control
->intercept
|= (1ULL << INTERCEPT_PAUSE
);
809 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
811 struct vcpu_svm
*svm
= to_svm(vcpu
);
815 if (!kvm_vcpu_is_bsp(vcpu
)) {
816 kvm_rip_write(vcpu
, 0);
817 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
818 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
820 vcpu
->arch
.regs_avail
= ~0;
821 vcpu
->arch
.regs_dirty
= ~0;
826 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
828 struct vcpu_svm
*svm
;
830 struct page
*msrpm_pages
;
831 struct page
*hsave_page
;
832 struct page
*nested_msrpm_pages
;
835 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
841 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
846 page
= alloc_page(GFP_KERNEL
);
850 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
854 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
855 if (!nested_msrpm_pages
)
858 hsave_page
= alloc_page(GFP_KERNEL
);
862 svm
->nested
.hsave
= page_address(hsave_page
);
864 svm
->msrpm
= page_address(msrpm_pages
);
865 svm_vcpu_init_msrpm(svm
->msrpm
);
867 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
868 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
870 svm
->vmcb
= page_address(page
);
871 clear_page(svm
->vmcb
);
872 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
873 svm
->asid_generation
= 0;
877 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
878 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
879 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
884 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
886 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
890 kvm_vcpu_uninit(&svm
->vcpu
);
892 kmem_cache_free(kvm_vcpu_cache
, svm
);
897 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
899 struct vcpu_svm
*svm
= to_svm(vcpu
);
901 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
902 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
903 __free_page(virt_to_page(svm
->nested
.hsave
));
904 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
905 kvm_vcpu_uninit(vcpu
);
906 kmem_cache_free(kvm_vcpu_cache
, svm
);
909 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
911 struct vcpu_svm
*svm
= to_svm(vcpu
);
914 if (unlikely(cpu
!= vcpu
->cpu
)) {
917 if (check_tsc_unstable()) {
919 * Make sure that the guest sees a monotonically
922 delta
= vcpu
->arch
.host_tsc
- native_read_tsc();
923 svm
->vmcb
->control
.tsc_offset
+= delta
;
925 svm
->nested
.hsave
->control
.tsc_offset
+= delta
;
928 kvm_migrate_timers(vcpu
);
929 svm
->asid_generation
= 0;
932 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
933 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
936 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
938 struct vcpu_svm
*svm
= to_svm(vcpu
);
941 ++vcpu
->stat
.host_state_reload
;
942 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
943 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
945 vcpu
->arch
.host_tsc
= native_read_tsc();
948 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
950 return to_svm(vcpu
)->vmcb
->save
.rflags
;
953 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
955 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
958 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
961 case VCPU_EXREG_PDPTR
:
962 BUG_ON(!npt_enabled
);
963 load_pdptrs(vcpu
, vcpu
->arch
.cr3
);
970 static void svm_set_vintr(struct vcpu_svm
*svm
)
972 svm
->vmcb
->control
.intercept
|= 1ULL << INTERCEPT_VINTR
;
975 static void svm_clear_vintr(struct vcpu_svm
*svm
)
977 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VINTR
);
980 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
982 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
985 case VCPU_SREG_CS
: return &save
->cs
;
986 case VCPU_SREG_DS
: return &save
->ds
;
987 case VCPU_SREG_ES
: return &save
->es
;
988 case VCPU_SREG_FS
: return &save
->fs
;
989 case VCPU_SREG_GS
: return &save
->gs
;
990 case VCPU_SREG_SS
: return &save
->ss
;
991 case VCPU_SREG_TR
: return &save
->tr
;
992 case VCPU_SREG_LDTR
: return &save
->ldtr
;
998 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1000 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1005 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1006 struct kvm_segment
*var
, int seg
)
1008 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1010 var
->base
= s
->base
;
1011 var
->limit
= s
->limit
;
1012 var
->selector
= s
->selector
;
1013 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1014 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1015 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1016 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1017 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1018 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1019 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1020 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
1023 * AMD's VMCB does not have an explicit unusable field, so emulate it
1024 * for cross vendor migration purposes by "not present"
1026 var
->unusable
= !var
->present
|| (var
->type
== 0);
1031 * SVM always stores 0 for the 'G' bit in the CS selector in
1032 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1033 * Intel's VMENTRY has a check on the 'G' bit.
1035 var
->g
= s
->limit
> 0xfffff;
1039 * Work around a bug where the busy flag in the tr selector
1049 * The accessed bit must always be set in the segment
1050 * descriptor cache, although it can be cleared in the
1051 * descriptor, the cached bit always remains at 1. Since
1052 * Intel has a check on this, set it here to support
1053 * cross-vendor migration.
1060 * On AMD CPUs sometimes the DB bit in the segment
1061 * descriptor is left as 1, although the whole segment has
1062 * been made unusable. Clear it here to pass an Intel VMX
1063 * entry check when cross vendor migrating.
1071 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1073 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1078 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1080 struct vcpu_svm
*svm
= to_svm(vcpu
);
1082 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1083 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1086 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1088 struct vcpu_svm
*svm
= to_svm(vcpu
);
1090 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1091 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1094 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1096 struct vcpu_svm
*svm
= to_svm(vcpu
);
1098 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1099 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1102 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1104 struct vcpu_svm
*svm
= to_svm(vcpu
);
1106 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1107 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1110 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1114 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1118 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1120 struct vmcb
*vmcb
= svm
->vmcb
;
1121 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1122 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1124 if (!svm
->vcpu
.fpu_active
)
1125 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1127 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1128 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1131 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1132 vmcb
->control
.intercept_cr_read
&= ~INTERCEPT_CR0_MASK
;
1133 vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR0_MASK
;
1134 if (is_nested(svm
)) {
1135 struct vmcb
*hsave
= svm
->nested
.hsave
;
1137 hsave
->control
.intercept_cr_read
&= ~INTERCEPT_CR0_MASK
;
1138 hsave
->control
.intercept_cr_write
&= ~INTERCEPT_CR0_MASK
;
1139 vmcb
->control
.intercept_cr_read
|= svm
->nested
.intercept_cr_read
;
1140 vmcb
->control
.intercept_cr_write
|= svm
->nested
.intercept_cr_write
;
1143 svm
->vmcb
->control
.intercept_cr_read
|= INTERCEPT_CR0_MASK
;
1144 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR0_MASK
;
1145 if (is_nested(svm
)) {
1146 struct vmcb
*hsave
= svm
->nested
.hsave
;
1148 hsave
->control
.intercept_cr_read
|= INTERCEPT_CR0_MASK
;
1149 hsave
->control
.intercept_cr_write
|= INTERCEPT_CR0_MASK
;
1154 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1156 struct vcpu_svm
*svm
= to_svm(vcpu
);
1158 if (is_nested(svm
)) {
1160 * We are here because we run in nested mode, the host kvm
1161 * intercepts cr0 writes but the l1 hypervisor does not.
1162 * But the L1 hypervisor may intercept selective cr0 writes.
1163 * This needs to be checked here.
1165 unsigned long old
, new;
1167 /* Remove bits that would trigger a real cr0 write intercept */
1168 old
= vcpu
->arch
.cr0
& SVM_CR0_SELECTIVE_MASK
;
1169 new = cr0
& SVM_CR0_SELECTIVE_MASK
;
1172 /* cr0 write with ts and mp unchanged */
1173 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
1174 if (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
)
1179 #ifdef CONFIG_X86_64
1180 if (vcpu
->arch
.efer
& EFER_LME
) {
1181 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1182 vcpu
->arch
.efer
|= EFER_LMA
;
1183 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1186 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1187 vcpu
->arch
.efer
&= ~EFER_LMA
;
1188 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1192 vcpu
->arch
.cr0
= cr0
;
1195 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1197 if (!vcpu
->fpu_active
)
1200 * re-enable caching here because the QEMU bios
1201 * does not do it - this results in some delay at
1204 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1205 svm
->vmcb
->save
.cr0
= cr0
;
1206 update_cr0_intercept(svm
);
1209 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1211 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1212 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1214 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1215 force_new_asid(vcpu
);
1217 vcpu
->arch
.cr4
= cr4
;
1220 cr4
|= host_cr4_mce
;
1221 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1224 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1225 struct kvm_segment
*var
, int seg
)
1227 struct vcpu_svm
*svm
= to_svm(vcpu
);
1228 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1230 s
->base
= var
->base
;
1231 s
->limit
= var
->limit
;
1232 s
->selector
= var
->selector
;
1236 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1237 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1238 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1239 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1240 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1241 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1242 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1243 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1245 if (seg
== VCPU_SREG_CS
)
1247 = (svm
->vmcb
->save
.cs
.attrib
1248 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1252 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1254 struct vcpu_svm
*svm
= to_svm(vcpu
);
1256 svm
->vmcb
->control
.intercept_exceptions
&=
1257 ~((1 << DB_VECTOR
) | (1 << BP_VECTOR
));
1259 if (svm
->nmi_singlestep
)
1260 svm
->vmcb
->control
.intercept_exceptions
|= (1 << DB_VECTOR
);
1262 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1263 if (vcpu
->guest_debug
&
1264 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1265 svm
->vmcb
->control
.intercept_exceptions
|=
1267 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1268 svm
->vmcb
->control
.intercept_exceptions
|=
1271 vcpu
->guest_debug
= 0;
1274 static void svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1276 struct vcpu_svm
*svm
= to_svm(vcpu
);
1278 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1279 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1281 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1283 update_db_intercept(vcpu
);
1286 static void load_host_msrs(struct kvm_vcpu
*vcpu
)
1288 #ifdef CONFIG_X86_64
1289 wrmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1293 static void save_host_msrs(struct kvm_vcpu
*vcpu
)
1295 #ifdef CONFIG_X86_64
1296 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1300 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1302 if (sd
->next_asid
> sd
->max_asid
) {
1303 ++sd
->asid_generation
;
1305 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1308 svm
->asid_generation
= sd
->asid_generation
;
1309 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1312 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1314 struct vcpu_svm
*svm
= to_svm(vcpu
);
1316 svm
->vmcb
->save
.dr7
= value
;
1319 static int pf_interception(struct vcpu_svm
*svm
)
1324 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1325 error_code
= svm
->vmcb
->control
.exit_info_1
;
1327 trace_kvm_page_fault(fault_address
, error_code
);
1328 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1329 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1330 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1333 static int db_interception(struct vcpu_svm
*svm
)
1335 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1337 if (!(svm
->vcpu
.guest_debug
&
1338 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1339 !svm
->nmi_singlestep
) {
1340 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1344 if (svm
->nmi_singlestep
) {
1345 svm
->nmi_singlestep
= false;
1346 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1347 svm
->vmcb
->save
.rflags
&=
1348 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1349 update_db_intercept(&svm
->vcpu
);
1352 if (svm
->vcpu
.guest_debug
&
1353 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1354 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1355 kvm_run
->debug
.arch
.pc
=
1356 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1357 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1364 static int bp_interception(struct vcpu_svm
*svm
)
1366 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1368 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1369 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1370 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1374 static int ud_interception(struct vcpu_svm
*svm
)
1378 er
= emulate_instruction(&svm
->vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
1379 if (er
!= EMULATE_DONE
)
1380 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1384 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1386 struct vcpu_svm
*svm
= to_svm(vcpu
);
1389 if (is_nested(svm
)) {
1392 h_excp
= svm
->nested
.hsave
->control
.intercept_exceptions
;
1393 n_excp
= svm
->nested
.intercept_exceptions
;
1394 h_excp
&= ~(1 << NM_VECTOR
);
1395 excp
= h_excp
| n_excp
;
1397 excp
= svm
->vmcb
->control
.intercept_exceptions
;
1398 excp
&= ~(1 << NM_VECTOR
);
1401 svm
->vmcb
->control
.intercept_exceptions
= excp
;
1403 svm
->vcpu
.fpu_active
= 1;
1404 update_cr0_intercept(svm
);
1407 static int nm_interception(struct vcpu_svm
*svm
)
1409 svm_fpu_activate(&svm
->vcpu
);
1413 static int mc_interception(struct vcpu_svm
*svm
)
1416 * On an #MC intercept the MCE handler is not called automatically in
1417 * the host. So do it by hand here.
1421 /* not sure if we ever come back to this point */
1426 static int shutdown_interception(struct vcpu_svm
*svm
)
1428 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1431 * VMCB is undefined after a SHUTDOWN intercept
1432 * so reinitialize it.
1434 clear_page(svm
->vmcb
);
1437 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1441 static int io_interception(struct vcpu_svm
*svm
)
1443 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1444 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1445 int size
, in
, string
;
1448 ++svm
->vcpu
.stat
.io_exits
;
1449 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1450 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1452 return !(emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DO_MMIO
);
1454 port
= io_info
>> 16;
1455 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1456 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1457 skip_emulated_instruction(&svm
->vcpu
);
1459 return kvm_fast_pio_out(vcpu
, size
, port
);
1462 static int nmi_interception(struct vcpu_svm
*svm
)
1467 static int intr_interception(struct vcpu_svm
*svm
)
1469 ++svm
->vcpu
.stat
.irq_exits
;
1473 static int nop_on_interception(struct vcpu_svm
*svm
)
1478 static int halt_interception(struct vcpu_svm
*svm
)
1480 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1481 skip_emulated_instruction(&svm
->vcpu
);
1482 return kvm_emulate_halt(&svm
->vcpu
);
1485 static int vmmcall_interception(struct vcpu_svm
*svm
)
1487 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1488 skip_emulated_instruction(&svm
->vcpu
);
1489 kvm_emulate_hypercall(&svm
->vcpu
);
1493 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1495 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
1496 || !is_paging(&svm
->vcpu
)) {
1497 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1501 if (svm
->vmcb
->save
.cpl
) {
1502 kvm_inject_gp(&svm
->vcpu
, 0);
1509 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1510 bool has_error_code
, u32 error_code
)
1514 if (!is_nested(svm
))
1517 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1518 svm
->vmcb
->control
.exit_code_hi
= 0;
1519 svm
->vmcb
->control
.exit_info_1
= error_code
;
1520 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1522 vmexit
= nested_svm_intercept(svm
);
1523 if (vmexit
== NESTED_EXIT_DONE
)
1524 svm
->nested
.exit_required
= true;
1529 /* This function returns true if it is save to enable the irq window */
1530 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
1532 if (!is_nested(svm
))
1535 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1538 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1541 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1542 svm
->vmcb
->control
.exit_info_1
= 0;
1543 svm
->vmcb
->control
.exit_info_2
= 0;
1545 if (svm
->nested
.intercept
& 1ULL) {
1547 * The #vmexit can't be emulated here directly because this
1548 * code path runs with irqs and preemtion disabled. A
1549 * #vmexit emulation might sleep. Only signal request for
1552 svm
->nested
.exit_required
= true;
1553 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
1560 /* This function returns true if it is save to enable the nmi window */
1561 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
1563 if (!is_nested(svm
))
1566 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
1569 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
1570 svm
->nested
.exit_required
= true;
1575 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
1581 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1582 if (is_error_page(page
))
1590 kvm_release_page_clean(page
);
1591 kvm_inject_gp(&svm
->vcpu
, 0);
1596 static void nested_svm_unmap(struct page
*page
)
1599 kvm_release_page_dirty(page
);
1602 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
1608 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
1609 return NESTED_EXIT_HOST
;
1611 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
1612 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
1616 if (kvm_read_guest(svm
->vcpu
.kvm
, gpa
, &val
, 1))
1619 return val
? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1622 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
1624 u32 offset
, msr
, value
;
1627 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1628 return NESTED_EXIT_HOST
;
1630 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1631 offset
= svm_msrpm_offset(msr
);
1632 write
= svm
->vmcb
->control
.exit_info_1
& 1;
1633 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
1635 if (offset
== MSR_INVALID
)
1636 return NESTED_EXIT_DONE
;
1638 /* Offset is in 32 bit units but need in 8 bit units */
1641 if (kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
1642 return NESTED_EXIT_DONE
;
1644 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1647 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
1649 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1651 switch (exit_code
) {
1654 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
1655 return NESTED_EXIT_HOST
;
1657 /* For now we are always handling NPFs when using them */
1659 return NESTED_EXIT_HOST
;
1661 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1662 /* When we're shadowing, trap PFs */
1664 return NESTED_EXIT_HOST
;
1666 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
1667 nm_interception(svm
);
1673 return NESTED_EXIT_CONTINUE
;
1677 * If this function returns true, this #vmexit was already handled
1679 static int nested_svm_intercept(struct vcpu_svm
*svm
)
1681 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1682 int vmexit
= NESTED_EXIT_HOST
;
1684 switch (exit_code
) {
1686 vmexit
= nested_svm_exit_handled_msr(svm
);
1689 vmexit
= nested_svm_intercept_ioio(svm
);
1691 case SVM_EXIT_READ_CR0
... SVM_EXIT_READ_CR8
: {
1692 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_READ_CR0
);
1693 if (svm
->nested
.intercept_cr_read
& cr_bits
)
1694 vmexit
= NESTED_EXIT_DONE
;
1697 case SVM_EXIT_WRITE_CR0
... SVM_EXIT_WRITE_CR8
: {
1698 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_CR0
);
1699 if (svm
->nested
.intercept_cr_write
& cr_bits
)
1700 vmexit
= NESTED_EXIT_DONE
;
1703 case SVM_EXIT_READ_DR0
... SVM_EXIT_READ_DR7
: {
1704 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_READ_DR0
);
1705 if (svm
->nested
.intercept_dr_read
& dr_bits
)
1706 vmexit
= NESTED_EXIT_DONE
;
1709 case SVM_EXIT_WRITE_DR0
... SVM_EXIT_WRITE_DR7
: {
1710 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_DR0
);
1711 if (svm
->nested
.intercept_dr_write
& dr_bits
)
1712 vmexit
= NESTED_EXIT_DONE
;
1715 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
1716 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
1717 if (svm
->nested
.intercept_exceptions
& excp_bits
)
1718 vmexit
= NESTED_EXIT_DONE
;
1721 case SVM_EXIT_ERR
: {
1722 vmexit
= NESTED_EXIT_DONE
;
1726 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
1727 if (svm
->nested
.intercept
& exit_bits
)
1728 vmexit
= NESTED_EXIT_DONE
;
1735 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
1739 vmexit
= nested_svm_intercept(svm
);
1741 if (vmexit
== NESTED_EXIT_DONE
)
1742 nested_svm_vmexit(svm
);
1747 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
1749 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
1750 struct vmcb_control_area
*from
= &from_vmcb
->control
;
1752 dst
->intercept_cr_read
= from
->intercept_cr_read
;
1753 dst
->intercept_cr_write
= from
->intercept_cr_write
;
1754 dst
->intercept_dr_read
= from
->intercept_dr_read
;
1755 dst
->intercept_dr_write
= from
->intercept_dr_write
;
1756 dst
->intercept_exceptions
= from
->intercept_exceptions
;
1757 dst
->intercept
= from
->intercept
;
1758 dst
->iopm_base_pa
= from
->iopm_base_pa
;
1759 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
1760 dst
->tsc_offset
= from
->tsc_offset
;
1761 dst
->asid
= from
->asid
;
1762 dst
->tlb_ctl
= from
->tlb_ctl
;
1763 dst
->int_ctl
= from
->int_ctl
;
1764 dst
->int_vector
= from
->int_vector
;
1765 dst
->int_state
= from
->int_state
;
1766 dst
->exit_code
= from
->exit_code
;
1767 dst
->exit_code_hi
= from
->exit_code_hi
;
1768 dst
->exit_info_1
= from
->exit_info_1
;
1769 dst
->exit_info_2
= from
->exit_info_2
;
1770 dst
->exit_int_info
= from
->exit_int_info
;
1771 dst
->exit_int_info_err
= from
->exit_int_info_err
;
1772 dst
->nested_ctl
= from
->nested_ctl
;
1773 dst
->event_inj
= from
->event_inj
;
1774 dst
->event_inj_err
= from
->event_inj_err
;
1775 dst
->nested_cr3
= from
->nested_cr3
;
1776 dst
->lbr_ctl
= from
->lbr_ctl
;
1779 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
1781 struct vmcb
*nested_vmcb
;
1782 struct vmcb
*hsave
= svm
->nested
.hsave
;
1783 struct vmcb
*vmcb
= svm
->vmcb
;
1786 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
1787 vmcb
->control
.exit_info_1
,
1788 vmcb
->control
.exit_info_2
,
1789 vmcb
->control
.exit_int_info
,
1790 vmcb
->control
.exit_int_info_err
);
1792 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
1796 /* Exit nested SVM mode */
1797 svm
->nested
.vmcb
= 0;
1799 /* Give the current vmcb to the guest */
1802 nested_vmcb
->save
.es
= vmcb
->save
.es
;
1803 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
1804 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
1805 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
1806 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
1807 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
1808 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
1809 nested_vmcb
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1810 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
1811 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1812 nested_vmcb
->save
.rflags
= vmcb
->save
.rflags
;
1813 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
1814 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
1815 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
1816 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
1817 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
1818 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
1820 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
1821 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
1822 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
1823 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
1824 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
1825 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
1826 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
1827 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
1828 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
1831 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1832 * to make sure that we do not lose injected events. So check event_inj
1833 * here and copy it to exit_int_info if it is valid.
1834 * Exit_int_info and event_inj can't be both valid because the case
1835 * below only happens on a VMRUN instruction intercept which has
1836 * no valid exit_int_info set.
1838 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
1839 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
1841 nc
->exit_int_info
= vmcb
->control
.event_inj
;
1842 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
1845 nested_vmcb
->control
.tlb_ctl
= 0;
1846 nested_vmcb
->control
.event_inj
= 0;
1847 nested_vmcb
->control
.event_inj_err
= 0;
1849 /* We always set V_INTR_MASKING and remember the old value in hflags */
1850 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1851 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
1853 /* Restore the original control entries */
1854 copy_vmcb_control_area(vmcb
, hsave
);
1856 kvm_clear_exception_queue(&svm
->vcpu
);
1857 kvm_clear_interrupt_queue(&svm
->vcpu
);
1859 /* Restore selected save entries */
1860 svm
->vmcb
->save
.es
= hsave
->save
.es
;
1861 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
1862 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
1863 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
1864 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
1865 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
1866 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
1867 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
1868 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
1869 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
1871 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
1872 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
1874 kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
1876 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
1877 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
1878 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
1879 svm
->vmcb
->save
.dr7
= 0;
1880 svm
->vmcb
->save
.cpl
= 0;
1881 svm
->vmcb
->control
.exit_int_info
= 0;
1883 nested_svm_unmap(page
);
1885 kvm_mmu_reset_context(&svm
->vcpu
);
1886 kvm_mmu_load(&svm
->vcpu
);
1891 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
1894 * This function merges the msr permission bitmaps of kvm and the
1895 * nested vmcb. It is omptimized in that it only merges the parts where
1896 * the kvm msr permission bitmap may contain zero bits
1900 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1903 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
1907 if (msrpm_offsets
[i
] == 0xffffffff)
1910 p
= msrpm_offsets
[i
];
1911 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
1913 if (kvm_read_guest(svm
->vcpu
.kvm
, offset
, &value
, 4))
1916 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
1919 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
1924 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
1926 struct vmcb
*nested_vmcb
;
1927 struct vmcb
*hsave
= svm
->nested
.hsave
;
1928 struct vmcb
*vmcb
= svm
->vmcb
;
1932 vmcb_gpa
= svm
->vmcb
->save
.rax
;
1934 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
1938 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
- 3, vmcb_gpa
,
1939 nested_vmcb
->save
.rip
,
1940 nested_vmcb
->control
.int_ctl
,
1941 nested_vmcb
->control
.event_inj
,
1942 nested_vmcb
->control
.nested_ctl
);
1944 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr_read
,
1945 nested_vmcb
->control
.intercept_cr_write
,
1946 nested_vmcb
->control
.intercept_exceptions
,
1947 nested_vmcb
->control
.intercept
);
1949 /* Clear internal status */
1950 kvm_clear_exception_queue(&svm
->vcpu
);
1951 kvm_clear_interrupt_queue(&svm
->vcpu
);
1954 * Save the old vmcb, so we don't need to pick what we save, but can
1955 * restore everything when a VMEXIT occurs
1957 hsave
->save
.es
= vmcb
->save
.es
;
1958 hsave
->save
.cs
= vmcb
->save
.cs
;
1959 hsave
->save
.ss
= vmcb
->save
.ss
;
1960 hsave
->save
.ds
= vmcb
->save
.ds
;
1961 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
1962 hsave
->save
.idtr
= vmcb
->save
.idtr
;
1963 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
1964 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
1965 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1966 hsave
->save
.rflags
= vmcb
->save
.rflags
;
1967 hsave
->save
.rip
= svm
->next_rip
;
1968 hsave
->save
.rsp
= vmcb
->save
.rsp
;
1969 hsave
->save
.rax
= vmcb
->save
.rax
;
1971 hsave
->save
.cr3
= vmcb
->save
.cr3
;
1973 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1975 copy_vmcb_control_area(hsave
, vmcb
);
1977 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
1978 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
1980 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
1982 /* Load the nested guest state */
1983 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
1984 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
1985 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
1986 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
1987 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
1988 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
1989 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
1990 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
1991 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
1992 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
1994 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
1995 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
1997 kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
1999 /* Guest paging mode is active - reset mmu */
2000 kvm_mmu_reset_context(&svm
->vcpu
);
2002 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2003 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2004 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2005 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2007 /* In case we don't even reach vcpu_run, the fields are not updated */
2008 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2009 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2010 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2011 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2012 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2013 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2015 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2016 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2018 /* cache intercepts */
2019 svm
->nested
.intercept_cr_read
= nested_vmcb
->control
.intercept_cr_read
;
2020 svm
->nested
.intercept_cr_write
= nested_vmcb
->control
.intercept_cr_write
;
2021 svm
->nested
.intercept_dr_read
= nested_vmcb
->control
.intercept_dr_read
;
2022 svm
->nested
.intercept_dr_write
= nested_vmcb
->control
.intercept_dr_write
;
2023 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2024 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2026 force_new_asid(&svm
->vcpu
);
2027 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2028 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2029 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2031 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2033 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2034 /* We only want the cr8 intercept bits of the guest */
2035 svm
->vmcb
->control
.intercept_cr_read
&= ~INTERCEPT_CR8_MASK
;
2036 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2040 * We don't want a nested guest to be more powerful than the guest, so
2041 * all intercepts are ORed
2043 svm
->vmcb
->control
.intercept_cr_read
|=
2044 nested_vmcb
->control
.intercept_cr_read
;
2045 svm
->vmcb
->control
.intercept_cr_write
|=
2046 nested_vmcb
->control
.intercept_cr_write
;
2047 svm
->vmcb
->control
.intercept_dr_read
|=
2048 nested_vmcb
->control
.intercept_dr_read
;
2049 svm
->vmcb
->control
.intercept_dr_write
|=
2050 nested_vmcb
->control
.intercept_dr_write
;
2051 svm
->vmcb
->control
.intercept_exceptions
|=
2052 nested_vmcb
->control
.intercept_exceptions
;
2054 svm
->vmcb
->control
.intercept
|= nested_vmcb
->control
.intercept
;
2056 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2057 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2058 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2059 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2060 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2061 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2063 nested_svm_unmap(page
);
2065 /* nested_vmcb is our indicator if nested SVM is activated */
2066 svm
->nested
.vmcb
= vmcb_gpa
;
2073 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2075 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2076 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2077 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2078 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2079 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2080 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2081 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2082 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2083 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2084 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2085 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2086 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2089 static int vmload_interception(struct vcpu_svm
*svm
)
2091 struct vmcb
*nested_vmcb
;
2094 if (nested_svm_check_permissions(svm
))
2097 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2098 skip_emulated_instruction(&svm
->vcpu
);
2100 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2104 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2105 nested_svm_unmap(page
);
2110 static int vmsave_interception(struct vcpu_svm
*svm
)
2112 struct vmcb
*nested_vmcb
;
2115 if (nested_svm_check_permissions(svm
))
2118 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2119 skip_emulated_instruction(&svm
->vcpu
);
2121 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2125 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2126 nested_svm_unmap(page
);
2131 static int vmrun_interception(struct vcpu_svm
*svm
)
2133 if (nested_svm_check_permissions(svm
))
2136 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2137 skip_emulated_instruction(&svm
->vcpu
);
2139 if (!nested_svm_vmrun(svm
))
2142 if (!nested_svm_vmrun_msrpm(svm
))
2149 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2150 svm
->vmcb
->control
.exit_code_hi
= 0;
2151 svm
->vmcb
->control
.exit_info_1
= 0;
2152 svm
->vmcb
->control
.exit_info_2
= 0;
2154 nested_svm_vmexit(svm
);
2159 static int stgi_interception(struct vcpu_svm
*svm
)
2161 if (nested_svm_check_permissions(svm
))
2164 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2165 skip_emulated_instruction(&svm
->vcpu
);
2172 static int clgi_interception(struct vcpu_svm
*svm
)
2174 if (nested_svm_check_permissions(svm
))
2177 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2178 skip_emulated_instruction(&svm
->vcpu
);
2182 /* After a CLGI no interrupts should come */
2183 svm_clear_vintr(svm
);
2184 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2189 static int invlpga_interception(struct vcpu_svm
*svm
)
2191 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2193 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2194 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2196 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2197 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2199 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2200 skip_emulated_instruction(&svm
->vcpu
);
2204 static int skinit_interception(struct vcpu_svm
*svm
)
2206 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2208 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2212 static int invalid_op_interception(struct vcpu_svm
*svm
)
2214 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2218 static int task_switch_interception(struct vcpu_svm
*svm
)
2222 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2223 SVM_EXITINTINFO_TYPE_MASK
;
2224 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2226 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2228 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2229 bool has_error_code
= false;
2232 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2234 if (svm
->vmcb
->control
.exit_info_2
&
2235 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2236 reason
= TASK_SWITCH_IRET
;
2237 else if (svm
->vmcb
->control
.exit_info_2
&
2238 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2239 reason
= TASK_SWITCH_JMP
;
2241 reason
= TASK_SWITCH_GATE
;
2243 reason
= TASK_SWITCH_CALL
;
2245 if (reason
== TASK_SWITCH_GATE
) {
2247 case SVM_EXITINTINFO_TYPE_NMI
:
2248 svm
->vcpu
.arch
.nmi_injected
= false;
2250 case SVM_EXITINTINFO_TYPE_EXEPT
:
2251 if (svm
->vmcb
->control
.exit_info_2
&
2252 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2253 has_error_code
= true;
2255 (u32
)svm
->vmcb
->control
.exit_info_2
;
2257 kvm_clear_exception_queue(&svm
->vcpu
);
2259 case SVM_EXITINTINFO_TYPE_INTR
:
2260 kvm_clear_interrupt_queue(&svm
->vcpu
);
2267 if (reason
!= TASK_SWITCH_GATE
||
2268 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2269 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2270 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2271 skip_emulated_instruction(&svm
->vcpu
);
2273 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
,
2274 has_error_code
, error_code
) == EMULATE_FAIL
) {
2275 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2276 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2277 svm
->vcpu
.run
->internal
.ndata
= 0;
2283 static int cpuid_interception(struct vcpu_svm
*svm
)
2285 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2286 kvm_emulate_cpuid(&svm
->vcpu
);
2290 static int iret_interception(struct vcpu_svm
*svm
)
2292 ++svm
->vcpu
.stat
.nmi_window_exits
;
2293 svm
->vmcb
->control
.intercept
&= ~(1UL << INTERCEPT_IRET
);
2294 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2298 static int invlpg_interception(struct vcpu_svm
*svm
)
2300 if (emulate_instruction(&svm
->vcpu
, 0, 0, 0) != EMULATE_DONE
)
2301 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
2305 static int emulate_on_interception(struct vcpu_svm
*svm
)
2307 if (emulate_instruction(&svm
->vcpu
, 0, 0, 0) != EMULATE_DONE
)
2308 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
2312 static int cr8_write_interception(struct vcpu_svm
*svm
)
2314 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2316 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
2317 /* instruction emulation calls kvm_set_cr8() */
2318 emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2319 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2320 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2323 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
2325 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2329 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
2331 struct vcpu_svm
*svm
= to_svm(vcpu
);
2334 case MSR_IA32_TSC
: {
2338 tsc_offset
= svm
->nested
.hsave
->control
.tsc_offset
;
2340 tsc_offset
= svm
->vmcb
->control
.tsc_offset
;
2342 *data
= tsc_offset
+ native_read_tsc();
2346 *data
= svm
->vmcb
->save
.star
;
2348 #ifdef CONFIG_X86_64
2350 *data
= svm
->vmcb
->save
.lstar
;
2353 *data
= svm
->vmcb
->save
.cstar
;
2355 case MSR_KERNEL_GS_BASE
:
2356 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2358 case MSR_SYSCALL_MASK
:
2359 *data
= svm
->vmcb
->save
.sfmask
;
2362 case MSR_IA32_SYSENTER_CS
:
2363 *data
= svm
->vmcb
->save
.sysenter_cs
;
2365 case MSR_IA32_SYSENTER_EIP
:
2366 *data
= svm
->sysenter_eip
;
2368 case MSR_IA32_SYSENTER_ESP
:
2369 *data
= svm
->sysenter_esp
;
2372 * Nobody will change the following 5 values in the VMCB so we can
2373 * safely return them on rdmsr. They will always be 0 until LBRV is
2376 case MSR_IA32_DEBUGCTLMSR
:
2377 *data
= svm
->vmcb
->save
.dbgctl
;
2379 case MSR_IA32_LASTBRANCHFROMIP
:
2380 *data
= svm
->vmcb
->save
.br_from
;
2382 case MSR_IA32_LASTBRANCHTOIP
:
2383 *data
= svm
->vmcb
->save
.br_to
;
2385 case MSR_IA32_LASTINTFROMIP
:
2386 *data
= svm
->vmcb
->save
.last_excp_from
;
2388 case MSR_IA32_LASTINTTOIP
:
2389 *data
= svm
->vmcb
->save
.last_excp_to
;
2391 case MSR_VM_HSAVE_PA
:
2392 *data
= svm
->nested
.hsave_msr
;
2395 *data
= svm
->nested
.vm_cr_msr
;
2397 case MSR_IA32_UCODE_REV
:
2401 return kvm_get_msr_common(vcpu
, ecx
, data
);
2406 static int rdmsr_interception(struct vcpu_svm
*svm
)
2408 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2411 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
2412 trace_kvm_msr_read_ex(ecx
);
2413 kvm_inject_gp(&svm
->vcpu
, 0);
2415 trace_kvm_msr_read(ecx
, data
);
2417 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2418 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2419 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2420 skip_emulated_instruction(&svm
->vcpu
);
2425 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
2427 struct vcpu_svm
*svm
= to_svm(vcpu
);
2428 int svm_dis
, chg_mask
;
2430 if (data
& ~SVM_VM_CR_VALID_MASK
)
2433 chg_mask
= SVM_VM_CR_VALID_MASK
;
2435 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
2436 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
2438 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
2439 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
2441 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
2443 /* check for svm_disable while efer.svme is set */
2444 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
2450 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2452 struct vcpu_svm
*svm
= to_svm(vcpu
);
2455 case MSR_IA32_TSC
: {
2456 u64 tsc_offset
= data
- native_read_tsc();
2457 u64 g_tsc_offset
= 0;
2459 if (is_nested(svm
)) {
2460 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
2461 svm
->nested
.hsave
->control
.tsc_offset
;
2462 svm
->nested
.hsave
->control
.tsc_offset
= tsc_offset
;
2465 svm
->vmcb
->control
.tsc_offset
= tsc_offset
+ g_tsc_offset
;
2470 svm
->vmcb
->save
.star
= data
;
2472 #ifdef CONFIG_X86_64
2474 svm
->vmcb
->save
.lstar
= data
;
2477 svm
->vmcb
->save
.cstar
= data
;
2479 case MSR_KERNEL_GS_BASE
:
2480 svm
->vmcb
->save
.kernel_gs_base
= data
;
2482 case MSR_SYSCALL_MASK
:
2483 svm
->vmcb
->save
.sfmask
= data
;
2486 case MSR_IA32_SYSENTER_CS
:
2487 svm
->vmcb
->save
.sysenter_cs
= data
;
2489 case MSR_IA32_SYSENTER_EIP
:
2490 svm
->sysenter_eip
= data
;
2491 svm
->vmcb
->save
.sysenter_eip
= data
;
2493 case MSR_IA32_SYSENTER_ESP
:
2494 svm
->sysenter_esp
= data
;
2495 svm
->vmcb
->save
.sysenter_esp
= data
;
2497 case MSR_IA32_DEBUGCTLMSR
:
2498 if (!svm_has(SVM_FEATURE_LBRV
)) {
2499 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2503 if (data
& DEBUGCTL_RESERVED_BITS
)
2506 svm
->vmcb
->save
.dbgctl
= data
;
2507 if (data
& (1ULL<<0))
2508 svm_enable_lbrv(svm
);
2510 svm_disable_lbrv(svm
);
2512 case MSR_VM_HSAVE_PA
:
2513 svm
->nested
.hsave_msr
= data
;
2516 return svm_set_vm_cr(vcpu
, data
);
2518 pr_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2521 return kvm_set_msr_common(vcpu
, ecx
, data
);
2526 static int wrmsr_interception(struct vcpu_svm
*svm
)
2528 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2529 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2530 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2533 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2534 if (svm_set_msr(&svm
->vcpu
, ecx
, data
)) {
2535 trace_kvm_msr_write_ex(ecx
, data
);
2536 kvm_inject_gp(&svm
->vcpu
, 0);
2538 trace_kvm_msr_write(ecx
, data
);
2539 skip_emulated_instruction(&svm
->vcpu
);
2544 static int msr_interception(struct vcpu_svm
*svm
)
2546 if (svm
->vmcb
->control
.exit_info_1
)
2547 return wrmsr_interception(svm
);
2549 return rdmsr_interception(svm
);
2552 static int interrupt_window_interception(struct vcpu_svm
*svm
)
2554 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2556 svm_clear_vintr(svm
);
2557 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2559 * If the user space waits to inject interrupts, exit as soon as
2562 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
2563 kvm_run
->request_interrupt_window
&&
2564 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
2565 ++svm
->vcpu
.stat
.irq_window_exits
;
2566 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2573 static int pause_interception(struct vcpu_svm
*svm
)
2575 kvm_vcpu_on_spin(&(svm
->vcpu
));
2579 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
2580 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2581 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2582 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2583 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2584 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
2585 [SVM_EXIT_WRITE_CR0
] = emulate_on_interception
,
2586 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2587 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2588 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2589 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2590 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2591 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2592 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2593 [SVM_EXIT_READ_DR4
] = emulate_on_interception
,
2594 [SVM_EXIT_READ_DR5
] = emulate_on_interception
,
2595 [SVM_EXIT_READ_DR6
] = emulate_on_interception
,
2596 [SVM_EXIT_READ_DR7
] = emulate_on_interception
,
2597 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2598 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2599 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2600 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2601 [SVM_EXIT_WRITE_DR4
] = emulate_on_interception
,
2602 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2603 [SVM_EXIT_WRITE_DR6
] = emulate_on_interception
,
2604 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2605 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2606 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2607 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2608 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2609 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2610 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2611 [SVM_EXIT_INTR
] = intr_interception
,
2612 [SVM_EXIT_NMI
] = nmi_interception
,
2613 [SVM_EXIT_SMI
] = nop_on_interception
,
2614 [SVM_EXIT_INIT
] = nop_on_interception
,
2615 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2616 [SVM_EXIT_CPUID
] = cpuid_interception
,
2617 [SVM_EXIT_IRET
] = iret_interception
,
2618 [SVM_EXIT_INVD
] = emulate_on_interception
,
2619 [SVM_EXIT_PAUSE
] = pause_interception
,
2620 [SVM_EXIT_HLT
] = halt_interception
,
2621 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2622 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
2623 [SVM_EXIT_IOIO
] = io_interception
,
2624 [SVM_EXIT_MSR
] = msr_interception
,
2625 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2626 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2627 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2628 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2629 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2630 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2631 [SVM_EXIT_STGI
] = stgi_interception
,
2632 [SVM_EXIT_CLGI
] = clgi_interception
,
2633 [SVM_EXIT_SKINIT
] = skinit_interception
,
2634 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2635 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2636 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2637 [SVM_EXIT_NPF
] = pf_interception
,
2640 static int handle_exit(struct kvm_vcpu
*vcpu
)
2642 struct vcpu_svm
*svm
= to_svm(vcpu
);
2643 struct kvm_run
*kvm_run
= vcpu
->run
;
2644 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2646 trace_kvm_exit(exit_code
, vcpu
);
2648 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR0_MASK
))
2649 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
2651 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
2653 if (unlikely(svm
->nested
.exit_required
)) {
2654 nested_svm_vmexit(svm
);
2655 svm
->nested
.exit_required
= false;
2660 if (is_nested(svm
)) {
2663 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
2664 svm
->vmcb
->control
.exit_info_1
,
2665 svm
->vmcb
->control
.exit_info_2
,
2666 svm
->vmcb
->control
.exit_int_info
,
2667 svm
->vmcb
->control
.exit_int_info_err
);
2669 vmexit
= nested_svm_exit_special(svm
);
2671 if (vmexit
== NESTED_EXIT_CONTINUE
)
2672 vmexit
= nested_svm_exit_handled(svm
);
2674 if (vmexit
== NESTED_EXIT_DONE
)
2678 svm_complete_interrupts(svm
);
2680 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
2681 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2682 kvm_run
->fail_entry
.hardware_entry_failure_reason
2683 = svm
->vmcb
->control
.exit_code
;
2687 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
2688 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
2689 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
)
2690 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
2692 __func__
, svm
->vmcb
->control
.exit_int_info
,
2695 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
2696 || !svm_exit_handlers
[exit_code
]) {
2697 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2698 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
2702 return svm_exit_handlers
[exit_code
](svm
);
2705 static void reload_tss(struct kvm_vcpu
*vcpu
)
2707 int cpu
= raw_smp_processor_id();
2709 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2710 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
2714 static void pre_svm_run(struct vcpu_svm
*svm
)
2716 int cpu
= raw_smp_processor_id();
2718 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2720 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
2721 /* FIXME: handle wraparound of asid_generation */
2722 if (svm
->asid_generation
!= sd
->asid_generation
)
2726 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
2728 struct vcpu_svm
*svm
= to_svm(vcpu
);
2730 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
2731 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
2732 svm
->vmcb
->control
.intercept
|= (1UL << INTERCEPT_IRET
);
2733 ++vcpu
->stat
.nmi_injections
;
2736 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
2738 struct vmcb_control_area
*control
;
2740 trace_kvm_inj_virq(irq
);
2742 ++svm
->vcpu
.stat
.irq_injections
;
2743 control
= &svm
->vmcb
->control
;
2744 control
->int_vector
= irq
;
2745 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
2746 control
->int_ctl
|= V_IRQ_MASK
|
2747 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
2750 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
2752 struct vcpu_svm
*svm
= to_svm(vcpu
);
2754 BUG_ON(!(gif_set(svm
)));
2756 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
2757 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
2760 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
2762 struct vcpu_svm
*svm
= to_svm(vcpu
);
2764 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
2771 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR8_MASK
;
2774 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
2776 struct vcpu_svm
*svm
= to_svm(vcpu
);
2777 struct vmcb
*vmcb
= svm
->vmcb
;
2779 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2780 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
2781 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
2786 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
2788 struct vcpu_svm
*svm
= to_svm(vcpu
);
2790 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
2793 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
2795 struct vcpu_svm
*svm
= to_svm(vcpu
);
2798 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
2799 svm
->vmcb
->control
.intercept
|= (1UL << INTERCEPT_IRET
);
2801 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
2802 svm
->vmcb
->control
.intercept
&= ~(1UL << INTERCEPT_IRET
);
2806 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2808 struct vcpu_svm
*svm
= to_svm(vcpu
);
2809 struct vmcb
*vmcb
= svm
->vmcb
;
2812 if (!gif_set(svm
) ||
2813 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
2816 ret
= !!(vmcb
->save
.rflags
& X86_EFLAGS_IF
);
2819 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
2824 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2826 struct vcpu_svm
*svm
= to_svm(vcpu
);
2829 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2830 * 1, because that's a separate STGI/VMRUN intercept. The next time we
2831 * get that intercept, this function will be called again though and
2832 * we'll get the vintr intercept.
2834 if (gif_set(svm
) && nested_svm_intr(svm
)) {
2836 svm_inject_irq(svm
, 0x0);
2840 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2842 struct vcpu_svm
*svm
= to_svm(vcpu
);
2844 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
2846 return; /* IRET will cause a vm exit */
2849 * Something prevents NMI from been injected. Single step over possible
2850 * problem (IRET or exception injection or interrupt shadow)
2852 svm
->nmi_singlestep
= true;
2853 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
2854 update_db_intercept(vcpu
);
2857 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2862 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
2864 force_new_asid(vcpu
);
2867 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
2871 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
2873 struct vcpu_svm
*svm
= to_svm(vcpu
);
2875 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
2878 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR8_MASK
)) {
2879 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
2880 kvm_set_cr8(vcpu
, cr8
);
2884 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
2886 struct vcpu_svm
*svm
= to_svm(vcpu
);
2889 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
2892 cr8
= kvm_get_cr8(vcpu
);
2893 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
2894 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
2897 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
2901 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
2902 unsigned int3_injected
= svm
->int3_injected
;
2904 svm
->int3_injected
= 0;
2906 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
2907 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
2909 svm
->vcpu
.arch
.nmi_injected
= false;
2910 kvm_clear_exception_queue(&svm
->vcpu
);
2911 kvm_clear_interrupt_queue(&svm
->vcpu
);
2913 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
2916 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
2917 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
2920 case SVM_EXITINTINFO_TYPE_NMI
:
2921 svm
->vcpu
.arch
.nmi_injected
= true;
2923 case SVM_EXITINTINFO_TYPE_EXEPT
:
2925 * In case of software exceptions, do not reinject the vector,
2926 * but re-execute the instruction instead. Rewind RIP first
2927 * if we emulated INT3 before.
2929 if (kvm_exception_is_soft(vector
)) {
2930 if (vector
== BP_VECTOR
&& int3_injected
&&
2931 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
2932 kvm_rip_write(&svm
->vcpu
,
2933 kvm_rip_read(&svm
->vcpu
) -
2937 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
2938 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
2939 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
2942 kvm_requeue_exception(&svm
->vcpu
, vector
);
2944 case SVM_EXITINTINFO_TYPE_INTR
:
2945 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
2952 #ifdef CONFIG_X86_64
2958 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
2960 struct vcpu_svm
*svm
= to_svm(vcpu
);
2965 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
2966 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
2967 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
2970 * A vmexit emulation is required before the vcpu can be executed
2973 if (unlikely(svm
->nested
.exit_required
))
2978 sync_lapic_to_cr8(vcpu
);
2980 save_host_msrs(vcpu
);
2981 fs_selector
= kvm_read_fs();
2982 gs_selector
= kvm_read_gs();
2983 ldt_selector
= kvm_read_ldt();
2984 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
2985 /* required for live migration with NPT */
2987 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
2994 "push %%"R
"bp; \n\t"
2995 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
2996 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
2997 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
2998 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
2999 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
3000 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
3001 #ifdef CONFIG_X86_64
3002 "mov %c[r8](%[svm]), %%r8 \n\t"
3003 "mov %c[r9](%[svm]), %%r9 \n\t"
3004 "mov %c[r10](%[svm]), %%r10 \n\t"
3005 "mov %c[r11](%[svm]), %%r11 \n\t"
3006 "mov %c[r12](%[svm]), %%r12 \n\t"
3007 "mov %c[r13](%[svm]), %%r13 \n\t"
3008 "mov %c[r14](%[svm]), %%r14 \n\t"
3009 "mov %c[r15](%[svm]), %%r15 \n\t"
3012 /* Enter guest mode */
3014 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
3015 __ex(SVM_VMLOAD
) "\n\t"
3016 __ex(SVM_VMRUN
) "\n\t"
3017 __ex(SVM_VMSAVE
) "\n\t"
3020 /* Save guest registers, load host registers */
3021 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
3022 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
3023 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
3024 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
3025 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
3026 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
3027 #ifdef CONFIG_X86_64
3028 "mov %%r8, %c[r8](%[svm]) \n\t"
3029 "mov %%r9, %c[r9](%[svm]) \n\t"
3030 "mov %%r10, %c[r10](%[svm]) \n\t"
3031 "mov %%r11, %c[r11](%[svm]) \n\t"
3032 "mov %%r12, %c[r12](%[svm]) \n\t"
3033 "mov %%r13, %c[r13](%[svm]) \n\t"
3034 "mov %%r14, %c[r14](%[svm]) \n\t"
3035 "mov %%r15, %c[r15](%[svm]) \n\t"
3040 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3041 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3042 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3043 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3044 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3045 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3046 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3047 #ifdef CONFIG_X86_64
3048 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3049 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3050 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3051 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3052 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3053 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3054 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3055 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3058 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
3059 #ifdef CONFIG_X86_64
3060 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3064 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3065 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3066 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3067 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3069 kvm_load_fs(fs_selector
);
3070 kvm_load_gs(gs_selector
);
3071 kvm_load_ldt(ldt_selector
);
3072 load_host_msrs(vcpu
);
3076 local_irq_disable();
3080 sync_cr8_to_lapic(vcpu
);
3085 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3086 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3092 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3094 struct vcpu_svm
*svm
= to_svm(vcpu
);
3097 svm
->vmcb
->control
.nested_cr3
= root
;
3098 force_new_asid(vcpu
);
3102 svm
->vmcb
->save
.cr3
= root
;
3103 force_new_asid(vcpu
);
3106 static int is_disabled(void)
3110 rdmsrl(MSR_VM_CR
, vm_cr
);
3111 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3118 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3121 * Patch in the VMMCALL instruction:
3123 hypercall
[0] = 0x0f;
3124 hypercall
[1] = 0x01;
3125 hypercall
[2] = 0xd9;
3128 static void svm_check_processor_compat(void *rtn
)
3133 static bool svm_cpu_has_accelerated_tpr(void)
3138 static int get_npt_level(void)
3140 #ifdef CONFIG_X86_64
3141 return PT64_ROOT_LEVEL
;
3143 return PT32E_ROOT_LEVEL
;
3147 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3152 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
3156 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
3160 entry
->eax
= 1; /* SVM revision 1 */
3161 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
3162 ASID emulation to nested SVM */
3163 entry
->ecx
= 0; /* Reserved */
3164 entry
->edx
= 0; /* Do not support any additional features */
3170 static const struct trace_print_flags svm_exit_reasons_str
[] = {
3171 { SVM_EXIT_READ_CR0
, "read_cr0" },
3172 { SVM_EXIT_READ_CR3
, "read_cr3" },
3173 { SVM_EXIT_READ_CR4
, "read_cr4" },
3174 { SVM_EXIT_READ_CR8
, "read_cr8" },
3175 { SVM_EXIT_WRITE_CR0
, "write_cr0" },
3176 { SVM_EXIT_WRITE_CR3
, "write_cr3" },
3177 { SVM_EXIT_WRITE_CR4
, "write_cr4" },
3178 { SVM_EXIT_WRITE_CR8
, "write_cr8" },
3179 { SVM_EXIT_READ_DR0
, "read_dr0" },
3180 { SVM_EXIT_READ_DR1
, "read_dr1" },
3181 { SVM_EXIT_READ_DR2
, "read_dr2" },
3182 { SVM_EXIT_READ_DR3
, "read_dr3" },
3183 { SVM_EXIT_WRITE_DR0
, "write_dr0" },
3184 { SVM_EXIT_WRITE_DR1
, "write_dr1" },
3185 { SVM_EXIT_WRITE_DR2
, "write_dr2" },
3186 { SVM_EXIT_WRITE_DR3
, "write_dr3" },
3187 { SVM_EXIT_WRITE_DR5
, "write_dr5" },
3188 { SVM_EXIT_WRITE_DR7
, "write_dr7" },
3189 { SVM_EXIT_EXCP_BASE
+ DB_VECTOR
, "DB excp" },
3190 { SVM_EXIT_EXCP_BASE
+ BP_VECTOR
, "BP excp" },
3191 { SVM_EXIT_EXCP_BASE
+ UD_VECTOR
, "UD excp" },
3192 { SVM_EXIT_EXCP_BASE
+ PF_VECTOR
, "PF excp" },
3193 { SVM_EXIT_EXCP_BASE
+ NM_VECTOR
, "NM excp" },
3194 { SVM_EXIT_EXCP_BASE
+ MC_VECTOR
, "MC excp" },
3195 { SVM_EXIT_INTR
, "interrupt" },
3196 { SVM_EXIT_NMI
, "nmi" },
3197 { SVM_EXIT_SMI
, "smi" },
3198 { SVM_EXIT_INIT
, "init" },
3199 { SVM_EXIT_VINTR
, "vintr" },
3200 { SVM_EXIT_CPUID
, "cpuid" },
3201 { SVM_EXIT_INVD
, "invd" },
3202 { SVM_EXIT_HLT
, "hlt" },
3203 { SVM_EXIT_INVLPG
, "invlpg" },
3204 { SVM_EXIT_INVLPGA
, "invlpga" },
3205 { SVM_EXIT_IOIO
, "io" },
3206 { SVM_EXIT_MSR
, "msr" },
3207 { SVM_EXIT_TASK_SWITCH
, "task_switch" },
3208 { SVM_EXIT_SHUTDOWN
, "shutdown" },
3209 { SVM_EXIT_VMRUN
, "vmrun" },
3210 { SVM_EXIT_VMMCALL
, "hypercall" },
3211 { SVM_EXIT_VMLOAD
, "vmload" },
3212 { SVM_EXIT_VMSAVE
, "vmsave" },
3213 { SVM_EXIT_STGI
, "stgi" },
3214 { SVM_EXIT_CLGI
, "clgi" },
3215 { SVM_EXIT_SKINIT
, "skinit" },
3216 { SVM_EXIT_WBINVD
, "wbinvd" },
3217 { SVM_EXIT_MONITOR
, "monitor" },
3218 { SVM_EXIT_MWAIT
, "mwait" },
3219 { SVM_EXIT_NPF
, "npf" },
3223 static int svm_get_lpage_level(void)
3225 return PT_PDPE_LEVEL
;
3228 static bool svm_rdtscp_supported(void)
3233 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
3235 struct vcpu_svm
*svm
= to_svm(vcpu
);
3237 svm
->vmcb
->control
.intercept_exceptions
|= 1 << NM_VECTOR
;
3239 svm
->nested
.hsave
->control
.intercept_exceptions
|= 1 << NM_VECTOR
;
3240 update_cr0_intercept(svm
);
3243 static struct kvm_x86_ops svm_x86_ops
= {
3244 .cpu_has_kvm_support
= has_svm
,
3245 .disabled_by_bios
= is_disabled
,
3246 .hardware_setup
= svm_hardware_setup
,
3247 .hardware_unsetup
= svm_hardware_unsetup
,
3248 .check_processor_compatibility
= svm_check_processor_compat
,
3249 .hardware_enable
= svm_hardware_enable
,
3250 .hardware_disable
= svm_hardware_disable
,
3251 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
3253 .vcpu_create
= svm_create_vcpu
,
3254 .vcpu_free
= svm_free_vcpu
,
3255 .vcpu_reset
= svm_vcpu_reset
,
3257 .prepare_guest_switch
= svm_prepare_guest_switch
,
3258 .vcpu_load
= svm_vcpu_load
,
3259 .vcpu_put
= svm_vcpu_put
,
3261 .set_guest_debug
= svm_guest_debug
,
3262 .get_msr
= svm_get_msr
,
3263 .set_msr
= svm_set_msr
,
3264 .get_segment_base
= svm_get_segment_base
,
3265 .get_segment
= svm_get_segment
,
3266 .set_segment
= svm_set_segment
,
3267 .get_cpl
= svm_get_cpl
,
3268 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
3269 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
3270 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
3271 .set_cr0
= svm_set_cr0
,
3272 .set_cr3
= svm_set_cr3
,
3273 .set_cr4
= svm_set_cr4
,
3274 .set_efer
= svm_set_efer
,
3275 .get_idt
= svm_get_idt
,
3276 .set_idt
= svm_set_idt
,
3277 .get_gdt
= svm_get_gdt
,
3278 .set_gdt
= svm_set_gdt
,
3279 .set_dr7
= svm_set_dr7
,
3280 .cache_reg
= svm_cache_reg
,
3281 .get_rflags
= svm_get_rflags
,
3282 .set_rflags
= svm_set_rflags
,
3283 .fpu_activate
= svm_fpu_activate
,
3284 .fpu_deactivate
= svm_fpu_deactivate
,
3286 .tlb_flush
= svm_flush_tlb
,
3288 .run
= svm_vcpu_run
,
3289 .handle_exit
= handle_exit
,
3290 .skip_emulated_instruction
= skip_emulated_instruction
,
3291 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
3292 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
3293 .patch_hypercall
= svm_patch_hypercall
,
3294 .set_irq
= svm_set_irq
,
3295 .set_nmi
= svm_inject_nmi
,
3296 .queue_exception
= svm_queue_exception
,
3297 .interrupt_allowed
= svm_interrupt_allowed
,
3298 .nmi_allowed
= svm_nmi_allowed
,
3299 .get_nmi_mask
= svm_get_nmi_mask
,
3300 .set_nmi_mask
= svm_set_nmi_mask
,
3301 .enable_nmi_window
= enable_nmi_window
,
3302 .enable_irq_window
= enable_irq_window
,
3303 .update_cr8_intercept
= update_cr8_intercept
,
3305 .set_tss_addr
= svm_set_tss_addr
,
3306 .get_tdp_level
= get_npt_level
,
3307 .get_mt_mask
= svm_get_mt_mask
,
3309 .exit_reasons_str
= svm_exit_reasons_str
,
3310 .get_lpage_level
= svm_get_lpage_level
,
3312 .cpuid_update
= svm_cpuid_update
,
3314 .rdtscp_supported
= svm_rdtscp_supported
,
3316 .set_supported_cpuid
= svm_set_supported_cpuid
,
3319 static int __init
svm_init(void)
3321 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
3322 __alignof__(struct vcpu_svm
), THIS_MODULE
);
3325 static void __exit
svm_exit(void)
3330 module_init(svm_init
)
3331 module_exit(svm_exit
)