2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
58 #define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
61 MODULE_AUTHOR("Qumranet");
62 MODULE_LICENSE("GPL");
64 static const struct x86_cpu_id vmx_cpu_id
[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
68 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
70 static bool __read_mostly enable_vpid
= 1;
71 module_param_named(vpid
, enable_vpid
, bool, 0444);
73 static bool __read_mostly flexpriority_enabled
= 1;
74 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
76 static bool __read_mostly enable_ept
= 1;
77 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
79 static bool __read_mostly enable_unrestricted_guest
= 1;
80 module_param_named(unrestricted_guest
,
81 enable_unrestricted_guest
, bool, S_IRUGO
);
83 static bool __read_mostly enable_ept_ad_bits
= 1;
84 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
86 static bool __read_mostly emulate_invalid_guest_state
= true;
87 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
89 static bool __read_mostly fasteoi
= 1;
90 module_param(fasteoi
, bool, S_IRUGO
);
92 static bool __read_mostly enable_apicv
= 1;
93 module_param(enable_apicv
, bool, S_IRUGO
);
95 static bool __read_mostly enable_shadow_vmcs
= 1;
96 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested
= 0;
103 module_param(nested
, bool, S_IRUGO
);
105 static u64 __read_mostly host_xss
;
107 static bool __read_mostly enable_pml
= 1;
108 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113 static int __read_mostly cpu_preemption_timer_multi
;
114 static bool __read_mostly enable_preemption_timer
= 1;
116 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
121 #define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
123 #define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
125 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
138 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
148 * According to test, this time is usually smaller than 128 cycles.
149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
155 #define KVM_VMX_DEFAULT_PLE_GAP 128
156 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
162 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
163 module_param(ple_gap
, int, S_IRUGO
);
165 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
166 module_param(ple_window
, int, S_IRUGO
);
168 /* Default doubles per-vcpu window every exit. */
169 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
170 module_param(ple_window_grow
, int, S_IRUGO
);
172 /* Default resets per-vcpu window every exit to ple_window. */
173 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
174 module_param(ple_window_shrink
, int, S_IRUGO
);
176 /* Default is to compute the maximum so we can never overflow. */
177 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
178 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
179 module_param(ple_window_max
, int, S_IRUGO
);
181 extern const ulong vmx_return
;
183 #define NR_AUTOLOAD_MSRS 8
184 #define VMCS02_POOL_SIZE 1
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
199 struct vmcs
*shadow_vmcs
;
202 bool nmi_known_unmasked
;
203 struct list_head loaded_vmcss_on_cpu_link
;
206 struct shared_msr_entry
{
213 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
214 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
215 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
216 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
217 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
218 * More than one of these structures may exist, if L1 runs multiple L2 guests.
219 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
220 * underlying hardware which will be used to run L2.
221 * This structure is packed to ensure that its layout is identical across
222 * machines (necessary for live migration).
223 * If there are changes in this struct, VMCS12_REVISION must be changed.
225 typedef u64 natural_width
;
226 struct __packed vmcs12
{
227 /* According to the Intel spec, a VMCS region must start with the
228 * following two fields. Then follow implementation-specific data.
233 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
234 u32 padding
[7]; /* room for future expansion */
239 u64 vm_exit_msr_store_addr
;
240 u64 vm_exit_msr_load_addr
;
241 u64 vm_entry_msr_load_addr
;
243 u64 virtual_apic_page_addr
;
244 u64 apic_access_addr
;
245 u64 posted_intr_desc_addr
;
247 u64 eoi_exit_bitmap0
;
248 u64 eoi_exit_bitmap1
;
249 u64 eoi_exit_bitmap2
;
250 u64 eoi_exit_bitmap3
;
252 u64 guest_physical_address
;
253 u64 vmcs_link_pointer
;
255 u64 guest_ia32_debugctl
;
258 u64 guest_ia32_perf_global_ctrl
;
266 u64 host_ia32_perf_global_ctrl
;
267 u64 padding64
[8]; /* room for future expansion */
269 * To allow migration of L1 (complete with its L2 guests) between
270 * machines of different natural widths (32 or 64 bit), we cannot have
271 * unsigned long fields with no explict size. We use u64 (aliased
272 * natural_width) instead. Luckily, x86 is little-endian.
274 natural_width cr0_guest_host_mask
;
275 natural_width cr4_guest_host_mask
;
276 natural_width cr0_read_shadow
;
277 natural_width cr4_read_shadow
;
278 natural_width cr3_target_value0
;
279 natural_width cr3_target_value1
;
280 natural_width cr3_target_value2
;
281 natural_width cr3_target_value3
;
282 natural_width exit_qualification
;
283 natural_width guest_linear_address
;
284 natural_width guest_cr0
;
285 natural_width guest_cr3
;
286 natural_width guest_cr4
;
287 natural_width guest_es_base
;
288 natural_width guest_cs_base
;
289 natural_width guest_ss_base
;
290 natural_width guest_ds_base
;
291 natural_width guest_fs_base
;
292 natural_width guest_gs_base
;
293 natural_width guest_ldtr_base
;
294 natural_width guest_tr_base
;
295 natural_width guest_gdtr_base
;
296 natural_width guest_idtr_base
;
297 natural_width guest_dr7
;
298 natural_width guest_rsp
;
299 natural_width guest_rip
;
300 natural_width guest_rflags
;
301 natural_width guest_pending_dbg_exceptions
;
302 natural_width guest_sysenter_esp
;
303 natural_width guest_sysenter_eip
;
304 natural_width host_cr0
;
305 natural_width host_cr3
;
306 natural_width host_cr4
;
307 natural_width host_fs_base
;
308 natural_width host_gs_base
;
309 natural_width host_tr_base
;
310 natural_width host_gdtr_base
;
311 natural_width host_idtr_base
;
312 natural_width host_ia32_sysenter_esp
;
313 natural_width host_ia32_sysenter_eip
;
314 natural_width host_rsp
;
315 natural_width host_rip
;
316 natural_width paddingl
[8]; /* room for future expansion */
317 u32 pin_based_vm_exec_control
;
318 u32 cpu_based_vm_exec_control
;
319 u32 exception_bitmap
;
320 u32 page_fault_error_code_mask
;
321 u32 page_fault_error_code_match
;
322 u32 cr3_target_count
;
323 u32 vm_exit_controls
;
324 u32 vm_exit_msr_store_count
;
325 u32 vm_exit_msr_load_count
;
326 u32 vm_entry_controls
;
327 u32 vm_entry_msr_load_count
;
328 u32 vm_entry_intr_info_field
;
329 u32 vm_entry_exception_error_code
;
330 u32 vm_entry_instruction_len
;
332 u32 secondary_vm_exec_control
;
333 u32 vm_instruction_error
;
335 u32 vm_exit_intr_info
;
336 u32 vm_exit_intr_error_code
;
337 u32 idt_vectoring_info_field
;
338 u32 idt_vectoring_error_code
;
339 u32 vm_exit_instruction_len
;
340 u32 vmx_instruction_info
;
347 u32 guest_ldtr_limit
;
349 u32 guest_gdtr_limit
;
350 u32 guest_idtr_limit
;
351 u32 guest_es_ar_bytes
;
352 u32 guest_cs_ar_bytes
;
353 u32 guest_ss_ar_bytes
;
354 u32 guest_ds_ar_bytes
;
355 u32 guest_fs_ar_bytes
;
356 u32 guest_gs_ar_bytes
;
357 u32 guest_ldtr_ar_bytes
;
358 u32 guest_tr_ar_bytes
;
359 u32 guest_interruptibility_info
;
360 u32 guest_activity_state
;
361 u32 guest_sysenter_cs
;
362 u32 host_ia32_sysenter_cs
;
363 u32 vmx_preemption_timer_value
;
364 u32 padding32
[7]; /* room for future expansion */
365 u16 virtual_processor_id
;
367 u16 guest_es_selector
;
368 u16 guest_cs_selector
;
369 u16 guest_ss_selector
;
370 u16 guest_ds_selector
;
371 u16 guest_fs_selector
;
372 u16 guest_gs_selector
;
373 u16 guest_ldtr_selector
;
374 u16 guest_tr_selector
;
375 u16 guest_intr_status
;
377 u16 host_es_selector
;
378 u16 host_cs_selector
;
379 u16 host_ss_selector
;
380 u16 host_ds_selector
;
381 u16 host_fs_selector
;
382 u16 host_gs_selector
;
383 u16 host_tr_selector
;
387 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
388 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
389 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
391 #define VMCS12_REVISION 0x11e57ed0
394 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
395 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
396 * current implementation, 4K are reserved to avoid future complications.
398 #define VMCS12_SIZE 0x1000
400 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
402 struct list_head list
;
404 struct loaded_vmcs vmcs02
;
408 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
409 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
412 /* Has the level1 guest done vmxon? */
417 /* The guest-physical address of the current VMCS L1 keeps for L2 */
420 * Cache of the guest's VMCS, existing outside of guest memory.
421 * Loaded from guest memory during VMPTRLD. Flushed to guest
422 * memory during VMXOFF, VMCLEAR, VMPTRLD.
424 struct vmcs12
*cached_vmcs12
;
426 * Indicates if the shadow vmcs must be updated with the
427 * data hold by vmcs12
429 bool sync_shadow_vmcs
;
431 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
432 struct list_head vmcs02_pool
;
434 bool change_vmcs01_virtual_x2apic_mode
;
435 /* L2 must run next, and mustn't decide to exit to L1. */
436 bool nested_run_pending
;
438 * Guest pages referred to in vmcs02 with host-physical pointers, so
439 * we must keep them pinned while L2 runs.
441 struct page
*apic_access_page
;
442 struct page
*virtual_apic_page
;
443 struct page
*pi_desc_page
;
444 struct pi_desc
*pi_desc
;
448 unsigned long *msr_bitmap
;
450 struct hrtimer preemption_timer
;
451 bool preemption_timer_expired
;
453 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
460 * We only store the "true" versions of the VMX capability MSRs. We
461 * generate the "non-true" versions by setting the must-be-1 bits
462 * according to the SDM.
464 u32 nested_vmx_procbased_ctls_low
;
465 u32 nested_vmx_procbased_ctls_high
;
466 u32 nested_vmx_secondary_ctls_low
;
467 u32 nested_vmx_secondary_ctls_high
;
468 u32 nested_vmx_pinbased_ctls_low
;
469 u32 nested_vmx_pinbased_ctls_high
;
470 u32 nested_vmx_exit_ctls_low
;
471 u32 nested_vmx_exit_ctls_high
;
472 u32 nested_vmx_entry_ctls_low
;
473 u32 nested_vmx_entry_ctls_high
;
474 u32 nested_vmx_misc_low
;
475 u32 nested_vmx_misc_high
;
476 u32 nested_vmx_ept_caps
;
477 u32 nested_vmx_vpid_caps
;
478 u64 nested_vmx_basic
;
479 u64 nested_vmx_cr0_fixed0
;
480 u64 nested_vmx_cr0_fixed1
;
481 u64 nested_vmx_cr4_fixed0
;
482 u64 nested_vmx_cr4_fixed1
;
483 u64 nested_vmx_vmcs_enum
;
486 #define POSTED_INTR_ON 0
487 #define POSTED_INTR_SN 1
489 /* Posted-Interrupt Descriptor */
491 u32 pir
[8]; /* Posted interrupt requested */
494 /* bit 256 - Outstanding Notification */
496 /* bit 257 - Suppress Notification */
498 /* bit 271:258 - Reserved */
500 /* bit 279:272 - Notification Vector */
502 /* bit 287:280 - Reserved */
504 /* bit 319:288 - Notification Destination */
512 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
514 return test_and_set_bit(POSTED_INTR_ON
,
515 (unsigned long *)&pi_desc
->control
);
518 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
520 return test_and_clear_bit(POSTED_INTR_ON
,
521 (unsigned long *)&pi_desc
->control
);
524 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
526 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
529 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
531 return clear_bit(POSTED_INTR_SN
,
532 (unsigned long *)&pi_desc
->control
);
535 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
537 return set_bit(POSTED_INTR_SN
,
538 (unsigned long *)&pi_desc
->control
);
541 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
543 clear_bit(POSTED_INTR_ON
,
544 (unsigned long *)&pi_desc
->control
);
547 static inline int pi_test_on(struct pi_desc
*pi_desc
)
549 return test_bit(POSTED_INTR_ON
,
550 (unsigned long *)&pi_desc
->control
);
553 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
555 return test_bit(POSTED_INTR_SN
,
556 (unsigned long *)&pi_desc
->control
);
560 struct kvm_vcpu vcpu
;
561 unsigned long host_rsp
;
564 u32 idt_vectoring_info
;
566 struct shared_msr_entry
*guest_msrs
;
569 unsigned long host_idt_base
;
571 u64 msr_host_kernel_gs_base
;
572 u64 msr_guest_kernel_gs_base
;
574 u32 vm_entry_controls_shadow
;
575 u32 vm_exit_controls_shadow
;
577 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
578 * non-nested (L1) guest, it always points to vmcs01. For a nested
579 * guest (L2), it points to a different VMCS.
581 struct loaded_vmcs vmcs01
;
582 struct loaded_vmcs
*loaded_vmcs
;
583 bool __launched
; /* temporary, used in vmx_vcpu_run */
584 struct msr_autoload
{
586 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
587 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
591 u16 fs_sel
, gs_sel
, ldt_sel
;
595 int gs_ldt_reload_needed
;
596 int fs_reload_needed
;
597 u64 msr_host_bndcfgs
;
598 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
599 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
604 struct kvm_segment segs
[8];
607 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
608 struct kvm_save_segment
{
616 bool emulation_required
;
620 /* Posted interrupt descriptor */
621 struct pi_desc pi_desc
;
623 /* Support for a guest hypervisor (nested VMX) */
624 struct nested_vmx nested
;
626 /* Dynamic PLE window. */
628 bool ple_window_dirty
;
630 /* Support for PML */
631 #define PML_ENTITY_NUM 512
634 /* apic deadline value in host tsc */
637 u64 current_tsc_ratio
;
639 bool guest_pkru_valid
;
644 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
645 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
646 * in msr_ia32_feature_control_valid_bits.
648 u64 msr_ia32_feature_control
;
649 u64 msr_ia32_feature_control_valid_bits
;
652 enum segment_cache_field
{
661 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
663 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
666 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
668 return &(to_vmx(vcpu
)->pi_desc
);
671 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
672 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
673 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
674 [number##_HIGH] = VMCS12_OFFSET(name)+4
677 static unsigned long shadow_read_only_fields
[] = {
679 * We do NOT shadow fields that are modified when L0
680 * traps and emulates any vmx instruction (e.g. VMPTRLD,
681 * VMXON...) executed by L1.
682 * For example, VM_INSTRUCTION_ERROR is read
683 * by L1 if a vmx instruction fails (part of the error path).
684 * Note the code assumes this logic. If for some reason
685 * we start shadowing these fields then we need to
686 * force a shadow sync when L0 emulates vmx instructions
687 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
688 * by nested_vmx_failValid)
692 VM_EXIT_INSTRUCTION_LEN
,
693 IDT_VECTORING_INFO_FIELD
,
694 IDT_VECTORING_ERROR_CODE
,
695 VM_EXIT_INTR_ERROR_CODE
,
697 GUEST_LINEAR_ADDRESS
,
698 GUEST_PHYSICAL_ADDRESS
700 static int max_shadow_read_only_fields
=
701 ARRAY_SIZE(shadow_read_only_fields
);
703 static unsigned long shadow_read_write_fields
[] = {
710 GUEST_INTERRUPTIBILITY_INFO
,
723 CPU_BASED_VM_EXEC_CONTROL
,
724 VM_ENTRY_EXCEPTION_ERROR_CODE
,
725 VM_ENTRY_INTR_INFO_FIELD
,
726 VM_ENTRY_INSTRUCTION_LEN
,
727 VM_ENTRY_EXCEPTION_ERROR_CODE
,
733 static int max_shadow_read_write_fields
=
734 ARRAY_SIZE(shadow_read_write_fields
);
736 static const unsigned short vmcs_field_to_offset_table
[] = {
737 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
738 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
739 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
740 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
741 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
742 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
743 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
744 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
745 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
746 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
747 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
748 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
749 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
750 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
751 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
752 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
753 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
754 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
755 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
756 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
757 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
758 FIELD64(MSR_BITMAP
, msr_bitmap
),
759 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
760 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
761 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
762 FIELD64(TSC_OFFSET
, tsc_offset
),
763 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
764 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
765 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
766 FIELD64(EPT_POINTER
, ept_pointer
),
767 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
768 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
769 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
770 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
771 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
772 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
773 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
774 FIELD64(PML_ADDRESS
, pml_address
),
775 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
776 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
777 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
778 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
779 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
780 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
781 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
782 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
783 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
784 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
785 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
786 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
787 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
788 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
789 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
790 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
791 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
792 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
793 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
794 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
795 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
796 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
797 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
798 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
799 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
800 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
801 FIELD(TPR_THRESHOLD
, tpr_threshold
),
802 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
803 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
804 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
805 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
806 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
807 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
808 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
809 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
810 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
811 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
812 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
813 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
814 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
815 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
816 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
817 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
818 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
819 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
820 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
821 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
822 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
823 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
824 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
825 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
826 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
827 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
828 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
829 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
830 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
831 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
832 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
833 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
834 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
835 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
836 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
837 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
838 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
839 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
840 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
841 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
842 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
843 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
844 FIELD(GUEST_CR0
, guest_cr0
),
845 FIELD(GUEST_CR3
, guest_cr3
),
846 FIELD(GUEST_CR4
, guest_cr4
),
847 FIELD(GUEST_ES_BASE
, guest_es_base
),
848 FIELD(GUEST_CS_BASE
, guest_cs_base
),
849 FIELD(GUEST_SS_BASE
, guest_ss_base
),
850 FIELD(GUEST_DS_BASE
, guest_ds_base
),
851 FIELD(GUEST_FS_BASE
, guest_fs_base
),
852 FIELD(GUEST_GS_BASE
, guest_gs_base
),
853 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
854 FIELD(GUEST_TR_BASE
, guest_tr_base
),
855 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
856 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
857 FIELD(GUEST_DR7
, guest_dr7
),
858 FIELD(GUEST_RSP
, guest_rsp
),
859 FIELD(GUEST_RIP
, guest_rip
),
860 FIELD(GUEST_RFLAGS
, guest_rflags
),
861 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
862 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
863 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
864 FIELD(HOST_CR0
, host_cr0
),
865 FIELD(HOST_CR3
, host_cr3
),
866 FIELD(HOST_CR4
, host_cr4
),
867 FIELD(HOST_FS_BASE
, host_fs_base
),
868 FIELD(HOST_GS_BASE
, host_gs_base
),
869 FIELD(HOST_TR_BASE
, host_tr_base
),
870 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
871 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
872 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
873 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
874 FIELD(HOST_RSP
, host_rsp
),
875 FIELD(HOST_RIP
, host_rip
),
878 static inline short vmcs_field_to_offset(unsigned long field
)
880 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
882 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
883 vmcs_field_to_offset_table
[field
] == 0)
886 return vmcs_field_to_offset_table
[field
];
889 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
891 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
894 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
896 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
897 if (is_error_page(page
))
903 static void nested_release_page(struct page
*page
)
905 kvm_release_page_dirty(page
);
908 static void nested_release_page_clean(struct page
*page
)
910 kvm_release_page_clean(page
);
913 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
914 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
915 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
916 static bool vmx_xsaves_supported(void);
917 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
918 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
919 struct kvm_segment
*var
, int seg
);
920 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
921 struct kvm_segment
*var
, int seg
);
922 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
923 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
924 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
925 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
926 static int alloc_identity_pagetable(struct kvm
*kvm
);
927 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
928 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
929 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
932 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
933 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
935 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
936 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
938 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
941 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
942 * can find which vCPU should be waken up.
944 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
945 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
950 VMX_MSR_BITMAP_LEGACY
,
951 VMX_MSR_BITMAP_LONGMODE
,
952 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
953 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
954 VMX_MSR_BITMAP_LEGACY_X2APIC
,
955 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
961 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
963 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
964 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
965 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
966 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
967 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
969 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
970 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
971 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
972 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
974 static bool cpu_has_load_ia32_efer
;
975 static bool cpu_has_load_perf_global_ctrl
;
977 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
978 static DEFINE_SPINLOCK(vmx_vpid_lock
);
980 static struct vmcs_config
{
985 u32 pin_based_exec_ctrl
;
986 u32 cpu_based_exec_ctrl
;
987 u32 cpu_based_2nd_exec_ctrl
;
992 static struct vmx_capability
{
997 #define VMX_SEGMENT_FIELD(seg) \
998 [VCPU_SREG_##seg] = { \
999 .selector = GUEST_##seg##_SELECTOR, \
1000 .base = GUEST_##seg##_BASE, \
1001 .limit = GUEST_##seg##_LIMIT, \
1002 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1005 static const struct kvm_vmx_segment_field
{
1010 } kvm_vmx_segment_fields
[] = {
1011 VMX_SEGMENT_FIELD(CS
),
1012 VMX_SEGMENT_FIELD(DS
),
1013 VMX_SEGMENT_FIELD(ES
),
1014 VMX_SEGMENT_FIELD(FS
),
1015 VMX_SEGMENT_FIELD(GS
),
1016 VMX_SEGMENT_FIELD(SS
),
1017 VMX_SEGMENT_FIELD(TR
),
1018 VMX_SEGMENT_FIELD(LDTR
),
1021 static u64 host_efer
;
1023 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1026 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027 * away by decrementing the array size.
1029 static const u32 vmx_msr_index
[] = {
1030 #ifdef CONFIG_X86_64
1031 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1033 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1036 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1038 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1039 INTR_INFO_VALID_MASK
)) ==
1040 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1043 static inline bool is_debug(u32 intr_info
)
1045 return is_exception_n(intr_info
, DB_VECTOR
);
1048 static inline bool is_breakpoint(u32 intr_info
)
1050 return is_exception_n(intr_info
, BP_VECTOR
);
1053 static inline bool is_page_fault(u32 intr_info
)
1055 return is_exception_n(intr_info
, PF_VECTOR
);
1058 static inline bool is_no_device(u32 intr_info
)
1060 return is_exception_n(intr_info
, NM_VECTOR
);
1063 static inline bool is_invalid_opcode(u32 intr_info
)
1065 return is_exception_n(intr_info
, UD_VECTOR
);
1068 static inline bool is_external_interrupt(u32 intr_info
)
1070 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1071 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1074 static inline bool is_machine_check(u32 intr_info
)
1076 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1077 INTR_INFO_VALID_MASK
)) ==
1078 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1083 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1088 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1093 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1098 return vmcs_config
.cpu_based_exec_ctrl
&
1099 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1104 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1105 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1110 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1111 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1116 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1117 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1122 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1123 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1127 * Comment's format: document - errata name - stepping - processor name.
1129 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1131 static u32 vmx_preemption_cpu_tfms
[] = {
1132 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1134 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1138 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1140 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1143 * 320767.pdf - AAP86 - B1 -
1144 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1153 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1161 u32 eax
= cpuid_eax(0x00000001), i
;
1163 /* Clear the reserved bits */
1164 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1165 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1166 if (eax
== vmx_preemption_cpu_tfms
[i
])
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1174 return vmcs_config
.pin_based_exec_ctrl
&
1175 PIN_BASED_VMX_PREEMPTION_TIMER
;
1178 static inline bool cpu_has_vmx_posted_intr(void)
1180 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1181 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1184 static inline bool cpu_has_vmx_apicv(void)
1186 return cpu_has_vmx_apic_register_virt() &&
1187 cpu_has_vmx_virtual_intr_delivery() &&
1188 cpu_has_vmx_posted_intr();
1191 static inline bool cpu_has_vmx_flexpriority(void)
1193 return cpu_has_vmx_tpr_shadow() &&
1194 cpu_has_vmx_virtualize_apic_accesses();
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1199 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1204 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1209 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1214 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1219 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1222 static inline bool cpu_has_vmx_invept_context(void)
1224 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1227 static inline bool cpu_has_vmx_invept_global(void)
1229 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1234 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1239 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1242 static inline bool cpu_has_vmx_invvpid(void)
1244 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1247 static inline bool cpu_has_vmx_ept(void)
1249 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1250 SECONDARY_EXEC_ENABLE_EPT
;
1253 static inline bool cpu_has_vmx_unrestricted_guest(void)
1255 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1256 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1259 static inline bool cpu_has_vmx_ple(void)
1261 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1262 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1265 static inline bool cpu_has_vmx_basic_inout(void)
1267 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1270 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1272 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1275 static inline bool cpu_has_vmx_vpid(void)
1277 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1278 SECONDARY_EXEC_ENABLE_VPID
;
1281 static inline bool cpu_has_vmx_rdtscp(void)
1283 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1284 SECONDARY_EXEC_RDTSCP
;
1287 static inline bool cpu_has_vmx_invpcid(void)
1289 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1290 SECONDARY_EXEC_ENABLE_INVPCID
;
1293 static inline bool cpu_has_vmx_wbinvd_exit(void)
1295 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1296 SECONDARY_EXEC_WBINVD_EXITING
;
1299 static inline bool cpu_has_vmx_shadow_vmcs(void)
1302 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1303 /* check if the cpu supports writing r/o exit information fields */
1304 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1307 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1308 SECONDARY_EXEC_SHADOW_VMCS
;
1311 static inline bool cpu_has_vmx_pml(void)
1313 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1316 static inline bool cpu_has_vmx_tsc_scaling(void)
1318 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1319 SECONDARY_EXEC_TSC_SCALING
;
1322 static inline bool report_flexpriority(void)
1324 return flexpriority_enabled
;
1327 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1329 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1332 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1334 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1337 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1339 return (vmcs12
->cpu_based_vm_exec_control
&
1340 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1341 (vmcs12
->secondary_vm_exec_control
& bit
);
1344 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1346 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1349 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1351 return vmcs12
->pin_based_vm_exec_control
&
1352 PIN_BASED_VMX_PREEMPTION_TIMER
;
1355 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1357 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1360 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1362 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1363 vmx_xsaves_supported();
1366 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1368 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1371 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1373 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1376 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1378 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1381 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1383 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1386 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1388 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1391 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1393 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1396 static inline bool is_nmi(u32 intr_info
)
1398 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1399 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1402 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1404 unsigned long exit_qualification
);
1405 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1406 struct vmcs12
*vmcs12
,
1407 u32 reason
, unsigned long qualification
);
1409 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1413 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1414 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1419 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1425 } operand
= { vpid
, 0, gva
};
1427 asm volatile (__ex(ASM_VMX_INVVPID
)
1428 /* CF==1 or ZF==1 --> rc = -1 */
1429 "; ja 1f ; ud2 ; 1:"
1430 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1433 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1437 } operand
= {eptp
, gpa
};
1439 asm volatile (__ex(ASM_VMX_INVEPT
)
1440 /* CF==1 or ZF==1 --> rc = -1 */
1441 "; ja 1f ; ud2 ; 1:\n"
1442 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1445 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1449 i
= __find_msr_index(vmx
, msr
);
1451 return &vmx
->guest_msrs
[i
];
1455 static void vmcs_clear(struct vmcs
*vmcs
)
1457 u64 phys_addr
= __pa(vmcs
);
1460 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1461 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1464 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1468 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1470 vmcs_clear(loaded_vmcs
->vmcs
);
1471 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1472 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1473 loaded_vmcs
->cpu
= -1;
1474 loaded_vmcs
->launched
= 0;
1477 static void vmcs_load(struct vmcs
*vmcs
)
1479 u64 phys_addr
= __pa(vmcs
);
1482 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1483 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1486 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1490 #ifdef CONFIG_KEXEC_CORE
1492 * This bitmap is used to indicate whether the vmclear
1493 * operation is enabled on all cpus. All disabled by
1496 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1498 static inline void crash_enable_local_vmclear(int cpu
)
1500 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1503 static inline void crash_disable_local_vmclear(int cpu
)
1505 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1508 static inline int crash_local_vmclear_enabled(int cpu
)
1510 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1513 static void crash_vmclear_local_loaded_vmcss(void)
1515 int cpu
= raw_smp_processor_id();
1516 struct loaded_vmcs
*v
;
1518 if (!crash_local_vmclear_enabled(cpu
))
1521 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1522 loaded_vmcss_on_cpu_link
)
1523 vmcs_clear(v
->vmcs
);
1526 static inline void crash_enable_local_vmclear(int cpu
) { }
1527 static inline void crash_disable_local_vmclear(int cpu
) { }
1528 #endif /* CONFIG_KEXEC_CORE */
1530 static void __loaded_vmcs_clear(void *arg
)
1532 struct loaded_vmcs
*loaded_vmcs
= arg
;
1533 int cpu
= raw_smp_processor_id();
1535 if (loaded_vmcs
->cpu
!= cpu
)
1536 return; /* vcpu migration can race with cpu offline */
1537 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1538 per_cpu(current_vmcs
, cpu
) = NULL
;
1539 crash_disable_local_vmclear(cpu
);
1540 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1543 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1544 * is before setting loaded_vmcs->vcpu to -1 which is done in
1545 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1546 * then adds the vmcs into percpu list before it is deleted.
1550 loaded_vmcs_init(loaded_vmcs
);
1551 crash_enable_local_vmclear(cpu
);
1554 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1556 int cpu
= loaded_vmcs
->cpu
;
1559 smp_call_function_single(cpu
,
1560 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1563 static inline void vpid_sync_vcpu_single(int vpid
)
1568 if (cpu_has_vmx_invvpid_single())
1569 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1572 static inline void vpid_sync_vcpu_global(void)
1574 if (cpu_has_vmx_invvpid_global())
1575 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1578 static inline void vpid_sync_context(int vpid
)
1580 if (cpu_has_vmx_invvpid_single())
1581 vpid_sync_vcpu_single(vpid
);
1583 vpid_sync_vcpu_global();
1586 static inline void ept_sync_global(void)
1588 if (cpu_has_vmx_invept_global())
1589 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1592 static inline void ept_sync_context(u64 eptp
)
1595 if (cpu_has_vmx_invept_context())
1596 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1602 static __always_inline
void vmcs_check16(unsigned long field
)
1604 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1605 "16-bit accessor invalid for 64-bit field");
1606 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1607 "16-bit accessor invalid for 64-bit high field");
1608 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1609 "16-bit accessor invalid for 32-bit high field");
1610 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1611 "16-bit accessor invalid for natural width field");
1614 static __always_inline
void vmcs_check32(unsigned long field
)
1616 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1617 "32-bit accessor invalid for 16-bit field");
1618 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1619 "32-bit accessor invalid for natural width field");
1622 static __always_inline
void vmcs_check64(unsigned long field
)
1624 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1625 "64-bit accessor invalid for 16-bit field");
1626 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1627 "64-bit accessor invalid for 64-bit high field");
1628 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1629 "64-bit accessor invalid for 32-bit field");
1630 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1631 "64-bit accessor invalid for natural width field");
1634 static __always_inline
void vmcs_checkl(unsigned long field
)
1636 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1637 "Natural width accessor invalid for 16-bit field");
1638 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1639 "Natural width accessor invalid for 64-bit field");
1640 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1641 "Natural width accessor invalid for 64-bit high field");
1642 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1643 "Natural width accessor invalid for 32-bit field");
1646 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1648 unsigned long value
;
1650 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1651 : "=a"(value
) : "d"(field
) : "cc");
1655 static __always_inline u16
vmcs_read16(unsigned long field
)
1657 vmcs_check16(field
);
1658 return __vmcs_readl(field
);
1661 static __always_inline u32
vmcs_read32(unsigned long field
)
1663 vmcs_check32(field
);
1664 return __vmcs_readl(field
);
1667 static __always_inline u64
vmcs_read64(unsigned long field
)
1669 vmcs_check64(field
);
1670 #ifdef CONFIG_X86_64
1671 return __vmcs_readl(field
);
1673 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1677 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1680 return __vmcs_readl(field
);
1683 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1685 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1686 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1690 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1694 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1695 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1696 if (unlikely(error
))
1697 vmwrite_error(field
, value
);
1700 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1702 vmcs_check16(field
);
1703 __vmcs_writel(field
, value
);
1706 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1708 vmcs_check32(field
);
1709 __vmcs_writel(field
, value
);
1712 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1714 vmcs_check64(field
);
1715 __vmcs_writel(field
, value
);
1716 #ifndef CONFIG_X86_64
1718 __vmcs_writel(field
+1, value
>> 32);
1722 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1725 __vmcs_writel(field
, value
);
1728 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1730 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1731 "vmcs_clear_bits does not support 64-bit fields");
1732 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1735 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1737 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1738 "vmcs_set_bits does not support 64-bit fields");
1739 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1742 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1744 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1747 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1749 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1750 vmx
->vm_entry_controls_shadow
= val
;
1753 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1755 if (vmx
->vm_entry_controls_shadow
!= val
)
1756 vm_entry_controls_init(vmx
, val
);
1759 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1761 return vmx
->vm_entry_controls_shadow
;
1765 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1767 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1770 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1772 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1775 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1777 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1780 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1782 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1783 vmx
->vm_exit_controls_shadow
= val
;
1786 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1788 if (vmx
->vm_exit_controls_shadow
!= val
)
1789 vm_exit_controls_init(vmx
, val
);
1792 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1794 return vmx
->vm_exit_controls_shadow
;
1798 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1800 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1803 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1805 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1808 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1810 vmx
->segment_cache
.bitmask
= 0;
1813 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1817 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1819 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1820 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1821 vmx
->segment_cache
.bitmask
= 0;
1823 ret
= vmx
->segment_cache
.bitmask
& mask
;
1824 vmx
->segment_cache
.bitmask
|= mask
;
1828 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1830 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1832 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1833 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1837 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1839 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1841 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1842 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1846 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1848 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1850 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1851 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1855 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1857 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1859 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1860 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1864 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1868 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1869 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1870 if ((vcpu
->guest_debug
&
1871 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1872 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1873 eb
|= 1u << BP_VECTOR
;
1874 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1877 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1879 /* When we are running a nested L2 guest and L1 specified for it a
1880 * certain exception bitmap, we must trap the same exceptions and pass
1881 * them to L1. When running L2, we will only handle the exceptions
1882 * specified above if L1 did not want them.
1884 if (is_guest_mode(vcpu
))
1885 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1887 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1890 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1891 unsigned long entry
, unsigned long exit
)
1893 vm_entry_controls_clearbit(vmx
, entry
);
1894 vm_exit_controls_clearbit(vmx
, exit
);
1897 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1900 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1904 if (cpu_has_load_ia32_efer
) {
1905 clear_atomic_switch_msr_special(vmx
,
1906 VM_ENTRY_LOAD_IA32_EFER
,
1907 VM_EXIT_LOAD_IA32_EFER
);
1911 case MSR_CORE_PERF_GLOBAL_CTRL
:
1912 if (cpu_has_load_perf_global_ctrl
) {
1913 clear_atomic_switch_msr_special(vmx
,
1914 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1915 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1921 for (i
= 0; i
< m
->nr
; ++i
)
1922 if (m
->guest
[i
].index
== msr
)
1928 m
->guest
[i
] = m
->guest
[m
->nr
];
1929 m
->host
[i
] = m
->host
[m
->nr
];
1930 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1931 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1934 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1935 unsigned long entry
, unsigned long exit
,
1936 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1937 u64 guest_val
, u64 host_val
)
1939 vmcs_write64(guest_val_vmcs
, guest_val
);
1940 vmcs_write64(host_val_vmcs
, host_val
);
1941 vm_entry_controls_setbit(vmx
, entry
);
1942 vm_exit_controls_setbit(vmx
, exit
);
1945 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1946 u64 guest_val
, u64 host_val
)
1949 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1953 if (cpu_has_load_ia32_efer
) {
1954 add_atomic_switch_msr_special(vmx
,
1955 VM_ENTRY_LOAD_IA32_EFER
,
1956 VM_EXIT_LOAD_IA32_EFER
,
1959 guest_val
, host_val
);
1963 case MSR_CORE_PERF_GLOBAL_CTRL
:
1964 if (cpu_has_load_perf_global_ctrl
) {
1965 add_atomic_switch_msr_special(vmx
,
1966 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1967 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1968 GUEST_IA32_PERF_GLOBAL_CTRL
,
1969 HOST_IA32_PERF_GLOBAL_CTRL
,
1970 guest_val
, host_val
);
1974 case MSR_IA32_PEBS_ENABLE
:
1975 /* PEBS needs a quiescent period after being disabled (to write
1976 * a record). Disabling PEBS through VMX MSR swapping doesn't
1977 * provide that period, so a CPU could write host's record into
1980 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1983 for (i
= 0; i
< m
->nr
; ++i
)
1984 if (m
->guest
[i
].index
== msr
)
1987 if (i
== NR_AUTOLOAD_MSRS
) {
1988 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1989 "Can't add msr %x\n", msr
);
1991 } else if (i
== m
->nr
) {
1993 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1994 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1997 m
->guest
[i
].index
= msr
;
1998 m
->guest
[i
].value
= guest_val
;
1999 m
->host
[i
].index
= msr
;
2000 m
->host
[i
].value
= host_val
;
2003 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2005 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2006 u64 ignore_bits
= 0;
2010 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2011 * host CPUID is more efficient than testing guest CPUID
2012 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2014 if (boot_cpu_has(X86_FEATURE_SMEP
))
2015 guest_efer
|= EFER_NX
;
2016 else if (!(guest_efer
& EFER_NX
))
2017 ignore_bits
|= EFER_NX
;
2021 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2023 ignore_bits
|= EFER_SCE
;
2024 #ifdef CONFIG_X86_64
2025 ignore_bits
|= EFER_LMA
| EFER_LME
;
2026 /* SCE is meaningful only in long mode on Intel */
2027 if (guest_efer
& EFER_LMA
)
2028 ignore_bits
&= ~(u64
)EFER_SCE
;
2031 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2034 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2035 * On CPUs that support "load IA32_EFER", always switch EFER
2036 * atomically, since it's faster than switching it manually.
2038 if (cpu_has_load_ia32_efer
||
2039 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2040 if (!(guest_efer
& EFER_LMA
))
2041 guest_efer
&= ~EFER_LME
;
2042 if (guest_efer
!= host_efer
)
2043 add_atomic_switch_msr(vmx
, MSR_EFER
,
2044 guest_efer
, host_efer
);
2047 guest_efer
&= ~ignore_bits
;
2048 guest_efer
|= host_efer
& ignore_bits
;
2050 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2051 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2057 #ifdef CONFIG_X86_32
2059 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2060 * VMCS rather than the segment table. KVM uses this helper to figure
2061 * out the current bases to poke them into the VMCS before entry.
2063 static unsigned long segment_base(u16 selector
)
2065 struct desc_struct
*table
;
2068 if (!(selector
& ~SEGMENT_RPL_MASK
))
2071 table
= get_current_gdt_ro();
2073 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2074 u16 ldt_selector
= kvm_read_ldt();
2076 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2079 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2081 v
= get_desc_base(&table
[selector
>> 3]);
2086 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2088 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2091 if (vmx
->host_state
.loaded
)
2094 vmx
->host_state
.loaded
= 1;
2096 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2097 * allow segment selectors with cpl > 0 or ti == 1.
2099 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2100 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2101 savesegment(fs
, vmx
->host_state
.fs_sel
);
2102 if (!(vmx
->host_state
.fs_sel
& 7)) {
2103 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2104 vmx
->host_state
.fs_reload_needed
= 0;
2106 vmcs_write16(HOST_FS_SELECTOR
, 0);
2107 vmx
->host_state
.fs_reload_needed
= 1;
2109 savesegment(gs
, vmx
->host_state
.gs_sel
);
2110 if (!(vmx
->host_state
.gs_sel
& 7))
2111 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2113 vmcs_write16(HOST_GS_SELECTOR
, 0);
2114 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2117 #ifdef CONFIG_X86_64
2118 savesegment(ds
, vmx
->host_state
.ds_sel
);
2119 savesegment(es
, vmx
->host_state
.es_sel
);
2122 #ifdef CONFIG_X86_64
2123 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2124 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2126 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2127 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2130 #ifdef CONFIG_X86_64
2131 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2132 if (is_long_mode(&vmx
->vcpu
))
2133 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2135 if (boot_cpu_has(X86_FEATURE_MPX
))
2136 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2137 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2138 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2139 vmx
->guest_msrs
[i
].data
,
2140 vmx
->guest_msrs
[i
].mask
);
2143 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2145 if (!vmx
->host_state
.loaded
)
2148 ++vmx
->vcpu
.stat
.host_state_reload
;
2149 vmx
->host_state
.loaded
= 0;
2150 #ifdef CONFIG_X86_64
2151 if (is_long_mode(&vmx
->vcpu
))
2152 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2154 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2155 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2156 #ifdef CONFIG_X86_64
2157 load_gs_index(vmx
->host_state
.gs_sel
);
2159 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2162 if (vmx
->host_state
.fs_reload_needed
)
2163 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2164 #ifdef CONFIG_X86_64
2165 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2166 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2167 loadsegment(es
, vmx
->host_state
.es_sel
);
2170 invalidate_tss_limit();
2171 #ifdef CONFIG_X86_64
2172 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2174 if (vmx
->host_state
.msr_host_bndcfgs
)
2175 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2176 load_fixmap_gdt(raw_smp_processor_id());
2179 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2182 __vmx_load_host_state(vmx
);
2186 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2188 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2189 struct pi_desc old
, new;
2192 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2193 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2194 !kvm_vcpu_apicv_active(vcpu
))
2198 old
.control
= new.control
= pi_desc
->control
;
2201 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2202 * are two possible cases:
2203 * 1. After running 'pre_block', context switch
2204 * happened. For this case, 'sn' was set in
2205 * vmx_vcpu_put(), so we need to clear it here.
2206 * 2. After running 'pre_block', we were blocked,
2207 * and woken up by some other guy. For this case,
2208 * we don't need to do anything, 'pi_post_block'
2209 * will do everything for us. However, we cannot
2210 * check whether it is case #1 or case #2 here
2211 * (maybe, not needed), so we also clear sn here,
2212 * I think it is not a big deal.
2214 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2215 if (vcpu
->cpu
!= cpu
) {
2216 dest
= cpu_physical_id(cpu
);
2218 if (x2apic_enabled())
2221 new.ndst
= (dest
<< 8) & 0xFF00;
2224 /* set 'NV' to 'notification vector' */
2225 new.nv
= POSTED_INTR_VECTOR
;
2228 /* Allow posting non-urgent interrupts */
2230 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2231 new.control
) != old
.control
);
2234 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2236 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2237 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2241 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2242 * vcpu mutex is already taken.
2244 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2246 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2247 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2249 if (!already_loaded
) {
2250 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2251 local_irq_disable();
2252 crash_disable_local_vmclear(cpu
);
2255 * Read loaded_vmcs->cpu should be before fetching
2256 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2257 * See the comments in __loaded_vmcs_clear().
2261 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2262 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2263 crash_enable_local_vmclear(cpu
);
2267 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2268 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2269 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2272 if (!already_loaded
) {
2273 void *gdt
= get_current_gdt_ro();
2274 unsigned long sysenter_esp
;
2276 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2279 * Linux uses per-cpu TSS and GDT, so set these when switching
2280 * processors. See 22.2.4.
2282 vmcs_writel(HOST_TR_BASE
,
2283 (unsigned long)this_cpu_ptr(&cpu_tss
));
2284 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2287 * VM exits change the host TR limit to 0x67 after a VM
2288 * exit. This is okay, since 0x67 covers everything except
2289 * the IO bitmap and have have code to handle the IO bitmap
2290 * being lost after a VM exit.
2292 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2294 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2295 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2297 vmx
->loaded_vmcs
->cpu
= cpu
;
2300 /* Setup TSC multiplier */
2301 if (kvm_has_tsc_control
&&
2302 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2303 decache_tsc_multiplier(vmx
);
2305 vmx_vcpu_pi_load(vcpu
, cpu
);
2306 vmx
->host_pkru
= read_pkru();
2309 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2311 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2313 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2314 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2315 !kvm_vcpu_apicv_active(vcpu
))
2318 /* Set SN when the vCPU is preempted */
2319 if (vcpu
->preempted
)
2323 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2325 vmx_vcpu_pi_put(vcpu
);
2327 __vmx_load_host_state(to_vmx(vcpu
));
2330 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2332 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2335 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2338 * Return the cr0 value that a nested guest would read. This is a combination
2339 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2340 * its hypervisor (cr0_read_shadow).
2342 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2344 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2345 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2347 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2349 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2350 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2353 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2355 unsigned long rflags
, save_rflags
;
2357 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2358 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2359 rflags
= vmcs_readl(GUEST_RFLAGS
);
2360 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2361 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2362 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2363 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2365 to_vmx(vcpu
)->rflags
= rflags
;
2367 return to_vmx(vcpu
)->rflags
;
2370 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2372 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2374 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2375 to_vmx(vcpu
)->rflags
= rflags
;
2376 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2377 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2378 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2380 vmcs_writel(GUEST_RFLAGS
, rflags
);
2382 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2383 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2386 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2388 return to_vmx(vcpu
)->guest_pkru
;
2391 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2393 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2396 if (interruptibility
& GUEST_INTR_STATE_STI
)
2397 ret
|= KVM_X86_SHADOW_INT_STI
;
2398 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2399 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2404 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2406 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2407 u32 interruptibility
= interruptibility_old
;
2409 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2411 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2412 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2413 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2414 interruptibility
|= GUEST_INTR_STATE_STI
;
2416 if ((interruptibility
!= interruptibility_old
))
2417 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2420 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2424 rip
= kvm_rip_read(vcpu
);
2425 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2426 kvm_rip_write(vcpu
, rip
);
2428 /* skipping an emulated instruction also counts */
2429 vmx_set_interrupt_shadow(vcpu
, 0);
2432 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2433 unsigned long exit_qual
)
2435 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2436 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2437 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2439 if (vcpu
->arch
.exception
.has_error_code
) {
2440 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2441 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2444 if (kvm_exception_is_soft(nr
))
2445 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2447 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2449 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2450 vmx_get_nmi_mask(vcpu
))
2451 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2453 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2457 * KVM wants to inject page-faults which it got to the guest. This function
2458 * checks whether in a nested guest, we need to inject them to L1 or L2.
2460 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
)
2462 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2463 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2465 if (nr
== PF_VECTOR
) {
2466 if (vcpu
->arch
.exception
.nested_apf
) {
2467 nested_vmx_inject_exception_vmexit(vcpu
,
2468 vcpu
->arch
.apf
.nested_apf_token
);
2472 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2473 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2474 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2475 * can be written only when inject_pending_event runs. This should be
2476 * conditional on a new capability---if the capability is disabled,
2477 * kvm_multiple_exception would write the ancillary information to
2478 * CR2 or DR6, for backwards ABI-compatibility.
2480 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2481 vcpu
->arch
.exception
.error_code
)) {
2482 nested_vmx_inject_exception_vmexit(vcpu
, vcpu
->arch
.cr2
);
2486 unsigned long exit_qual
= 0;
2487 if (nr
== DB_VECTOR
)
2488 exit_qual
= vcpu
->arch
.dr6
;
2490 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2491 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
2499 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2501 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2502 unsigned nr
= vcpu
->arch
.exception
.nr
;
2503 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2504 bool reinject
= vcpu
->arch
.exception
.reinject
;
2505 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2506 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2508 if (!reinject
&& is_guest_mode(vcpu
) &&
2509 nested_vmx_check_exception(vcpu
))
2512 if (has_error_code
) {
2513 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2514 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2517 if (vmx
->rmode
.vm86_active
) {
2519 if (kvm_exception_is_soft(nr
))
2520 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2521 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2522 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2526 if (kvm_exception_is_soft(nr
)) {
2527 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2528 vmx
->vcpu
.arch
.event_exit_inst_len
);
2529 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2531 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2533 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2536 static bool vmx_rdtscp_supported(void)
2538 return cpu_has_vmx_rdtscp();
2541 static bool vmx_invpcid_supported(void)
2543 return cpu_has_vmx_invpcid() && enable_ept
;
2547 * Swap MSR entry in host/guest MSR entry array.
2549 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2551 struct shared_msr_entry tmp
;
2553 tmp
= vmx
->guest_msrs
[to
];
2554 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2555 vmx
->guest_msrs
[from
] = tmp
;
2558 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2560 unsigned long *msr_bitmap
;
2562 if (is_guest_mode(vcpu
))
2563 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2564 else if (cpu_has_secondary_exec_ctrls() &&
2565 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2566 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2567 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2568 if (is_long_mode(vcpu
))
2569 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2571 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2573 if (is_long_mode(vcpu
))
2574 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2576 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2579 if (is_long_mode(vcpu
))
2580 msr_bitmap
= vmx_msr_bitmap_longmode
;
2582 msr_bitmap
= vmx_msr_bitmap_legacy
;
2585 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2589 * Set up the vmcs to automatically save and restore system
2590 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2591 * mode, as fiddling with msrs is very expensive.
2593 static void setup_msrs(struct vcpu_vmx
*vmx
)
2595 int save_nmsrs
, index
;
2598 #ifdef CONFIG_X86_64
2599 if (is_long_mode(&vmx
->vcpu
)) {
2600 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2602 move_msr_up(vmx
, index
, save_nmsrs
++);
2603 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2605 move_msr_up(vmx
, index
, save_nmsrs
++);
2606 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2608 move_msr_up(vmx
, index
, save_nmsrs
++);
2609 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2610 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2611 move_msr_up(vmx
, index
, save_nmsrs
++);
2613 * MSR_STAR is only needed on long mode guests, and only
2614 * if efer.sce is enabled.
2616 index
= __find_msr_index(vmx
, MSR_STAR
);
2617 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2618 move_msr_up(vmx
, index
, save_nmsrs
++);
2621 index
= __find_msr_index(vmx
, MSR_EFER
);
2622 if (index
>= 0 && update_transition_efer(vmx
, index
))
2623 move_msr_up(vmx
, index
, save_nmsrs
++);
2625 vmx
->save_nmsrs
= save_nmsrs
;
2627 if (cpu_has_vmx_msr_bitmap())
2628 vmx_set_msr_bitmap(&vmx
->vcpu
);
2632 * reads and returns guest's timestamp counter "register"
2633 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2634 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2636 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2638 u64 host_tsc
, tsc_offset
;
2641 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2642 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2646 * writes 'offset' into guest's timestamp counter offset register
2648 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2650 if (is_guest_mode(vcpu
)) {
2652 * We're here if L1 chose not to trap WRMSR to TSC. According
2653 * to the spec, this should set L1's TSC; The offset that L1
2654 * set for L2 remains unchanged, and still needs to be added
2655 * to the newly set TSC to get L2's TSC.
2657 struct vmcs12
*vmcs12
;
2658 /* recalculate vmcs02.TSC_OFFSET: */
2659 vmcs12
= get_vmcs12(vcpu
);
2660 vmcs_write64(TSC_OFFSET
, offset
+
2661 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2662 vmcs12
->tsc_offset
: 0));
2664 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2665 vmcs_read64(TSC_OFFSET
), offset
);
2666 vmcs_write64(TSC_OFFSET
, offset
);
2670 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2672 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2673 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2677 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2678 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2679 * all guests if the "nested" module option is off, and can also be disabled
2680 * for a single guest by disabling its VMX cpuid bit.
2682 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2684 return nested
&& guest_cpuid_has_vmx(vcpu
);
2688 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2689 * returned for the various VMX controls MSRs when nested VMX is enabled.
2690 * The same values should also be used to verify that vmcs12 control fields are
2691 * valid during nested entry from L1 to L2.
2692 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2693 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2694 * bit in the high half is on if the corresponding bit in the control field
2695 * may be on. See also vmx_control_verify().
2697 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2700 * Note that as a general rule, the high half of the MSRs (bits in
2701 * the control fields which may be 1) should be initialized by the
2702 * intersection of the underlying hardware's MSR (i.e., features which
2703 * can be supported) and the list of features we want to expose -
2704 * because they are known to be properly supported in our code.
2705 * Also, usually, the low half of the MSRs (bits which must be 1) can
2706 * be set to 0, meaning that L1 may turn off any of these bits. The
2707 * reason is that if one of these bits is necessary, it will appear
2708 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2709 * fields of vmcs01 and vmcs02, will turn these bits off - and
2710 * nested_vmx_exit_reflected() will not pass related exits to L1.
2711 * These rules have exceptions below.
2714 /* pin-based controls */
2715 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2716 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2717 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2718 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2719 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2720 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2721 PIN_BASED_EXT_INTR_MASK
|
2722 PIN_BASED_NMI_EXITING
|
2723 PIN_BASED_VIRTUAL_NMIS
;
2724 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2725 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2726 PIN_BASED_VMX_PREEMPTION_TIMER
;
2727 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2728 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2729 PIN_BASED_POSTED_INTR
;
2732 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2733 vmx
->nested
.nested_vmx_exit_ctls_low
,
2734 vmx
->nested
.nested_vmx_exit_ctls_high
);
2735 vmx
->nested
.nested_vmx_exit_ctls_low
=
2736 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2738 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2739 #ifdef CONFIG_X86_64
2740 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2742 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2743 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2744 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2745 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2746 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2748 if (kvm_mpx_supported())
2749 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2751 /* We support free control of debug control saving. */
2752 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2754 /* entry controls */
2755 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2756 vmx
->nested
.nested_vmx_entry_ctls_low
,
2757 vmx
->nested
.nested_vmx_entry_ctls_high
);
2758 vmx
->nested
.nested_vmx_entry_ctls_low
=
2759 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2760 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2761 #ifdef CONFIG_X86_64
2762 VM_ENTRY_IA32E_MODE
|
2764 VM_ENTRY_LOAD_IA32_PAT
;
2765 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2766 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2767 if (kvm_mpx_supported())
2768 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2770 /* We support free control of debug control loading. */
2771 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2773 /* cpu-based controls */
2774 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2775 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2776 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2777 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2778 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2779 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2780 CPU_BASED_VIRTUAL_INTR_PENDING
|
2781 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2782 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2783 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2784 CPU_BASED_CR3_STORE_EXITING
|
2785 #ifdef CONFIG_X86_64
2786 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2788 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2789 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2790 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2791 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2792 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2794 * We can allow some features even when not supported by the
2795 * hardware. For example, L1 can specify an MSR bitmap - and we
2796 * can use it to avoid exits to L1 - even when L0 runs L2
2797 * without MSR bitmaps.
2799 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2800 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2801 CPU_BASED_USE_MSR_BITMAPS
;
2803 /* We support free control of CR3 access interception. */
2804 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2805 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2807 /* secondary cpu-based controls */
2808 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2809 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2810 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2811 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2812 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2813 SECONDARY_EXEC_RDRAND
| SECONDARY_EXEC_RDSEED
|
2814 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2815 SECONDARY_EXEC_RDTSCP
|
2816 SECONDARY_EXEC_DESC
|
2817 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2818 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2819 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2820 SECONDARY_EXEC_WBINVD_EXITING
|
2821 SECONDARY_EXEC_XSAVES
;
2824 /* nested EPT: emulate EPT also to L1 */
2825 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2826 SECONDARY_EXEC_ENABLE_EPT
;
2827 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2828 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2829 if (cpu_has_vmx_ept_execute_only())
2830 vmx
->nested
.nested_vmx_ept_caps
|=
2831 VMX_EPT_EXECUTE_ONLY_BIT
;
2832 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2833 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2834 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2835 VMX_EPT_1GB_PAGE_BIT
;
2836 if (enable_ept_ad_bits
) {
2837 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2838 SECONDARY_EXEC_ENABLE_PML
;
2839 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2842 vmx
->nested
.nested_vmx_ept_caps
= 0;
2845 * Old versions of KVM use the single-context version without
2846 * checking for support, so declare that it is supported even
2847 * though it is treated as global context. The alternative is
2848 * not failing the single-context invvpid, and it is worse.
2851 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2852 SECONDARY_EXEC_ENABLE_VPID
;
2853 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2854 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2856 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2858 if (enable_unrestricted_guest
)
2859 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2860 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2862 /* miscellaneous data */
2863 rdmsr(MSR_IA32_VMX_MISC
,
2864 vmx
->nested
.nested_vmx_misc_low
,
2865 vmx
->nested
.nested_vmx_misc_high
);
2866 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2867 vmx
->nested
.nested_vmx_misc_low
|=
2868 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2869 VMX_MISC_ACTIVITY_HLT
;
2870 vmx
->nested
.nested_vmx_misc_high
= 0;
2873 * This MSR reports some information about VMX support. We
2874 * should return information about the VMX we emulate for the
2875 * guest, and the VMCS structure we give it - not about the
2876 * VMX support of the underlying hardware.
2878 vmx
->nested
.nested_vmx_basic
=
2880 VMX_BASIC_TRUE_CTLS
|
2881 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2882 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2884 if (cpu_has_vmx_basic_inout())
2885 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2888 * These MSRs specify bits which the guest must keep fixed on
2889 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2890 * We picked the standard core2 setting.
2892 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2893 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2894 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2895 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2897 /* These MSRs specify bits which the guest must keep fixed off. */
2898 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2899 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2901 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2902 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2906 * if fixed0[i] == 1: val[i] must be 1
2907 * if fixed1[i] == 0: val[i] must be 0
2909 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2911 return ((val
& fixed1
) | fixed0
) == val
;
2914 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2916 return fixed_bits_valid(control
, low
, high
);
2919 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2921 return low
| ((u64
)high
<< 32);
2924 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2929 return (superset
| subset
) == superset
;
2932 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2934 const u64 feature_and_reserved
=
2935 /* feature (except bit 48; see below) */
2936 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2938 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2939 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2941 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2945 * KVM does not emulate a version of VMX that constrains physical
2946 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2948 if (data
& BIT_ULL(48))
2951 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2952 vmx_basic_vmcs_revision_id(data
))
2955 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2958 vmx
->nested
.nested_vmx_basic
= data
;
2963 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2968 switch (msr_index
) {
2969 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2970 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2971 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2973 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2974 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2975 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2977 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2978 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2979 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2981 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2982 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2983 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2985 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2986 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2987 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2993 supported
= vmx_control_msr(*lowp
, *highp
);
2995 /* Check must-be-1 bits are still 1. */
2996 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
2999 /* Check must-be-0 bits are still 0. */
3000 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3004 *highp
= data
>> 32;
3008 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3010 const u64 feature_and_reserved_bits
=
3012 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3013 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3015 GENMASK_ULL(13, 9) | BIT_ULL(31);
3018 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3019 vmx
->nested
.nested_vmx_misc_high
);
3021 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3024 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3025 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3026 vmx_misc_preemption_timer_rate(data
) !=
3027 vmx_misc_preemption_timer_rate(vmx_misc
))
3030 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3033 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3036 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3039 vmx
->nested
.nested_vmx_misc_low
= data
;
3040 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3044 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3046 u64 vmx_ept_vpid_cap
;
3048 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3049 vmx
->nested
.nested_vmx_vpid_caps
);
3051 /* Every bit is either reserved or a feature bit. */
3052 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3055 vmx
->nested
.nested_vmx_ept_caps
= data
;
3056 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3060 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3064 switch (msr_index
) {
3065 case MSR_IA32_VMX_CR0_FIXED0
:
3066 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3068 case MSR_IA32_VMX_CR4_FIXED0
:
3069 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3076 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3077 * must be 1 in the restored value.
3079 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3087 * Called when userspace is restoring VMX MSRs.
3089 * Returns 0 on success, non-0 otherwise.
3091 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3093 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3095 switch (msr_index
) {
3096 case MSR_IA32_VMX_BASIC
:
3097 return vmx_restore_vmx_basic(vmx
, data
);
3098 case MSR_IA32_VMX_PINBASED_CTLS
:
3099 case MSR_IA32_VMX_PROCBASED_CTLS
:
3100 case MSR_IA32_VMX_EXIT_CTLS
:
3101 case MSR_IA32_VMX_ENTRY_CTLS
:
3103 * The "non-true" VMX capability MSRs are generated from the
3104 * "true" MSRs, so we do not support restoring them directly.
3106 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3107 * should restore the "true" MSRs with the must-be-1 bits
3108 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3109 * DEFAULT SETTINGS".
3112 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3113 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3114 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3115 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3116 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3117 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3118 case MSR_IA32_VMX_MISC
:
3119 return vmx_restore_vmx_misc(vmx
, data
);
3120 case MSR_IA32_VMX_CR0_FIXED0
:
3121 case MSR_IA32_VMX_CR4_FIXED0
:
3122 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3123 case MSR_IA32_VMX_CR0_FIXED1
:
3124 case MSR_IA32_VMX_CR4_FIXED1
:
3126 * These MSRs are generated based on the vCPU's CPUID, so we
3127 * do not support restoring them directly.
3130 case MSR_IA32_VMX_EPT_VPID_CAP
:
3131 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3132 case MSR_IA32_VMX_VMCS_ENUM
:
3133 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3137 * The rest of the VMX capability MSRs do not support restore.
3143 /* Returns 0 on success, non-0 otherwise. */
3144 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3146 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3148 switch (msr_index
) {
3149 case MSR_IA32_VMX_BASIC
:
3150 *pdata
= vmx
->nested
.nested_vmx_basic
;
3152 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3153 case MSR_IA32_VMX_PINBASED_CTLS
:
3154 *pdata
= vmx_control_msr(
3155 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3156 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3157 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3158 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3160 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3161 case MSR_IA32_VMX_PROCBASED_CTLS
:
3162 *pdata
= vmx_control_msr(
3163 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3164 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3165 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3166 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3168 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3169 case MSR_IA32_VMX_EXIT_CTLS
:
3170 *pdata
= vmx_control_msr(
3171 vmx
->nested
.nested_vmx_exit_ctls_low
,
3172 vmx
->nested
.nested_vmx_exit_ctls_high
);
3173 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3174 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3176 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3177 case MSR_IA32_VMX_ENTRY_CTLS
:
3178 *pdata
= vmx_control_msr(
3179 vmx
->nested
.nested_vmx_entry_ctls_low
,
3180 vmx
->nested
.nested_vmx_entry_ctls_high
);
3181 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3182 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3184 case MSR_IA32_VMX_MISC
:
3185 *pdata
= vmx_control_msr(
3186 vmx
->nested
.nested_vmx_misc_low
,
3187 vmx
->nested
.nested_vmx_misc_high
);
3189 case MSR_IA32_VMX_CR0_FIXED0
:
3190 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3192 case MSR_IA32_VMX_CR0_FIXED1
:
3193 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3195 case MSR_IA32_VMX_CR4_FIXED0
:
3196 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3198 case MSR_IA32_VMX_CR4_FIXED1
:
3199 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3201 case MSR_IA32_VMX_VMCS_ENUM
:
3202 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3204 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3205 *pdata
= vmx_control_msr(
3206 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3207 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3209 case MSR_IA32_VMX_EPT_VPID_CAP
:
3210 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3211 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3220 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3223 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3225 return !(val
& ~valid_bits
);
3229 * Reads an msr value (of 'msr_index') into 'pdata'.
3230 * Returns 0 on success, non-0 otherwise.
3231 * Assumes vcpu_load() was already called.
3233 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3235 struct shared_msr_entry
*msr
;
3237 switch (msr_info
->index
) {
3238 #ifdef CONFIG_X86_64
3240 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3243 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3245 case MSR_KERNEL_GS_BASE
:
3246 vmx_load_host_state(to_vmx(vcpu
));
3247 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3251 return kvm_get_msr_common(vcpu
, msr_info
);
3253 msr_info
->data
= guest_read_tsc(vcpu
);
3255 case MSR_IA32_SYSENTER_CS
:
3256 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3258 case MSR_IA32_SYSENTER_EIP
:
3259 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3261 case MSR_IA32_SYSENTER_ESP
:
3262 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3264 case MSR_IA32_BNDCFGS
:
3265 if (!kvm_mpx_supported() ||
3266 (!msr_info
->host_initiated
&& !guest_cpuid_has_mpx(vcpu
)))
3268 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3270 case MSR_IA32_MCG_EXT_CTL
:
3271 if (!msr_info
->host_initiated
&&
3272 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3273 FEATURE_CONTROL_LMCE
))
3275 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3277 case MSR_IA32_FEATURE_CONTROL
:
3278 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3280 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3281 if (!nested_vmx_allowed(vcpu
))
3283 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3285 if (!vmx_xsaves_supported())
3287 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3290 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3292 /* Otherwise falls through */
3294 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3296 msr_info
->data
= msr
->data
;
3299 return kvm_get_msr_common(vcpu
, msr_info
);
3305 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3308 * Writes msr value into into the appropriate "register".
3309 * Returns 0 on success, non-0 otherwise.
3310 * Assumes vcpu_load() was already called.
3312 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3314 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3315 struct shared_msr_entry
*msr
;
3317 u32 msr_index
= msr_info
->index
;
3318 u64 data
= msr_info
->data
;
3320 switch (msr_index
) {
3322 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3324 #ifdef CONFIG_X86_64
3326 vmx_segment_cache_clear(vmx
);
3327 vmcs_writel(GUEST_FS_BASE
, data
);
3330 vmx_segment_cache_clear(vmx
);
3331 vmcs_writel(GUEST_GS_BASE
, data
);
3333 case MSR_KERNEL_GS_BASE
:
3334 vmx_load_host_state(vmx
);
3335 vmx
->msr_guest_kernel_gs_base
= data
;
3338 case MSR_IA32_SYSENTER_CS
:
3339 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3341 case MSR_IA32_SYSENTER_EIP
:
3342 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3344 case MSR_IA32_SYSENTER_ESP
:
3345 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3347 case MSR_IA32_BNDCFGS
:
3348 if (!kvm_mpx_supported() ||
3349 (!msr_info
->host_initiated
&& !guest_cpuid_has_mpx(vcpu
)))
3351 if (is_noncanonical_address(data
& PAGE_MASK
) ||
3352 (data
& MSR_IA32_BNDCFGS_RSVD
))
3354 vmcs_write64(GUEST_BNDCFGS
, data
);
3357 kvm_write_tsc(vcpu
, msr_info
);
3359 case MSR_IA32_CR_PAT
:
3360 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3361 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3363 vmcs_write64(GUEST_IA32_PAT
, data
);
3364 vcpu
->arch
.pat
= data
;
3367 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3369 case MSR_IA32_TSC_ADJUST
:
3370 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3372 case MSR_IA32_MCG_EXT_CTL
:
3373 if ((!msr_info
->host_initiated
&&
3374 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3375 FEATURE_CONTROL_LMCE
)) ||
3376 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3378 vcpu
->arch
.mcg_ext_ctl
= data
;
3380 case MSR_IA32_FEATURE_CONTROL
:
3381 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3382 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3383 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3385 vmx
->msr_ia32_feature_control
= data
;
3386 if (msr_info
->host_initiated
&& data
== 0)
3387 vmx_leave_nested(vcpu
);
3389 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3390 if (!msr_info
->host_initiated
)
3391 return 1; /* they are read-only */
3392 if (!nested_vmx_allowed(vcpu
))
3394 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3396 if (!vmx_xsaves_supported())
3399 * The only supported bit as of Skylake is bit 8, but
3400 * it is not supported on KVM.
3404 vcpu
->arch
.ia32_xss
= data
;
3405 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3406 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3407 vcpu
->arch
.ia32_xss
, host_xss
);
3409 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3412 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3414 /* Check reserved bit, higher 32 bits should be zero */
3415 if ((data
>> 32) != 0)
3417 /* Otherwise falls through */
3419 msr
= find_msr_entry(vmx
, msr_index
);
3421 u64 old_msr_data
= msr
->data
;
3423 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3425 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3429 msr
->data
= old_msr_data
;
3433 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3439 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3441 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3444 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3447 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3449 case VCPU_EXREG_PDPTR
:
3451 ept_save_pdptrs(vcpu
);
3458 static __init
int cpu_has_kvm_support(void)
3460 return cpu_has_vmx();
3463 static __init
int vmx_disabled_by_bios(void)
3467 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3468 if (msr
& FEATURE_CONTROL_LOCKED
) {
3469 /* launched w/ TXT and VMX disabled */
3470 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3473 /* launched w/o TXT and VMX only enabled w/ TXT */
3474 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3475 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3476 && !tboot_enabled()) {
3477 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3478 "activate TXT before enabling KVM\n");
3481 /* launched w/o TXT and VMX disabled */
3482 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3483 && !tboot_enabled())
3490 static void kvm_cpu_vmxon(u64 addr
)
3492 cr4_set_bits(X86_CR4_VMXE
);
3493 intel_pt_handle_vmx(1);
3495 asm volatile (ASM_VMX_VMXON_RAX
3496 : : "a"(&addr
), "m"(addr
)
3500 static int hardware_enable(void)
3502 int cpu
= raw_smp_processor_id();
3503 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3506 if (cr4_read_shadow() & X86_CR4_VMXE
)
3509 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3510 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3511 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3514 * Now we can enable the vmclear operation in kdump
3515 * since the loaded_vmcss_on_cpu list on this cpu
3516 * has been initialized.
3518 * Though the cpu is not in VMX operation now, there
3519 * is no problem to enable the vmclear operation
3520 * for the loaded_vmcss_on_cpu list is empty!
3522 crash_enable_local_vmclear(cpu
);
3524 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3526 test_bits
= FEATURE_CONTROL_LOCKED
;
3527 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3528 if (tboot_enabled())
3529 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3531 if ((old
& test_bits
) != test_bits
) {
3532 /* enable and lock */
3533 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3535 kvm_cpu_vmxon(phys_addr
);
3541 static void vmclear_local_loaded_vmcss(void)
3543 int cpu
= raw_smp_processor_id();
3544 struct loaded_vmcs
*v
, *n
;
3546 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3547 loaded_vmcss_on_cpu_link
)
3548 __loaded_vmcs_clear(v
);
3552 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3555 static void kvm_cpu_vmxoff(void)
3557 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3559 intel_pt_handle_vmx(0);
3560 cr4_clear_bits(X86_CR4_VMXE
);
3563 static void hardware_disable(void)
3565 vmclear_local_loaded_vmcss();
3569 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3570 u32 msr
, u32
*result
)
3572 u32 vmx_msr_low
, vmx_msr_high
;
3573 u32 ctl
= ctl_min
| ctl_opt
;
3575 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3577 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3578 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3580 /* Ensure minimum (required) set of control bits are supported. */
3588 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3590 u32 vmx_msr_low
, vmx_msr_high
;
3592 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3593 return vmx_msr_high
& ctl
;
3596 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3598 u32 vmx_msr_low
, vmx_msr_high
;
3599 u32 min
, opt
, min2
, opt2
;
3600 u32 _pin_based_exec_control
= 0;
3601 u32 _cpu_based_exec_control
= 0;
3602 u32 _cpu_based_2nd_exec_control
= 0;
3603 u32 _vmexit_control
= 0;
3604 u32 _vmentry_control
= 0;
3606 min
= CPU_BASED_HLT_EXITING
|
3607 #ifdef CONFIG_X86_64
3608 CPU_BASED_CR8_LOAD_EXITING
|
3609 CPU_BASED_CR8_STORE_EXITING
|
3611 CPU_BASED_CR3_LOAD_EXITING
|
3612 CPU_BASED_CR3_STORE_EXITING
|
3613 CPU_BASED_USE_IO_BITMAPS
|
3614 CPU_BASED_MOV_DR_EXITING
|
3615 CPU_BASED_USE_TSC_OFFSETING
|
3616 CPU_BASED_INVLPG_EXITING
|
3617 CPU_BASED_RDPMC_EXITING
;
3619 if (!kvm_mwait_in_guest())
3620 min
|= CPU_BASED_MWAIT_EXITING
|
3621 CPU_BASED_MONITOR_EXITING
;
3623 opt
= CPU_BASED_TPR_SHADOW
|
3624 CPU_BASED_USE_MSR_BITMAPS
|
3625 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3626 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3627 &_cpu_based_exec_control
) < 0)
3629 #ifdef CONFIG_X86_64
3630 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3631 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3632 ~CPU_BASED_CR8_STORE_EXITING
;
3634 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3636 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3637 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3638 SECONDARY_EXEC_WBINVD_EXITING
|
3639 SECONDARY_EXEC_ENABLE_VPID
|
3640 SECONDARY_EXEC_ENABLE_EPT
|
3641 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3642 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3643 SECONDARY_EXEC_RDTSCP
|
3644 SECONDARY_EXEC_ENABLE_INVPCID
|
3645 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3646 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3647 SECONDARY_EXEC_SHADOW_VMCS
|
3648 SECONDARY_EXEC_XSAVES
|
3649 SECONDARY_EXEC_ENABLE_PML
|
3650 SECONDARY_EXEC_TSC_SCALING
;
3651 if (adjust_vmx_controls(min2
, opt2
,
3652 MSR_IA32_VMX_PROCBASED_CTLS2
,
3653 &_cpu_based_2nd_exec_control
) < 0)
3656 #ifndef CONFIG_X86_64
3657 if (!(_cpu_based_2nd_exec_control
&
3658 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3659 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3662 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3663 _cpu_based_2nd_exec_control
&= ~(
3664 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3665 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3666 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3668 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3669 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3671 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3672 CPU_BASED_CR3_STORE_EXITING
|
3673 CPU_BASED_INVLPG_EXITING
);
3674 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3675 vmx_capability
.ept
, vmx_capability
.vpid
);
3678 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3679 #ifdef CONFIG_X86_64
3680 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3682 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3683 VM_EXIT_CLEAR_BNDCFGS
;
3684 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3685 &_vmexit_control
) < 0)
3688 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
3689 PIN_BASED_VIRTUAL_NMIS
;
3690 opt
= PIN_BASED_POSTED_INTR
| PIN_BASED_VMX_PREEMPTION_TIMER
;
3691 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3692 &_pin_based_exec_control
) < 0)
3695 if (cpu_has_broken_vmx_preemption_timer())
3696 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3697 if (!(_cpu_based_2nd_exec_control
&
3698 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3699 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3701 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3702 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3703 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3704 &_vmentry_control
) < 0)
3707 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3709 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3710 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3713 #ifdef CONFIG_X86_64
3714 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3715 if (vmx_msr_high
& (1u<<16))
3719 /* Require Write-Back (WB) memory type for VMCS accesses. */
3720 if (((vmx_msr_high
>> 18) & 15) != 6)
3723 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3724 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3725 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3726 vmcs_conf
->revision_id
= vmx_msr_low
;
3728 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3729 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3730 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3731 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3732 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3734 cpu_has_load_ia32_efer
=
3735 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3736 VM_ENTRY_LOAD_IA32_EFER
)
3737 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3738 VM_EXIT_LOAD_IA32_EFER
);
3740 cpu_has_load_perf_global_ctrl
=
3741 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3742 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3743 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3744 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3747 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3748 * but due to errata below it can't be used. Workaround is to use
3749 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3751 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3756 * BC86,AAY89,BD102 (model 44)
3760 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3761 switch (boot_cpu_data
.x86_model
) {
3767 cpu_has_load_perf_global_ctrl
= false;
3768 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3769 "does not work properly. Using workaround\n");
3776 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3777 rdmsrl(MSR_IA32_XSS
, host_xss
);
3782 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3784 int node
= cpu_to_node(cpu
);
3788 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3791 vmcs
= page_address(pages
);
3792 memset(vmcs
, 0, vmcs_config
.size
);
3793 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3797 static struct vmcs
*alloc_vmcs(void)
3799 return alloc_vmcs_cpu(raw_smp_processor_id());
3802 static void free_vmcs(struct vmcs
*vmcs
)
3804 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3808 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3810 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3812 if (!loaded_vmcs
->vmcs
)
3814 loaded_vmcs_clear(loaded_vmcs
);
3815 free_vmcs(loaded_vmcs
->vmcs
);
3816 loaded_vmcs
->vmcs
= NULL
;
3817 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3820 static void free_kvm_area(void)
3824 for_each_possible_cpu(cpu
) {
3825 free_vmcs(per_cpu(vmxarea
, cpu
));
3826 per_cpu(vmxarea
, cpu
) = NULL
;
3830 enum vmcs_field_type
{
3831 VMCS_FIELD_TYPE_U16
= 0,
3832 VMCS_FIELD_TYPE_U64
= 1,
3833 VMCS_FIELD_TYPE_U32
= 2,
3834 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3837 static inline int vmcs_field_type(unsigned long field
)
3839 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3840 return VMCS_FIELD_TYPE_U32
;
3841 return (field
>> 13) & 0x3 ;
3844 static inline int vmcs_field_readonly(unsigned long field
)
3846 return (((field
>> 10) & 0x3) == 1);
3849 static void init_vmcs_shadow_fields(void)
3853 /* No checks for read only fields yet */
3855 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3856 switch (shadow_read_write_fields
[i
]) {
3858 if (!kvm_mpx_supported())
3866 shadow_read_write_fields
[j
] =
3867 shadow_read_write_fields
[i
];
3870 max_shadow_read_write_fields
= j
;
3872 /* shadowed fields guest access without vmexit */
3873 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3874 unsigned long field
= shadow_read_write_fields
[i
];
3876 clear_bit(field
, vmx_vmwrite_bitmap
);
3877 clear_bit(field
, vmx_vmread_bitmap
);
3878 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
3879 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
3880 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3883 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
3884 unsigned long field
= shadow_read_only_fields
[i
];
3886 clear_bit(field
, vmx_vmread_bitmap
);
3887 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
3888 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3892 static __init
int alloc_kvm_area(void)
3896 for_each_possible_cpu(cpu
) {
3899 vmcs
= alloc_vmcs_cpu(cpu
);
3905 per_cpu(vmxarea
, cpu
) = vmcs
;
3910 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3911 struct kvm_segment
*save
)
3913 if (!emulate_invalid_guest_state
) {
3915 * CS and SS RPL should be equal during guest entry according
3916 * to VMX spec, but in reality it is not always so. Since vcpu
3917 * is in the middle of the transition from real mode to
3918 * protected mode it is safe to assume that RPL 0 is a good
3921 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3922 save
->selector
&= ~SEGMENT_RPL_MASK
;
3923 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3926 vmx_set_segment(vcpu
, save
, seg
);
3929 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3931 unsigned long flags
;
3932 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3935 * Update real mode segment cache. It may be not up-to-date if sement
3936 * register was written while vcpu was in a guest mode.
3938 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3939 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3940 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3941 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3942 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3943 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3945 vmx
->rmode
.vm86_active
= 0;
3947 vmx_segment_cache_clear(vmx
);
3949 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3951 flags
= vmcs_readl(GUEST_RFLAGS
);
3952 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3953 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3954 vmcs_writel(GUEST_RFLAGS
, flags
);
3956 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3957 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3959 update_exception_bitmap(vcpu
);
3961 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3962 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3963 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3964 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3965 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3966 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3969 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3971 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3972 struct kvm_segment var
= *save
;
3975 if (seg
== VCPU_SREG_CS
)
3978 if (!emulate_invalid_guest_state
) {
3979 var
.selector
= var
.base
>> 4;
3980 var
.base
= var
.base
& 0xffff0;
3990 if (save
->base
& 0xf)
3991 printk_once(KERN_WARNING
"kvm: segment base is not "
3992 "paragraph aligned when entering "
3993 "protected mode (seg=%d)", seg
);
3996 vmcs_write16(sf
->selector
, var
.selector
);
3997 vmcs_writel(sf
->base
, var
.base
);
3998 vmcs_write32(sf
->limit
, var
.limit
);
3999 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4002 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4004 unsigned long flags
;
4005 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4007 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4008 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4009 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4010 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4011 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4012 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4013 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4015 vmx
->rmode
.vm86_active
= 1;
4018 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4019 * vcpu. Warn the user that an update is overdue.
4021 if (!vcpu
->kvm
->arch
.tss_addr
)
4022 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4023 "called before entering vcpu\n");
4025 vmx_segment_cache_clear(vmx
);
4027 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4028 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4029 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4031 flags
= vmcs_readl(GUEST_RFLAGS
);
4032 vmx
->rmode
.save_rflags
= flags
;
4034 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4036 vmcs_writel(GUEST_RFLAGS
, flags
);
4037 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4038 update_exception_bitmap(vcpu
);
4040 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4041 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4042 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4043 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4044 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4045 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4047 kvm_mmu_reset_context(vcpu
);
4050 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4052 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4053 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4059 * Force kernel_gs_base reloading before EFER changes, as control
4060 * of this msr depends on is_long_mode().
4062 vmx_load_host_state(to_vmx(vcpu
));
4063 vcpu
->arch
.efer
= efer
;
4064 if (efer
& EFER_LMA
) {
4065 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4068 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4070 msr
->data
= efer
& ~EFER_LME
;
4075 #ifdef CONFIG_X86_64
4077 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4081 vmx_segment_cache_clear(to_vmx(vcpu
));
4083 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4084 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4085 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4087 vmcs_write32(GUEST_TR_AR_BYTES
,
4088 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4089 | VMX_AR_TYPE_BUSY_64_TSS
);
4091 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4094 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4096 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4097 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4102 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4105 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4107 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4109 vpid_sync_context(vpid
);
4113 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4115 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4118 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4121 vmx_flush_tlb(vcpu
);
4124 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4126 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4128 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4129 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4132 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4134 if (enable_ept
&& is_paging(vcpu
))
4135 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4136 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4139 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4141 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4143 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4144 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4147 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4149 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4151 if (!test_bit(VCPU_EXREG_PDPTR
,
4152 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4155 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4156 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4157 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4158 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4159 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4163 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4165 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4167 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4168 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4169 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4170 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4171 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4174 __set_bit(VCPU_EXREG_PDPTR
,
4175 (unsigned long *)&vcpu
->arch
.regs_avail
);
4176 __set_bit(VCPU_EXREG_PDPTR
,
4177 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4180 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4182 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4183 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4184 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4186 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4187 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4188 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4189 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4191 return fixed_bits_valid(val
, fixed0
, fixed1
);
4194 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4196 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4197 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4199 return fixed_bits_valid(val
, fixed0
, fixed1
);
4202 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4204 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4205 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4207 return fixed_bits_valid(val
, fixed0
, fixed1
);
4210 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4211 #define nested_guest_cr4_valid nested_cr4_valid
4212 #define nested_host_cr4_valid nested_cr4_valid
4214 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4216 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4218 struct kvm_vcpu
*vcpu
)
4220 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4221 vmx_decache_cr3(vcpu
);
4222 if (!(cr0
& X86_CR0_PG
)) {
4223 /* From paging/starting to nonpaging */
4224 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4225 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4226 (CPU_BASED_CR3_LOAD_EXITING
|
4227 CPU_BASED_CR3_STORE_EXITING
));
4228 vcpu
->arch
.cr0
= cr0
;
4229 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4230 } else if (!is_paging(vcpu
)) {
4231 /* From nonpaging to paging */
4232 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4233 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4234 ~(CPU_BASED_CR3_LOAD_EXITING
|
4235 CPU_BASED_CR3_STORE_EXITING
));
4236 vcpu
->arch
.cr0
= cr0
;
4237 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4240 if (!(cr0
& X86_CR0_WP
))
4241 *hw_cr0
&= ~X86_CR0_WP
;
4244 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4246 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4247 unsigned long hw_cr0
;
4249 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4250 if (enable_unrestricted_guest
)
4251 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4253 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4255 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4258 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4262 #ifdef CONFIG_X86_64
4263 if (vcpu
->arch
.efer
& EFER_LME
) {
4264 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4266 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4272 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4274 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4275 vmcs_writel(GUEST_CR0
, hw_cr0
);
4276 vcpu
->arch
.cr0
= cr0
;
4278 /* depends on vcpu->arch.cr0 to be set to a new value */
4279 vmx
->emulation_required
= emulation_required(vcpu
);
4282 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4286 /* TODO write the value reading from MSR */
4287 eptp
= VMX_EPT_DEFAULT_MT
|
4288 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
4289 if (enable_ept_ad_bits
&&
4290 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4291 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
4292 eptp
|= (root_hpa
& PAGE_MASK
);
4297 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4299 unsigned long guest_cr3
;
4304 eptp
= construct_eptp(vcpu
, cr3
);
4305 vmcs_write64(EPT_POINTER
, eptp
);
4306 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4307 guest_cr3
= kvm_read_cr3(vcpu
);
4309 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4310 ept_load_pdptrs(vcpu
);
4313 vmx_flush_tlb(vcpu
);
4314 vmcs_writel(GUEST_CR3
, guest_cr3
);
4317 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4320 * Pass through host's Machine Check Enable value to hw_cr4, which
4321 * is in force while we are in guest mode. Do not let guests control
4322 * this bit, even if host CR4.MCE == 0.
4324 unsigned long hw_cr4
=
4325 (cr4_read_shadow() & X86_CR4_MCE
) |
4326 (cr4
& ~X86_CR4_MCE
) |
4327 (to_vmx(vcpu
)->rmode
.vm86_active
?
4328 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4330 if (cr4
& X86_CR4_VMXE
) {
4332 * To use VMXON (and later other VMX instructions), a guest
4333 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4334 * So basically the check on whether to allow nested VMX
4337 if (!nested_vmx_allowed(vcpu
))
4341 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4344 vcpu
->arch
.cr4
= cr4
;
4346 if (!is_paging(vcpu
)) {
4347 hw_cr4
&= ~X86_CR4_PAE
;
4348 hw_cr4
|= X86_CR4_PSE
;
4349 } else if (!(cr4
& X86_CR4_PAE
)) {
4350 hw_cr4
&= ~X86_CR4_PAE
;
4354 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4356 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4357 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4358 * to be manually disabled when guest switches to non-paging
4361 * If !enable_unrestricted_guest, the CPU is always running
4362 * with CR0.PG=1 and CR4 needs to be modified.
4363 * If enable_unrestricted_guest, the CPU automatically
4364 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4366 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4368 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4369 vmcs_writel(GUEST_CR4
, hw_cr4
);
4373 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4374 struct kvm_segment
*var
, int seg
)
4376 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4379 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4380 *var
= vmx
->rmode
.segs
[seg
];
4381 if (seg
== VCPU_SREG_TR
4382 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4384 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4385 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4388 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4389 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4390 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4391 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4392 var
->unusable
= (ar
>> 16) & 1;
4393 var
->type
= ar
& 15;
4394 var
->s
= (ar
>> 4) & 1;
4395 var
->dpl
= (ar
>> 5) & 3;
4397 * Some userspaces do not preserve unusable property. Since usable
4398 * segment has to be present according to VMX spec we can use present
4399 * property to amend userspace bug by making unusable segment always
4400 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4401 * segment as unusable.
4403 var
->present
= !var
->unusable
;
4404 var
->avl
= (ar
>> 12) & 1;
4405 var
->l
= (ar
>> 13) & 1;
4406 var
->db
= (ar
>> 14) & 1;
4407 var
->g
= (ar
>> 15) & 1;
4410 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4412 struct kvm_segment s
;
4414 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4415 vmx_get_segment(vcpu
, &s
, seg
);
4418 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4421 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4423 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4425 if (unlikely(vmx
->rmode
.vm86_active
))
4428 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4429 return VMX_AR_DPL(ar
);
4433 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4437 if (var
->unusable
|| !var
->present
)
4440 ar
= var
->type
& 15;
4441 ar
|= (var
->s
& 1) << 4;
4442 ar
|= (var
->dpl
& 3) << 5;
4443 ar
|= (var
->present
& 1) << 7;
4444 ar
|= (var
->avl
& 1) << 12;
4445 ar
|= (var
->l
& 1) << 13;
4446 ar
|= (var
->db
& 1) << 14;
4447 ar
|= (var
->g
& 1) << 15;
4453 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4454 struct kvm_segment
*var
, int seg
)
4456 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4457 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4459 vmx_segment_cache_clear(vmx
);
4461 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4462 vmx
->rmode
.segs
[seg
] = *var
;
4463 if (seg
== VCPU_SREG_TR
)
4464 vmcs_write16(sf
->selector
, var
->selector
);
4466 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4470 vmcs_writel(sf
->base
, var
->base
);
4471 vmcs_write32(sf
->limit
, var
->limit
);
4472 vmcs_write16(sf
->selector
, var
->selector
);
4475 * Fix the "Accessed" bit in AR field of segment registers for older
4477 * IA32 arch specifies that at the time of processor reset the
4478 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4479 * is setting it to 0 in the userland code. This causes invalid guest
4480 * state vmexit when "unrestricted guest" mode is turned on.
4481 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4482 * tree. Newer qemu binaries with that qemu fix would not need this
4485 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4486 var
->type
|= 0x1; /* Accessed */
4488 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4491 vmx
->emulation_required
= emulation_required(vcpu
);
4494 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4496 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4498 *db
= (ar
>> 14) & 1;
4499 *l
= (ar
>> 13) & 1;
4502 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4504 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4505 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4508 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4510 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4511 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4514 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4516 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4517 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4520 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4522 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4523 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4526 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4528 struct kvm_segment var
;
4531 vmx_get_segment(vcpu
, &var
, seg
);
4533 if (seg
== VCPU_SREG_CS
)
4535 ar
= vmx_segment_access_rights(&var
);
4537 if (var
.base
!= (var
.selector
<< 4))
4539 if (var
.limit
!= 0xffff)
4547 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4549 struct kvm_segment cs
;
4550 unsigned int cs_rpl
;
4552 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4553 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4557 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4561 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4562 if (cs
.dpl
> cs_rpl
)
4565 if (cs
.dpl
!= cs_rpl
)
4571 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4575 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4577 struct kvm_segment ss
;
4578 unsigned int ss_rpl
;
4580 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4581 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4585 if (ss
.type
!= 3 && ss
.type
!= 7)
4589 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4597 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4599 struct kvm_segment var
;
4602 vmx_get_segment(vcpu
, &var
, seg
);
4603 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4611 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4612 if (var
.dpl
< rpl
) /* DPL < RPL */
4616 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4622 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4624 struct kvm_segment tr
;
4626 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4630 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4632 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4640 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4642 struct kvm_segment ldtr
;
4644 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4648 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4658 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4660 struct kvm_segment cs
, ss
;
4662 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4663 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4665 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4666 (ss
.selector
& SEGMENT_RPL_MASK
));
4670 * Check if guest state is valid. Returns true if valid, false if
4672 * We assume that registers are always usable
4674 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4676 if (enable_unrestricted_guest
)
4679 /* real mode guest state checks */
4680 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4681 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4683 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4685 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4687 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4689 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4691 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4694 /* protected mode guest state checks */
4695 if (!cs_ss_rpl_check(vcpu
))
4697 if (!code_segment_valid(vcpu
))
4699 if (!stack_segment_valid(vcpu
))
4701 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4703 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4705 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4707 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4709 if (!tr_valid(vcpu
))
4711 if (!ldtr_valid(vcpu
))
4715 * - Add checks on RIP
4716 * - Add checks on RFLAGS
4722 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4724 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4727 static int init_rmode_tss(struct kvm
*kvm
)
4733 idx
= srcu_read_lock(&kvm
->srcu
);
4734 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4735 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4738 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4739 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4740 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4743 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4746 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4750 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4751 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4754 srcu_read_unlock(&kvm
->srcu
, idx
);
4758 static int init_rmode_identity_map(struct kvm
*kvm
)
4761 kvm_pfn_t identity_map_pfn
;
4767 /* Protect kvm->arch.ept_identity_pagetable_done. */
4768 mutex_lock(&kvm
->slots_lock
);
4770 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4773 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4775 r
= alloc_identity_pagetable(kvm
);
4779 idx
= srcu_read_lock(&kvm
->srcu
);
4780 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4783 /* Set up identity-mapping pagetable for EPT in real mode */
4784 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4785 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4786 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4787 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4788 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4792 kvm
->arch
.ept_identity_pagetable_done
= true;
4795 srcu_read_unlock(&kvm
->srcu
, idx
);
4798 mutex_unlock(&kvm
->slots_lock
);
4802 static void seg_setup(int seg
)
4804 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4807 vmcs_write16(sf
->selector
, 0);
4808 vmcs_writel(sf
->base
, 0);
4809 vmcs_write32(sf
->limit
, 0xffff);
4811 if (seg
== VCPU_SREG_CS
)
4812 ar
|= 0x08; /* code segment */
4814 vmcs_write32(sf
->ar_bytes
, ar
);
4817 static int alloc_apic_access_page(struct kvm
*kvm
)
4822 mutex_lock(&kvm
->slots_lock
);
4823 if (kvm
->arch
.apic_access_page_done
)
4825 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4826 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4830 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4831 if (is_error_page(page
)) {
4837 * Do not pin the page in memory, so that memory hot-unplug
4838 * is able to migrate it.
4841 kvm
->arch
.apic_access_page_done
= true;
4843 mutex_unlock(&kvm
->slots_lock
);
4847 static int alloc_identity_pagetable(struct kvm
*kvm
)
4849 /* Called with kvm->slots_lock held. */
4853 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4855 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4856 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4861 static int allocate_vpid(void)
4867 spin_lock(&vmx_vpid_lock
);
4868 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4869 if (vpid
< VMX_NR_VPIDS
)
4870 __set_bit(vpid
, vmx_vpid_bitmap
);
4873 spin_unlock(&vmx_vpid_lock
);
4877 static void free_vpid(int vpid
)
4879 if (!enable_vpid
|| vpid
== 0)
4881 spin_lock(&vmx_vpid_lock
);
4882 __clear_bit(vpid
, vmx_vpid_bitmap
);
4883 spin_unlock(&vmx_vpid_lock
);
4886 #define MSR_TYPE_R 1
4887 #define MSR_TYPE_W 2
4888 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4891 int f
= sizeof(unsigned long);
4893 if (!cpu_has_vmx_msr_bitmap())
4897 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4898 * have the write-low and read-high bitmap offsets the wrong way round.
4899 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4901 if (msr
<= 0x1fff) {
4902 if (type
& MSR_TYPE_R
)
4904 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4906 if (type
& MSR_TYPE_W
)
4908 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4910 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4912 if (type
& MSR_TYPE_R
)
4914 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4916 if (type
& MSR_TYPE_W
)
4918 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4924 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4925 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4927 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4928 unsigned long *msr_bitmap_nested
,
4931 int f
= sizeof(unsigned long);
4933 if (!cpu_has_vmx_msr_bitmap()) {
4939 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4940 * have the write-low and read-high bitmap offsets the wrong way round.
4941 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4943 if (msr
<= 0x1fff) {
4944 if (type
& MSR_TYPE_R
&&
4945 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4947 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4949 if (type
& MSR_TYPE_W
&&
4950 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4952 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4954 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4956 if (type
& MSR_TYPE_R
&&
4957 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4959 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4961 if (type
& MSR_TYPE_W
&&
4962 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4964 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4969 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4972 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4973 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4974 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4975 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4978 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
4981 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
4983 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
4986 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4988 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4993 static bool vmx_get_enable_apicv(void)
4995 return enable_apicv
;
4998 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5000 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5005 if (vmx
->nested
.pi_desc
&&
5006 vmx
->nested
.pi_pending
) {
5007 vmx
->nested
.pi_pending
= false;
5008 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5011 max_irr
= find_last_bit(
5012 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5017 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5018 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5019 kunmap(vmx
->nested
.virtual_apic_page
);
5021 status
= vmcs_read16(GUEST_INTR_STATUS
);
5022 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5024 status
|= (u8
)max_irr
;
5025 vmcs_write16(GUEST_INTR_STATUS
, status
);
5030 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5034 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5036 if (vcpu
->mode
== IN_GUEST_MODE
) {
5037 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5040 * Currently, we don't support urgent interrupt,
5041 * all interrupts are recognized as non-urgent
5042 * interrupt, so we cannot post interrupts when
5045 * If the vcpu is in guest mode, it means it is
5046 * running instead of being scheduled out and
5047 * waiting in the run queue, and that's the only
5048 * case when 'SN' is set currently, warning if
5051 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
5053 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5060 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5063 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5065 if (is_guest_mode(vcpu
) &&
5066 vector
== vmx
->nested
.posted_intr_nv
) {
5067 /* the PIR and ON have been set by L1. */
5068 kvm_vcpu_trigger_posted_interrupt(vcpu
, true);
5070 * If a posted intr is not recognized by hardware,
5071 * we will accomplish it in the next vmentry.
5073 vmx
->nested
.pi_pending
= true;
5074 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5080 * Send interrupt to vcpu via posted interrupt way.
5081 * 1. If target vcpu is running(non-root mode), send posted interrupt
5082 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5083 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5084 * interrupt from PIR in next vmentry.
5086 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5088 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5091 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5095 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5098 /* If a previous notification has sent the IPI, nothing to do. */
5099 if (pi_test_and_set_on(&vmx
->pi_desc
))
5102 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5103 kvm_vcpu_kick(vcpu
);
5107 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5108 * will not change in the lifetime of the guest.
5109 * Note that host-state that does change is set elsewhere. E.g., host-state
5110 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5112 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5117 unsigned long cr0
, cr3
, cr4
;
5120 WARN_ON(cr0
& X86_CR0_TS
);
5121 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5124 * Save the most likely value for this task's CR3 in the VMCS.
5125 * We can't use __get_current_cr3_fast() because we're not atomic.
5128 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5129 vmx
->host_state
.vmcs_host_cr3
= cr3
;
5131 /* Save the most likely value for this task's CR4 in the VMCS. */
5132 cr4
= cr4_read_shadow();
5133 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5134 vmx
->host_state
.vmcs_host_cr4
= cr4
;
5136 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5137 #ifdef CONFIG_X86_64
5139 * Load null selectors, so we can avoid reloading them in
5140 * __vmx_load_host_state(), in case userspace uses the null selectors
5141 * too (the expected case).
5143 vmcs_write16(HOST_DS_SELECTOR
, 0);
5144 vmcs_write16(HOST_ES_SELECTOR
, 0);
5146 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5147 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5149 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5150 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5152 native_store_idt(&dt
);
5153 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5154 vmx
->host_idt_base
= dt
.address
;
5156 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5158 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5159 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5160 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5161 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5163 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5164 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5165 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5169 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5171 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5173 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5174 if (is_guest_mode(&vmx
->vcpu
))
5175 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5176 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5177 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5180 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5182 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5184 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5185 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5186 /* Enable the preemption timer dynamically */
5187 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5188 return pin_based_exec_ctrl
;
5191 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5193 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5195 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5196 if (cpu_has_secondary_exec_ctrls()) {
5197 if (kvm_vcpu_apicv_active(vcpu
))
5198 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5199 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5200 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5202 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5203 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5204 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5207 if (cpu_has_vmx_msr_bitmap())
5208 vmx_set_msr_bitmap(vcpu
);
5211 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5213 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5215 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5216 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5218 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5219 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5220 #ifdef CONFIG_X86_64
5221 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5222 CPU_BASED_CR8_LOAD_EXITING
;
5226 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5227 CPU_BASED_CR3_LOAD_EXITING
|
5228 CPU_BASED_INVLPG_EXITING
;
5229 return exec_control
;
5232 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
5234 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5235 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
5236 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5238 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5240 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5241 enable_unrestricted_guest
= 0;
5242 /* Enable INVPCID for non-ept guests may cause performance regression. */
5243 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5245 if (!enable_unrestricted_guest
)
5246 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5248 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5249 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5250 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5251 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5252 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5253 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5255 We can NOT enable shadow_vmcs here because we don't have yet
5258 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5261 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5263 return exec_control
;
5266 static void ept_set_mmio_spte_mask(void)
5269 * EPT Misconfigurations can be generated if the value of bits 2:0
5270 * of an EPT paging-structure entry is 110b (write/execute).
5272 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5273 VMX_EPT_MISCONFIG_WX_VALUE
);
5276 #define VMX_XSS_EXIT_BITMAP 0
5278 * Sets up the vmcs for emulated real mode.
5280 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5282 #ifdef CONFIG_X86_64
5288 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5289 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5291 if (enable_shadow_vmcs
) {
5292 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5293 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5295 if (cpu_has_vmx_msr_bitmap())
5296 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5298 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5301 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5302 vmx
->hv_deadline_tsc
= -1;
5304 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5306 if (cpu_has_secondary_exec_ctrls()) {
5307 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5308 vmx_secondary_exec_control(vmx
));
5311 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5312 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5313 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5314 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5315 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5317 vmcs_write16(GUEST_INTR_STATUS
, 0);
5319 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5320 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5324 vmcs_write32(PLE_GAP
, ple_gap
);
5325 vmx
->ple_window
= ple_window
;
5326 vmx
->ple_window_dirty
= true;
5329 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5330 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5331 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5333 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5334 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5335 vmx_set_constant_host_state(vmx
);
5336 #ifdef CONFIG_X86_64
5337 rdmsrl(MSR_FS_BASE
, a
);
5338 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5339 rdmsrl(MSR_GS_BASE
, a
);
5340 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5342 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5343 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5346 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5347 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5348 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5349 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5350 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5352 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5353 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5355 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5356 u32 index
= vmx_msr_index
[i
];
5357 u32 data_low
, data_high
;
5360 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5362 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5364 vmx
->guest_msrs
[j
].index
= i
;
5365 vmx
->guest_msrs
[j
].data
= 0;
5366 vmx
->guest_msrs
[j
].mask
= -1ull;
5371 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5373 /* 22.2.1, 20.8.1 */
5374 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5376 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5377 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5379 set_cr4_guest_host_mask(vmx
);
5381 if (vmx_xsaves_supported())
5382 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5385 ASSERT(vmx
->pml_pg
);
5386 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5387 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5393 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5395 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5396 struct msr_data apic_base_msr
;
5399 vmx
->rmode
.vm86_active
= 0;
5401 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5402 kvm_set_cr8(vcpu
, 0);
5405 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5406 MSR_IA32_APICBASE_ENABLE
;
5407 if (kvm_vcpu_is_reset_bsp(vcpu
))
5408 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5409 apic_base_msr
.host_initiated
= true;
5410 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5413 vmx_segment_cache_clear(vmx
);
5415 seg_setup(VCPU_SREG_CS
);
5416 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5417 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5419 seg_setup(VCPU_SREG_DS
);
5420 seg_setup(VCPU_SREG_ES
);
5421 seg_setup(VCPU_SREG_FS
);
5422 seg_setup(VCPU_SREG_GS
);
5423 seg_setup(VCPU_SREG_SS
);
5425 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5426 vmcs_writel(GUEST_TR_BASE
, 0);
5427 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5428 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5430 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5431 vmcs_writel(GUEST_LDTR_BASE
, 0);
5432 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5433 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5436 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5437 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5438 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5439 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5442 vmcs_writel(GUEST_RFLAGS
, 0x02);
5443 kvm_rip_write(vcpu
, 0xfff0);
5445 vmcs_writel(GUEST_GDTR_BASE
, 0);
5446 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5448 vmcs_writel(GUEST_IDTR_BASE
, 0);
5449 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5451 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5452 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5453 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5457 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5459 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5460 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5461 if (cpu_need_tpr_shadow(vcpu
))
5462 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5463 __pa(vcpu
->arch
.apic
->regs
));
5464 vmcs_write32(TPR_THRESHOLD
, 0);
5467 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5469 if (kvm_vcpu_apicv_active(vcpu
))
5470 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5473 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5475 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5476 vmx
->vcpu
.arch
.cr0
= cr0
;
5477 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5478 vmx_set_cr4(vcpu
, 0);
5479 vmx_set_efer(vcpu
, 0);
5481 update_exception_bitmap(vcpu
);
5483 vpid_sync_context(vmx
->vpid
);
5487 * In nested virtualization, check if L1 asked to exit on external interrupts.
5488 * For most existing hypervisors, this will always return true.
5490 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5492 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5493 PIN_BASED_EXT_INTR_MASK
;
5497 * In nested virtualization, check if L1 has set
5498 * VM_EXIT_ACK_INTR_ON_EXIT
5500 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5502 return get_vmcs12(vcpu
)->vm_exit_controls
&
5503 VM_EXIT_ACK_INTR_ON_EXIT
;
5506 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5508 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5509 PIN_BASED_NMI_EXITING
;
5512 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5514 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5515 CPU_BASED_VIRTUAL_INTR_PENDING
);
5518 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5520 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5521 enable_irq_window(vcpu
);
5525 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5526 CPU_BASED_VIRTUAL_NMI_PENDING
);
5529 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5531 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5533 int irq
= vcpu
->arch
.interrupt
.nr
;
5535 trace_kvm_inj_virq(irq
);
5537 ++vcpu
->stat
.irq_injections
;
5538 if (vmx
->rmode
.vm86_active
) {
5540 if (vcpu
->arch
.interrupt
.soft
)
5541 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5542 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5543 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5546 intr
= irq
| INTR_INFO_VALID_MASK
;
5547 if (vcpu
->arch
.interrupt
.soft
) {
5548 intr
|= INTR_TYPE_SOFT_INTR
;
5549 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5550 vmx
->vcpu
.arch
.event_exit_inst_len
);
5552 intr
|= INTR_TYPE_EXT_INTR
;
5553 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5556 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5558 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5560 ++vcpu
->stat
.nmi_injections
;
5561 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5563 if (vmx
->rmode
.vm86_active
) {
5564 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5565 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5569 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5570 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5573 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5575 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5578 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5580 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5581 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5585 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5587 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5589 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5591 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5592 GUEST_INTR_STATE_NMI
);
5594 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5595 GUEST_INTR_STATE_NMI
);
5598 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5600 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5603 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5604 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5605 | GUEST_INTR_STATE_NMI
));
5608 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5610 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5611 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5612 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5613 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5616 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5620 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5624 kvm
->arch
.tss_addr
= addr
;
5625 return init_rmode_tss(kvm
);
5628 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5633 * Update instruction length as we may reinject the exception
5634 * from user space while in guest debugging mode.
5636 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5637 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5638 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5642 if (vcpu
->guest_debug
&
5643 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5660 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5661 int vec
, u32 err_code
)
5664 * Instruction with address size override prefix opcode 0x67
5665 * Cause the #SS fault with 0 error code in VM86 mode.
5667 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5668 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5669 if (vcpu
->arch
.halt_request
) {
5670 vcpu
->arch
.halt_request
= 0;
5671 return kvm_vcpu_halt(vcpu
);
5679 * Forward all other exceptions that are valid in real mode.
5680 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5681 * the required debugging infrastructure rework.
5683 kvm_queue_exception(vcpu
, vec
);
5688 * Trigger machine check on the host. We assume all the MSRs are already set up
5689 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5690 * We pass a fake environment to the machine check handler because we want
5691 * the guest to be always treated like user space, no matter what context
5692 * it used internally.
5694 static void kvm_machine_check(void)
5696 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5697 struct pt_regs regs
= {
5698 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5699 .flags
= X86_EFLAGS_IF
,
5702 do_machine_check(®s
, 0);
5706 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5708 /* already handled by vcpu_run */
5712 static int handle_exception(struct kvm_vcpu
*vcpu
)
5714 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5715 struct kvm_run
*kvm_run
= vcpu
->run
;
5716 u32 intr_info
, ex_no
, error_code
;
5717 unsigned long cr2
, rip
, dr6
;
5719 enum emulation_result er
;
5721 vect_info
= vmx
->idt_vectoring_info
;
5722 intr_info
= vmx
->exit_intr_info
;
5724 if (is_machine_check(intr_info
))
5725 return handle_machine_check(vcpu
);
5727 if (is_nmi(intr_info
))
5728 return 1; /* already handled by vmx_vcpu_run() */
5730 if (is_invalid_opcode(intr_info
)) {
5731 if (is_guest_mode(vcpu
)) {
5732 kvm_queue_exception(vcpu
, UD_VECTOR
);
5735 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5736 if (er
!= EMULATE_DONE
)
5737 kvm_queue_exception(vcpu
, UD_VECTOR
);
5742 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5743 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5746 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5747 * MMIO, it is better to report an internal error.
5748 * See the comments in vmx_handle_exit.
5750 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5751 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5752 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5753 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5754 vcpu
->run
->internal
.ndata
= 3;
5755 vcpu
->run
->internal
.data
[0] = vect_info
;
5756 vcpu
->run
->internal
.data
[1] = intr_info
;
5757 vcpu
->run
->internal
.data
[2] = error_code
;
5761 if (is_page_fault(intr_info
)) {
5762 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5763 /* EPT won't cause page fault directly */
5764 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5765 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0,
5769 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5771 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5772 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5776 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5779 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5780 if (!(vcpu
->guest_debug
&
5781 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5782 vcpu
->arch
.dr6
&= ~15;
5783 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5784 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5785 skip_emulated_instruction(vcpu
);
5787 kvm_queue_exception(vcpu
, DB_VECTOR
);
5790 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5791 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5795 * Update instruction length as we may reinject #BP from
5796 * user space while in guest debugging mode. Reading it for
5797 * #DB as well causes no harm, it is not used in that case.
5799 vmx
->vcpu
.arch
.event_exit_inst_len
=
5800 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5801 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5802 rip
= kvm_rip_read(vcpu
);
5803 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5804 kvm_run
->debug
.arch
.exception
= ex_no
;
5807 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5808 kvm_run
->ex
.exception
= ex_no
;
5809 kvm_run
->ex
.error_code
= error_code
;
5815 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5817 ++vcpu
->stat
.irq_exits
;
5821 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5823 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5827 static int handle_io(struct kvm_vcpu
*vcpu
)
5829 unsigned long exit_qualification
;
5830 int size
, in
, string
, ret
;
5833 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5834 string
= (exit_qualification
& 16) != 0;
5835 in
= (exit_qualification
& 8) != 0;
5837 ++vcpu
->stat
.io_exits
;
5840 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5842 port
= exit_qualification
>> 16;
5843 size
= (exit_qualification
& 7) + 1;
5845 ret
= kvm_skip_emulated_instruction(vcpu
);
5848 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5849 * KVM_EXIT_DEBUG here.
5851 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
5855 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5858 * Patch in the VMCALL instruction:
5860 hypercall
[0] = 0x0f;
5861 hypercall
[1] = 0x01;
5862 hypercall
[2] = 0xc1;
5865 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5866 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5868 if (is_guest_mode(vcpu
)) {
5869 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5870 unsigned long orig_val
= val
;
5873 * We get here when L2 changed cr0 in a way that did not change
5874 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5875 * but did change L0 shadowed bits. So we first calculate the
5876 * effective cr0 value that L1 would like to write into the
5877 * hardware. It consists of the L2-owned bits from the new
5878 * value combined with the L1-owned bits from L1's guest_cr0.
5880 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5881 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5883 if (!nested_guest_cr0_valid(vcpu
, val
))
5886 if (kvm_set_cr0(vcpu
, val
))
5888 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5891 if (to_vmx(vcpu
)->nested
.vmxon
&&
5892 !nested_host_cr0_valid(vcpu
, val
))
5895 return kvm_set_cr0(vcpu
, val
);
5899 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5901 if (is_guest_mode(vcpu
)) {
5902 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5903 unsigned long orig_val
= val
;
5905 /* analogously to handle_set_cr0 */
5906 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5907 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5908 if (kvm_set_cr4(vcpu
, val
))
5910 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5913 return kvm_set_cr4(vcpu
, val
);
5916 static int handle_cr(struct kvm_vcpu
*vcpu
)
5918 unsigned long exit_qualification
, val
;
5924 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5925 cr
= exit_qualification
& 15;
5926 reg
= (exit_qualification
>> 8) & 15;
5927 switch ((exit_qualification
>> 4) & 3) {
5928 case 0: /* mov to cr */
5929 val
= kvm_register_readl(vcpu
, reg
);
5930 trace_kvm_cr_write(cr
, val
);
5933 err
= handle_set_cr0(vcpu
, val
);
5934 return kvm_complete_insn_gp(vcpu
, err
);
5936 err
= kvm_set_cr3(vcpu
, val
);
5937 return kvm_complete_insn_gp(vcpu
, err
);
5939 err
= handle_set_cr4(vcpu
, val
);
5940 return kvm_complete_insn_gp(vcpu
, err
);
5942 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5944 err
= kvm_set_cr8(vcpu
, cr8
);
5945 ret
= kvm_complete_insn_gp(vcpu
, err
);
5946 if (lapic_in_kernel(vcpu
))
5948 if (cr8_prev
<= cr8
)
5951 * TODO: we might be squashing a
5952 * KVM_GUESTDBG_SINGLESTEP-triggered
5953 * KVM_EXIT_DEBUG here.
5955 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5961 WARN_ONCE(1, "Guest should always own CR0.TS");
5962 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5963 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5964 return kvm_skip_emulated_instruction(vcpu
);
5965 case 1: /*mov from cr*/
5968 val
= kvm_read_cr3(vcpu
);
5969 kvm_register_write(vcpu
, reg
, val
);
5970 trace_kvm_cr_read(cr
, val
);
5971 return kvm_skip_emulated_instruction(vcpu
);
5973 val
= kvm_get_cr8(vcpu
);
5974 kvm_register_write(vcpu
, reg
, val
);
5975 trace_kvm_cr_read(cr
, val
);
5976 return kvm_skip_emulated_instruction(vcpu
);
5980 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5981 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5982 kvm_lmsw(vcpu
, val
);
5984 return kvm_skip_emulated_instruction(vcpu
);
5988 vcpu
->run
->exit_reason
= 0;
5989 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5990 (int)(exit_qualification
>> 4) & 3, cr
);
5994 static int handle_dr(struct kvm_vcpu
*vcpu
)
5996 unsigned long exit_qualification
;
5999 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6000 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6002 /* First, if DR does not exist, trigger UD */
6003 if (!kvm_require_dr(vcpu
, dr
))
6006 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6007 if (!kvm_require_cpl(vcpu
, 0))
6009 dr7
= vmcs_readl(GUEST_DR7
);
6012 * As the vm-exit takes precedence over the debug trap, we
6013 * need to emulate the latter, either for the host or the
6014 * guest debugging itself.
6016 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6017 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6018 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6019 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6020 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6021 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6024 vcpu
->arch
.dr6
&= ~15;
6025 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6026 kvm_queue_exception(vcpu
, DB_VECTOR
);
6031 if (vcpu
->guest_debug
== 0) {
6032 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6033 CPU_BASED_MOV_DR_EXITING
);
6036 * No more DR vmexits; force a reload of the debug registers
6037 * and reenter on this instruction. The next vmexit will
6038 * retrieve the full state of the debug registers.
6040 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6044 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6045 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6048 if (kvm_get_dr(vcpu
, dr
, &val
))
6050 kvm_register_write(vcpu
, reg
, val
);
6052 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6055 return kvm_skip_emulated_instruction(vcpu
);
6058 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6060 return vcpu
->arch
.dr6
;
6063 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6067 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6069 get_debugreg(vcpu
->arch
.db
[0], 0);
6070 get_debugreg(vcpu
->arch
.db
[1], 1);
6071 get_debugreg(vcpu
->arch
.db
[2], 2);
6072 get_debugreg(vcpu
->arch
.db
[3], 3);
6073 get_debugreg(vcpu
->arch
.dr6
, 6);
6074 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6076 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6077 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6080 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6082 vmcs_writel(GUEST_DR7
, val
);
6085 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6087 return kvm_emulate_cpuid(vcpu
);
6090 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6092 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6093 struct msr_data msr_info
;
6095 msr_info
.index
= ecx
;
6096 msr_info
.host_initiated
= false;
6097 if (vmx_get_msr(vcpu
, &msr_info
)) {
6098 trace_kvm_msr_read_ex(ecx
);
6099 kvm_inject_gp(vcpu
, 0);
6103 trace_kvm_msr_read(ecx
, msr_info
.data
);
6105 /* FIXME: handling of bits 32:63 of rax, rdx */
6106 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6107 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6108 return kvm_skip_emulated_instruction(vcpu
);
6111 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6113 struct msr_data msr
;
6114 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6115 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6116 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6120 msr
.host_initiated
= false;
6121 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6122 trace_kvm_msr_write_ex(ecx
, data
);
6123 kvm_inject_gp(vcpu
, 0);
6127 trace_kvm_msr_write(ecx
, data
);
6128 return kvm_skip_emulated_instruction(vcpu
);
6131 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6133 kvm_apic_update_ppr(vcpu
);
6137 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6139 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6140 CPU_BASED_VIRTUAL_INTR_PENDING
);
6142 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6144 ++vcpu
->stat
.irq_window_exits
;
6148 static int handle_halt(struct kvm_vcpu
*vcpu
)
6150 return kvm_emulate_halt(vcpu
);
6153 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6155 return kvm_emulate_hypercall(vcpu
);
6158 static int handle_invd(struct kvm_vcpu
*vcpu
)
6160 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6163 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6165 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6167 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6168 return kvm_skip_emulated_instruction(vcpu
);
6171 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6175 err
= kvm_rdpmc(vcpu
);
6176 return kvm_complete_insn_gp(vcpu
, err
);
6179 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6181 return kvm_emulate_wbinvd(vcpu
);
6184 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6186 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6187 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6189 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6190 return kvm_skip_emulated_instruction(vcpu
);
6194 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6196 kvm_skip_emulated_instruction(vcpu
);
6197 WARN(1, "this should never happen\n");
6201 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6203 kvm_skip_emulated_instruction(vcpu
);
6204 WARN(1, "this should never happen\n");
6208 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6210 if (likely(fasteoi
)) {
6211 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6212 int access_type
, offset
;
6214 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6215 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6217 * Sane guest uses MOV to write EOI, with written value
6218 * not cared. So make a short-circuit here by avoiding
6219 * heavy instruction emulation.
6221 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6222 (offset
== APIC_EOI
)) {
6223 kvm_lapic_set_eoi(vcpu
);
6224 return kvm_skip_emulated_instruction(vcpu
);
6227 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6230 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6232 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6233 int vector
= exit_qualification
& 0xff;
6235 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6236 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6240 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6242 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6243 u32 offset
= exit_qualification
& 0xfff;
6245 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6246 kvm_apic_write_nodecode(vcpu
, offset
);
6250 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6252 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6253 unsigned long exit_qualification
;
6254 bool has_error_code
= false;
6257 int reason
, type
, idt_v
, idt_index
;
6259 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6260 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6261 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6263 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6265 reason
= (u32
)exit_qualification
>> 30;
6266 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6268 case INTR_TYPE_NMI_INTR
:
6269 vcpu
->arch
.nmi_injected
= false;
6270 vmx_set_nmi_mask(vcpu
, true);
6272 case INTR_TYPE_EXT_INTR
:
6273 case INTR_TYPE_SOFT_INTR
:
6274 kvm_clear_interrupt_queue(vcpu
);
6276 case INTR_TYPE_HARD_EXCEPTION
:
6277 if (vmx
->idt_vectoring_info
&
6278 VECTORING_INFO_DELIVER_CODE_MASK
) {
6279 has_error_code
= true;
6281 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6284 case INTR_TYPE_SOFT_EXCEPTION
:
6285 kvm_clear_exception_queue(vcpu
);
6291 tss_selector
= exit_qualification
;
6293 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6294 type
!= INTR_TYPE_EXT_INTR
&&
6295 type
!= INTR_TYPE_NMI_INTR
))
6296 skip_emulated_instruction(vcpu
);
6298 if (kvm_task_switch(vcpu
, tss_selector
,
6299 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6300 has_error_code
, error_code
) == EMULATE_FAIL
) {
6301 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6302 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6303 vcpu
->run
->internal
.ndata
= 0;
6308 * TODO: What about debug traps on tss switch?
6309 * Are we supposed to inject them and update dr6?
6315 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6317 unsigned long exit_qualification
;
6321 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6324 * EPT violation happened while executing iret from NMI,
6325 * "blocked by NMI" bit has to be set before next VM entry.
6326 * There are errata that may cause this bit to not be set:
6329 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6330 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6331 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6333 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6334 trace_kvm_page_fault(gpa
, exit_qualification
);
6336 /* Is it a read fault? */
6337 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6338 ? PFERR_USER_MASK
: 0;
6339 /* Is it a write fault? */
6340 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6341 ? PFERR_WRITE_MASK
: 0;
6342 /* Is it a fetch fault? */
6343 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6344 ? PFERR_FETCH_MASK
: 0;
6345 /* ept page table entry is present? */
6346 error_code
|= (exit_qualification
&
6347 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6348 EPT_VIOLATION_EXECUTABLE
))
6349 ? PFERR_PRESENT_MASK
: 0;
6351 vcpu
->arch
.gpa_available
= true;
6352 vcpu
->arch
.exit_qualification
= exit_qualification
;
6354 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6357 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6362 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6363 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6364 trace_kvm_fast_mmio(gpa
);
6365 return kvm_skip_emulated_instruction(vcpu
);
6368 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6369 vcpu
->arch
.gpa_available
= true;
6370 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6371 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6374 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6375 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6377 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6380 /* It is the real ept misconfig */
6383 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6384 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6389 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6391 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6392 CPU_BASED_VIRTUAL_NMI_PENDING
);
6393 ++vcpu
->stat
.nmi_window_exits
;
6394 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6399 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6401 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6402 enum emulation_result err
= EMULATE_DONE
;
6405 bool intr_window_requested
;
6406 unsigned count
= 130;
6408 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6409 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6411 while (vmx
->emulation_required
&& count
-- != 0) {
6412 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6413 return handle_interrupt_window(&vmx
->vcpu
);
6415 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6418 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6420 if (err
== EMULATE_USER_EXIT
) {
6421 ++vcpu
->stat
.mmio_exits
;
6426 if (err
!= EMULATE_DONE
) {
6427 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6428 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6429 vcpu
->run
->internal
.ndata
= 0;
6433 if (vcpu
->arch
.halt_request
) {
6434 vcpu
->arch
.halt_request
= 0;
6435 ret
= kvm_vcpu_halt(vcpu
);
6439 if (signal_pending(current
))
6449 static int __grow_ple_window(int val
)
6451 if (ple_window_grow
< 1)
6454 val
= min(val
, ple_window_actual_max
);
6456 if (ple_window_grow
< ple_window
)
6457 val
*= ple_window_grow
;
6459 val
+= ple_window_grow
;
6464 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6469 if (modifier
< ple_window
)
6474 return max(val
, minimum
);
6477 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6479 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6480 int old
= vmx
->ple_window
;
6482 vmx
->ple_window
= __grow_ple_window(old
);
6484 if (vmx
->ple_window
!= old
)
6485 vmx
->ple_window_dirty
= true;
6487 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6490 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6492 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6493 int old
= vmx
->ple_window
;
6495 vmx
->ple_window
= __shrink_ple_window(old
,
6496 ple_window_shrink
, ple_window
);
6498 if (vmx
->ple_window
!= old
)
6499 vmx
->ple_window_dirty
= true;
6501 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6505 * ple_window_actual_max is computed to be one grow_ple_window() below
6506 * ple_window_max. (See __grow_ple_window for the reason.)
6507 * This prevents overflows, because ple_window_max is int.
6508 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6510 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6512 static void update_ple_window_actual_max(void)
6514 ple_window_actual_max
=
6515 __shrink_ple_window(max(ple_window_max
, ple_window
),
6516 ple_window_grow
, INT_MIN
);
6520 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6522 static void wakeup_handler(void)
6524 struct kvm_vcpu
*vcpu
;
6525 int cpu
= smp_processor_id();
6527 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6528 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6529 blocked_vcpu_list
) {
6530 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6532 if (pi_test_on(pi_desc
) == 1)
6533 kvm_vcpu_kick(vcpu
);
6535 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6538 void vmx_enable_tdp(void)
6540 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6541 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6542 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6543 0ull, VMX_EPT_EXECUTABLE_MASK
,
6544 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6547 ept_set_mmio_spte_mask();
6551 static __init
int hardware_setup(void)
6553 int r
= -ENOMEM
, i
, msr
;
6555 rdmsrl_safe(MSR_EFER
, &host_efer
);
6557 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6558 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6560 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6561 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6566 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6567 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6568 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6571 * Allow direct access to the PC debug port (it is often used for I/O
6572 * delays, but the vmexits simply slow things down).
6574 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6575 clear_bit(0x80, vmx_io_bitmap_a
);
6577 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6579 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6580 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6582 if (setup_vmcs_config(&vmcs_config
) < 0) {
6587 if (boot_cpu_has(X86_FEATURE_NX
))
6588 kvm_enable_efer_bits(EFER_NX
);
6590 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6591 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6594 if (!cpu_has_vmx_shadow_vmcs())
6595 enable_shadow_vmcs
= 0;
6596 if (enable_shadow_vmcs
)
6597 init_vmcs_shadow_fields();
6599 if (!cpu_has_vmx_ept() ||
6600 !cpu_has_vmx_ept_4levels()) {
6602 enable_unrestricted_guest
= 0;
6603 enable_ept_ad_bits
= 0;
6606 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6607 enable_ept_ad_bits
= 0;
6609 if (!cpu_has_vmx_unrestricted_guest())
6610 enable_unrestricted_guest
= 0;
6612 if (!cpu_has_vmx_flexpriority())
6613 flexpriority_enabled
= 0;
6616 * set_apic_access_page_addr() is used to reload apic access
6617 * page upon invalidation. No need to do anything if not
6618 * using the APIC_ACCESS_ADDR VMCS field.
6620 if (!flexpriority_enabled
)
6621 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6623 if (!cpu_has_vmx_tpr_shadow())
6624 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6626 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6627 kvm_disable_largepages();
6629 if (!cpu_has_vmx_ple())
6632 if (!cpu_has_vmx_apicv()) {
6634 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6637 if (cpu_has_vmx_tsc_scaling()) {
6638 kvm_has_tsc_control
= true;
6639 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6640 kvm_tsc_scaling_ratio_frac_bits
= 48;
6643 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6644 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6645 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6646 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6647 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6648 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6650 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6651 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6652 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6653 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6654 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6655 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6656 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6657 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6659 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6661 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6662 if (msr
== 0x839 /* TMCCT */)
6664 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6668 * TPR reads and writes can be virtualized even if virtual interrupt
6669 * delivery is not in use.
6671 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6672 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6675 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6677 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6684 update_ple_window_actual_max();
6687 * Only enable PML when hardware supports PML feature, and both EPT
6688 * and EPT A/D bit features are enabled -- PML depends on them to work.
6690 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6694 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6695 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6696 kvm_x86_ops
->flush_log_dirty
= NULL
;
6697 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6700 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6703 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6704 cpu_preemption_timer_multi
=
6705 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6707 kvm_x86_ops
->set_hv_timer
= NULL
;
6708 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6711 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6713 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6715 return alloc_kvm_area();
6718 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6719 free_page((unsigned long)vmx_bitmap
[i
]);
6724 static __exit
void hardware_unsetup(void)
6728 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6729 free_page((unsigned long)vmx_bitmap
[i
]);
6735 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6736 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6738 static int handle_pause(struct kvm_vcpu
*vcpu
)
6741 grow_ple_window(vcpu
);
6743 kvm_vcpu_on_spin(vcpu
);
6744 return kvm_skip_emulated_instruction(vcpu
);
6747 static int handle_nop(struct kvm_vcpu
*vcpu
)
6749 return kvm_skip_emulated_instruction(vcpu
);
6752 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6754 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6755 return handle_nop(vcpu
);
6758 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6763 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6765 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6766 return handle_nop(vcpu
);
6770 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6771 * We could reuse a single VMCS for all the L2 guests, but we also want the
6772 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6773 * allows keeping them loaded on the processor, and in the future will allow
6774 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6775 * every entry if they never change.
6776 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6777 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6779 * The following functions allocate and free a vmcs02 in this pool.
6782 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6783 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6785 struct vmcs02_list
*item
;
6786 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6787 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6788 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6789 return &item
->vmcs02
;
6792 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6793 /* Recycle the least recently used VMCS. */
6794 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6795 struct vmcs02_list
, list
);
6796 item
->vmptr
= vmx
->nested
.current_vmptr
;
6797 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6798 return &item
->vmcs02
;
6801 /* Create a new VMCS */
6802 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6805 item
->vmcs02
.vmcs
= alloc_vmcs();
6806 item
->vmcs02
.shadow_vmcs
= NULL
;
6807 if (!item
->vmcs02
.vmcs
) {
6811 loaded_vmcs_init(&item
->vmcs02
);
6812 item
->vmptr
= vmx
->nested
.current_vmptr
;
6813 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6814 vmx
->nested
.vmcs02_num
++;
6815 return &item
->vmcs02
;
6818 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6819 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6821 struct vmcs02_list
*item
;
6822 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6823 if (item
->vmptr
== vmptr
) {
6824 free_loaded_vmcs(&item
->vmcs02
);
6825 list_del(&item
->list
);
6827 vmx
->nested
.vmcs02_num
--;
6833 * Free all VMCSs saved for this vcpu, except the one pointed by
6834 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6835 * must be &vmx->vmcs01.
6837 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6839 struct vmcs02_list
*item
, *n
;
6841 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6842 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6844 * Something will leak if the above WARN triggers. Better than
6847 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6850 free_loaded_vmcs(&item
->vmcs02
);
6851 list_del(&item
->list
);
6853 vmx
->nested
.vmcs02_num
--;
6858 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6859 * set the success or error code of an emulated VMX instruction, as specified
6860 * by Vol 2B, VMX Instruction Reference, "Conventions".
6862 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6864 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6865 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6866 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6869 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6871 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6872 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6873 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6877 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6878 u32 vm_instruction_error
)
6880 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6882 * failValid writes the error number to the current VMCS, which
6883 * can't be done there isn't a current VMCS.
6885 nested_vmx_failInvalid(vcpu
);
6888 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6889 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6890 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6892 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6894 * We don't need to force a shadow sync because
6895 * VM_INSTRUCTION_ERROR is not shadowed
6899 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6901 /* TODO: not to reset guest simply here. */
6902 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6903 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6906 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6908 struct vcpu_vmx
*vmx
=
6909 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6911 vmx
->nested
.preemption_timer_expired
= true;
6912 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6913 kvm_vcpu_kick(&vmx
->vcpu
);
6915 return HRTIMER_NORESTART
;
6919 * Decode the memory-address operand of a vmx instruction, as recorded on an
6920 * exit caused by such an instruction (run by a guest hypervisor).
6921 * On success, returns 0. When the operand is invalid, returns 1 and throws
6924 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6925 unsigned long exit_qualification
,
6926 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6930 struct kvm_segment s
;
6933 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6934 * Execution", on an exit, vmx_instruction_info holds most of the
6935 * addressing components of the operand. Only the displacement part
6936 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6937 * For how an actual address is calculated from all these components,
6938 * refer to Vol. 1, "Operand Addressing".
6940 int scaling
= vmx_instruction_info
& 3;
6941 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6942 bool is_reg
= vmx_instruction_info
& (1u << 10);
6943 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6944 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6945 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6946 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6947 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6950 kvm_queue_exception(vcpu
, UD_VECTOR
);
6954 /* Addr = segment_base + offset */
6955 /* offset = base + [index * scale] + displacement */
6956 off
= exit_qualification
; /* holds the displacement */
6958 off
+= kvm_register_read(vcpu
, base_reg
);
6960 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6961 vmx_get_segment(vcpu
, &s
, seg_reg
);
6962 *ret
= s
.base
+ off
;
6964 if (addr_size
== 1) /* 32 bit */
6967 /* Checks for #GP/#SS exceptions. */
6969 if (is_long_mode(vcpu
)) {
6970 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6971 * non-canonical form. This is the only check on the memory
6972 * destination for long mode!
6974 exn
= is_noncanonical_address(*ret
);
6975 } else if (is_protmode(vcpu
)) {
6976 /* Protected mode: apply checks for segment validity in the
6978 * - segment type check (#GP(0) may be thrown)
6979 * - usability check (#GP(0)/#SS(0))
6980 * - limit check (#GP(0)/#SS(0))
6983 /* #GP(0) if the destination operand is located in a
6984 * read-only data segment or any code segment.
6986 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6988 /* #GP(0) if the source operand is located in an
6989 * execute-only code segment
6991 exn
= ((s
.type
& 0xa) == 8);
6993 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6996 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6998 exn
= (s
.unusable
!= 0);
6999 /* Protected mode: #GP(0)/#SS(0) if the memory
7000 * operand is outside the segment limit.
7002 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7005 kvm_queue_exception_e(vcpu
,
7006 seg_reg
== VCPU_SREG_SS
?
7007 SS_VECTOR
: GP_VECTOR
,
7015 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7018 struct x86_exception e
;
7020 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7021 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7024 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7025 sizeof(*vmpointer
), &e
)) {
7026 kvm_inject_page_fault(vcpu
, &e
);
7033 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7035 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7036 struct vmcs
*shadow_vmcs
;
7038 if (cpu_has_vmx_msr_bitmap()) {
7039 vmx
->nested
.msr_bitmap
=
7040 (unsigned long *)__get_free_page(GFP_KERNEL
);
7041 if (!vmx
->nested
.msr_bitmap
)
7042 goto out_msr_bitmap
;
7045 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7046 if (!vmx
->nested
.cached_vmcs12
)
7047 goto out_cached_vmcs12
;
7049 if (enable_shadow_vmcs
) {
7050 shadow_vmcs
= alloc_vmcs();
7052 goto out_shadow_vmcs
;
7053 /* mark vmcs as shadow */
7054 shadow_vmcs
->revision_id
|= (1u << 31);
7055 /* init shadow vmcs */
7056 vmcs_clear(shadow_vmcs
);
7057 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7060 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7061 vmx
->nested
.vmcs02_num
= 0;
7063 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7064 HRTIMER_MODE_REL_PINNED
);
7065 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7067 vmx
->nested
.vmxon
= true;
7071 kfree(vmx
->nested
.cached_vmcs12
);
7074 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7081 * Emulate the VMXON instruction.
7082 * Currently, we just remember that VMX is active, and do not save or even
7083 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7084 * do not currently need to store anything in that guest-allocated memory
7085 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7086 * argument is different from the VMXON pointer (which the spec says they do).
7088 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7093 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7094 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7095 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7098 * The Intel VMX Instruction Reference lists a bunch of bits that are
7099 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7100 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7101 * Otherwise, we should fail with #UD. But most faulting conditions
7102 * have already been checked by hardware, prior to the VM-exit for
7103 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7104 * that bit set to 1 in non-root mode.
7106 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7107 kvm_queue_exception(vcpu
, UD_VECTOR
);
7111 if (vmx
->nested
.vmxon
) {
7112 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7113 return kvm_skip_emulated_instruction(vcpu
);
7116 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7117 != VMXON_NEEDED_FEATURES
) {
7118 kvm_inject_gp(vcpu
, 0);
7122 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7127 * The first 4 bytes of VMXON region contain the supported
7128 * VMCS revision identifier
7130 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7131 * which replaces physical address width with 32
7133 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7134 nested_vmx_failInvalid(vcpu
);
7135 return kvm_skip_emulated_instruction(vcpu
);
7138 page
= nested_get_page(vcpu
, vmptr
);
7140 nested_vmx_failInvalid(vcpu
);
7141 return kvm_skip_emulated_instruction(vcpu
);
7143 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7145 nested_release_page_clean(page
);
7146 nested_vmx_failInvalid(vcpu
);
7147 return kvm_skip_emulated_instruction(vcpu
);
7150 nested_release_page_clean(page
);
7152 vmx
->nested
.vmxon_ptr
= vmptr
;
7153 ret
= enter_vmx_operation(vcpu
);
7157 nested_vmx_succeed(vcpu
);
7158 return kvm_skip_emulated_instruction(vcpu
);
7162 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7163 * for running VMX instructions (except VMXON, whose prerequisites are
7164 * slightly different). It also specifies what exception to inject otherwise.
7165 * Note that many of these exceptions have priority over VM exits, so they
7166 * don't have to be checked again here.
7168 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7170 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7171 kvm_queue_exception(vcpu
, UD_VECTOR
);
7177 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7179 if (vmx
->nested
.current_vmptr
== -1ull)
7182 if (enable_shadow_vmcs
) {
7183 /* copy to memory all shadowed fields in case
7184 they were modified */
7185 copy_shadow_to_vmcs12(vmx
);
7186 vmx
->nested
.sync_shadow_vmcs
= false;
7187 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
7188 SECONDARY_EXEC_SHADOW_VMCS
);
7189 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7191 vmx
->nested
.posted_intr_nv
= -1;
7193 /* Flush VMCS12 to guest memory */
7194 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7195 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7196 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7198 vmx
->nested
.current_vmptr
= -1ull;
7202 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7203 * just stops using VMX.
7205 static void free_nested(struct vcpu_vmx
*vmx
)
7207 if (!vmx
->nested
.vmxon
)
7210 vmx
->nested
.vmxon
= false;
7211 free_vpid(vmx
->nested
.vpid02
);
7212 nested_release_vmcs12(vmx
);
7213 if (vmx
->nested
.msr_bitmap
) {
7214 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7215 vmx
->nested
.msr_bitmap
= NULL
;
7217 if (enable_shadow_vmcs
) {
7218 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7219 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7220 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7222 kfree(vmx
->nested
.cached_vmcs12
);
7223 /* Unpin physical memory we referred to in current vmcs02 */
7224 if (vmx
->nested
.apic_access_page
) {
7225 nested_release_page(vmx
->nested
.apic_access_page
);
7226 vmx
->nested
.apic_access_page
= NULL
;
7228 if (vmx
->nested
.virtual_apic_page
) {
7229 nested_release_page(vmx
->nested
.virtual_apic_page
);
7230 vmx
->nested
.virtual_apic_page
= NULL
;
7232 if (vmx
->nested
.pi_desc_page
) {
7233 kunmap(vmx
->nested
.pi_desc_page
);
7234 nested_release_page(vmx
->nested
.pi_desc_page
);
7235 vmx
->nested
.pi_desc_page
= NULL
;
7236 vmx
->nested
.pi_desc
= NULL
;
7239 nested_free_all_saved_vmcss(vmx
);
7242 /* Emulate the VMXOFF instruction */
7243 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7245 if (!nested_vmx_check_permission(vcpu
))
7247 free_nested(to_vmx(vcpu
));
7248 nested_vmx_succeed(vcpu
);
7249 return kvm_skip_emulated_instruction(vcpu
);
7252 /* Emulate the VMCLEAR instruction */
7253 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7255 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7259 if (!nested_vmx_check_permission(vcpu
))
7262 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7265 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7266 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7267 return kvm_skip_emulated_instruction(vcpu
);
7270 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7271 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7272 return kvm_skip_emulated_instruction(vcpu
);
7275 if (vmptr
== vmx
->nested
.current_vmptr
)
7276 nested_release_vmcs12(vmx
);
7278 kvm_vcpu_write_guest(vcpu
,
7279 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7280 &zero
, sizeof(zero
));
7282 nested_free_vmcs02(vmx
, vmptr
);
7284 nested_vmx_succeed(vcpu
);
7285 return kvm_skip_emulated_instruction(vcpu
);
7288 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7290 /* Emulate the VMLAUNCH instruction */
7291 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7293 return nested_vmx_run(vcpu
, true);
7296 /* Emulate the VMRESUME instruction */
7297 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7300 return nested_vmx_run(vcpu
, false);
7304 * Read a vmcs12 field. Since these can have varying lengths and we return
7305 * one type, we chose the biggest type (u64) and zero-extend the return value
7306 * to that size. Note that the caller, handle_vmread, might need to use only
7307 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7308 * 64-bit fields are to be returned).
7310 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7311 unsigned long field
, u64
*ret
)
7313 short offset
= vmcs_field_to_offset(field
);
7319 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7321 switch (vmcs_field_type(field
)) {
7322 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7323 *ret
= *((natural_width
*)p
);
7325 case VMCS_FIELD_TYPE_U16
:
7328 case VMCS_FIELD_TYPE_U32
:
7331 case VMCS_FIELD_TYPE_U64
:
7341 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7342 unsigned long field
, u64 field_value
){
7343 short offset
= vmcs_field_to_offset(field
);
7344 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7348 switch (vmcs_field_type(field
)) {
7349 case VMCS_FIELD_TYPE_U16
:
7350 *(u16
*)p
= field_value
;
7352 case VMCS_FIELD_TYPE_U32
:
7353 *(u32
*)p
= field_value
;
7355 case VMCS_FIELD_TYPE_U64
:
7356 *(u64
*)p
= field_value
;
7358 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7359 *(natural_width
*)p
= field_value
;
7368 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7371 unsigned long field
;
7373 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7374 const unsigned long *fields
= shadow_read_write_fields
;
7375 const int num_fields
= max_shadow_read_write_fields
;
7379 vmcs_load(shadow_vmcs
);
7381 for (i
= 0; i
< num_fields
; i
++) {
7383 switch (vmcs_field_type(field
)) {
7384 case VMCS_FIELD_TYPE_U16
:
7385 field_value
= vmcs_read16(field
);
7387 case VMCS_FIELD_TYPE_U32
:
7388 field_value
= vmcs_read32(field
);
7390 case VMCS_FIELD_TYPE_U64
:
7391 field_value
= vmcs_read64(field
);
7393 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7394 field_value
= vmcs_readl(field
);
7400 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7403 vmcs_clear(shadow_vmcs
);
7404 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7409 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7411 const unsigned long *fields
[] = {
7412 shadow_read_write_fields
,
7413 shadow_read_only_fields
7415 const int max_fields
[] = {
7416 max_shadow_read_write_fields
,
7417 max_shadow_read_only_fields
7420 unsigned long field
;
7421 u64 field_value
= 0;
7422 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7424 vmcs_load(shadow_vmcs
);
7426 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7427 for (i
= 0; i
< max_fields
[q
]; i
++) {
7428 field
= fields
[q
][i
];
7429 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7431 switch (vmcs_field_type(field
)) {
7432 case VMCS_FIELD_TYPE_U16
:
7433 vmcs_write16(field
, (u16
)field_value
);
7435 case VMCS_FIELD_TYPE_U32
:
7436 vmcs_write32(field
, (u32
)field_value
);
7438 case VMCS_FIELD_TYPE_U64
:
7439 vmcs_write64(field
, (u64
)field_value
);
7441 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7442 vmcs_writel(field
, (long)field_value
);
7451 vmcs_clear(shadow_vmcs
);
7452 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7456 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7457 * used before) all generate the same failure when it is missing.
7459 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7461 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7462 if (vmx
->nested
.current_vmptr
== -1ull) {
7463 nested_vmx_failInvalid(vcpu
);
7469 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7471 unsigned long field
;
7473 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7474 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7477 if (!nested_vmx_check_permission(vcpu
))
7480 if (!nested_vmx_check_vmcs12(vcpu
))
7481 return kvm_skip_emulated_instruction(vcpu
);
7483 /* Decode instruction info and find the field to read */
7484 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7485 /* Read the field, zero-extended to a u64 field_value */
7486 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7487 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7488 return kvm_skip_emulated_instruction(vcpu
);
7491 * Now copy part of this value to register or memory, as requested.
7492 * Note that the number of bits actually copied is 32 or 64 depending
7493 * on the guest's mode (32 or 64 bit), not on the given field's length.
7495 if (vmx_instruction_info
& (1u << 10)) {
7496 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7499 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7500 vmx_instruction_info
, true, &gva
))
7502 /* _system ok, as hardware has verified cpl=0 */
7503 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7504 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7507 nested_vmx_succeed(vcpu
);
7508 return kvm_skip_emulated_instruction(vcpu
);
7512 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7514 unsigned long field
;
7516 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7517 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7518 /* The value to write might be 32 or 64 bits, depending on L1's long
7519 * mode, and eventually we need to write that into a field of several
7520 * possible lengths. The code below first zero-extends the value to 64
7521 * bit (field_value), and then copies only the appropriate number of
7522 * bits into the vmcs12 field.
7524 u64 field_value
= 0;
7525 struct x86_exception e
;
7527 if (!nested_vmx_check_permission(vcpu
))
7530 if (!nested_vmx_check_vmcs12(vcpu
))
7531 return kvm_skip_emulated_instruction(vcpu
);
7533 if (vmx_instruction_info
& (1u << 10))
7534 field_value
= kvm_register_readl(vcpu
,
7535 (((vmx_instruction_info
) >> 3) & 0xf));
7537 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7538 vmx_instruction_info
, false, &gva
))
7540 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7541 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7542 kvm_inject_page_fault(vcpu
, &e
);
7548 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7549 if (vmcs_field_readonly(field
)) {
7550 nested_vmx_failValid(vcpu
,
7551 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7552 return kvm_skip_emulated_instruction(vcpu
);
7555 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7556 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7557 return kvm_skip_emulated_instruction(vcpu
);
7560 nested_vmx_succeed(vcpu
);
7561 return kvm_skip_emulated_instruction(vcpu
);
7564 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7566 vmx
->nested
.current_vmptr
= vmptr
;
7567 if (enable_shadow_vmcs
) {
7568 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7569 SECONDARY_EXEC_SHADOW_VMCS
);
7570 vmcs_write64(VMCS_LINK_POINTER
,
7571 __pa(vmx
->vmcs01
.shadow_vmcs
));
7572 vmx
->nested
.sync_shadow_vmcs
= true;
7576 /* Emulate the VMPTRLD instruction */
7577 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7579 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7582 if (!nested_vmx_check_permission(vcpu
))
7585 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7588 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7589 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7590 return kvm_skip_emulated_instruction(vcpu
);
7593 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7594 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7595 return kvm_skip_emulated_instruction(vcpu
);
7598 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7599 struct vmcs12
*new_vmcs12
;
7601 page
= nested_get_page(vcpu
, vmptr
);
7603 nested_vmx_failInvalid(vcpu
);
7604 return kvm_skip_emulated_instruction(vcpu
);
7606 new_vmcs12
= kmap(page
);
7607 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7609 nested_release_page_clean(page
);
7610 nested_vmx_failValid(vcpu
,
7611 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7612 return kvm_skip_emulated_instruction(vcpu
);
7615 nested_release_vmcs12(vmx
);
7617 * Load VMCS12 from guest memory since it is not already
7620 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7622 nested_release_page_clean(page
);
7624 set_current_vmptr(vmx
, vmptr
);
7627 nested_vmx_succeed(vcpu
);
7628 return kvm_skip_emulated_instruction(vcpu
);
7631 /* Emulate the VMPTRST instruction */
7632 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7634 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7635 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7637 struct x86_exception e
;
7639 if (!nested_vmx_check_permission(vcpu
))
7642 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7643 vmx_instruction_info
, true, &vmcs_gva
))
7645 /* ok to use *_system, as hardware has verified cpl=0 */
7646 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7647 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7649 kvm_inject_page_fault(vcpu
, &e
);
7652 nested_vmx_succeed(vcpu
);
7653 return kvm_skip_emulated_instruction(vcpu
);
7656 /* Emulate the INVEPT instruction */
7657 static int handle_invept(struct kvm_vcpu
*vcpu
)
7659 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7660 u32 vmx_instruction_info
, types
;
7663 struct x86_exception e
;
7668 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7669 SECONDARY_EXEC_ENABLE_EPT
) ||
7670 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7671 kvm_queue_exception(vcpu
, UD_VECTOR
);
7675 if (!nested_vmx_check_permission(vcpu
))
7678 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7679 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7681 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7683 if (type
>= 32 || !(types
& (1 << type
))) {
7684 nested_vmx_failValid(vcpu
,
7685 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7686 return kvm_skip_emulated_instruction(vcpu
);
7689 /* According to the Intel VMX instruction reference, the memory
7690 * operand is read even if it isn't needed (e.g., for type==global)
7692 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7693 vmx_instruction_info
, false, &gva
))
7695 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7696 sizeof(operand
), &e
)) {
7697 kvm_inject_page_fault(vcpu
, &e
);
7702 case VMX_EPT_EXTENT_GLOBAL
:
7704 * TODO: track mappings and invalidate
7705 * single context requests appropriately
7707 case VMX_EPT_EXTENT_CONTEXT
:
7708 kvm_mmu_sync_roots(vcpu
);
7709 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7710 nested_vmx_succeed(vcpu
);
7717 return kvm_skip_emulated_instruction(vcpu
);
7720 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7722 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7723 u32 vmx_instruction_info
;
7724 unsigned long type
, types
;
7726 struct x86_exception e
;
7732 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7733 SECONDARY_EXEC_ENABLE_VPID
) ||
7734 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7735 kvm_queue_exception(vcpu
, UD_VECTOR
);
7739 if (!nested_vmx_check_permission(vcpu
))
7742 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7743 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7745 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7746 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7748 if (type
>= 32 || !(types
& (1 << type
))) {
7749 nested_vmx_failValid(vcpu
,
7750 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7751 return kvm_skip_emulated_instruction(vcpu
);
7754 /* according to the intel vmx instruction reference, the memory
7755 * operand is read even if it isn't needed (e.g., for type==global)
7757 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7758 vmx_instruction_info
, false, &gva
))
7760 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7761 sizeof(operand
), &e
)) {
7762 kvm_inject_page_fault(vcpu
, &e
);
7765 if (operand
.vpid
>> 16) {
7766 nested_vmx_failValid(vcpu
,
7767 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7768 return kvm_skip_emulated_instruction(vcpu
);
7772 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7773 if (is_noncanonical_address(operand
.gla
)) {
7774 nested_vmx_failValid(vcpu
,
7775 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7776 return kvm_skip_emulated_instruction(vcpu
);
7779 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7780 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7781 if (!operand
.vpid
) {
7782 nested_vmx_failValid(vcpu
,
7783 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7784 return kvm_skip_emulated_instruction(vcpu
);
7787 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7791 return kvm_skip_emulated_instruction(vcpu
);
7794 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7795 nested_vmx_succeed(vcpu
);
7797 return kvm_skip_emulated_instruction(vcpu
);
7800 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7802 unsigned long exit_qualification
;
7804 trace_kvm_pml_full(vcpu
->vcpu_id
);
7806 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7809 * PML buffer FULL happened while executing iret from NMI,
7810 * "blocked by NMI" bit has to be set before next VM entry.
7812 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7813 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7814 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7815 GUEST_INTR_STATE_NMI
);
7818 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7819 * here.., and there's no userspace involvement needed for PML.
7824 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7826 kvm_lapic_expired_hv_timer(vcpu
);
7831 * The exit handlers return 1 if the exit was handled fully and guest execution
7832 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7833 * to be done to userspace and return 0.
7835 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7836 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7837 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7838 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7839 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7840 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7841 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7842 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7843 [EXIT_REASON_CPUID
] = handle_cpuid
,
7844 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7845 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7846 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7847 [EXIT_REASON_HLT
] = handle_halt
,
7848 [EXIT_REASON_INVD
] = handle_invd
,
7849 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7850 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7851 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7852 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7853 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7854 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7855 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7856 [EXIT_REASON_VMREAD
] = handle_vmread
,
7857 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7858 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7859 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7860 [EXIT_REASON_VMON
] = handle_vmon
,
7861 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7862 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7863 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7864 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7865 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7866 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7867 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7868 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7869 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7870 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7871 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7872 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7873 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7874 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7875 [EXIT_REASON_INVEPT
] = handle_invept
,
7876 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7877 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7878 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7879 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7880 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7883 static const int kvm_vmx_max_exit_handlers
=
7884 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7886 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7887 struct vmcs12
*vmcs12
)
7889 unsigned long exit_qualification
;
7890 gpa_t bitmap
, last_bitmap
;
7895 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7896 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7898 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7900 port
= exit_qualification
>> 16;
7901 size
= (exit_qualification
& 7) + 1;
7903 last_bitmap
= (gpa_t
)-1;
7908 bitmap
= vmcs12
->io_bitmap_a
;
7909 else if (port
< 0x10000)
7910 bitmap
= vmcs12
->io_bitmap_b
;
7913 bitmap
+= (port
& 0x7fff) / 8;
7915 if (last_bitmap
!= bitmap
)
7916 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7918 if (b
& (1 << (port
& 7)))
7923 last_bitmap
= bitmap
;
7930 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7931 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7932 * disinterest in the current event (read or write a specific MSR) by using an
7933 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7935 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7936 struct vmcs12
*vmcs12
, u32 exit_reason
)
7938 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7941 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7945 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7946 * for the four combinations of read/write and low/high MSR numbers.
7947 * First we need to figure out which of the four to use:
7949 bitmap
= vmcs12
->msr_bitmap
;
7950 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7952 if (msr_index
>= 0xc0000000) {
7953 msr_index
-= 0xc0000000;
7957 /* Then read the msr_index'th bit from this bitmap: */
7958 if (msr_index
< 1024*8) {
7960 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7962 return 1 & (b
>> (msr_index
& 7));
7964 return true; /* let L1 handle the wrong parameter */
7968 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7969 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7970 * intercept (via guest_host_mask etc.) the current event.
7972 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7973 struct vmcs12
*vmcs12
)
7975 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7976 int cr
= exit_qualification
& 15;
7980 switch ((exit_qualification
>> 4) & 3) {
7981 case 0: /* mov to cr */
7982 reg
= (exit_qualification
>> 8) & 15;
7983 val
= kvm_register_readl(vcpu
, reg
);
7986 if (vmcs12
->cr0_guest_host_mask
&
7987 (val
^ vmcs12
->cr0_read_shadow
))
7991 if ((vmcs12
->cr3_target_count
>= 1 &&
7992 vmcs12
->cr3_target_value0
== val
) ||
7993 (vmcs12
->cr3_target_count
>= 2 &&
7994 vmcs12
->cr3_target_value1
== val
) ||
7995 (vmcs12
->cr3_target_count
>= 3 &&
7996 vmcs12
->cr3_target_value2
== val
) ||
7997 (vmcs12
->cr3_target_count
>= 4 &&
7998 vmcs12
->cr3_target_value3
== val
))
8000 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8004 if (vmcs12
->cr4_guest_host_mask
&
8005 (vmcs12
->cr4_read_shadow
^ val
))
8009 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8015 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8016 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8019 case 1: /* mov from cr */
8022 if (vmcs12
->cpu_based_vm_exec_control
&
8023 CPU_BASED_CR3_STORE_EXITING
)
8027 if (vmcs12
->cpu_based_vm_exec_control
&
8028 CPU_BASED_CR8_STORE_EXITING
)
8035 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8036 * cr0. Other attempted changes are ignored, with no exit.
8038 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8039 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8040 (val
^ vmcs12
->cr0_read_shadow
))
8042 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8043 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8052 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8053 * should handle it ourselves in L0 (and then continue L2). Only call this
8054 * when in is_guest_mode (L2).
8056 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8058 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8059 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8060 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8062 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8063 vmcs_readl(EXIT_QUALIFICATION
),
8064 vmx
->idt_vectoring_info
,
8066 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8069 if (vmx
->nested
.nested_run_pending
)
8072 if (unlikely(vmx
->fail
)) {
8073 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8074 vmcs_read32(VM_INSTRUCTION_ERROR
));
8078 switch (exit_reason
) {
8079 case EXIT_REASON_EXCEPTION_NMI
:
8080 if (is_nmi(intr_info
))
8082 else if (is_page_fault(intr_info
))
8083 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8084 else if (is_no_device(intr_info
) &&
8085 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8087 else if (is_debug(intr_info
) &&
8089 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8091 else if (is_breakpoint(intr_info
) &&
8092 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8094 return vmcs12
->exception_bitmap
&
8095 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8096 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8098 case EXIT_REASON_TRIPLE_FAULT
:
8100 case EXIT_REASON_PENDING_INTERRUPT
:
8101 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8102 case EXIT_REASON_NMI_WINDOW
:
8103 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8104 case EXIT_REASON_TASK_SWITCH
:
8106 case EXIT_REASON_CPUID
:
8108 case EXIT_REASON_HLT
:
8109 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8110 case EXIT_REASON_INVD
:
8112 case EXIT_REASON_INVLPG
:
8113 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8114 case EXIT_REASON_RDPMC
:
8115 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8116 case EXIT_REASON_RDRAND
:
8117 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND
);
8118 case EXIT_REASON_RDSEED
:
8119 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED
);
8120 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8121 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8122 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8123 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8124 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8125 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8126 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8127 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8129 * VMX instructions trap unconditionally. This allows L1 to
8130 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8133 case EXIT_REASON_CR_ACCESS
:
8134 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8135 case EXIT_REASON_DR_ACCESS
:
8136 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8137 case EXIT_REASON_IO_INSTRUCTION
:
8138 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8139 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8140 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8141 case EXIT_REASON_MSR_READ
:
8142 case EXIT_REASON_MSR_WRITE
:
8143 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8144 case EXIT_REASON_INVALID_STATE
:
8146 case EXIT_REASON_MWAIT_INSTRUCTION
:
8147 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8148 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8149 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8150 case EXIT_REASON_MONITOR_INSTRUCTION
:
8151 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8152 case EXIT_REASON_PAUSE_INSTRUCTION
:
8153 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8154 nested_cpu_has2(vmcs12
,
8155 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8156 case EXIT_REASON_MCE_DURING_VMENTRY
:
8158 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8159 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8160 case EXIT_REASON_APIC_ACCESS
:
8161 return nested_cpu_has2(vmcs12
,
8162 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8163 case EXIT_REASON_APIC_WRITE
:
8164 case EXIT_REASON_EOI_INDUCED
:
8165 /* apic_write and eoi_induced should exit unconditionally. */
8167 case EXIT_REASON_EPT_VIOLATION
:
8169 * L0 always deals with the EPT violation. If nested EPT is
8170 * used, and the nested mmu code discovers that the address is
8171 * missing in the guest EPT table (EPT12), the EPT violation
8172 * will be injected with nested_ept_inject_page_fault()
8175 case EXIT_REASON_EPT_MISCONFIG
:
8177 * L2 never uses directly L1's EPT, but rather L0's own EPT
8178 * table (shadow on EPT) or a merged EPT table that L0 built
8179 * (EPT on EPT). So any problems with the structure of the
8180 * table is L0's fault.
8183 case EXIT_REASON_WBINVD
:
8184 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8185 case EXIT_REASON_XSETBV
:
8187 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8189 * This should never happen, since it is not possible to
8190 * set XSS to a non-zero value---neither in L1 nor in L2.
8191 * If if it were, XSS would have to be checked against
8192 * the XSS exit bitmap in vmcs12.
8194 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8195 case EXIT_REASON_PREEMPTION_TIMER
:
8197 case EXIT_REASON_PML_FULL
:
8198 /* We emulate PML support to L1. */
8205 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8207 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8210 * At this point, the exit interruption info in exit_intr_info
8211 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8212 * we need to query the in-kernel LAPIC.
8214 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8215 if ((exit_intr_info
&
8216 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8217 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8218 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8219 vmcs12
->vm_exit_intr_error_code
=
8220 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8223 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8224 vmcs_readl(EXIT_QUALIFICATION
));
8228 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8230 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8231 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8234 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8237 __free_page(vmx
->pml_pg
);
8242 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8244 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8248 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8250 /* Do nothing if PML buffer is empty */
8251 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8254 /* PML index always points to next available PML buffer entity */
8255 if (pml_idx
>= PML_ENTITY_NUM
)
8260 pml_buf
= page_address(vmx
->pml_pg
);
8261 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8264 gpa
= pml_buf
[pml_idx
];
8265 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8266 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8269 /* reset PML index */
8270 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8274 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8275 * Called before reporting dirty_bitmap to userspace.
8277 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8280 struct kvm_vcpu
*vcpu
;
8282 * We only need to kick vcpu out of guest mode here, as PML buffer
8283 * is flushed at beginning of all VMEXITs, and it's obvious that only
8284 * vcpus running in guest are possible to have unflushed GPAs in PML
8287 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8288 kvm_vcpu_kick(vcpu
);
8291 static void vmx_dump_sel(char *name
, uint32_t sel
)
8293 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8294 name
, vmcs_read16(sel
),
8295 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8296 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8297 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8300 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8302 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8303 name
, vmcs_read32(limit
),
8304 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8307 static void dump_vmcs(void)
8309 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8310 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8311 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8312 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8313 u32 secondary_exec_control
= 0;
8314 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8315 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8318 if (cpu_has_secondary_exec_ctrls())
8319 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8321 pr_err("*** Guest State ***\n");
8322 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8323 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8324 vmcs_readl(CR0_GUEST_HOST_MASK
));
8325 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8326 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8327 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8328 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8329 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8331 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8332 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8333 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8334 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8336 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8337 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8338 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8339 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8340 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8341 vmcs_readl(GUEST_SYSENTER_ESP
),
8342 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8343 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8344 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8345 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8346 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8347 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8348 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8349 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8350 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8351 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8352 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8353 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8354 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8355 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8356 efer
, vmcs_read64(GUEST_IA32_PAT
));
8357 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8358 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8359 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8360 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8361 pr_err("PerfGlobCtl = 0x%016llx\n",
8362 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8363 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8364 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8365 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8366 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8367 vmcs_read32(GUEST_ACTIVITY_STATE
));
8368 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8369 pr_err("InterruptStatus = %04x\n",
8370 vmcs_read16(GUEST_INTR_STATUS
));
8372 pr_err("*** Host State ***\n");
8373 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8374 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8375 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8376 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8377 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8378 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8379 vmcs_read16(HOST_TR_SELECTOR
));
8380 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8381 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8382 vmcs_readl(HOST_TR_BASE
));
8383 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8384 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8385 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8386 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8387 vmcs_readl(HOST_CR4
));
8388 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8389 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8390 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8391 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8392 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8393 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8394 vmcs_read64(HOST_IA32_EFER
),
8395 vmcs_read64(HOST_IA32_PAT
));
8396 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8397 pr_err("PerfGlobCtl = 0x%016llx\n",
8398 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8400 pr_err("*** Control State ***\n");
8401 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8402 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8403 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8404 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8405 vmcs_read32(EXCEPTION_BITMAP
),
8406 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8407 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8408 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8409 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8410 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8411 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8412 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8413 vmcs_read32(VM_EXIT_INTR_INFO
),
8414 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8415 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8416 pr_err(" reason=%08x qualification=%016lx\n",
8417 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8418 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8419 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8420 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8421 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8422 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8423 pr_err("TSC Multiplier = 0x%016llx\n",
8424 vmcs_read64(TSC_MULTIPLIER
));
8425 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8426 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8427 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8428 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8429 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8430 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8431 n
= vmcs_read32(CR3_TARGET_COUNT
);
8432 for (i
= 0; i
+ 1 < n
; i
+= 4)
8433 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8434 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8435 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8437 pr_err("CR3 target%u=%016lx\n",
8438 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8439 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8440 pr_err("PLE Gap=%08x Window=%08x\n",
8441 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8442 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8443 pr_err("Virtual processor ID = 0x%04x\n",
8444 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8448 * The guest has exited. See if we can fix it or if we need userspace
8451 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8453 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8454 u32 exit_reason
= vmx
->exit_reason
;
8455 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8457 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8458 vcpu
->arch
.gpa_available
= false;
8461 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8462 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8463 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8464 * mode as if vcpus is in root mode, the PML buffer must has been
8468 vmx_flush_pml_buffer(vcpu
);
8470 /* If guest state is invalid, start emulating */
8471 if (vmx
->emulation_required
)
8472 return handle_invalid_guest_state(vcpu
);
8474 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8475 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8477 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8479 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8480 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8485 if (unlikely(vmx
->fail
)) {
8486 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8487 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8488 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8494 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8495 * delivery event since it indicates guest is accessing MMIO.
8496 * The vm-exit can be triggered again after return to guest that
8497 * will cause infinite loop.
8499 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8500 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8501 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8502 exit_reason
!= EXIT_REASON_PML_FULL
&&
8503 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8504 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8505 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8506 vcpu
->run
->internal
.ndata
= 3;
8507 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8508 vcpu
->run
->internal
.data
[1] = exit_reason
;
8509 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8510 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8511 vcpu
->run
->internal
.ndata
++;
8512 vcpu
->run
->internal
.data
[3] =
8513 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8518 if (exit_reason
< kvm_vmx_max_exit_handlers
8519 && kvm_vmx_exit_handlers
[exit_reason
])
8520 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8522 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8524 kvm_queue_exception(vcpu
, UD_VECTOR
);
8529 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8531 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8533 if (is_guest_mode(vcpu
) &&
8534 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8537 if (irr
== -1 || tpr
< irr
) {
8538 vmcs_write32(TPR_THRESHOLD
, 0);
8542 vmcs_write32(TPR_THRESHOLD
, irr
);
8545 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8547 u32 sec_exec_control
;
8549 /* Postpone execution until vmcs01 is the current VMCS. */
8550 if (is_guest_mode(vcpu
)) {
8551 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8555 if (!cpu_has_vmx_virtualize_x2apic_mode())
8558 if (!cpu_need_tpr_shadow(vcpu
))
8561 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8564 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8565 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8567 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8568 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8569 vmx_flush_tlb_ept_only(vcpu
);
8571 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8573 vmx_set_msr_bitmap(vcpu
);
8576 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8578 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8581 * Currently we do not handle the nested case where L2 has an
8582 * APIC access page of its own; that page is still pinned.
8583 * Hence, we skip the case where the VCPU is in guest mode _and_
8584 * L1 prepared an APIC access page for L2.
8586 * For the case where L1 and L2 share the same APIC access page
8587 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8588 * in the vmcs12), this function will only update either the vmcs01
8589 * or the vmcs02. If the former, the vmcs02 will be updated by
8590 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8591 * the next L2->L1 exit.
8593 if (!is_guest_mode(vcpu
) ||
8594 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8595 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8596 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8597 vmx_flush_tlb_ept_only(vcpu
);
8601 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8609 status
= vmcs_read16(GUEST_INTR_STATUS
);
8611 if (max_isr
!= old
) {
8613 status
|= max_isr
<< 8;
8614 vmcs_write16(GUEST_INTR_STATUS
, status
);
8618 static void vmx_set_rvi(int vector
)
8626 status
= vmcs_read16(GUEST_INTR_STATUS
);
8627 old
= (u8
)status
& 0xff;
8628 if ((u8
)vector
!= old
) {
8630 status
|= (u8
)vector
;
8631 vmcs_write16(GUEST_INTR_STATUS
, status
);
8635 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8637 if (!is_guest_mode(vcpu
)) {
8638 vmx_set_rvi(max_irr
);
8646 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8649 if (nested_exit_on_intr(vcpu
))
8653 * Else, fall back to pre-APICv interrupt injection since L2
8654 * is run without virtual interrupt delivery.
8656 if (!kvm_event_needs_reinjection(vcpu
) &&
8657 vmx_interrupt_allowed(vcpu
)) {
8658 kvm_queue_interrupt(vcpu
, max_irr
, false);
8659 vmx_inject_irq(vcpu
);
8663 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8665 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8668 WARN_ON(!vcpu
->arch
.apicv_active
);
8669 if (pi_test_on(&vmx
->pi_desc
)) {
8670 pi_clear_on(&vmx
->pi_desc
);
8672 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8673 * But on x86 this is just a compiler barrier anyway.
8675 smp_mb__after_atomic();
8676 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8678 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8680 vmx_hwapic_irr_update(vcpu
, max_irr
);
8684 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8686 if (!kvm_vcpu_apicv_active(vcpu
))
8689 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8690 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8691 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8692 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8695 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
8697 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8699 pi_clear_on(&vmx
->pi_desc
);
8700 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
8703 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8705 u32 exit_intr_info
= 0;
8706 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
8708 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8709 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8712 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
8713 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8714 vmx
->exit_intr_info
= exit_intr_info
;
8716 /* if exit due to PF check for async PF */
8717 if (is_page_fault(exit_intr_info
))
8718 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
8720 /* Handle machine checks before interrupts are enabled */
8721 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
8722 is_machine_check(exit_intr_info
))
8723 kvm_machine_check();
8725 /* We need to handle NMIs before interrupts are enabled */
8726 if (is_nmi(exit_intr_info
)) {
8727 kvm_before_handle_nmi(&vmx
->vcpu
);
8729 kvm_after_handle_nmi(&vmx
->vcpu
);
8733 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8735 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8736 register void *__sp
asm(_ASM_SP
);
8738 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8739 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8740 unsigned int vector
;
8741 unsigned long entry
;
8743 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8744 #ifdef CONFIG_X86_64
8748 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8749 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8750 entry
= gate_offset(*desc
);
8752 #ifdef CONFIG_X86_64
8753 "mov %%" _ASM_SP
", %[sp]\n\t"
8754 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8759 __ASM_SIZE(push
) " $%c[cs]\n\t"
8760 "call *%[entry]\n\t"
8762 #ifdef CONFIG_X86_64
8768 [ss
]"i"(__KERNEL_DS
),
8769 [cs
]"i"(__KERNEL_CS
)
8773 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
8775 static bool vmx_has_high_real_mode_segbase(void)
8777 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8780 static bool vmx_mpx_supported(void)
8782 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8783 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8786 static bool vmx_xsaves_supported(void)
8788 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8789 SECONDARY_EXEC_XSAVES
;
8792 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8797 bool idtv_info_valid
;
8799 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8801 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
8804 * Can't use vmx->exit_intr_info since we're not sure what
8805 * the exit reason is.
8807 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8808 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8809 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8811 * SDM 3: 27.7.1.2 (September 2008)
8812 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8813 * a guest IRET fault.
8814 * SDM 3: 23.2.2 (September 2008)
8815 * Bit 12 is undefined in any of the following cases:
8816 * If the VM exit sets the valid bit in the IDT-vectoring
8817 * information field.
8818 * If the VM exit is due to a double fault.
8820 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8821 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8822 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8823 GUEST_INTR_STATE_NMI
);
8825 vmx
->loaded_vmcs
->nmi_known_unmasked
=
8826 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8827 & GUEST_INTR_STATE_NMI
);
8830 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8831 u32 idt_vectoring_info
,
8832 int instr_len_field
,
8833 int error_code_field
)
8837 bool idtv_info_valid
;
8839 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8841 vcpu
->arch
.nmi_injected
= false;
8842 kvm_clear_exception_queue(vcpu
);
8843 kvm_clear_interrupt_queue(vcpu
);
8845 if (!idtv_info_valid
)
8848 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8850 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8851 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8854 case INTR_TYPE_NMI_INTR
:
8855 vcpu
->arch
.nmi_injected
= true;
8857 * SDM 3: 27.7.1.2 (September 2008)
8858 * Clear bit "block by NMI" before VM entry if a NMI
8861 vmx_set_nmi_mask(vcpu
, false);
8863 case INTR_TYPE_SOFT_EXCEPTION
:
8864 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8866 case INTR_TYPE_HARD_EXCEPTION
:
8867 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8868 u32 err
= vmcs_read32(error_code_field
);
8869 kvm_requeue_exception_e(vcpu
, vector
, err
);
8871 kvm_requeue_exception(vcpu
, vector
);
8873 case INTR_TYPE_SOFT_INTR
:
8874 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8876 case INTR_TYPE_EXT_INTR
:
8877 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8884 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8886 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8887 VM_EXIT_INSTRUCTION_LEN
,
8888 IDT_VECTORING_ERROR_CODE
);
8891 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8893 __vmx_complete_interrupts(vcpu
,
8894 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8895 VM_ENTRY_INSTRUCTION_LEN
,
8896 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8898 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8901 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8904 struct perf_guest_switch_msr
*msrs
;
8906 msrs
= perf_guest_get_msrs(&nr_msrs
);
8911 for (i
= 0; i
< nr_msrs
; i
++)
8912 if (msrs
[i
].host
== msrs
[i
].guest
)
8913 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8915 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8919 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8921 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8925 if (vmx
->hv_deadline_tsc
== -1)
8929 if (vmx
->hv_deadline_tsc
> tscl
)
8930 /* sure to be 32 bit only because checked on set_hv_timer */
8931 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8932 cpu_preemption_timer_multi
);
8936 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8939 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8941 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8942 unsigned long debugctlmsr
, cr3
, cr4
;
8944 /* Don't enter VMX if guest state is invalid, let the exit handler
8945 start emulation until we arrive back to a valid state */
8946 if (vmx
->emulation_required
)
8949 if (vmx
->ple_window_dirty
) {
8950 vmx
->ple_window_dirty
= false;
8951 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8954 if (vmx
->nested
.sync_shadow_vmcs
) {
8955 copy_vmcs12_to_shadow(vmx
);
8956 vmx
->nested
.sync_shadow_vmcs
= false;
8959 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8960 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8961 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8962 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8964 cr3
= __get_current_cr3_fast();
8965 if (unlikely(cr3
!= vmx
->host_state
.vmcs_host_cr3
)) {
8966 vmcs_writel(HOST_CR3
, cr3
);
8967 vmx
->host_state
.vmcs_host_cr3
= cr3
;
8970 cr4
= cr4_read_shadow();
8971 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8972 vmcs_writel(HOST_CR4
, cr4
);
8973 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8976 /* When single-stepping over STI and MOV SS, we must clear the
8977 * corresponding interruptibility bits in the guest state. Otherwise
8978 * vmentry fails as it then expects bit 14 (BS) in pending debug
8979 * exceptions being set, but that's not correct for the guest debugging
8981 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8982 vmx_set_interrupt_shadow(vcpu
, 0);
8984 if (vmx
->guest_pkru_valid
)
8985 __write_pkru(vmx
->guest_pkru
);
8987 atomic_switch_perf_msrs(vmx
);
8988 debugctlmsr
= get_debugctlmsr();
8990 vmx_arm_hv_timer(vcpu
);
8992 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8994 /* Store host registers */
8995 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8996 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8997 "push %%" _ASM_CX
" \n\t"
8998 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9000 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9001 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9003 /* Reload cr2 if changed */
9004 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9005 "mov %%cr2, %%" _ASM_DX
" \n\t"
9006 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9008 "mov %%" _ASM_AX
", %%cr2 \n\t"
9010 /* Check if vmlaunch of vmresume is needed */
9011 "cmpl $0, %c[launched](%0) \n\t"
9012 /* Load guest registers. Don't clobber flags. */
9013 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9014 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9015 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9016 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9017 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9018 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9019 #ifdef CONFIG_X86_64
9020 "mov %c[r8](%0), %%r8 \n\t"
9021 "mov %c[r9](%0), %%r9 \n\t"
9022 "mov %c[r10](%0), %%r10 \n\t"
9023 "mov %c[r11](%0), %%r11 \n\t"
9024 "mov %c[r12](%0), %%r12 \n\t"
9025 "mov %c[r13](%0), %%r13 \n\t"
9026 "mov %c[r14](%0), %%r14 \n\t"
9027 "mov %c[r15](%0), %%r15 \n\t"
9029 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9031 /* Enter guest mode */
9033 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9035 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9037 /* Save guest registers, load host registers, keep flags */
9038 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9040 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9041 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9042 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9043 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9044 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9045 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9046 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9047 #ifdef CONFIG_X86_64
9048 "mov %%r8, %c[r8](%0) \n\t"
9049 "mov %%r9, %c[r9](%0) \n\t"
9050 "mov %%r10, %c[r10](%0) \n\t"
9051 "mov %%r11, %c[r11](%0) \n\t"
9052 "mov %%r12, %c[r12](%0) \n\t"
9053 "mov %%r13, %c[r13](%0) \n\t"
9054 "mov %%r14, %c[r14](%0) \n\t"
9055 "mov %%r15, %c[r15](%0) \n\t"
9057 "mov %%cr2, %%" _ASM_AX
" \n\t"
9058 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9060 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9061 "setbe %c[fail](%0) \n\t"
9062 ".pushsection .rodata \n\t"
9063 ".global vmx_return \n\t"
9064 "vmx_return: " _ASM_PTR
" 2b \n\t"
9066 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9067 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9068 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9069 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9070 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9071 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9072 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9073 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9074 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9075 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9076 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9077 #ifdef CONFIG_X86_64
9078 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9079 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9080 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9081 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9082 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9083 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9084 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9085 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9087 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9088 [wordsize
]"i"(sizeof(ulong
))
9090 #ifdef CONFIG_X86_64
9091 , "rax", "rbx", "rdi", "rsi"
9092 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9094 , "eax", "ebx", "edi", "esi"
9098 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9100 update_debugctlmsr(debugctlmsr
);
9102 #ifndef CONFIG_X86_64
9104 * The sysexit path does not restore ds/es, so we must set them to
9105 * a reasonable value ourselves.
9107 * We can't defer this to vmx_load_host_state() since that function
9108 * may be executed in interrupt context, which saves and restore segments
9109 * around it, nullifying its effect.
9111 loadsegment(ds
, __USER_DS
);
9112 loadsegment(es
, __USER_DS
);
9115 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9116 | (1 << VCPU_EXREG_RFLAGS
)
9117 | (1 << VCPU_EXREG_PDPTR
)
9118 | (1 << VCPU_EXREG_SEGMENTS
)
9119 | (1 << VCPU_EXREG_CR3
));
9120 vcpu
->arch
.regs_dirty
= 0;
9122 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9124 vmx
->loaded_vmcs
->launched
= 1;
9126 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
9129 * eager fpu is enabled if PKEY is supported and CR4 is switched
9130 * back on host, so it is safe to read guest PKRU from current
9133 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
9134 vmx
->guest_pkru
= __read_pkru();
9135 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
9136 vmx
->guest_pkru_valid
= true;
9137 __write_pkru(vmx
->host_pkru
);
9139 vmx
->guest_pkru_valid
= false;
9143 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9144 * we did not inject a still-pending event to L1 now because of
9145 * nested_run_pending, we need to re-enable this bit.
9147 if (vmx
->nested
.nested_run_pending
)
9148 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9150 vmx
->nested
.nested_run_pending
= 0;
9152 vmx_complete_atomic_exit(vmx
);
9153 vmx_recover_nmi_blocking(vmx
);
9154 vmx_complete_interrupts(vmx
);
9156 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9158 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9160 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9163 if (vmx
->loaded_vmcs
== vmcs
)
9167 vmx
->loaded_vmcs
= vmcs
;
9169 vmx_vcpu_load(vcpu
, cpu
);
9175 * Ensure that the current vmcs of the logical processor is the
9176 * vmcs01 of the vcpu before calling free_nested().
9178 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9180 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9183 r
= vcpu_load(vcpu
);
9185 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9190 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9192 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9195 vmx_destroy_pml_buffer(vmx
);
9196 free_vpid(vmx
->vpid
);
9197 leave_guest_mode(vcpu
);
9198 vmx_free_vcpu_nested(vcpu
);
9199 free_loaded_vmcs(vmx
->loaded_vmcs
);
9200 kfree(vmx
->guest_msrs
);
9201 kvm_vcpu_uninit(vcpu
);
9202 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9205 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9208 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9212 return ERR_PTR(-ENOMEM
);
9214 vmx
->vpid
= allocate_vpid();
9216 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9223 * If PML is turned on, failure on enabling PML just results in failure
9224 * of creating the vcpu, therefore we can simplify PML logic (by
9225 * avoiding dealing with cases, such as enabling PML partially on vcpus
9226 * for the guest, etc.
9229 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9234 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9235 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9238 if (!vmx
->guest_msrs
)
9241 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9242 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9243 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9244 if (!vmx
->loaded_vmcs
->vmcs
)
9246 loaded_vmcs_init(vmx
->loaded_vmcs
);
9249 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9250 vmx
->vcpu
.cpu
= cpu
;
9251 err
= vmx_vcpu_setup(vmx
);
9252 vmx_vcpu_put(&vmx
->vcpu
);
9256 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9257 err
= alloc_apic_access_page(kvm
);
9263 if (!kvm
->arch
.ept_identity_map_addr
)
9264 kvm
->arch
.ept_identity_map_addr
=
9265 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9266 err
= init_rmode_identity_map(kvm
);
9272 nested_vmx_setup_ctls_msrs(vmx
);
9273 vmx
->nested
.vpid02
= allocate_vpid();
9276 vmx
->nested
.posted_intr_nv
= -1;
9277 vmx
->nested
.current_vmptr
= -1ull;
9279 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9284 free_vpid(vmx
->nested
.vpid02
);
9285 free_loaded_vmcs(vmx
->loaded_vmcs
);
9287 kfree(vmx
->guest_msrs
);
9289 vmx_destroy_pml_buffer(vmx
);
9291 kvm_vcpu_uninit(&vmx
->vcpu
);
9293 free_vpid(vmx
->vpid
);
9294 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9295 return ERR_PTR(err
);
9298 static void __init
vmx_check_processor_compat(void *rtn
)
9300 struct vmcs_config vmcs_conf
;
9303 if (setup_vmcs_config(&vmcs_conf
) < 0)
9305 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9306 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9307 smp_processor_id());
9312 static int get_ept_level(void)
9314 return VMX_EPT_DEFAULT_GAW
+ 1;
9317 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9322 /* For VT-d and EPT combination
9323 * 1. MMIO: always map as UC
9325 * a. VT-d without snooping control feature: can't guarantee the
9326 * result, try to trust guest.
9327 * b. VT-d with snooping control feature: snooping control feature of
9328 * VT-d engine can guarantee the cache correctness. Just set it
9329 * to WB to keep consistent with host. So the same as item 3.
9330 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9331 * consistent with host MTRR
9334 cache
= MTRR_TYPE_UNCACHABLE
;
9338 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9339 ipat
= VMX_EPT_IPAT_BIT
;
9340 cache
= MTRR_TYPE_WRBACK
;
9344 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9345 ipat
= VMX_EPT_IPAT_BIT
;
9346 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9347 cache
= MTRR_TYPE_WRBACK
;
9349 cache
= MTRR_TYPE_UNCACHABLE
;
9353 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9356 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9359 static int vmx_get_lpage_level(void)
9361 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9362 return PT_DIRECTORY_LEVEL
;
9364 /* For shadow and EPT supported 1GB page */
9365 return PT_PDPE_LEVEL
;
9368 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9371 * These bits in the secondary execution controls field
9372 * are dynamic, the others are mostly based on the hypervisor
9373 * architecture and the guest's CPUID. Do not touch the
9377 SECONDARY_EXEC_SHADOW_VMCS
|
9378 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9379 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9381 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9383 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9384 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9388 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9389 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9391 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9393 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9394 struct kvm_cpuid_entry2
*entry
;
9396 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9397 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9399 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9400 if (entry && (entry->_reg & (_cpuid_mask))) \
9401 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9404 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9405 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9406 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9407 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9408 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9409 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9410 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9411 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9412 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9413 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9414 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9415 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9416 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9417 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9418 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9420 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9421 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9422 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9423 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9424 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9425 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9426 cr4_fixed1_update(bit(11), ecx
, bit(2));
9428 #undef cr4_fixed1_update
9431 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9433 struct kvm_cpuid_entry2
*best
;
9434 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9435 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9437 if (vmx_rdtscp_supported()) {
9438 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9439 if (!rdtscp_enabled
)
9440 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9444 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9445 SECONDARY_EXEC_RDTSCP
;
9447 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9448 ~SECONDARY_EXEC_RDTSCP
;
9452 /* Exposing INVPCID only when PCID is exposed */
9453 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9454 if (vmx_invpcid_supported() &&
9455 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9456 !guest_cpuid_has_pcid(vcpu
))) {
9457 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9460 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9463 if (cpu_has_secondary_exec_ctrls())
9464 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9466 if (nested_vmx_allowed(vcpu
))
9467 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9468 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9470 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9471 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9473 if (nested_vmx_allowed(vcpu
))
9474 nested_vmx_cr_fixed1_bits_update(vcpu
);
9477 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9479 if (func
== 1 && nested
)
9480 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9483 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9484 struct x86_exception
*fault
)
9486 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9487 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9489 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9491 if (vmx
->nested
.pml_full
) {
9492 exit_reason
= EXIT_REASON_PML_FULL
;
9493 vmx
->nested
.pml_full
= false;
9494 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9495 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9496 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9498 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9500 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9501 vmcs12
->guest_physical_address
= fault
->address
;
9504 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9506 return nested_ept_get_cr3(vcpu
) & VMX_EPT_AD_ENABLE_BIT
;
9509 /* Callbacks for nested_ept_init_mmu_context: */
9511 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9513 /* return the page table to be shadowed - in our case, EPT12 */
9514 return get_vmcs12(vcpu
)->ept_pointer
;
9517 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9521 WARN_ON(mmu_is_nested(vcpu
));
9522 wants_ad
= nested_ept_ad_enabled(vcpu
);
9523 if (wants_ad
&& !enable_ept_ad_bits
)
9526 kvm_mmu_unload(vcpu
);
9527 kvm_init_shadow_ept_mmu(vcpu
,
9528 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9529 VMX_EPT_EXECUTE_ONLY_BIT
,
9531 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9532 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9533 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9535 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9539 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9541 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9544 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9547 bool inequality
, bit
;
9549 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9551 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9552 vmcs12
->page_fault_error_code_match
;
9553 return inequality
^ bit
;
9556 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9557 struct x86_exception
*fault
)
9559 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9561 WARN_ON(!is_guest_mode(vcpu
));
9563 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
)) {
9564 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9565 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9566 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9567 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9570 kvm_inject_page_fault(vcpu
, fault
);
9574 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9575 struct vmcs12
*vmcs12
);
9577 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9578 struct vmcs12
*vmcs12
)
9580 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9583 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9585 * Translate L1 physical address to host physical
9586 * address for vmcs02. Keep the page pinned, so this
9587 * physical address remains valid. We keep a reference
9588 * to it so we can release it later.
9590 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9591 nested_release_page(vmx
->nested
.apic_access_page
);
9592 vmx
->nested
.apic_access_page
=
9593 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9595 * If translation failed, no matter: This feature asks
9596 * to exit when accessing the given address, and if it
9597 * can never be accessed, this feature won't do
9600 if (vmx
->nested
.apic_access_page
) {
9601 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9602 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9604 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9605 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9607 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9608 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9609 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9610 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9611 kvm_vcpu_reload_apic_access_page(vcpu
);
9614 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9615 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9616 nested_release_page(vmx
->nested
.virtual_apic_page
);
9617 vmx
->nested
.virtual_apic_page
=
9618 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9621 * If translation failed, VM entry will fail because
9622 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9623 * Failing the vm entry is _not_ what the processor
9624 * does but it's basically the only possibility we
9625 * have. We could still enter the guest if CR8 load
9626 * exits are enabled, CR8 store exits are enabled, and
9627 * virtualize APIC access is disabled; in this case
9628 * the processor would never use the TPR shadow and we
9629 * could simply clear the bit from the execution
9630 * control. But such a configuration is useless, so
9631 * let's keep the code simple.
9633 if (vmx
->nested
.virtual_apic_page
) {
9634 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9635 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9639 if (nested_cpu_has_posted_intr(vmcs12
)) {
9640 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9641 kunmap(vmx
->nested
.pi_desc_page
);
9642 nested_release_page(vmx
->nested
.pi_desc_page
);
9644 vmx
->nested
.pi_desc_page
=
9645 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9646 vmx
->nested
.pi_desc
=
9647 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9648 if (!vmx
->nested
.pi_desc
) {
9649 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9652 vmx
->nested
.pi_desc
=
9653 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9654 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9656 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9657 page_to_phys(vmx
->nested
.pi_desc_page
) +
9658 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9661 if (cpu_has_vmx_msr_bitmap() &&
9662 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9663 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9666 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9667 CPU_BASED_USE_MSR_BITMAPS
);
9670 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9672 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9673 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9675 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9678 /* Make sure short timeouts reliably trigger an immediate vmexit.
9679 * hrtimer_start does not guarantee this. */
9680 if (preemption_timeout
<= 1) {
9681 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9685 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9686 preemption_timeout
*= 1000000;
9687 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9688 hrtimer_start(&vmx
->nested
.preemption_timer
,
9689 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9692 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
9693 struct vmcs12
*vmcs12
)
9695 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
9698 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
9699 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
9705 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9706 struct vmcs12
*vmcs12
)
9708 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9711 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
9718 * Merge L0's and L1's MSR bitmap, return false to indicate that
9719 * we do not use the hardware.
9721 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9722 struct vmcs12
*vmcs12
)
9726 unsigned long *msr_bitmap_l1
;
9727 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
9729 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9730 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9733 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9736 msr_bitmap_l1
= (unsigned long *)kmap(page
);
9738 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
9740 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9741 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9742 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9743 nested_vmx_disable_intercept_for_msr(
9744 msr_bitmap_l1
, msr_bitmap_l0
,
9747 nested_vmx_disable_intercept_for_msr(
9748 msr_bitmap_l1
, msr_bitmap_l0
,
9749 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9750 MSR_TYPE_R
| MSR_TYPE_W
);
9752 if (nested_cpu_has_vid(vmcs12
)) {
9753 nested_vmx_disable_intercept_for_msr(
9754 msr_bitmap_l1
, msr_bitmap_l0
,
9755 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9757 nested_vmx_disable_intercept_for_msr(
9758 msr_bitmap_l1
, msr_bitmap_l0
,
9759 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9764 nested_release_page_clean(page
);
9769 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9770 struct vmcs12
*vmcs12
)
9772 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9773 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9774 !nested_cpu_has_vid(vmcs12
) &&
9775 !nested_cpu_has_posted_intr(vmcs12
))
9779 * If virtualize x2apic mode is enabled,
9780 * virtualize apic access must be disabled.
9782 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9783 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9787 * If virtual interrupt delivery is enabled,
9788 * we must exit on external interrupts.
9790 if (nested_cpu_has_vid(vmcs12
) &&
9791 !nested_exit_on_intr(vcpu
))
9795 * bits 15:8 should be zero in posted_intr_nv,
9796 * the descriptor address has been already checked
9797 * in nested_get_vmcs12_pages.
9799 if (nested_cpu_has_posted_intr(vmcs12
) &&
9800 (!nested_cpu_has_vid(vmcs12
) ||
9801 !nested_exit_intr_ack_set(vcpu
) ||
9802 vmcs12
->posted_intr_nv
& 0xff00))
9805 /* tpr shadow is needed by all apicv features. */
9806 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9812 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9813 unsigned long count_field
,
9814 unsigned long addr_field
)
9819 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9820 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9826 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9827 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9828 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9829 pr_debug_ratelimited(
9830 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9831 addr_field
, maxphyaddr
, count
, addr
);
9837 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9838 struct vmcs12
*vmcs12
)
9840 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9841 vmcs12
->vm_exit_msr_store_count
== 0 &&
9842 vmcs12
->vm_entry_msr_load_count
== 0)
9843 return 0; /* Fast path */
9844 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9845 VM_EXIT_MSR_LOAD_ADDR
) ||
9846 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9847 VM_EXIT_MSR_STORE_ADDR
) ||
9848 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9849 VM_ENTRY_MSR_LOAD_ADDR
))
9854 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
9855 struct vmcs12
*vmcs12
)
9857 u64 address
= vmcs12
->pml_address
;
9858 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9860 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
9861 if (!nested_cpu_has_ept(vmcs12
) ||
9862 !IS_ALIGNED(address
, 4096) ||
9863 address
>> maxphyaddr
)
9870 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9871 struct vmx_msr_entry
*e
)
9873 /* x2APIC MSR accesses are not allowed */
9874 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9876 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9877 e
->index
== MSR_IA32_UCODE_REV
)
9879 if (e
->reserved
!= 0)
9884 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9885 struct vmx_msr_entry
*e
)
9887 if (e
->index
== MSR_FS_BASE
||
9888 e
->index
== MSR_GS_BASE
||
9889 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9890 nested_vmx_msr_check_common(vcpu
, e
))
9895 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9896 struct vmx_msr_entry
*e
)
9898 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9899 nested_vmx_msr_check_common(vcpu
, e
))
9905 * Load guest's/host's msr at nested entry/exit.
9906 * return 0 for success, entry index for failure.
9908 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9911 struct vmx_msr_entry e
;
9912 struct msr_data msr
;
9914 msr
.host_initiated
= false;
9915 for (i
= 0; i
< count
; i
++) {
9916 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9918 pr_debug_ratelimited(
9919 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9920 __func__
, i
, gpa
+ i
* sizeof(e
));
9923 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9924 pr_debug_ratelimited(
9925 "%s check failed (%u, 0x%x, 0x%x)\n",
9926 __func__
, i
, e
.index
, e
.reserved
);
9929 msr
.index
= e
.index
;
9931 if (kvm_set_msr(vcpu
, &msr
)) {
9932 pr_debug_ratelimited(
9933 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9934 __func__
, i
, e
.index
, e
.value
);
9943 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9946 struct vmx_msr_entry e
;
9948 for (i
= 0; i
< count
; i
++) {
9949 struct msr_data msr_info
;
9950 if (kvm_vcpu_read_guest(vcpu
,
9951 gpa
+ i
* sizeof(e
),
9952 &e
, 2 * sizeof(u32
))) {
9953 pr_debug_ratelimited(
9954 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9955 __func__
, i
, gpa
+ i
* sizeof(e
));
9958 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9959 pr_debug_ratelimited(
9960 "%s check failed (%u, 0x%x, 0x%x)\n",
9961 __func__
, i
, e
.index
, e
.reserved
);
9964 msr_info
.host_initiated
= false;
9965 msr_info
.index
= e
.index
;
9966 if (kvm_get_msr(vcpu
, &msr_info
)) {
9967 pr_debug_ratelimited(
9968 "%s cannot read MSR (%u, 0x%x)\n",
9969 __func__
, i
, e
.index
);
9972 if (kvm_vcpu_write_guest(vcpu
,
9973 gpa
+ i
* sizeof(e
) +
9974 offsetof(struct vmx_msr_entry
, value
),
9975 &msr_info
.data
, sizeof(msr_info
.data
))) {
9976 pr_debug_ratelimited(
9977 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9978 __func__
, i
, e
.index
, msr_info
.data
);
9985 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
9987 unsigned long invalid_mask
;
9989 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
9990 return (val
& invalid_mask
) == 0;
9994 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9995 * emulating VM entry into a guest with EPT enabled.
9996 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9997 * is assigned to entry_failure_code on failure.
9999 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10000 u32
*entry_failure_code
)
10002 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10003 if (!nested_cr3_valid(vcpu
, cr3
)) {
10004 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10009 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10010 * must not be dereferenced.
10012 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10014 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10015 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10020 vcpu
->arch
.cr3
= cr3
;
10021 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10024 kvm_mmu_reset_context(vcpu
);
10029 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10030 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10031 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10032 * guest in a way that will both be appropriate to L1's requests, and our
10033 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10034 * function also has additional necessary side-effects, like setting various
10035 * vcpu->arch fields.
10036 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10037 * is assigned to entry_failure_code on failure.
10039 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10040 bool from_vmentry
, u32
*entry_failure_code
)
10042 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10043 u32 exec_control
, vmcs12_exec_ctrl
;
10045 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10046 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10047 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10048 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10049 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10050 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10051 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10052 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10053 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10054 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10055 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10056 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10057 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10058 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10059 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10060 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10061 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10062 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10063 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10064 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10065 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10066 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10067 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10068 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10069 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10070 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10071 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10072 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10073 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10074 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10075 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10076 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10077 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10078 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10079 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10080 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10082 if (from_vmentry
&&
10083 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10084 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10085 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10087 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10088 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10090 if (from_vmentry
) {
10091 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10092 vmcs12
->vm_entry_intr_info_field
);
10093 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10094 vmcs12
->vm_entry_exception_error_code
);
10095 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10096 vmcs12
->vm_entry_instruction_len
);
10097 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10098 vmcs12
->guest_interruptibility_info
);
10099 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10100 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10102 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10104 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10105 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10106 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10107 vmcs12
->guest_pending_dbg_exceptions
);
10108 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10109 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10111 if (nested_cpu_has_xsaves(vmcs12
))
10112 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10113 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10115 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10117 /* Preemption timer setting is only taken from vmcs01. */
10118 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10119 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10120 if (vmx
->hv_deadline_tsc
== -1)
10121 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10123 /* Posted interrupts setting is only taken from vmcs12. */
10124 if (nested_cpu_has_posted_intr(vmcs12
)) {
10125 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10126 vmx
->nested
.pi_pending
= false;
10127 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10129 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10132 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10134 vmx
->nested
.preemption_timer_expired
= false;
10135 if (nested_cpu_has_preemption_timer(vmcs12
))
10136 vmx_start_preemption_timer(vcpu
);
10139 * Whether page-faults are trapped is determined by a combination of
10140 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10141 * If enable_ept, L0 doesn't care about page faults and we should
10142 * set all of these to L1's desires. However, if !enable_ept, L0 does
10143 * care about (at least some) page faults, and because it is not easy
10144 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10145 * to exit on each and every L2 page fault. This is done by setting
10146 * MASK=MATCH=0 and (see below) EB.PF=1.
10147 * Note that below we don't need special code to set EB.PF beyond the
10148 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10149 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10150 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10152 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10153 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10154 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10155 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10157 if (cpu_has_secondary_exec_ctrls()) {
10158 exec_control
= vmx_secondary_exec_control(vmx
);
10160 /* Take the following fields only from vmcs12 */
10161 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10162 SECONDARY_EXEC_RDTSCP
|
10163 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10164 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
10165 if (nested_cpu_has(vmcs12
,
10166 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10167 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10168 ~SECONDARY_EXEC_ENABLE_PML
;
10169 exec_control
|= vmcs12_exec_ctrl
;
10172 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10173 vmcs_write64(EOI_EXIT_BITMAP0
,
10174 vmcs12
->eoi_exit_bitmap0
);
10175 vmcs_write64(EOI_EXIT_BITMAP1
,
10176 vmcs12
->eoi_exit_bitmap1
);
10177 vmcs_write64(EOI_EXIT_BITMAP2
,
10178 vmcs12
->eoi_exit_bitmap2
);
10179 vmcs_write64(EOI_EXIT_BITMAP3
,
10180 vmcs12
->eoi_exit_bitmap3
);
10181 vmcs_write16(GUEST_INTR_STATUS
,
10182 vmcs12
->guest_intr_status
);
10186 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10187 * nested_get_vmcs12_pages will either fix it up or
10188 * remove the VM execution control.
10190 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10191 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10193 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10198 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10199 * Some constant fields are set here by vmx_set_constant_host_state().
10200 * Other fields are different per CPU, and will be set later when
10201 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10203 vmx_set_constant_host_state(vmx
);
10206 * Set the MSR load/store lists to match L0's settings.
10208 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10209 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10210 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10211 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10212 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10215 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10216 * entry, but only if the current (host) sp changed from the value
10217 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10218 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10219 * here we just force the write to happen on entry.
10223 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10224 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10225 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10226 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10227 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10230 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10231 * nested_get_vmcs12_pages can't fix it up, the illegal value
10232 * will result in a VM entry failure.
10234 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10235 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10236 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10240 * Merging of IO bitmap not currently supported.
10241 * Rather, exit every time.
10243 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10244 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10246 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10248 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10249 * bitwise-or of what L1 wants to trap for L2, and what we want to
10250 * trap. Note that CR0.TS also needs updating - we do this later.
10252 update_exception_bitmap(vcpu
);
10253 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10254 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10256 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10257 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10258 * bits are further modified by vmx_set_efer() below.
10260 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10262 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10263 * emulated by vmx_set_efer(), below.
10265 vm_entry_controls_init(vmx
,
10266 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10267 ~VM_ENTRY_IA32E_MODE
) |
10268 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10270 if (from_vmentry
&&
10271 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10272 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10273 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10274 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10275 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10278 set_cr4_guest_host_mask(vmx
);
10280 if (from_vmentry
&&
10281 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10282 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10284 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10285 vmcs_write64(TSC_OFFSET
,
10286 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10288 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10289 if (kvm_has_tsc_control
)
10290 decache_tsc_multiplier(vmx
);
10294 * There is no direct mapping between vpid02 and vpid12, the
10295 * vpid02 is per-vCPU for L0 and reused while the value of
10296 * vpid12 is changed w/ one invvpid during nested vmentry.
10297 * The vpid12 is allocated by L1 for L2, so it will not
10298 * influence global bitmap(for vpid01 and vpid02 allocation)
10299 * even if spawn a lot of nested vCPUs.
10301 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10302 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10303 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10304 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10305 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10308 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10309 vmx_flush_tlb(vcpu
);
10316 * Conceptually we want to copy the PML address and index from
10317 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10318 * since we always flush the log on each vmexit, this happens
10319 * to be equivalent to simply resetting the fields in vmcs02.
10321 ASSERT(vmx
->pml_pg
);
10322 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10323 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10326 if (nested_cpu_has_ept(vmcs12
)) {
10327 if (nested_ept_init_mmu_context(vcpu
)) {
10328 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10331 } else if (nested_cpu_has2(vmcs12
,
10332 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10333 vmx_flush_tlb_ept_only(vcpu
);
10337 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10338 * bits which we consider mandatory enabled.
10339 * The CR0_READ_SHADOW is what L2 should have expected to read given
10340 * the specifications by L1; It's not enough to take
10341 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10342 * have more bits than L1 expected.
10344 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10345 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10347 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10348 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10350 if (from_vmentry
&&
10351 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10352 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10353 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10354 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10356 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10357 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10358 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10360 /* Shadow page tables on either EPT or shadow page tables. */
10361 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10362 entry_failure_code
))
10366 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10369 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10372 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10373 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10374 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10375 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10378 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10379 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10383 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10385 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10387 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10388 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10389 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10391 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10392 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10394 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10395 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10397 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10398 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10400 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10401 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10403 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10404 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10406 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10407 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10408 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10409 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10410 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10411 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10412 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10413 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10414 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10415 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10416 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10417 vmx
->nested
.nested_vmx_exit_ctls_low
,
10418 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10419 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10420 vmx
->nested
.nested_vmx_entry_ctls_low
,
10421 vmx
->nested
.nested_vmx_entry_ctls_high
))
10422 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10424 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10425 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10427 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10428 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10429 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10430 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10435 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10440 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10442 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10443 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10446 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10447 vmcs12
->vmcs_link_pointer
!= -1ull) {
10448 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10453 * If the load IA32_EFER VM-entry control is 1, the following checks
10454 * are performed on the field for the IA32_EFER MSR:
10455 * - Bits reserved in the IA32_EFER MSR must be 0.
10456 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10457 * the IA-32e mode guest VM-exit control. It must also be identical
10458 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10461 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10462 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10463 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10464 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10465 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10466 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10467 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10472 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10473 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10474 * the values of the LMA and LME bits in the field must each be that of
10475 * the host address-space size VM-exit control.
10477 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10478 ia32e
= (vmcs12
->vm_exit_controls
&
10479 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10480 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10481 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10482 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10489 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10491 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10492 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10493 struct loaded_vmcs
*vmcs02
;
10497 vmcs02
= nested_get_current_vmcs02(vmx
);
10501 enter_guest_mode(vcpu
);
10503 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10504 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10506 vmx_switch_vmcs(vcpu
, vmcs02
);
10507 vmx_segment_cache_clear(vmx
);
10509 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10510 leave_guest_mode(vcpu
);
10511 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10512 nested_vmx_entry_failure(vcpu
, vmcs12
,
10513 EXIT_REASON_INVALID_STATE
, exit_qual
);
10517 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10519 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10520 vmcs12
->vm_entry_msr_load_addr
,
10521 vmcs12
->vm_entry_msr_load_count
);
10522 if (msr_entry_idx
) {
10523 leave_guest_mode(vcpu
);
10524 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10525 nested_vmx_entry_failure(vcpu
, vmcs12
,
10526 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10531 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10532 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10533 * returned as far as L1 is concerned. It will only return (and set
10534 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10540 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10541 * for running an L2 nested guest.
10543 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10545 struct vmcs12
*vmcs12
;
10546 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10547 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
10551 if (!nested_vmx_check_permission(vcpu
))
10554 if (!nested_vmx_check_vmcs12(vcpu
))
10557 vmcs12
= get_vmcs12(vcpu
);
10559 if (enable_shadow_vmcs
)
10560 copy_shadow_to_vmcs12(vmx
);
10563 * The nested entry process starts with enforcing various prerequisites
10564 * on vmcs12 as required by the Intel SDM, and act appropriately when
10565 * they fail: As the SDM explains, some conditions should cause the
10566 * instruction to fail, while others will cause the instruction to seem
10567 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10568 * To speed up the normal (success) code path, we should avoid checking
10569 * for misconfigurations which will anyway be caught by the processor
10570 * when using the merged vmcs02.
10572 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
10573 nested_vmx_failValid(vcpu
,
10574 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
10578 if (vmcs12
->launch_state
== launch
) {
10579 nested_vmx_failValid(vcpu
,
10580 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10581 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10585 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10587 nested_vmx_failValid(vcpu
, ret
);
10592 * After this point, the trap flag no longer triggers a singlestep trap
10593 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10594 * This is not 100% correct; for performance reasons, we delegate most
10595 * of the checks on host state to the processor. If those fail,
10596 * the singlestep trap is missed.
10598 skip_emulated_instruction(vcpu
);
10600 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10602 nested_vmx_entry_failure(vcpu
, vmcs12
,
10603 EXIT_REASON_INVALID_STATE
, exit_qual
);
10608 * We're finally done with prerequisite checking, and can start with
10609 * the nested entry.
10612 ret
= enter_vmx_non_root_mode(vcpu
, true);
10616 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10617 return kvm_vcpu_halt(vcpu
);
10619 vmx
->nested
.nested_run_pending
= 1;
10624 return kvm_skip_emulated_instruction(vcpu
);
10628 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10629 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10630 * This function returns the new value we should put in vmcs12.guest_cr0.
10631 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10632 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10633 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10634 * didn't trap the bit, because if L1 did, so would L0).
10635 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10636 * been modified by L2, and L1 knows it. So just leave the old value of
10637 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10638 * isn't relevant, because if L0 traps this bit it can set it to anything.
10639 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10640 * changed these bits, and therefore they need to be updated, but L0
10641 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10642 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10644 static inline unsigned long
10645 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10648 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10649 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10650 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10651 vcpu
->arch
.cr0_guest_owned_bits
));
10654 static inline unsigned long
10655 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10658 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10659 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10660 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10661 vcpu
->arch
.cr4_guest_owned_bits
));
10664 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10665 struct vmcs12
*vmcs12
)
10670 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10671 nr
= vcpu
->arch
.exception
.nr
;
10672 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10674 if (kvm_exception_is_soft(nr
)) {
10675 vmcs12
->vm_exit_instruction_len
=
10676 vcpu
->arch
.event_exit_inst_len
;
10677 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10679 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10681 if (vcpu
->arch
.exception
.has_error_code
) {
10682 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10683 vmcs12
->idt_vectoring_error_code
=
10684 vcpu
->arch
.exception
.error_code
;
10687 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10688 } else if (vcpu
->arch
.nmi_injected
) {
10689 vmcs12
->idt_vectoring_info_field
=
10690 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10691 } else if (vcpu
->arch
.interrupt
.pending
) {
10692 nr
= vcpu
->arch
.interrupt
.nr
;
10693 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10695 if (vcpu
->arch
.interrupt
.soft
) {
10696 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10697 vmcs12
->vm_entry_instruction_len
=
10698 vcpu
->arch
.event_exit_inst_len
;
10700 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10702 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10706 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10708 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10710 if (vcpu
->arch
.exception
.pending
||
10711 vcpu
->arch
.nmi_injected
||
10712 vcpu
->arch
.interrupt
.pending
)
10715 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10716 vmx
->nested
.preemption_timer_expired
) {
10717 if (vmx
->nested
.nested_run_pending
)
10719 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10723 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10724 if (vmx
->nested
.nested_run_pending
)
10726 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10727 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10728 INTR_INFO_VALID_MASK
, 0);
10730 * The NMI-triggered VM exit counts as injection:
10731 * clear this one and block further NMIs.
10733 vcpu
->arch
.nmi_pending
= 0;
10734 vmx_set_nmi_mask(vcpu
, true);
10738 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10739 nested_exit_on_intr(vcpu
)) {
10740 if (vmx
->nested
.nested_run_pending
)
10742 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10746 vmx_complete_nested_posted_interrupt(vcpu
);
10750 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10752 ktime_t remaining
=
10753 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10756 if (ktime_to_ns(remaining
) <= 0)
10759 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10760 do_div(value
, 1000000);
10761 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10765 * Update the guest state fields of vmcs12 to reflect changes that
10766 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10767 * VM-entry controls is also updated, since this is really a guest
10770 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10772 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10773 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10775 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10776 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10777 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10779 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10780 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10781 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10782 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10783 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10784 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10785 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10786 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10787 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10788 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10789 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10790 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10791 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10792 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10793 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10794 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10795 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10796 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10797 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10798 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10799 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10800 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10801 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10802 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10803 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10804 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10805 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10806 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10807 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10808 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10809 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10810 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10811 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10812 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10813 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10814 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10816 vmcs12
->guest_interruptibility_info
=
10817 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10818 vmcs12
->guest_pending_dbg_exceptions
=
10819 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10820 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10821 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10823 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10825 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10826 if (vmcs12
->vm_exit_controls
&
10827 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10828 vmcs12
->vmx_preemption_timer_value
=
10829 vmx_get_preemption_timer_value(vcpu
);
10830 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10834 * In some cases (usually, nested EPT), L2 is allowed to change its
10835 * own CR3 without exiting. If it has changed it, we must keep it.
10836 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10837 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10839 * Additionally, restore L2's PDPTR to vmcs12.
10842 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10843 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10844 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10845 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10846 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10849 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
10851 if (nested_cpu_has_vid(vmcs12
))
10852 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10854 vmcs12
->vm_entry_controls
=
10855 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10856 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10858 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10859 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10860 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10863 /* TODO: These cannot have changed unless we have MSR bitmaps and
10864 * the relevant bit asks not to trap the change */
10865 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10866 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10867 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10868 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10869 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10870 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10871 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10872 if (kvm_mpx_supported())
10873 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10877 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10878 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10879 * and this function updates it to reflect the changes to the guest state while
10880 * L2 was running (and perhaps made some exits which were handled directly by L0
10881 * without going back to L1), and to reflect the exit reason.
10882 * Note that we do not have to copy here all VMCS fields, just those that
10883 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10884 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10885 * which already writes to vmcs12 directly.
10887 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10888 u32 exit_reason
, u32 exit_intr_info
,
10889 unsigned long exit_qualification
)
10891 /* update guest state fields: */
10892 sync_vmcs12(vcpu
, vmcs12
);
10894 /* update exit information fields: */
10896 vmcs12
->vm_exit_reason
= exit_reason
;
10897 vmcs12
->exit_qualification
= exit_qualification
;
10898 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10900 vmcs12
->idt_vectoring_info_field
= 0;
10901 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10902 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10904 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10905 vmcs12
->launch_state
= 1;
10907 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10908 * instead of reading the real value. */
10909 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10912 * Transfer the event that L0 or L1 may wanted to inject into
10913 * L2 to IDT_VECTORING_INFO_FIELD.
10915 vmcs12_save_pending_event(vcpu
, vmcs12
);
10919 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10920 * preserved above and would only end up incorrectly in L1.
10922 vcpu
->arch
.nmi_injected
= false;
10923 kvm_clear_exception_queue(vcpu
);
10924 kvm_clear_interrupt_queue(vcpu
);
10928 * A part of what we need to when the nested L2 guest exits and we want to
10929 * run its L1 parent, is to reset L1's guest state to the host state specified
10931 * This function is to be called not only on normal nested exit, but also on
10932 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10933 * Failures During or After Loading Guest State").
10934 * This function should be called when the active VMCS is L1's (vmcs01).
10936 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10937 struct vmcs12
*vmcs12
)
10939 struct kvm_segment seg
;
10940 u32 entry_failure_code
;
10942 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10943 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10944 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10945 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10947 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10948 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10950 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10951 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10952 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10954 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10955 * actually changed, because vmx_set_cr0 refers to efer set above.
10957 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10958 * (KVM doesn't change it);
10960 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
10961 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10963 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
10964 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10965 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10967 nested_ept_uninit_mmu_context(vcpu
);
10970 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10971 * couldn't have changed.
10973 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
10974 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
10977 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10981 * Trivially support vpid by letting L2s share their parent
10982 * L1's vpid. TODO: move to a more elaborate solution, giving
10983 * each L2 its own vpid and exposing the vpid feature to L1.
10985 vmx_flush_tlb(vcpu
);
10987 /* Restore posted intr vector. */
10988 if (nested_cpu_has_posted_intr(vmcs12
))
10989 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
10991 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10992 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10993 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10994 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10995 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10997 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10998 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10999 vmcs_write64(GUEST_BNDCFGS
, 0);
11001 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11002 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11003 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11005 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11006 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11007 vmcs12
->host_ia32_perf_global_ctrl
);
11009 /* Set L1 segment info according to Intel SDM
11010 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11011 seg
= (struct kvm_segment
) {
11013 .limit
= 0xFFFFFFFF,
11014 .selector
= vmcs12
->host_cs_selector
,
11020 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11024 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11025 seg
= (struct kvm_segment
) {
11027 .limit
= 0xFFFFFFFF,
11034 seg
.selector
= vmcs12
->host_ds_selector
;
11035 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11036 seg
.selector
= vmcs12
->host_es_selector
;
11037 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11038 seg
.selector
= vmcs12
->host_ss_selector
;
11039 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11040 seg
.selector
= vmcs12
->host_fs_selector
;
11041 seg
.base
= vmcs12
->host_fs_base
;
11042 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11043 seg
.selector
= vmcs12
->host_gs_selector
;
11044 seg
.base
= vmcs12
->host_gs_base
;
11045 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11046 seg
= (struct kvm_segment
) {
11047 .base
= vmcs12
->host_tr_base
,
11049 .selector
= vmcs12
->host_tr_selector
,
11053 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11055 kvm_set_dr(vcpu
, 7, 0x400);
11056 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11058 if (cpu_has_vmx_msr_bitmap())
11059 vmx_set_msr_bitmap(vcpu
);
11061 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11062 vmcs12
->vm_exit_msr_load_count
))
11063 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11067 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11068 * and modify vmcs12 to make it see what it would expect to see there if
11069 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11071 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11072 u32 exit_intr_info
,
11073 unsigned long exit_qualification
)
11075 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11076 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11077 u32 vm_inst_error
= 0;
11079 /* trying to cancel vmlaunch/vmresume is a bug */
11080 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11082 leave_guest_mode(vcpu
);
11083 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11084 exit_qualification
);
11086 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11087 vmcs12
->vm_exit_msr_store_count
))
11088 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11090 if (unlikely(vmx
->fail
))
11091 vm_inst_error
= vmcs_read32(VM_INSTRUCTION_ERROR
);
11093 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11095 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
11096 && nested_exit_intr_ack_set(vcpu
)) {
11097 int irq
= kvm_cpu_get_interrupt(vcpu
);
11099 vmcs12
->vm_exit_intr_info
= irq
|
11100 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11103 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11104 vmcs12
->exit_qualification
,
11105 vmcs12
->idt_vectoring_info_field
,
11106 vmcs12
->vm_exit_intr_info
,
11107 vmcs12
->vm_exit_intr_error_code
,
11110 vm_entry_controls_reset_shadow(vmx
);
11111 vm_exit_controls_reset_shadow(vmx
);
11112 vmx_segment_cache_clear(vmx
);
11114 /* if no vmcs02 cache requested, remove the one we used */
11115 if (VMCS02_POOL_SIZE
== 0)
11116 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11118 load_vmcs12_host_state(vcpu
, vmcs12
);
11120 /* Update any VMCS fields that might have changed while L2 ran */
11121 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11122 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11123 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11124 if (vmx
->hv_deadline_tsc
== -1)
11125 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11126 PIN_BASED_VMX_PREEMPTION_TIMER
);
11128 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11129 PIN_BASED_VMX_PREEMPTION_TIMER
);
11130 if (kvm_has_tsc_control
)
11131 decache_tsc_multiplier(vmx
);
11133 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11134 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11135 vmx_set_virtual_x2apic_mode(vcpu
,
11136 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11137 } else if (!nested_cpu_has_ept(vmcs12
) &&
11138 nested_cpu_has2(vmcs12
,
11139 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11140 vmx_flush_tlb_ept_only(vcpu
);
11143 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11146 /* Unpin physical memory we referred to in vmcs02 */
11147 if (vmx
->nested
.apic_access_page
) {
11148 nested_release_page(vmx
->nested
.apic_access_page
);
11149 vmx
->nested
.apic_access_page
= NULL
;
11151 if (vmx
->nested
.virtual_apic_page
) {
11152 nested_release_page(vmx
->nested
.virtual_apic_page
);
11153 vmx
->nested
.virtual_apic_page
= NULL
;
11155 if (vmx
->nested
.pi_desc_page
) {
11156 kunmap(vmx
->nested
.pi_desc_page
);
11157 nested_release_page(vmx
->nested
.pi_desc_page
);
11158 vmx
->nested
.pi_desc_page
= NULL
;
11159 vmx
->nested
.pi_desc
= NULL
;
11163 * We are now running in L2, mmu_notifier will force to reload the
11164 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11166 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11169 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11170 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11171 * success or failure flag accordingly.
11173 if (unlikely(vmx
->fail
)) {
11175 nested_vmx_failValid(vcpu
, vm_inst_error
);
11177 nested_vmx_succeed(vcpu
);
11178 if (enable_shadow_vmcs
)
11179 vmx
->nested
.sync_shadow_vmcs
= true;
11181 /* in case we halted in L2 */
11182 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11186 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11188 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11190 if (is_guest_mode(vcpu
)) {
11191 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11192 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11194 free_nested(to_vmx(vcpu
));
11198 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11199 * 23.7 "VM-entry failures during or after loading guest state" (this also
11200 * lists the acceptable exit-reason and exit-qualification parameters).
11201 * It should only be called before L2 actually succeeded to run, and when
11202 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11204 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11205 struct vmcs12
*vmcs12
,
11206 u32 reason
, unsigned long qualification
)
11208 load_vmcs12_host_state(vcpu
, vmcs12
);
11209 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11210 vmcs12
->exit_qualification
= qualification
;
11211 nested_vmx_succeed(vcpu
);
11212 if (enable_shadow_vmcs
)
11213 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11216 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11217 struct x86_instruction_info
*info
,
11218 enum x86_intercept_stage stage
)
11220 return X86EMUL_CONTINUE
;
11223 #ifdef CONFIG_X86_64
11224 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11225 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11226 u64 divisor
, u64
*result
)
11228 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11230 /* To avoid the overflow on divq */
11231 if (high
>= divisor
)
11234 /* Low hold the result, high hold rem which is discarded */
11235 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11236 "rm" (divisor
), "0" (low
), "1" (high
));
11242 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11244 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11245 u64 tscl
= rdtsc();
11246 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11247 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11249 /* Convert to host delta tsc if tsc scaling is enabled */
11250 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11251 u64_shl_div_u64(delta_tsc
,
11252 kvm_tsc_scaling_ratio_frac_bits
,
11253 vcpu
->arch
.tsc_scaling_ratio
,
11258 * If the delta tsc can't fit in the 32 bit after the multi shift,
11259 * we can't use the preemption timer.
11260 * It's possible that it fits on later vmentries, but checking
11261 * on every vmentry is costly so we just use an hrtimer.
11263 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11266 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11267 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11268 PIN_BASED_VMX_PREEMPTION_TIMER
);
11270 return delta_tsc
== 0;
11273 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11275 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11276 vmx
->hv_deadline_tsc
= -1;
11277 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11278 PIN_BASED_VMX_PREEMPTION_TIMER
);
11282 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11285 shrink_ple_window(vcpu
);
11288 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11289 struct kvm_memory_slot
*slot
)
11291 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11292 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11295 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11296 struct kvm_memory_slot
*slot
)
11298 kvm_mmu_slot_set_dirty(kvm
, slot
);
11301 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11303 kvm_flush_pml_buffers(kvm
);
11306 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11308 struct vmcs12
*vmcs12
;
11309 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11311 struct page
*page
= NULL
;
11314 if (is_guest_mode(vcpu
)) {
11315 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11318 * Check if PML is enabled for the nested guest.
11319 * Whether eptp bit 6 is set is already checked
11320 * as part of A/D emulation.
11322 vmcs12
= get_vmcs12(vcpu
);
11323 if (!nested_cpu_has_pml(vmcs12
))
11326 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11327 vmx
->nested
.pml_full
= true;
11331 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11333 page
= nested_get_page(vcpu
, vmcs12
->pml_address
);
11337 pml_address
= kmap(page
);
11338 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11340 nested_release_page_clean(page
);
11346 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11347 struct kvm_memory_slot
*memslot
,
11348 gfn_t offset
, unsigned long mask
)
11350 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11354 * This routine does the following things for vCPU which is going
11355 * to be blocked if VT-d PI is enabled.
11356 * - Store the vCPU to the wakeup list, so when interrupts happen
11357 * we can find the right vCPU to wake up.
11358 * - Change the Posted-interrupt descriptor as below:
11359 * 'NDST' <-- vcpu->pre_pcpu
11360 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11361 * - If 'ON' is set during this process, which means at least one
11362 * interrupt is posted for this vCPU, we cannot block it, in
11363 * this case, return 1, otherwise, return 0.
11366 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11368 unsigned long flags
;
11370 struct pi_desc old
, new;
11371 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11373 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11374 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11375 !kvm_vcpu_apicv_active(vcpu
))
11378 vcpu
->pre_pcpu
= vcpu
->cpu
;
11379 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11380 vcpu
->pre_pcpu
), flags
);
11381 list_add_tail(&vcpu
->blocked_vcpu_list
,
11382 &per_cpu(blocked_vcpu_on_cpu
,
11384 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
11385 vcpu
->pre_pcpu
), flags
);
11388 old
.control
= new.control
= pi_desc
->control
;
11391 * We should not block the vCPU if
11392 * an interrupt is posted for it.
11394 if (pi_test_on(pi_desc
) == 1) {
11395 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11396 vcpu
->pre_pcpu
), flags
);
11397 list_del(&vcpu
->blocked_vcpu_list
);
11398 spin_unlock_irqrestore(
11399 &per_cpu(blocked_vcpu_on_cpu_lock
,
11400 vcpu
->pre_pcpu
), flags
);
11401 vcpu
->pre_pcpu
= -1;
11406 WARN((pi_desc
->sn
== 1),
11407 "Warning: SN field of posted-interrupts "
11408 "is set before blocking\n");
11411 * Since vCPU can be preempted during this process,
11412 * vcpu->cpu could be different with pre_pcpu, we
11413 * need to set pre_pcpu as the destination of wakeup
11414 * notification event, then we can find the right vCPU
11415 * to wakeup in wakeup handler if interrupts happen
11416 * when the vCPU is in blocked state.
11418 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11420 if (x2apic_enabled())
11423 new.ndst
= (dest
<< 8) & 0xFF00;
11425 /* set 'NV' to 'wakeup vector' */
11426 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11427 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11428 new.control
) != old
.control
);
11433 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11435 if (pi_pre_block(vcpu
))
11438 if (kvm_lapic_hv_timer_in_use(vcpu
))
11439 kvm_lapic_switch_to_sw_timer(vcpu
);
11444 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11446 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11447 struct pi_desc old
, new;
11449 unsigned long flags
;
11451 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11452 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11453 !kvm_vcpu_apicv_active(vcpu
))
11457 old
.control
= new.control
= pi_desc
->control
;
11459 dest
= cpu_physical_id(vcpu
->cpu
);
11461 if (x2apic_enabled())
11464 new.ndst
= (dest
<< 8) & 0xFF00;
11466 /* Allow posting non-urgent interrupts */
11469 /* set 'NV' to 'notification vector' */
11470 new.nv
= POSTED_INTR_VECTOR
;
11471 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11472 new.control
) != old
.control
);
11474 if(vcpu
->pre_pcpu
!= -1) {
11476 &per_cpu(blocked_vcpu_on_cpu_lock
,
11477 vcpu
->pre_pcpu
), flags
);
11478 list_del(&vcpu
->blocked_vcpu_list
);
11479 spin_unlock_irqrestore(
11480 &per_cpu(blocked_vcpu_on_cpu_lock
,
11481 vcpu
->pre_pcpu
), flags
);
11482 vcpu
->pre_pcpu
= -1;
11486 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11488 if (kvm_x86_ops
->set_hv_timer
)
11489 kvm_lapic_switch_to_hv_timer(vcpu
);
11491 pi_post_block(vcpu
);
11495 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11498 * @host_irq: host irq of the interrupt
11499 * @guest_irq: gsi of the interrupt
11500 * @set: set or unset PI
11501 * returns 0 on success, < 0 on failure
11503 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11504 uint32_t guest_irq
, bool set
)
11506 struct kvm_kernel_irq_routing_entry
*e
;
11507 struct kvm_irq_routing_table
*irq_rt
;
11508 struct kvm_lapic_irq irq
;
11509 struct kvm_vcpu
*vcpu
;
11510 struct vcpu_data vcpu_info
;
11511 int idx
, ret
= -EINVAL
;
11513 if (!kvm_arch_has_assigned_device(kvm
) ||
11514 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11515 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11518 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11519 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11520 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
11522 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11523 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11526 * VT-d PI cannot support posting multicast/broadcast
11527 * interrupts to a vCPU, we still use interrupt remapping
11528 * for these kind of interrupts.
11530 * For lowest-priority interrupts, we only support
11531 * those with single CPU as the destination, e.g. user
11532 * configures the interrupts via /proc/irq or uses
11533 * irqbalance to make the interrupts single-CPU.
11535 * We will support full lowest-priority interrupt later.
11538 kvm_set_msi_irq(kvm
, e
, &irq
);
11539 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11541 * Make sure the IRTE is in remapped mode if
11542 * we don't handle it in posted mode.
11544 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11547 "failed to back to remapped mode, irq: %u\n",
11555 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11556 vcpu_info
.vector
= irq
.vector
;
11558 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11559 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11562 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11564 /* suppress notification event before unposting */
11565 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11566 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11567 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11571 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11579 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11583 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11585 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11586 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11587 FEATURE_CONTROL_LMCE
;
11589 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11590 ~FEATURE_CONTROL_LMCE
;
11593 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11594 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11595 .disabled_by_bios
= vmx_disabled_by_bios
,
11596 .hardware_setup
= hardware_setup
,
11597 .hardware_unsetup
= hardware_unsetup
,
11598 .check_processor_compatibility
= vmx_check_processor_compat
,
11599 .hardware_enable
= hardware_enable
,
11600 .hardware_disable
= hardware_disable
,
11601 .cpu_has_accelerated_tpr
= report_flexpriority
,
11602 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11604 .vcpu_create
= vmx_create_vcpu
,
11605 .vcpu_free
= vmx_free_vcpu
,
11606 .vcpu_reset
= vmx_vcpu_reset
,
11608 .prepare_guest_switch
= vmx_save_host_state
,
11609 .vcpu_load
= vmx_vcpu_load
,
11610 .vcpu_put
= vmx_vcpu_put
,
11612 .update_bp_intercept
= update_exception_bitmap
,
11613 .get_msr
= vmx_get_msr
,
11614 .set_msr
= vmx_set_msr
,
11615 .get_segment_base
= vmx_get_segment_base
,
11616 .get_segment
= vmx_get_segment
,
11617 .set_segment
= vmx_set_segment
,
11618 .get_cpl
= vmx_get_cpl
,
11619 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11620 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11621 .decache_cr3
= vmx_decache_cr3
,
11622 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11623 .set_cr0
= vmx_set_cr0
,
11624 .set_cr3
= vmx_set_cr3
,
11625 .set_cr4
= vmx_set_cr4
,
11626 .set_efer
= vmx_set_efer
,
11627 .get_idt
= vmx_get_idt
,
11628 .set_idt
= vmx_set_idt
,
11629 .get_gdt
= vmx_get_gdt
,
11630 .set_gdt
= vmx_set_gdt
,
11631 .get_dr6
= vmx_get_dr6
,
11632 .set_dr6
= vmx_set_dr6
,
11633 .set_dr7
= vmx_set_dr7
,
11634 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11635 .cache_reg
= vmx_cache_reg
,
11636 .get_rflags
= vmx_get_rflags
,
11637 .set_rflags
= vmx_set_rflags
,
11639 .get_pkru
= vmx_get_pkru
,
11641 .tlb_flush
= vmx_flush_tlb
,
11643 .run
= vmx_vcpu_run
,
11644 .handle_exit
= vmx_handle_exit
,
11645 .skip_emulated_instruction
= skip_emulated_instruction
,
11646 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11647 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11648 .patch_hypercall
= vmx_patch_hypercall
,
11649 .set_irq
= vmx_inject_irq
,
11650 .set_nmi
= vmx_inject_nmi
,
11651 .queue_exception
= vmx_queue_exception
,
11652 .cancel_injection
= vmx_cancel_injection
,
11653 .interrupt_allowed
= vmx_interrupt_allowed
,
11654 .nmi_allowed
= vmx_nmi_allowed
,
11655 .get_nmi_mask
= vmx_get_nmi_mask
,
11656 .set_nmi_mask
= vmx_set_nmi_mask
,
11657 .enable_nmi_window
= enable_nmi_window
,
11658 .enable_irq_window
= enable_irq_window
,
11659 .update_cr8_intercept
= update_cr8_intercept
,
11660 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11661 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11662 .get_enable_apicv
= vmx_get_enable_apicv
,
11663 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11664 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11665 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
11666 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11667 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11668 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11669 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11671 .set_tss_addr
= vmx_set_tss_addr
,
11672 .get_tdp_level
= get_ept_level
,
11673 .get_mt_mask
= vmx_get_mt_mask
,
11675 .get_exit_info
= vmx_get_exit_info
,
11677 .get_lpage_level
= vmx_get_lpage_level
,
11679 .cpuid_update
= vmx_cpuid_update
,
11681 .rdtscp_supported
= vmx_rdtscp_supported
,
11682 .invpcid_supported
= vmx_invpcid_supported
,
11684 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11686 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11688 .write_tsc_offset
= vmx_write_tsc_offset
,
11690 .set_tdp_cr3
= vmx_set_cr3
,
11692 .check_intercept
= vmx_check_intercept
,
11693 .handle_external_intr
= vmx_handle_external_intr
,
11694 .mpx_supported
= vmx_mpx_supported
,
11695 .xsaves_supported
= vmx_xsaves_supported
,
11697 .check_nested_events
= vmx_check_nested_events
,
11699 .sched_in
= vmx_sched_in
,
11701 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11702 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11703 .flush_log_dirty
= vmx_flush_log_dirty
,
11704 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11705 .write_log_dirty
= vmx_write_pml_buffer
,
11707 .pre_block
= vmx_pre_block
,
11708 .post_block
= vmx_post_block
,
11710 .pmu_ops
= &intel_pmu_ops
,
11712 .update_pi_irte
= vmx_update_pi_irte
,
11714 #ifdef CONFIG_X86_64
11715 .set_hv_timer
= vmx_set_hv_timer
,
11716 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11719 .setup_mce
= vmx_setup_mce
,
11722 static int __init
vmx_init(void)
11724 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11725 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11729 #ifdef CONFIG_KEXEC_CORE
11730 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11731 crash_vmclear_local_loaded_vmcss
);
11737 static void __exit
vmx_exit(void)
11739 #ifdef CONFIG_KEXEC_CORE
11740 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11747 module_init(vmx_init
)
11748 module_exit(vmx_exit
)