2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
58 #define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
61 MODULE_AUTHOR("Qumranet");
62 MODULE_LICENSE("GPL");
64 static const struct x86_cpu_id vmx_cpu_id
[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
68 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
70 static bool __read_mostly enable_vpid
= 1;
71 module_param_named(vpid
, enable_vpid
, bool, 0444);
73 static bool __read_mostly flexpriority_enabled
= 1;
74 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
76 static bool __read_mostly enable_ept
= 1;
77 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
79 static bool __read_mostly enable_unrestricted_guest
= 1;
80 module_param_named(unrestricted_guest
,
81 enable_unrestricted_guest
, bool, S_IRUGO
);
83 static bool __read_mostly enable_ept_ad_bits
= 1;
84 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
86 static bool __read_mostly emulate_invalid_guest_state
= true;
87 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
89 static bool __read_mostly fasteoi
= 1;
90 module_param(fasteoi
, bool, S_IRUGO
);
92 static bool __read_mostly enable_apicv
= 1;
93 module_param(enable_apicv
, bool, S_IRUGO
);
95 static bool __read_mostly enable_shadow_vmcs
= 1;
96 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested
= 0;
103 module_param(nested
, bool, S_IRUGO
);
105 static u64 __read_mostly host_xss
;
107 static bool __read_mostly enable_pml
= 1;
108 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113 static int __read_mostly cpu_preemption_timer_multi
;
114 static bool __read_mostly enable_preemption_timer
= 1;
116 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
121 #define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
123 #define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
125 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
138 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
148 * According to test, this time is usually smaller than 128 cycles.
149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
155 #define KVM_VMX_DEFAULT_PLE_GAP 128
156 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
162 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
163 module_param(ple_gap
, int, S_IRUGO
);
165 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
166 module_param(ple_window
, int, S_IRUGO
);
168 /* Default doubles per-vcpu window every exit. */
169 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
170 module_param(ple_window_grow
, int, S_IRUGO
);
172 /* Default resets per-vcpu window every exit to ple_window. */
173 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
174 module_param(ple_window_shrink
, int, S_IRUGO
);
176 /* Default is to compute the maximum so we can never overflow. */
177 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
178 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
179 module_param(ple_window_max
, int, S_IRUGO
);
181 extern const ulong vmx_return
;
183 #define NR_AUTOLOAD_MSRS 8
184 #define VMCS02_POOL_SIZE 1
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
199 struct vmcs
*shadow_vmcs
;
202 struct list_head loaded_vmcss_on_cpu_link
;
205 struct shared_msr_entry
{
212 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
213 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
214 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
215 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
216 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
217 * More than one of these structures may exist, if L1 runs multiple L2 guests.
218 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
219 * underlying hardware which will be used to run L2.
220 * This structure is packed to ensure that its layout is identical across
221 * machines (necessary for live migration).
222 * If there are changes in this struct, VMCS12_REVISION must be changed.
224 typedef u64 natural_width
;
225 struct __packed vmcs12
{
226 /* According to the Intel spec, a VMCS region must start with the
227 * following two fields. Then follow implementation-specific data.
232 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
233 u32 padding
[7]; /* room for future expansion */
238 u64 vm_exit_msr_store_addr
;
239 u64 vm_exit_msr_load_addr
;
240 u64 vm_entry_msr_load_addr
;
242 u64 virtual_apic_page_addr
;
243 u64 apic_access_addr
;
244 u64 posted_intr_desc_addr
;
246 u64 eoi_exit_bitmap0
;
247 u64 eoi_exit_bitmap1
;
248 u64 eoi_exit_bitmap2
;
249 u64 eoi_exit_bitmap3
;
251 u64 guest_physical_address
;
252 u64 vmcs_link_pointer
;
254 u64 guest_ia32_debugctl
;
257 u64 guest_ia32_perf_global_ctrl
;
265 u64 host_ia32_perf_global_ctrl
;
266 u64 padding64
[8]; /* room for future expansion */
268 * To allow migration of L1 (complete with its L2 guests) between
269 * machines of different natural widths (32 or 64 bit), we cannot have
270 * unsigned long fields with no explict size. We use u64 (aliased
271 * natural_width) instead. Luckily, x86 is little-endian.
273 natural_width cr0_guest_host_mask
;
274 natural_width cr4_guest_host_mask
;
275 natural_width cr0_read_shadow
;
276 natural_width cr4_read_shadow
;
277 natural_width cr3_target_value0
;
278 natural_width cr3_target_value1
;
279 natural_width cr3_target_value2
;
280 natural_width cr3_target_value3
;
281 natural_width exit_qualification
;
282 natural_width guest_linear_address
;
283 natural_width guest_cr0
;
284 natural_width guest_cr3
;
285 natural_width guest_cr4
;
286 natural_width guest_es_base
;
287 natural_width guest_cs_base
;
288 natural_width guest_ss_base
;
289 natural_width guest_ds_base
;
290 natural_width guest_fs_base
;
291 natural_width guest_gs_base
;
292 natural_width guest_ldtr_base
;
293 natural_width guest_tr_base
;
294 natural_width guest_gdtr_base
;
295 natural_width guest_idtr_base
;
296 natural_width guest_dr7
;
297 natural_width guest_rsp
;
298 natural_width guest_rip
;
299 natural_width guest_rflags
;
300 natural_width guest_pending_dbg_exceptions
;
301 natural_width guest_sysenter_esp
;
302 natural_width guest_sysenter_eip
;
303 natural_width host_cr0
;
304 natural_width host_cr3
;
305 natural_width host_cr4
;
306 natural_width host_fs_base
;
307 natural_width host_gs_base
;
308 natural_width host_tr_base
;
309 natural_width host_gdtr_base
;
310 natural_width host_idtr_base
;
311 natural_width host_ia32_sysenter_esp
;
312 natural_width host_ia32_sysenter_eip
;
313 natural_width host_rsp
;
314 natural_width host_rip
;
315 natural_width paddingl
[8]; /* room for future expansion */
316 u32 pin_based_vm_exec_control
;
317 u32 cpu_based_vm_exec_control
;
318 u32 exception_bitmap
;
319 u32 page_fault_error_code_mask
;
320 u32 page_fault_error_code_match
;
321 u32 cr3_target_count
;
322 u32 vm_exit_controls
;
323 u32 vm_exit_msr_store_count
;
324 u32 vm_exit_msr_load_count
;
325 u32 vm_entry_controls
;
326 u32 vm_entry_msr_load_count
;
327 u32 vm_entry_intr_info_field
;
328 u32 vm_entry_exception_error_code
;
329 u32 vm_entry_instruction_len
;
331 u32 secondary_vm_exec_control
;
332 u32 vm_instruction_error
;
334 u32 vm_exit_intr_info
;
335 u32 vm_exit_intr_error_code
;
336 u32 idt_vectoring_info_field
;
337 u32 idt_vectoring_error_code
;
338 u32 vm_exit_instruction_len
;
339 u32 vmx_instruction_info
;
346 u32 guest_ldtr_limit
;
348 u32 guest_gdtr_limit
;
349 u32 guest_idtr_limit
;
350 u32 guest_es_ar_bytes
;
351 u32 guest_cs_ar_bytes
;
352 u32 guest_ss_ar_bytes
;
353 u32 guest_ds_ar_bytes
;
354 u32 guest_fs_ar_bytes
;
355 u32 guest_gs_ar_bytes
;
356 u32 guest_ldtr_ar_bytes
;
357 u32 guest_tr_ar_bytes
;
358 u32 guest_interruptibility_info
;
359 u32 guest_activity_state
;
360 u32 guest_sysenter_cs
;
361 u32 host_ia32_sysenter_cs
;
362 u32 vmx_preemption_timer_value
;
363 u32 padding32
[7]; /* room for future expansion */
364 u16 virtual_processor_id
;
366 u16 guest_es_selector
;
367 u16 guest_cs_selector
;
368 u16 guest_ss_selector
;
369 u16 guest_ds_selector
;
370 u16 guest_fs_selector
;
371 u16 guest_gs_selector
;
372 u16 guest_ldtr_selector
;
373 u16 guest_tr_selector
;
374 u16 guest_intr_status
;
376 u16 host_es_selector
;
377 u16 host_cs_selector
;
378 u16 host_ss_selector
;
379 u16 host_ds_selector
;
380 u16 host_fs_selector
;
381 u16 host_gs_selector
;
382 u16 host_tr_selector
;
386 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
387 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
388 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
390 #define VMCS12_REVISION 0x11e57ed0
393 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
394 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
395 * current implementation, 4K are reserved to avoid future complications.
397 #define VMCS12_SIZE 0x1000
399 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
401 struct list_head list
;
403 struct loaded_vmcs vmcs02
;
407 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
408 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
411 /* Has the level1 guest done vmxon? */
416 /* The guest-physical address of the current VMCS L1 keeps for L2 */
418 /* The host-usable pointer to the above */
419 struct page
*current_vmcs12_page
;
420 struct vmcs12
*current_vmcs12
;
422 * Cache of the guest's VMCS, existing outside of guest memory.
423 * Loaded from guest memory during VMPTRLD. Flushed to guest
424 * memory during VMXOFF, VMCLEAR, VMPTRLD.
426 struct vmcs12
*cached_vmcs12
;
428 * Indicates if the shadow vmcs must be updated with the
429 * data hold by vmcs12
431 bool sync_shadow_vmcs
;
433 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
434 struct list_head vmcs02_pool
;
436 bool change_vmcs01_virtual_x2apic_mode
;
437 /* L2 must run next, and mustn't decide to exit to L1. */
438 bool nested_run_pending
;
440 * Guest pages referred to in vmcs02 with host-physical pointers, so
441 * we must keep them pinned while L2 runs.
443 struct page
*apic_access_page
;
444 struct page
*virtual_apic_page
;
445 struct page
*pi_desc_page
;
446 struct pi_desc
*pi_desc
;
450 unsigned long *msr_bitmap
;
452 struct hrtimer preemption_timer
;
453 bool preemption_timer_expired
;
455 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
462 * We only store the "true" versions of the VMX capability MSRs. We
463 * generate the "non-true" versions by setting the must-be-1 bits
464 * according to the SDM.
466 u32 nested_vmx_procbased_ctls_low
;
467 u32 nested_vmx_procbased_ctls_high
;
468 u32 nested_vmx_secondary_ctls_low
;
469 u32 nested_vmx_secondary_ctls_high
;
470 u32 nested_vmx_pinbased_ctls_low
;
471 u32 nested_vmx_pinbased_ctls_high
;
472 u32 nested_vmx_exit_ctls_low
;
473 u32 nested_vmx_exit_ctls_high
;
474 u32 nested_vmx_entry_ctls_low
;
475 u32 nested_vmx_entry_ctls_high
;
476 u32 nested_vmx_misc_low
;
477 u32 nested_vmx_misc_high
;
478 u32 nested_vmx_ept_caps
;
479 u32 nested_vmx_vpid_caps
;
480 u64 nested_vmx_basic
;
481 u64 nested_vmx_cr0_fixed0
;
482 u64 nested_vmx_cr0_fixed1
;
483 u64 nested_vmx_cr4_fixed0
;
484 u64 nested_vmx_cr4_fixed1
;
485 u64 nested_vmx_vmcs_enum
;
488 #define POSTED_INTR_ON 0
489 #define POSTED_INTR_SN 1
491 /* Posted-Interrupt Descriptor */
493 u32 pir
[8]; /* Posted interrupt requested */
496 /* bit 256 - Outstanding Notification */
498 /* bit 257 - Suppress Notification */
500 /* bit 271:258 - Reserved */
502 /* bit 279:272 - Notification Vector */
504 /* bit 287:280 - Reserved */
506 /* bit 319:288 - Notification Destination */
514 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
516 return test_and_set_bit(POSTED_INTR_ON
,
517 (unsigned long *)&pi_desc
->control
);
520 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
522 return test_and_clear_bit(POSTED_INTR_ON
,
523 (unsigned long *)&pi_desc
->control
);
526 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
528 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
531 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
533 return clear_bit(POSTED_INTR_SN
,
534 (unsigned long *)&pi_desc
->control
);
537 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
539 return set_bit(POSTED_INTR_SN
,
540 (unsigned long *)&pi_desc
->control
);
543 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
545 clear_bit(POSTED_INTR_ON
,
546 (unsigned long *)&pi_desc
->control
);
549 static inline int pi_test_on(struct pi_desc
*pi_desc
)
551 return test_bit(POSTED_INTR_ON
,
552 (unsigned long *)&pi_desc
->control
);
555 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
557 return test_bit(POSTED_INTR_SN
,
558 (unsigned long *)&pi_desc
->control
);
562 struct kvm_vcpu vcpu
;
563 unsigned long host_rsp
;
565 bool nmi_known_unmasked
;
567 u32 idt_vectoring_info
;
569 struct shared_msr_entry
*guest_msrs
;
572 unsigned long host_idt_base
;
574 u64 msr_host_kernel_gs_base
;
575 u64 msr_guest_kernel_gs_base
;
577 u32 vm_entry_controls_shadow
;
578 u32 vm_exit_controls_shadow
;
580 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
581 * non-nested (L1) guest, it always points to vmcs01. For a nested
582 * guest (L2), it points to a different VMCS.
584 struct loaded_vmcs vmcs01
;
585 struct loaded_vmcs
*loaded_vmcs
;
586 bool __launched
; /* temporary, used in vmx_vcpu_run */
587 struct msr_autoload
{
589 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
590 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
594 u16 fs_sel
, gs_sel
, ldt_sel
;
598 int gs_ldt_reload_needed
;
599 int fs_reload_needed
;
600 u64 msr_host_bndcfgs
;
601 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
602 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
607 struct kvm_segment segs
[8];
610 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
611 struct kvm_save_segment
{
619 bool emulation_required
;
623 /* Posted interrupt descriptor */
624 struct pi_desc pi_desc
;
626 /* Support for a guest hypervisor (nested VMX) */
627 struct nested_vmx nested
;
629 /* Dynamic PLE window. */
631 bool ple_window_dirty
;
633 /* Support for PML */
634 #define PML_ENTITY_NUM 512
637 /* apic deadline value in host tsc */
640 u64 current_tsc_ratio
;
642 bool guest_pkru_valid
;
647 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
648 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
649 * in msr_ia32_feature_control_valid_bits.
651 u64 msr_ia32_feature_control
;
652 u64 msr_ia32_feature_control_valid_bits
;
655 enum segment_cache_field
{
664 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
666 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
669 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
671 return &(to_vmx(vcpu
)->pi_desc
);
674 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
675 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
676 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
677 [number##_HIGH] = VMCS12_OFFSET(name)+4
680 static unsigned long shadow_read_only_fields
[] = {
682 * We do NOT shadow fields that are modified when L0
683 * traps and emulates any vmx instruction (e.g. VMPTRLD,
684 * VMXON...) executed by L1.
685 * For example, VM_INSTRUCTION_ERROR is read
686 * by L1 if a vmx instruction fails (part of the error path).
687 * Note the code assumes this logic. If for some reason
688 * we start shadowing these fields then we need to
689 * force a shadow sync when L0 emulates vmx instructions
690 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
691 * by nested_vmx_failValid)
695 VM_EXIT_INSTRUCTION_LEN
,
696 IDT_VECTORING_INFO_FIELD
,
697 IDT_VECTORING_ERROR_CODE
,
698 VM_EXIT_INTR_ERROR_CODE
,
700 GUEST_LINEAR_ADDRESS
,
701 GUEST_PHYSICAL_ADDRESS
703 static int max_shadow_read_only_fields
=
704 ARRAY_SIZE(shadow_read_only_fields
);
706 static unsigned long shadow_read_write_fields
[] = {
713 GUEST_INTERRUPTIBILITY_INFO
,
726 CPU_BASED_VM_EXEC_CONTROL
,
727 VM_ENTRY_EXCEPTION_ERROR_CODE
,
728 VM_ENTRY_INTR_INFO_FIELD
,
729 VM_ENTRY_INSTRUCTION_LEN
,
730 VM_ENTRY_EXCEPTION_ERROR_CODE
,
736 static int max_shadow_read_write_fields
=
737 ARRAY_SIZE(shadow_read_write_fields
);
739 static const unsigned short vmcs_field_to_offset_table
[] = {
740 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
741 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
742 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
743 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
744 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
745 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
746 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
747 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
748 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
749 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
750 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
751 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
752 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
753 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
754 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
755 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
756 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
757 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
758 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
759 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
760 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
761 FIELD64(MSR_BITMAP
, msr_bitmap
),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
765 FIELD64(TSC_OFFSET
, tsc_offset
),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
767 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
768 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
769 FIELD64(EPT_POINTER
, ept_pointer
),
770 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
771 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
772 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
773 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
774 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
775 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
776 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
777 FIELD64(PML_ADDRESS
, pml_address
),
778 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
779 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
780 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
781 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
782 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
783 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
784 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
785 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
786 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
787 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
788 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
789 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
790 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
791 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
792 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
793 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
794 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
795 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
796 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
797 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
798 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
799 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
800 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
801 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
802 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
803 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
804 FIELD(TPR_THRESHOLD
, tpr_threshold
),
805 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
806 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
807 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
808 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
809 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
810 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
811 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
812 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
813 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
814 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
815 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
816 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
817 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
818 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
819 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
820 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
821 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
822 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
823 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
824 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
825 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
826 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
827 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
828 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
829 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
830 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
831 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
832 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
833 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
834 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
835 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
836 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
837 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
838 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
839 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
840 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
841 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
842 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
843 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
844 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
845 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
846 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
847 FIELD(GUEST_CR0
, guest_cr0
),
848 FIELD(GUEST_CR3
, guest_cr3
),
849 FIELD(GUEST_CR4
, guest_cr4
),
850 FIELD(GUEST_ES_BASE
, guest_es_base
),
851 FIELD(GUEST_CS_BASE
, guest_cs_base
),
852 FIELD(GUEST_SS_BASE
, guest_ss_base
),
853 FIELD(GUEST_DS_BASE
, guest_ds_base
),
854 FIELD(GUEST_FS_BASE
, guest_fs_base
),
855 FIELD(GUEST_GS_BASE
, guest_gs_base
),
856 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
857 FIELD(GUEST_TR_BASE
, guest_tr_base
),
858 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
859 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
860 FIELD(GUEST_DR7
, guest_dr7
),
861 FIELD(GUEST_RSP
, guest_rsp
),
862 FIELD(GUEST_RIP
, guest_rip
),
863 FIELD(GUEST_RFLAGS
, guest_rflags
),
864 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
865 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
866 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
867 FIELD(HOST_CR0
, host_cr0
),
868 FIELD(HOST_CR3
, host_cr3
),
869 FIELD(HOST_CR4
, host_cr4
),
870 FIELD(HOST_FS_BASE
, host_fs_base
),
871 FIELD(HOST_GS_BASE
, host_gs_base
),
872 FIELD(HOST_TR_BASE
, host_tr_base
),
873 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
874 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
875 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
876 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
877 FIELD(HOST_RSP
, host_rsp
),
878 FIELD(HOST_RIP
, host_rip
),
881 static inline short vmcs_field_to_offset(unsigned long field
)
883 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
885 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
886 vmcs_field_to_offset_table
[field
] == 0)
889 return vmcs_field_to_offset_table
[field
];
892 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
894 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
897 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
899 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
900 if (is_error_page(page
))
906 static void nested_release_page(struct page
*page
)
908 kvm_release_page_dirty(page
);
911 static void nested_release_page_clean(struct page
*page
)
913 kvm_release_page_clean(page
);
916 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
917 static u64
construct_eptp(unsigned long root_hpa
);
918 static bool vmx_xsaves_supported(void);
919 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
920 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
921 struct kvm_segment
*var
, int seg
);
922 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
923 struct kvm_segment
*var
, int seg
);
924 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
925 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
926 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
927 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
928 static int alloc_identity_pagetable(struct kvm
*kvm
);
930 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
931 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
933 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
934 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
936 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
939 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
940 * can find which vCPU should be waken up.
942 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
943 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
948 VMX_MSR_BITMAP_LEGACY
,
949 VMX_MSR_BITMAP_LONGMODE
,
950 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
951 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
952 VMX_MSR_BITMAP_LEGACY_X2APIC
,
953 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
959 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
961 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
962 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
963 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
964 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
965 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
966 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
967 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
968 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
969 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
970 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
972 static bool cpu_has_load_ia32_efer
;
973 static bool cpu_has_load_perf_global_ctrl
;
975 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
976 static DEFINE_SPINLOCK(vmx_vpid_lock
);
978 static struct vmcs_config
{
983 u32 pin_based_exec_ctrl
;
984 u32 cpu_based_exec_ctrl
;
985 u32 cpu_based_2nd_exec_ctrl
;
990 static struct vmx_capability
{
995 #define VMX_SEGMENT_FIELD(seg) \
996 [VCPU_SREG_##seg] = { \
997 .selector = GUEST_##seg##_SELECTOR, \
998 .base = GUEST_##seg##_BASE, \
999 .limit = GUEST_##seg##_LIMIT, \
1000 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1003 static const struct kvm_vmx_segment_field
{
1008 } kvm_vmx_segment_fields
[] = {
1009 VMX_SEGMENT_FIELD(CS
),
1010 VMX_SEGMENT_FIELD(DS
),
1011 VMX_SEGMENT_FIELD(ES
),
1012 VMX_SEGMENT_FIELD(FS
),
1013 VMX_SEGMENT_FIELD(GS
),
1014 VMX_SEGMENT_FIELD(SS
),
1015 VMX_SEGMENT_FIELD(TR
),
1016 VMX_SEGMENT_FIELD(LDTR
),
1019 static u64 host_efer
;
1021 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1024 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1025 * away by decrementing the array size.
1027 static const u32 vmx_msr_index
[] = {
1028 #ifdef CONFIG_X86_64
1029 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1031 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1034 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1036 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1037 INTR_INFO_VALID_MASK
)) ==
1038 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1041 static inline bool is_debug(u32 intr_info
)
1043 return is_exception_n(intr_info
, DB_VECTOR
);
1046 static inline bool is_breakpoint(u32 intr_info
)
1048 return is_exception_n(intr_info
, BP_VECTOR
);
1051 static inline bool is_page_fault(u32 intr_info
)
1053 return is_exception_n(intr_info
, PF_VECTOR
);
1056 static inline bool is_no_device(u32 intr_info
)
1058 return is_exception_n(intr_info
, NM_VECTOR
);
1061 static inline bool is_invalid_opcode(u32 intr_info
)
1063 return is_exception_n(intr_info
, UD_VECTOR
);
1066 static inline bool is_external_interrupt(u32 intr_info
)
1068 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1069 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1072 static inline bool is_machine_check(u32 intr_info
)
1074 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1075 INTR_INFO_VALID_MASK
)) ==
1076 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1079 static inline bool cpu_has_vmx_msr_bitmap(void)
1081 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1084 static inline bool cpu_has_vmx_tpr_shadow(void)
1086 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1089 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1091 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1094 static inline bool cpu_has_secondary_exec_ctrls(void)
1096 return vmcs_config
.cpu_based_exec_ctrl
&
1097 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1100 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1102 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1103 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1106 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1108 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1109 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1112 static inline bool cpu_has_vmx_apic_register_virt(void)
1114 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1115 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1118 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1120 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1121 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1125 * Comment's format: document - errata name - stepping - processor name.
1127 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1129 static u32 vmx_preemption_cpu_tfms
[] = {
1130 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1132 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1133 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1134 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1136 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1138 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1139 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1141 * 320767.pdf - AAP86 - B1 -
1142 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1145 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1147 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1149 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1151 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1152 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1153 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1157 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1159 u32 eax
= cpuid_eax(0x00000001), i
;
1161 /* Clear the reserved bits */
1162 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1163 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1164 if (eax
== vmx_preemption_cpu_tfms
[i
])
1170 static inline bool cpu_has_vmx_preemption_timer(void)
1172 return vmcs_config
.pin_based_exec_ctrl
&
1173 PIN_BASED_VMX_PREEMPTION_TIMER
;
1176 static inline bool cpu_has_vmx_posted_intr(void)
1178 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1179 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1182 static inline bool cpu_has_vmx_apicv(void)
1184 return cpu_has_vmx_apic_register_virt() &&
1185 cpu_has_vmx_virtual_intr_delivery() &&
1186 cpu_has_vmx_posted_intr();
1189 static inline bool cpu_has_vmx_flexpriority(void)
1191 return cpu_has_vmx_tpr_shadow() &&
1192 cpu_has_vmx_virtualize_apic_accesses();
1195 static inline bool cpu_has_vmx_ept_execute_only(void)
1197 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1200 static inline bool cpu_has_vmx_ept_2m_page(void)
1202 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1205 static inline bool cpu_has_vmx_ept_1g_page(void)
1207 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1210 static inline bool cpu_has_vmx_ept_4levels(void)
1212 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1215 static inline bool cpu_has_vmx_ept_ad_bits(void)
1217 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1220 static inline bool cpu_has_vmx_invept_context(void)
1222 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1225 static inline bool cpu_has_vmx_invept_global(void)
1227 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1230 static inline bool cpu_has_vmx_invvpid_single(void)
1232 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1235 static inline bool cpu_has_vmx_invvpid_global(void)
1237 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1240 static inline bool cpu_has_vmx_invvpid(void)
1242 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1245 static inline bool cpu_has_vmx_ept(void)
1247 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1248 SECONDARY_EXEC_ENABLE_EPT
;
1251 static inline bool cpu_has_vmx_unrestricted_guest(void)
1253 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1254 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1257 static inline bool cpu_has_vmx_ple(void)
1259 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1260 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1263 static inline bool cpu_has_vmx_basic_inout(void)
1265 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1268 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1270 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1273 static inline bool cpu_has_vmx_vpid(void)
1275 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1276 SECONDARY_EXEC_ENABLE_VPID
;
1279 static inline bool cpu_has_vmx_rdtscp(void)
1281 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1282 SECONDARY_EXEC_RDTSCP
;
1285 static inline bool cpu_has_vmx_invpcid(void)
1287 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1288 SECONDARY_EXEC_ENABLE_INVPCID
;
1291 static inline bool cpu_has_vmx_wbinvd_exit(void)
1293 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1294 SECONDARY_EXEC_WBINVD_EXITING
;
1297 static inline bool cpu_has_vmx_shadow_vmcs(void)
1300 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1301 /* check if the cpu supports writing r/o exit information fields */
1302 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1305 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1306 SECONDARY_EXEC_SHADOW_VMCS
;
1309 static inline bool cpu_has_vmx_pml(void)
1311 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1314 static inline bool cpu_has_vmx_tsc_scaling(void)
1316 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1317 SECONDARY_EXEC_TSC_SCALING
;
1320 static inline bool report_flexpriority(void)
1322 return flexpriority_enabled
;
1325 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1327 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1330 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1332 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1335 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1337 return (vmcs12
->cpu_based_vm_exec_control
&
1338 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1339 (vmcs12
->secondary_vm_exec_control
& bit
);
1342 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1344 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1347 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1349 return vmcs12
->pin_based_vm_exec_control
&
1350 PIN_BASED_VMX_PREEMPTION_TIMER
;
1353 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1355 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1358 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1360 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1361 vmx_xsaves_supported();
1364 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1366 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1369 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1371 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1374 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1376 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1379 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1381 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1384 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1386 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1389 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1391 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1394 static inline bool is_nmi(u32 intr_info
)
1396 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1397 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1400 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1402 unsigned long exit_qualification
);
1403 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1404 struct vmcs12
*vmcs12
,
1405 u32 reason
, unsigned long qualification
);
1407 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1411 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1412 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1417 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1423 } operand
= { vpid
, 0, gva
};
1425 asm volatile (__ex(ASM_VMX_INVVPID
)
1426 /* CF==1 or ZF==1 --> rc = -1 */
1427 "; ja 1f ; ud2 ; 1:"
1428 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1431 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1435 } operand
= {eptp
, gpa
};
1437 asm volatile (__ex(ASM_VMX_INVEPT
)
1438 /* CF==1 or ZF==1 --> rc = -1 */
1439 "; ja 1f ; ud2 ; 1:\n"
1440 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1443 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1447 i
= __find_msr_index(vmx
, msr
);
1449 return &vmx
->guest_msrs
[i
];
1453 static void vmcs_clear(struct vmcs
*vmcs
)
1455 u64 phys_addr
= __pa(vmcs
);
1458 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1459 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1462 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1466 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1468 vmcs_clear(loaded_vmcs
->vmcs
);
1469 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1470 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1471 loaded_vmcs
->cpu
= -1;
1472 loaded_vmcs
->launched
= 0;
1475 static void vmcs_load(struct vmcs
*vmcs
)
1477 u64 phys_addr
= __pa(vmcs
);
1480 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1481 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1484 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1488 #ifdef CONFIG_KEXEC_CORE
1490 * This bitmap is used to indicate whether the vmclear
1491 * operation is enabled on all cpus. All disabled by
1494 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1496 static inline void crash_enable_local_vmclear(int cpu
)
1498 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1501 static inline void crash_disable_local_vmclear(int cpu
)
1503 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1506 static inline int crash_local_vmclear_enabled(int cpu
)
1508 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1511 static void crash_vmclear_local_loaded_vmcss(void)
1513 int cpu
= raw_smp_processor_id();
1514 struct loaded_vmcs
*v
;
1516 if (!crash_local_vmclear_enabled(cpu
))
1519 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1520 loaded_vmcss_on_cpu_link
)
1521 vmcs_clear(v
->vmcs
);
1524 static inline void crash_enable_local_vmclear(int cpu
) { }
1525 static inline void crash_disable_local_vmclear(int cpu
) { }
1526 #endif /* CONFIG_KEXEC_CORE */
1528 static void __loaded_vmcs_clear(void *arg
)
1530 struct loaded_vmcs
*loaded_vmcs
= arg
;
1531 int cpu
= raw_smp_processor_id();
1533 if (loaded_vmcs
->cpu
!= cpu
)
1534 return; /* vcpu migration can race with cpu offline */
1535 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1536 per_cpu(current_vmcs
, cpu
) = NULL
;
1537 crash_disable_local_vmclear(cpu
);
1538 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1541 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1542 * is before setting loaded_vmcs->vcpu to -1 which is done in
1543 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1544 * then adds the vmcs into percpu list before it is deleted.
1548 loaded_vmcs_init(loaded_vmcs
);
1549 crash_enable_local_vmclear(cpu
);
1552 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1554 int cpu
= loaded_vmcs
->cpu
;
1557 smp_call_function_single(cpu
,
1558 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1561 static inline void vpid_sync_vcpu_single(int vpid
)
1566 if (cpu_has_vmx_invvpid_single())
1567 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1570 static inline void vpid_sync_vcpu_global(void)
1572 if (cpu_has_vmx_invvpid_global())
1573 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1576 static inline void vpid_sync_context(int vpid
)
1578 if (cpu_has_vmx_invvpid_single())
1579 vpid_sync_vcpu_single(vpid
);
1581 vpid_sync_vcpu_global();
1584 static inline void ept_sync_global(void)
1586 if (cpu_has_vmx_invept_global())
1587 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1590 static inline void ept_sync_context(u64 eptp
)
1593 if (cpu_has_vmx_invept_context())
1594 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1600 static __always_inline
void vmcs_check16(unsigned long field
)
1602 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1603 "16-bit accessor invalid for 64-bit field");
1604 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1605 "16-bit accessor invalid for 64-bit high field");
1606 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1607 "16-bit accessor invalid for 32-bit high field");
1608 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1609 "16-bit accessor invalid for natural width field");
1612 static __always_inline
void vmcs_check32(unsigned long field
)
1614 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1615 "32-bit accessor invalid for 16-bit field");
1616 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1617 "32-bit accessor invalid for natural width field");
1620 static __always_inline
void vmcs_check64(unsigned long field
)
1622 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1623 "64-bit accessor invalid for 16-bit field");
1624 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1625 "64-bit accessor invalid for 64-bit high field");
1626 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1627 "64-bit accessor invalid for 32-bit field");
1628 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1629 "64-bit accessor invalid for natural width field");
1632 static __always_inline
void vmcs_checkl(unsigned long field
)
1634 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1635 "Natural width accessor invalid for 16-bit field");
1636 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1637 "Natural width accessor invalid for 64-bit field");
1638 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1639 "Natural width accessor invalid for 64-bit high field");
1640 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1641 "Natural width accessor invalid for 32-bit field");
1644 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1646 unsigned long value
;
1648 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1649 : "=a"(value
) : "d"(field
) : "cc");
1653 static __always_inline u16
vmcs_read16(unsigned long field
)
1655 vmcs_check16(field
);
1656 return __vmcs_readl(field
);
1659 static __always_inline u32
vmcs_read32(unsigned long field
)
1661 vmcs_check32(field
);
1662 return __vmcs_readl(field
);
1665 static __always_inline u64
vmcs_read64(unsigned long field
)
1667 vmcs_check64(field
);
1668 #ifdef CONFIG_X86_64
1669 return __vmcs_readl(field
);
1671 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1675 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1678 return __vmcs_readl(field
);
1681 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1683 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1684 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1688 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1692 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1693 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1694 if (unlikely(error
))
1695 vmwrite_error(field
, value
);
1698 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1700 vmcs_check16(field
);
1701 __vmcs_writel(field
, value
);
1704 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1706 vmcs_check32(field
);
1707 __vmcs_writel(field
, value
);
1710 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1712 vmcs_check64(field
);
1713 __vmcs_writel(field
, value
);
1714 #ifndef CONFIG_X86_64
1716 __vmcs_writel(field
+1, value
>> 32);
1720 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1723 __vmcs_writel(field
, value
);
1726 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1728 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1729 "vmcs_clear_bits does not support 64-bit fields");
1730 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1733 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1735 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1736 "vmcs_set_bits does not support 64-bit fields");
1737 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1740 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1742 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1745 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1747 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1748 vmx
->vm_entry_controls_shadow
= val
;
1751 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1753 if (vmx
->vm_entry_controls_shadow
!= val
)
1754 vm_entry_controls_init(vmx
, val
);
1757 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1759 return vmx
->vm_entry_controls_shadow
;
1763 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1765 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1768 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1770 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1773 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1775 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1778 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1780 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1781 vmx
->vm_exit_controls_shadow
= val
;
1784 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1786 if (vmx
->vm_exit_controls_shadow
!= val
)
1787 vm_exit_controls_init(vmx
, val
);
1790 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1792 return vmx
->vm_exit_controls_shadow
;
1796 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1798 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1801 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1803 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1806 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1808 vmx
->segment_cache
.bitmask
= 0;
1811 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1815 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1817 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1818 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1819 vmx
->segment_cache
.bitmask
= 0;
1821 ret
= vmx
->segment_cache
.bitmask
& mask
;
1822 vmx
->segment_cache
.bitmask
|= mask
;
1826 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1828 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1830 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1831 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1835 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1837 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1839 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1840 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1844 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1846 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1848 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1849 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1853 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1855 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1857 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1858 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1862 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1866 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1867 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1868 if ((vcpu
->guest_debug
&
1869 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1870 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1871 eb
|= 1u << BP_VECTOR
;
1872 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1875 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1877 /* When we are running a nested L2 guest and L1 specified for it a
1878 * certain exception bitmap, we must trap the same exceptions and pass
1879 * them to L1. When running L2, we will only handle the exceptions
1880 * specified above if L1 did not want them.
1882 if (is_guest_mode(vcpu
))
1883 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1885 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1888 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1889 unsigned long entry
, unsigned long exit
)
1891 vm_entry_controls_clearbit(vmx
, entry
);
1892 vm_exit_controls_clearbit(vmx
, exit
);
1895 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1898 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1902 if (cpu_has_load_ia32_efer
) {
1903 clear_atomic_switch_msr_special(vmx
,
1904 VM_ENTRY_LOAD_IA32_EFER
,
1905 VM_EXIT_LOAD_IA32_EFER
);
1909 case MSR_CORE_PERF_GLOBAL_CTRL
:
1910 if (cpu_has_load_perf_global_ctrl
) {
1911 clear_atomic_switch_msr_special(vmx
,
1912 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1913 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1919 for (i
= 0; i
< m
->nr
; ++i
)
1920 if (m
->guest
[i
].index
== msr
)
1926 m
->guest
[i
] = m
->guest
[m
->nr
];
1927 m
->host
[i
] = m
->host
[m
->nr
];
1928 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1929 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1932 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1933 unsigned long entry
, unsigned long exit
,
1934 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1935 u64 guest_val
, u64 host_val
)
1937 vmcs_write64(guest_val_vmcs
, guest_val
);
1938 vmcs_write64(host_val_vmcs
, host_val
);
1939 vm_entry_controls_setbit(vmx
, entry
);
1940 vm_exit_controls_setbit(vmx
, exit
);
1943 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1944 u64 guest_val
, u64 host_val
)
1947 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1951 if (cpu_has_load_ia32_efer
) {
1952 add_atomic_switch_msr_special(vmx
,
1953 VM_ENTRY_LOAD_IA32_EFER
,
1954 VM_EXIT_LOAD_IA32_EFER
,
1957 guest_val
, host_val
);
1961 case MSR_CORE_PERF_GLOBAL_CTRL
:
1962 if (cpu_has_load_perf_global_ctrl
) {
1963 add_atomic_switch_msr_special(vmx
,
1964 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1965 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1966 GUEST_IA32_PERF_GLOBAL_CTRL
,
1967 HOST_IA32_PERF_GLOBAL_CTRL
,
1968 guest_val
, host_val
);
1972 case MSR_IA32_PEBS_ENABLE
:
1973 /* PEBS needs a quiescent period after being disabled (to write
1974 * a record). Disabling PEBS through VMX MSR swapping doesn't
1975 * provide that period, so a CPU could write host's record into
1978 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1981 for (i
= 0; i
< m
->nr
; ++i
)
1982 if (m
->guest
[i
].index
== msr
)
1985 if (i
== NR_AUTOLOAD_MSRS
) {
1986 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1987 "Can't add msr %x\n", msr
);
1989 } else if (i
== m
->nr
) {
1991 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1992 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1995 m
->guest
[i
].index
= msr
;
1996 m
->guest
[i
].value
= guest_val
;
1997 m
->host
[i
].index
= msr
;
1998 m
->host
[i
].value
= host_val
;
2001 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2003 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2004 u64 ignore_bits
= 0;
2008 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2009 * host CPUID is more efficient than testing guest CPUID
2010 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2012 if (boot_cpu_has(X86_FEATURE_SMEP
))
2013 guest_efer
|= EFER_NX
;
2014 else if (!(guest_efer
& EFER_NX
))
2015 ignore_bits
|= EFER_NX
;
2019 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2021 ignore_bits
|= EFER_SCE
;
2022 #ifdef CONFIG_X86_64
2023 ignore_bits
|= EFER_LMA
| EFER_LME
;
2024 /* SCE is meaningful only in long mode on Intel */
2025 if (guest_efer
& EFER_LMA
)
2026 ignore_bits
&= ~(u64
)EFER_SCE
;
2029 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2032 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2033 * On CPUs that support "load IA32_EFER", always switch EFER
2034 * atomically, since it's faster than switching it manually.
2036 if (cpu_has_load_ia32_efer
||
2037 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2038 if (!(guest_efer
& EFER_LMA
))
2039 guest_efer
&= ~EFER_LME
;
2040 if (guest_efer
!= host_efer
)
2041 add_atomic_switch_msr(vmx
, MSR_EFER
,
2042 guest_efer
, host_efer
);
2045 guest_efer
&= ~ignore_bits
;
2046 guest_efer
|= host_efer
& ignore_bits
;
2048 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2049 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2055 #ifdef CONFIG_X86_32
2057 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2058 * VMCS rather than the segment table. KVM uses this helper to figure
2059 * out the current bases to poke them into the VMCS before entry.
2061 static unsigned long segment_base(u16 selector
)
2063 struct desc_struct
*table
;
2066 if (!(selector
& ~SEGMENT_RPL_MASK
))
2069 table
= get_current_gdt_ro();
2071 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2072 u16 ldt_selector
= kvm_read_ldt();
2074 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2077 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2079 v
= get_desc_base(&table
[selector
>> 3]);
2084 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2086 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2089 if (vmx
->host_state
.loaded
)
2092 vmx
->host_state
.loaded
= 1;
2094 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2095 * allow segment selectors with cpl > 0 or ti == 1.
2097 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2098 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2099 savesegment(fs
, vmx
->host_state
.fs_sel
);
2100 if (!(vmx
->host_state
.fs_sel
& 7)) {
2101 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2102 vmx
->host_state
.fs_reload_needed
= 0;
2104 vmcs_write16(HOST_FS_SELECTOR
, 0);
2105 vmx
->host_state
.fs_reload_needed
= 1;
2107 savesegment(gs
, vmx
->host_state
.gs_sel
);
2108 if (!(vmx
->host_state
.gs_sel
& 7))
2109 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2111 vmcs_write16(HOST_GS_SELECTOR
, 0);
2112 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2115 #ifdef CONFIG_X86_64
2116 savesegment(ds
, vmx
->host_state
.ds_sel
);
2117 savesegment(es
, vmx
->host_state
.es_sel
);
2120 #ifdef CONFIG_X86_64
2121 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2122 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2124 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2125 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2128 #ifdef CONFIG_X86_64
2129 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2130 if (is_long_mode(&vmx
->vcpu
))
2131 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2133 if (boot_cpu_has(X86_FEATURE_MPX
))
2134 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2135 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2136 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2137 vmx
->guest_msrs
[i
].data
,
2138 vmx
->guest_msrs
[i
].mask
);
2141 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2143 if (!vmx
->host_state
.loaded
)
2146 ++vmx
->vcpu
.stat
.host_state_reload
;
2147 vmx
->host_state
.loaded
= 0;
2148 #ifdef CONFIG_X86_64
2149 if (is_long_mode(&vmx
->vcpu
))
2150 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2152 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2153 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2154 #ifdef CONFIG_X86_64
2155 load_gs_index(vmx
->host_state
.gs_sel
);
2157 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2160 if (vmx
->host_state
.fs_reload_needed
)
2161 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2162 #ifdef CONFIG_X86_64
2163 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2164 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2165 loadsegment(es
, vmx
->host_state
.es_sel
);
2168 invalidate_tss_limit();
2169 #ifdef CONFIG_X86_64
2170 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2172 if (vmx
->host_state
.msr_host_bndcfgs
)
2173 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2174 load_fixmap_gdt(raw_smp_processor_id());
2177 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2180 __vmx_load_host_state(vmx
);
2184 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2186 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2187 struct pi_desc old
, new;
2190 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2191 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2192 !kvm_vcpu_apicv_active(vcpu
))
2196 old
.control
= new.control
= pi_desc
->control
;
2199 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2200 * are two possible cases:
2201 * 1. After running 'pre_block', context switch
2202 * happened. For this case, 'sn' was set in
2203 * vmx_vcpu_put(), so we need to clear it here.
2204 * 2. After running 'pre_block', we were blocked,
2205 * and woken up by some other guy. For this case,
2206 * we don't need to do anything, 'pi_post_block'
2207 * will do everything for us. However, we cannot
2208 * check whether it is case #1 or case #2 here
2209 * (maybe, not needed), so we also clear sn here,
2210 * I think it is not a big deal.
2212 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2213 if (vcpu
->cpu
!= cpu
) {
2214 dest
= cpu_physical_id(cpu
);
2216 if (x2apic_enabled())
2219 new.ndst
= (dest
<< 8) & 0xFF00;
2222 /* set 'NV' to 'notification vector' */
2223 new.nv
= POSTED_INTR_VECTOR
;
2226 /* Allow posting non-urgent interrupts */
2228 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2229 new.control
) != old
.control
);
2232 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2234 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2235 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2239 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2240 * vcpu mutex is already taken.
2242 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2244 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2245 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2247 if (!already_loaded
) {
2248 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2249 local_irq_disable();
2250 crash_disable_local_vmclear(cpu
);
2253 * Read loaded_vmcs->cpu should be before fetching
2254 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2255 * See the comments in __loaded_vmcs_clear().
2259 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2260 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2261 crash_enable_local_vmclear(cpu
);
2265 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2266 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2267 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2270 if (!already_loaded
) {
2271 void *gdt
= get_current_gdt_ro();
2272 unsigned long sysenter_esp
;
2274 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2277 * Linux uses per-cpu TSS and GDT, so set these when switching
2278 * processors. See 22.2.4.
2280 vmcs_writel(HOST_TR_BASE
,
2281 (unsigned long)this_cpu_ptr(&cpu_tss
));
2282 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2285 * VM exits change the host TR limit to 0x67 after a VM
2286 * exit. This is okay, since 0x67 covers everything except
2287 * the IO bitmap and have have code to handle the IO bitmap
2288 * being lost after a VM exit.
2290 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2292 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2293 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2295 vmx
->loaded_vmcs
->cpu
= cpu
;
2298 /* Setup TSC multiplier */
2299 if (kvm_has_tsc_control
&&
2300 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2301 decache_tsc_multiplier(vmx
);
2303 vmx_vcpu_pi_load(vcpu
, cpu
);
2304 vmx
->host_pkru
= read_pkru();
2307 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2309 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2311 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2312 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2313 !kvm_vcpu_apicv_active(vcpu
))
2316 /* Set SN when the vCPU is preempted */
2317 if (vcpu
->preempted
)
2321 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2323 vmx_vcpu_pi_put(vcpu
);
2325 __vmx_load_host_state(to_vmx(vcpu
));
2328 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2331 * Return the cr0 value that a nested guest would read. This is a combination
2332 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2333 * its hypervisor (cr0_read_shadow).
2335 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2337 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2338 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2340 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2342 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2343 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2346 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2348 unsigned long rflags
, save_rflags
;
2350 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2351 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2352 rflags
= vmcs_readl(GUEST_RFLAGS
);
2353 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2354 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2355 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2356 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2358 to_vmx(vcpu
)->rflags
= rflags
;
2360 return to_vmx(vcpu
)->rflags
;
2363 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2365 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2366 to_vmx(vcpu
)->rflags
= rflags
;
2367 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2368 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2369 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2371 vmcs_writel(GUEST_RFLAGS
, rflags
);
2374 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2376 return to_vmx(vcpu
)->guest_pkru
;
2379 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2381 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2384 if (interruptibility
& GUEST_INTR_STATE_STI
)
2385 ret
|= KVM_X86_SHADOW_INT_STI
;
2386 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2387 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2392 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2394 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2395 u32 interruptibility
= interruptibility_old
;
2397 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2399 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2400 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2401 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2402 interruptibility
|= GUEST_INTR_STATE_STI
;
2404 if ((interruptibility
!= interruptibility_old
))
2405 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2408 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2412 rip
= kvm_rip_read(vcpu
);
2413 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2414 kvm_rip_write(vcpu
, rip
);
2416 /* skipping an emulated instruction also counts */
2417 vmx_set_interrupt_shadow(vcpu
, 0);
2421 * KVM wants to inject page-faults which it got to the guest. This function
2422 * checks whether in a nested guest, we need to inject them to L1 or L2.
2424 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2426 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2428 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2431 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
2432 vmcs_read32(VM_EXIT_INTR_INFO
),
2433 vmcs_readl(EXIT_QUALIFICATION
));
2437 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2438 bool has_error_code
, u32 error_code
,
2441 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2442 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2444 if (!reinject
&& is_guest_mode(vcpu
) &&
2445 nested_vmx_check_exception(vcpu
, nr
))
2448 if (has_error_code
) {
2449 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2450 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2453 if (vmx
->rmode
.vm86_active
) {
2455 if (kvm_exception_is_soft(nr
))
2456 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2457 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2458 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2462 if (kvm_exception_is_soft(nr
)) {
2463 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2464 vmx
->vcpu
.arch
.event_exit_inst_len
);
2465 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2467 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2469 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2472 static bool vmx_rdtscp_supported(void)
2474 return cpu_has_vmx_rdtscp();
2477 static bool vmx_invpcid_supported(void)
2479 return cpu_has_vmx_invpcid() && enable_ept
;
2483 * Swap MSR entry in host/guest MSR entry array.
2485 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2487 struct shared_msr_entry tmp
;
2489 tmp
= vmx
->guest_msrs
[to
];
2490 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2491 vmx
->guest_msrs
[from
] = tmp
;
2494 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2496 unsigned long *msr_bitmap
;
2498 if (is_guest_mode(vcpu
))
2499 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2500 else if (cpu_has_secondary_exec_ctrls() &&
2501 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2502 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2503 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2504 if (is_long_mode(vcpu
))
2505 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2507 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2509 if (is_long_mode(vcpu
))
2510 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2512 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2515 if (is_long_mode(vcpu
))
2516 msr_bitmap
= vmx_msr_bitmap_longmode
;
2518 msr_bitmap
= vmx_msr_bitmap_legacy
;
2521 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2525 * Set up the vmcs to automatically save and restore system
2526 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2527 * mode, as fiddling with msrs is very expensive.
2529 static void setup_msrs(struct vcpu_vmx
*vmx
)
2531 int save_nmsrs
, index
;
2534 #ifdef CONFIG_X86_64
2535 if (is_long_mode(&vmx
->vcpu
)) {
2536 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2538 move_msr_up(vmx
, index
, save_nmsrs
++);
2539 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2541 move_msr_up(vmx
, index
, save_nmsrs
++);
2542 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2544 move_msr_up(vmx
, index
, save_nmsrs
++);
2545 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2546 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2547 move_msr_up(vmx
, index
, save_nmsrs
++);
2549 * MSR_STAR is only needed on long mode guests, and only
2550 * if efer.sce is enabled.
2552 index
= __find_msr_index(vmx
, MSR_STAR
);
2553 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2554 move_msr_up(vmx
, index
, save_nmsrs
++);
2557 index
= __find_msr_index(vmx
, MSR_EFER
);
2558 if (index
>= 0 && update_transition_efer(vmx
, index
))
2559 move_msr_up(vmx
, index
, save_nmsrs
++);
2561 vmx
->save_nmsrs
= save_nmsrs
;
2563 if (cpu_has_vmx_msr_bitmap())
2564 vmx_set_msr_bitmap(&vmx
->vcpu
);
2568 * reads and returns guest's timestamp counter "register"
2569 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2570 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2572 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2574 u64 host_tsc
, tsc_offset
;
2577 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2578 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2582 * writes 'offset' into guest's timestamp counter offset register
2584 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2586 if (is_guest_mode(vcpu
)) {
2588 * We're here if L1 chose not to trap WRMSR to TSC. According
2589 * to the spec, this should set L1's TSC; The offset that L1
2590 * set for L2 remains unchanged, and still needs to be added
2591 * to the newly set TSC to get L2's TSC.
2593 struct vmcs12
*vmcs12
;
2594 /* recalculate vmcs02.TSC_OFFSET: */
2595 vmcs12
= get_vmcs12(vcpu
);
2596 vmcs_write64(TSC_OFFSET
, offset
+
2597 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2598 vmcs12
->tsc_offset
: 0));
2600 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2601 vmcs_read64(TSC_OFFSET
), offset
);
2602 vmcs_write64(TSC_OFFSET
, offset
);
2606 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2608 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2609 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2613 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2614 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2615 * all guests if the "nested" module option is off, and can also be disabled
2616 * for a single guest by disabling its VMX cpuid bit.
2618 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2620 return nested
&& guest_cpuid_has_vmx(vcpu
);
2624 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2625 * returned for the various VMX controls MSRs when nested VMX is enabled.
2626 * The same values should also be used to verify that vmcs12 control fields are
2627 * valid during nested entry from L1 to L2.
2628 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2629 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2630 * bit in the high half is on if the corresponding bit in the control field
2631 * may be on. See also vmx_control_verify().
2633 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2636 * Note that as a general rule, the high half of the MSRs (bits in
2637 * the control fields which may be 1) should be initialized by the
2638 * intersection of the underlying hardware's MSR (i.e., features which
2639 * can be supported) and the list of features we want to expose -
2640 * because they are known to be properly supported in our code.
2641 * Also, usually, the low half of the MSRs (bits which must be 1) can
2642 * be set to 0, meaning that L1 may turn off any of these bits. The
2643 * reason is that if one of these bits is necessary, it will appear
2644 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2645 * fields of vmcs01 and vmcs02, will turn these bits off - and
2646 * nested_vmx_exit_handled() will not pass related exits to L1.
2647 * These rules have exceptions below.
2650 /* pin-based controls */
2651 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2652 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2653 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2654 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2655 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2656 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2657 PIN_BASED_EXT_INTR_MASK
|
2658 PIN_BASED_NMI_EXITING
|
2659 PIN_BASED_VIRTUAL_NMIS
;
2660 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2661 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2662 PIN_BASED_VMX_PREEMPTION_TIMER
;
2663 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2664 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2665 PIN_BASED_POSTED_INTR
;
2668 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2669 vmx
->nested
.nested_vmx_exit_ctls_low
,
2670 vmx
->nested
.nested_vmx_exit_ctls_high
);
2671 vmx
->nested
.nested_vmx_exit_ctls_low
=
2672 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2674 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2675 #ifdef CONFIG_X86_64
2676 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2678 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2679 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2680 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2681 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2682 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2684 if (kvm_mpx_supported())
2685 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2687 /* We support free control of debug control saving. */
2688 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2690 /* entry controls */
2691 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2692 vmx
->nested
.nested_vmx_entry_ctls_low
,
2693 vmx
->nested
.nested_vmx_entry_ctls_high
);
2694 vmx
->nested
.nested_vmx_entry_ctls_low
=
2695 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2696 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2697 #ifdef CONFIG_X86_64
2698 VM_ENTRY_IA32E_MODE
|
2700 VM_ENTRY_LOAD_IA32_PAT
;
2701 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2702 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2703 if (kvm_mpx_supported())
2704 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2706 /* We support free control of debug control loading. */
2707 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2709 /* cpu-based controls */
2710 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2711 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2712 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2713 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2714 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2715 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2716 CPU_BASED_VIRTUAL_INTR_PENDING
|
2717 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2718 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2719 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2720 CPU_BASED_CR3_STORE_EXITING
|
2721 #ifdef CONFIG_X86_64
2722 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2724 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2725 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2726 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2727 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2728 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2730 * We can allow some features even when not supported by the
2731 * hardware. For example, L1 can specify an MSR bitmap - and we
2732 * can use it to avoid exits to L1 - even when L0 runs L2
2733 * without MSR bitmaps.
2735 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2736 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2737 CPU_BASED_USE_MSR_BITMAPS
;
2739 /* We support free control of CR3 access interception. */
2740 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2741 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2743 /* secondary cpu-based controls */
2744 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2745 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2746 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2747 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2748 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2749 SECONDARY_EXEC_RDRAND
| SECONDARY_EXEC_RDSEED
|
2750 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2751 SECONDARY_EXEC_RDTSCP
|
2752 SECONDARY_EXEC_DESC
|
2753 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2754 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2755 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2756 SECONDARY_EXEC_WBINVD_EXITING
|
2757 SECONDARY_EXEC_XSAVES
;
2760 /* nested EPT: emulate EPT also to L1 */
2761 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2762 SECONDARY_EXEC_ENABLE_EPT
;
2763 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2764 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2765 if (cpu_has_vmx_ept_execute_only())
2766 vmx
->nested
.nested_vmx_ept_caps
|=
2767 VMX_EPT_EXECUTE_ONLY_BIT
;
2768 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2769 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2770 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2771 VMX_EPT_1GB_PAGE_BIT
;
2772 if (enable_ept_ad_bits
) {
2773 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2774 SECONDARY_EXEC_ENABLE_PML
;
2775 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2778 vmx
->nested
.nested_vmx_ept_caps
= 0;
2781 * Old versions of KVM use the single-context version without
2782 * checking for support, so declare that it is supported even
2783 * though it is treated as global context. The alternative is
2784 * not failing the single-context invvpid, and it is worse.
2787 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2788 SECONDARY_EXEC_ENABLE_VPID
;
2789 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2790 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2792 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2794 if (enable_unrestricted_guest
)
2795 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2796 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2798 /* miscellaneous data */
2799 rdmsr(MSR_IA32_VMX_MISC
,
2800 vmx
->nested
.nested_vmx_misc_low
,
2801 vmx
->nested
.nested_vmx_misc_high
);
2802 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2803 vmx
->nested
.nested_vmx_misc_low
|=
2804 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2805 VMX_MISC_ACTIVITY_HLT
;
2806 vmx
->nested
.nested_vmx_misc_high
= 0;
2809 * This MSR reports some information about VMX support. We
2810 * should return information about the VMX we emulate for the
2811 * guest, and the VMCS structure we give it - not about the
2812 * VMX support of the underlying hardware.
2814 vmx
->nested
.nested_vmx_basic
=
2816 VMX_BASIC_TRUE_CTLS
|
2817 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2818 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2820 if (cpu_has_vmx_basic_inout())
2821 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2824 * These MSRs specify bits which the guest must keep fixed on
2825 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2826 * We picked the standard core2 setting.
2828 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2829 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2830 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2831 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2833 /* These MSRs specify bits which the guest must keep fixed off. */
2834 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2835 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2837 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2838 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2842 * if fixed0[i] == 1: val[i] must be 1
2843 * if fixed1[i] == 0: val[i] must be 0
2845 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2847 return ((val
& fixed1
) | fixed0
) == val
;
2850 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2852 return fixed_bits_valid(control
, low
, high
);
2855 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2857 return low
| ((u64
)high
<< 32);
2860 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2865 return (superset
| subset
) == superset
;
2868 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2870 const u64 feature_and_reserved
=
2871 /* feature (except bit 48; see below) */
2872 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2874 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2875 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2877 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2881 * KVM does not emulate a version of VMX that constrains physical
2882 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2884 if (data
& BIT_ULL(48))
2887 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2888 vmx_basic_vmcs_revision_id(data
))
2891 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2894 vmx
->nested
.nested_vmx_basic
= data
;
2899 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2904 switch (msr_index
) {
2905 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2906 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2907 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2909 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2910 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2911 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2913 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2914 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2915 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2917 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2918 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2919 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2921 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2922 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2923 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2929 supported
= vmx_control_msr(*lowp
, *highp
);
2931 /* Check must-be-1 bits are still 1. */
2932 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
2935 /* Check must-be-0 bits are still 0. */
2936 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
2940 *highp
= data
>> 32;
2944 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
2946 const u64 feature_and_reserved_bits
=
2948 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2949 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2951 GENMASK_ULL(13, 9) | BIT_ULL(31);
2954 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
2955 vmx
->nested
.nested_vmx_misc_high
);
2957 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
2960 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
2961 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
2962 vmx_misc_preemption_timer_rate(data
) !=
2963 vmx_misc_preemption_timer_rate(vmx_misc
))
2966 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
2969 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
2972 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
2975 vmx
->nested
.nested_vmx_misc_low
= data
;
2976 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
2980 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
2982 u64 vmx_ept_vpid_cap
;
2984 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
2985 vmx
->nested
.nested_vmx_vpid_caps
);
2987 /* Every bit is either reserved or a feature bit. */
2988 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
2991 vmx
->nested
.nested_vmx_ept_caps
= data
;
2992 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
2996 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3000 switch (msr_index
) {
3001 case MSR_IA32_VMX_CR0_FIXED0
:
3002 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3004 case MSR_IA32_VMX_CR4_FIXED0
:
3005 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3012 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3013 * must be 1 in the restored value.
3015 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3023 * Called when userspace is restoring VMX MSRs.
3025 * Returns 0 on success, non-0 otherwise.
3027 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3029 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3031 switch (msr_index
) {
3032 case MSR_IA32_VMX_BASIC
:
3033 return vmx_restore_vmx_basic(vmx
, data
);
3034 case MSR_IA32_VMX_PINBASED_CTLS
:
3035 case MSR_IA32_VMX_PROCBASED_CTLS
:
3036 case MSR_IA32_VMX_EXIT_CTLS
:
3037 case MSR_IA32_VMX_ENTRY_CTLS
:
3039 * The "non-true" VMX capability MSRs are generated from the
3040 * "true" MSRs, so we do not support restoring them directly.
3042 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3043 * should restore the "true" MSRs with the must-be-1 bits
3044 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3045 * DEFAULT SETTINGS".
3048 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3049 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3050 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3051 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3052 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3053 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3054 case MSR_IA32_VMX_MISC
:
3055 return vmx_restore_vmx_misc(vmx
, data
);
3056 case MSR_IA32_VMX_CR0_FIXED0
:
3057 case MSR_IA32_VMX_CR4_FIXED0
:
3058 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3059 case MSR_IA32_VMX_CR0_FIXED1
:
3060 case MSR_IA32_VMX_CR4_FIXED1
:
3062 * These MSRs are generated based on the vCPU's CPUID, so we
3063 * do not support restoring them directly.
3066 case MSR_IA32_VMX_EPT_VPID_CAP
:
3067 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3068 case MSR_IA32_VMX_VMCS_ENUM
:
3069 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3073 * The rest of the VMX capability MSRs do not support restore.
3079 /* Returns 0 on success, non-0 otherwise. */
3080 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3082 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3084 switch (msr_index
) {
3085 case MSR_IA32_VMX_BASIC
:
3086 *pdata
= vmx
->nested
.nested_vmx_basic
;
3088 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3089 case MSR_IA32_VMX_PINBASED_CTLS
:
3090 *pdata
= vmx_control_msr(
3091 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3092 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3093 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3094 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3096 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3097 case MSR_IA32_VMX_PROCBASED_CTLS
:
3098 *pdata
= vmx_control_msr(
3099 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3100 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3101 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3102 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3104 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3105 case MSR_IA32_VMX_EXIT_CTLS
:
3106 *pdata
= vmx_control_msr(
3107 vmx
->nested
.nested_vmx_exit_ctls_low
,
3108 vmx
->nested
.nested_vmx_exit_ctls_high
);
3109 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3110 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3112 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3113 case MSR_IA32_VMX_ENTRY_CTLS
:
3114 *pdata
= vmx_control_msr(
3115 vmx
->nested
.nested_vmx_entry_ctls_low
,
3116 vmx
->nested
.nested_vmx_entry_ctls_high
);
3117 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3118 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3120 case MSR_IA32_VMX_MISC
:
3121 *pdata
= vmx_control_msr(
3122 vmx
->nested
.nested_vmx_misc_low
,
3123 vmx
->nested
.nested_vmx_misc_high
);
3125 case MSR_IA32_VMX_CR0_FIXED0
:
3126 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3128 case MSR_IA32_VMX_CR0_FIXED1
:
3129 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3131 case MSR_IA32_VMX_CR4_FIXED0
:
3132 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3134 case MSR_IA32_VMX_CR4_FIXED1
:
3135 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3137 case MSR_IA32_VMX_VMCS_ENUM
:
3138 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3140 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3141 *pdata
= vmx_control_msr(
3142 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3143 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3145 case MSR_IA32_VMX_EPT_VPID_CAP
:
3146 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3147 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3156 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3159 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3161 return !(val
& ~valid_bits
);
3165 * Reads an msr value (of 'msr_index') into 'pdata'.
3166 * Returns 0 on success, non-0 otherwise.
3167 * Assumes vcpu_load() was already called.
3169 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3171 struct shared_msr_entry
*msr
;
3173 switch (msr_info
->index
) {
3174 #ifdef CONFIG_X86_64
3176 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3179 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3181 case MSR_KERNEL_GS_BASE
:
3182 vmx_load_host_state(to_vmx(vcpu
));
3183 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3187 return kvm_get_msr_common(vcpu
, msr_info
);
3189 msr_info
->data
= guest_read_tsc(vcpu
);
3191 case MSR_IA32_SYSENTER_CS
:
3192 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3194 case MSR_IA32_SYSENTER_EIP
:
3195 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3197 case MSR_IA32_SYSENTER_ESP
:
3198 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3200 case MSR_IA32_BNDCFGS
:
3201 if (!kvm_mpx_supported())
3203 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3205 case MSR_IA32_MCG_EXT_CTL
:
3206 if (!msr_info
->host_initiated
&&
3207 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3208 FEATURE_CONTROL_LMCE
))
3210 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3212 case MSR_IA32_FEATURE_CONTROL
:
3213 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3215 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3216 if (!nested_vmx_allowed(vcpu
))
3218 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3220 if (!vmx_xsaves_supported())
3222 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3225 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3227 /* Otherwise falls through */
3229 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3231 msr_info
->data
= msr
->data
;
3234 return kvm_get_msr_common(vcpu
, msr_info
);
3240 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3243 * Writes msr value into into the appropriate "register".
3244 * Returns 0 on success, non-0 otherwise.
3245 * Assumes vcpu_load() was already called.
3247 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3249 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3250 struct shared_msr_entry
*msr
;
3252 u32 msr_index
= msr_info
->index
;
3253 u64 data
= msr_info
->data
;
3255 switch (msr_index
) {
3257 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3259 #ifdef CONFIG_X86_64
3261 vmx_segment_cache_clear(vmx
);
3262 vmcs_writel(GUEST_FS_BASE
, data
);
3265 vmx_segment_cache_clear(vmx
);
3266 vmcs_writel(GUEST_GS_BASE
, data
);
3268 case MSR_KERNEL_GS_BASE
:
3269 vmx_load_host_state(vmx
);
3270 vmx
->msr_guest_kernel_gs_base
= data
;
3273 case MSR_IA32_SYSENTER_CS
:
3274 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3276 case MSR_IA32_SYSENTER_EIP
:
3277 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3279 case MSR_IA32_SYSENTER_ESP
:
3280 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3282 case MSR_IA32_BNDCFGS
:
3283 if (!kvm_mpx_supported())
3285 vmcs_write64(GUEST_BNDCFGS
, data
);
3288 kvm_write_tsc(vcpu
, msr_info
);
3290 case MSR_IA32_CR_PAT
:
3291 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3292 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3294 vmcs_write64(GUEST_IA32_PAT
, data
);
3295 vcpu
->arch
.pat
= data
;
3298 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3300 case MSR_IA32_TSC_ADJUST
:
3301 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3303 case MSR_IA32_MCG_EXT_CTL
:
3304 if ((!msr_info
->host_initiated
&&
3305 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3306 FEATURE_CONTROL_LMCE
)) ||
3307 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3309 vcpu
->arch
.mcg_ext_ctl
= data
;
3311 case MSR_IA32_FEATURE_CONTROL
:
3312 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3313 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3314 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3316 vmx
->msr_ia32_feature_control
= data
;
3317 if (msr_info
->host_initiated
&& data
== 0)
3318 vmx_leave_nested(vcpu
);
3320 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3321 if (!msr_info
->host_initiated
)
3322 return 1; /* they are read-only */
3323 if (!nested_vmx_allowed(vcpu
))
3325 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3327 if (!vmx_xsaves_supported())
3330 * The only supported bit as of Skylake is bit 8, but
3331 * it is not supported on KVM.
3335 vcpu
->arch
.ia32_xss
= data
;
3336 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3337 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3338 vcpu
->arch
.ia32_xss
, host_xss
);
3340 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3343 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3345 /* Check reserved bit, higher 32 bits should be zero */
3346 if ((data
>> 32) != 0)
3348 /* Otherwise falls through */
3350 msr
= find_msr_entry(vmx
, msr_index
);
3352 u64 old_msr_data
= msr
->data
;
3354 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3356 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3360 msr
->data
= old_msr_data
;
3364 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3370 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3372 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3375 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3378 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3380 case VCPU_EXREG_PDPTR
:
3382 ept_save_pdptrs(vcpu
);
3389 static __init
int cpu_has_kvm_support(void)
3391 return cpu_has_vmx();
3394 static __init
int vmx_disabled_by_bios(void)
3398 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3399 if (msr
& FEATURE_CONTROL_LOCKED
) {
3400 /* launched w/ TXT and VMX disabled */
3401 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3404 /* launched w/o TXT and VMX only enabled w/ TXT */
3405 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3406 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3407 && !tboot_enabled()) {
3408 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3409 "activate TXT before enabling KVM\n");
3412 /* launched w/o TXT and VMX disabled */
3413 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3414 && !tboot_enabled())
3421 static void kvm_cpu_vmxon(u64 addr
)
3423 cr4_set_bits(X86_CR4_VMXE
);
3424 intel_pt_handle_vmx(1);
3426 asm volatile (ASM_VMX_VMXON_RAX
3427 : : "a"(&addr
), "m"(addr
)
3431 static int hardware_enable(void)
3433 int cpu
= raw_smp_processor_id();
3434 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3437 if (cr4_read_shadow() & X86_CR4_VMXE
)
3440 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3441 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3442 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3445 * Now we can enable the vmclear operation in kdump
3446 * since the loaded_vmcss_on_cpu list on this cpu
3447 * has been initialized.
3449 * Though the cpu is not in VMX operation now, there
3450 * is no problem to enable the vmclear operation
3451 * for the loaded_vmcss_on_cpu list is empty!
3453 crash_enable_local_vmclear(cpu
);
3455 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3457 test_bits
= FEATURE_CONTROL_LOCKED
;
3458 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3459 if (tboot_enabled())
3460 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3462 if ((old
& test_bits
) != test_bits
) {
3463 /* enable and lock */
3464 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3466 kvm_cpu_vmxon(phys_addr
);
3472 static void vmclear_local_loaded_vmcss(void)
3474 int cpu
= raw_smp_processor_id();
3475 struct loaded_vmcs
*v
, *n
;
3477 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3478 loaded_vmcss_on_cpu_link
)
3479 __loaded_vmcs_clear(v
);
3483 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3486 static void kvm_cpu_vmxoff(void)
3488 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3490 intel_pt_handle_vmx(0);
3491 cr4_clear_bits(X86_CR4_VMXE
);
3494 static void hardware_disable(void)
3496 vmclear_local_loaded_vmcss();
3500 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3501 u32 msr
, u32
*result
)
3503 u32 vmx_msr_low
, vmx_msr_high
;
3504 u32 ctl
= ctl_min
| ctl_opt
;
3506 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3508 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3509 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3511 /* Ensure minimum (required) set of control bits are supported. */
3519 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3521 u32 vmx_msr_low
, vmx_msr_high
;
3523 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3524 return vmx_msr_high
& ctl
;
3527 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3529 u32 vmx_msr_low
, vmx_msr_high
;
3530 u32 min
, opt
, min2
, opt2
;
3531 u32 _pin_based_exec_control
= 0;
3532 u32 _cpu_based_exec_control
= 0;
3533 u32 _cpu_based_2nd_exec_control
= 0;
3534 u32 _vmexit_control
= 0;
3535 u32 _vmentry_control
= 0;
3537 min
= CPU_BASED_HLT_EXITING
|
3538 #ifdef CONFIG_X86_64
3539 CPU_BASED_CR8_LOAD_EXITING
|
3540 CPU_BASED_CR8_STORE_EXITING
|
3542 CPU_BASED_CR3_LOAD_EXITING
|
3543 CPU_BASED_CR3_STORE_EXITING
|
3544 CPU_BASED_USE_IO_BITMAPS
|
3545 CPU_BASED_MOV_DR_EXITING
|
3546 CPU_BASED_USE_TSC_OFFSETING
|
3547 CPU_BASED_INVLPG_EXITING
|
3548 CPU_BASED_RDPMC_EXITING
;
3550 if (!kvm_mwait_in_guest())
3551 min
|= CPU_BASED_MWAIT_EXITING
|
3552 CPU_BASED_MONITOR_EXITING
;
3554 opt
= CPU_BASED_TPR_SHADOW
|
3555 CPU_BASED_USE_MSR_BITMAPS
|
3556 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3557 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3558 &_cpu_based_exec_control
) < 0)
3560 #ifdef CONFIG_X86_64
3561 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3562 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3563 ~CPU_BASED_CR8_STORE_EXITING
;
3565 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3567 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3568 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3569 SECONDARY_EXEC_WBINVD_EXITING
|
3570 SECONDARY_EXEC_ENABLE_VPID
|
3571 SECONDARY_EXEC_ENABLE_EPT
|
3572 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3573 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3574 SECONDARY_EXEC_RDTSCP
|
3575 SECONDARY_EXEC_ENABLE_INVPCID
|
3576 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3577 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3578 SECONDARY_EXEC_SHADOW_VMCS
|
3579 SECONDARY_EXEC_XSAVES
|
3580 SECONDARY_EXEC_ENABLE_PML
|
3581 SECONDARY_EXEC_TSC_SCALING
;
3582 if (adjust_vmx_controls(min2
, opt2
,
3583 MSR_IA32_VMX_PROCBASED_CTLS2
,
3584 &_cpu_based_2nd_exec_control
) < 0)
3587 #ifndef CONFIG_X86_64
3588 if (!(_cpu_based_2nd_exec_control
&
3589 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3590 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3593 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3594 _cpu_based_2nd_exec_control
&= ~(
3595 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3596 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3597 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3599 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3600 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3602 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3603 CPU_BASED_CR3_STORE_EXITING
|
3604 CPU_BASED_INVLPG_EXITING
);
3605 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3606 vmx_capability
.ept
, vmx_capability
.vpid
);
3609 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3610 #ifdef CONFIG_X86_64
3611 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3613 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3614 VM_EXIT_CLEAR_BNDCFGS
;
3615 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3616 &_vmexit_control
) < 0)
3619 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
3620 PIN_BASED_VIRTUAL_NMIS
;
3621 opt
= PIN_BASED_POSTED_INTR
| PIN_BASED_VMX_PREEMPTION_TIMER
;
3622 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3623 &_pin_based_exec_control
) < 0)
3626 if (cpu_has_broken_vmx_preemption_timer())
3627 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3628 if (!(_cpu_based_2nd_exec_control
&
3629 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3630 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3632 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3633 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3634 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3635 &_vmentry_control
) < 0)
3638 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3640 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3641 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3644 #ifdef CONFIG_X86_64
3645 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3646 if (vmx_msr_high
& (1u<<16))
3650 /* Require Write-Back (WB) memory type for VMCS accesses. */
3651 if (((vmx_msr_high
>> 18) & 15) != 6)
3654 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3655 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3656 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3657 vmcs_conf
->revision_id
= vmx_msr_low
;
3659 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3660 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3661 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3662 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3663 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3665 cpu_has_load_ia32_efer
=
3666 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3667 VM_ENTRY_LOAD_IA32_EFER
)
3668 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3669 VM_EXIT_LOAD_IA32_EFER
);
3671 cpu_has_load_perf_global_ctrl
=
3672 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3673 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3674 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3675 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3678 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3679 * but due to errata below it can't be used. Workaround is to use
3680 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3682 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3687 * BC86,AAY89,BD102 (model 44)
3691 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3692 switch (boot_cpu_data
.x86_model
) {
3698 cpu_has_load_perf_global_ctrl
= false;
3699 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3700 "does not work properly. Using workaround\n");
3707 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3708 rdmsrl(MSR_IA32_XSS
, host_xss
);
3713 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3715 int node
= cpu_to_node(cpu
);
3719 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3722 vmcs
= page_address(pages
);
3723 memset(vmcs
, 0, vmcs_config
.size
);
3724 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3728 static struct vmcs
*alloc_vmcs(void)
3730 return alloc_vmcs_cpu(raw_smp_processor_id());
3733 static void free_vmcs(struct vmcs
*vmcs
)
3735 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3739 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3741 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3743 if (!loaded_vmcs
->vmcs
)
3745 loaded_vmcs_clear(loaded_vmcs
);
3746 free_vmcs(loaded_vmcs
->vmcs
);
3747 loaded_vmcs
->vmcs
= NULL
;
3748 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3751 static void free_kvm_area(void)
3755 for_each_possible_cpu(cpu
) {
3756 free_vmcs(per_cpu(vmxarea
, cpu
));
3757 per_cpu(vmxarea
, cpu
) = NULL
;
3761 static void init_vmcs_shadow_fields(void)
3765 /* No checks for read only fields yet */
3767 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3768 switch (shadow_read_write_fields
[i
]) {
3770 if (!kvm_mpx_supported())
3778 shadow_read_write_fields
[j
] =
3779 shadow_read_write_fields
[i
];
3782 max_shadow_read_write_fields
= j
;
3784 /* shadowed fields guest access without vmexit */
3785 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3786 clear_bit(shadow_read_write_fields
[i
],
3787 vmx_vmwrite_bitmap
);
3788 clear_bit(shadow_read_write_fields
[i
],
3791 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3792 clear_bit(shadow_read_only_fields
[i
],
3796 static __init
int alloc_kvm_area(void)
3800 for_each_possible_cpu(cpu
) {
3803 vmcs
= alloc_vmcs_cpu(cpu
);
3809 per_cpu(vmxarea
, cpu
) = vmcs
;
3814 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3816 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3819 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3820 struct kvm_segment
*save
)
3822 if (!emulate_invalid_guest_state
) {
3824 * CS and SS RPL should be equal during guest entry according
3825 * to VMX spec, but in reality it is not always so. Since vcpu
3826 * is in the middle of the transition from real mode to
3827 * protected mode it is safe to assume that RPL 0 is a good
3830 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3831 save
->selector
&= ~SEGMENT_RPL_MASK
;
3832 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3835 vmx_set_segment(vcpu
, save
, seg
);
3838 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3840 unsigned long flags
;
3841 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3844 * Update real mode segment cache. It may be not up-to-date if sement
3845 * register was written while vcpu was in a guest mode.
3847 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3848 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3849 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3850 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3851 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3852 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3854 vmx
->rmode
.vm86_active
= 0;
3856 vmx_segment_cache_clear(vmx
);
3858 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3860 flags
= vmcs_readl(GUEST_RFLAGS
);
3861 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3862 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3863 vmcs_writel(GUEST_RFLAGS
, flags
);
3865 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3866 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3868 update_exception_bitmap(vcpu
);
3870 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3871 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3872 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3873 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3874 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3875 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3878 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3880 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3881 struct kvm_segment var
= *save
;
3884 if (seg
== VCPU_SREG_CS
)
3887 if (!emulate_invalid_guest_state
) {
3888 var
.selector
= var
.base
>> 4;
3889 var
.base
= var
.base
& 0xffff0;
3899 if (save
->base
& 0xf)
3900 printk_once(KERN_WARNING
"kvm: segment base is not "
3901 "paragraph aligned when entering "
3902 "protected mode (seg=%d)", seg
);
3905 vmcs_write16(sf
->selector
, var
.selector
);
3906 vmcs_writel(sf
->base
, var
.base
);
3907 vmcs_write32(sf
->limit
, var
.limit
);
3908 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3911 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3913 unsigned long flags
;
3914 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3916 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3917 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3918 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3919 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3920 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3921 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3922 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3924 vmx
->rmode
.vm86_active
= 1;
3927 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3928 * vcpu. Warn the user that an update is overdue.
3930 if (!vcpu
->kvm
->arch
.tss_addr
)
3931 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3932 "called before entering vcpu\n");
3934 vmx_segment_cache_clear(vmx
);
3936 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3937 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3938 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3940 flags
= vmcs_readl(GUEST_RFLAGS
);
3941 vmx
->rmode
.save_rflags
= flags
;
3943 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3945 vmcs_writel(GUEST_RFLAGS
, flags
);
3946 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3947 update_exception_bitmap(vcpu
);
3949 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3950 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3951 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3952 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3953 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3954 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3956 kvm_mmu_reset_context(vcpu
);
3959 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3961 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3962 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3968 * Force kernel_gs_base reloading before EFER changes, as control
3969 * of this msr depends on is_long_mode().
3971 vmx_load_host_state(to_vmx(vcpu
));
3972 vcpu
->arch
.efer
= efer
;
3973 if (efer
& EFER_LMA
) {
3974 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3977 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3979 msr
->data
= efer
& ~EFER_LME
;
3984 #ifdef CONFIG_X86_64
3986 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3990 vmx_segment_cache_clear(to_vmx(vcpu
));
3992 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3993 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3994 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3996 vmcs_write32(GUEST_TR_AR_BYTES
,
3997 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3998 | VMX_AR_TYPE_BUSY_64_TSS
);
4000 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4003 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4005 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4006 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4011 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4014 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4016 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
4018 vpid_sync_context(vpid
);
4022 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4024 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4027 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4030 vmx_flush_tlb(vcpu
);
4033 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4035 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4037 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4038 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4041 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4043 if (enable_ept
&& is_paging(vcpu
))
4044 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4045 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4048 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4050 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4052 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4053 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4056 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4058 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4060 if (!test_bit(VCPU_EXREG_PDPTR
,
4061 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4064 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4065 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4066 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4067 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4068 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4072 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4074 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4076 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4077 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4078 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4079 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4080 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4083 __set_bit(VCPU_EXREG_PDPTR
,
4084 (unsigned long *)&vcpu
->arch
.regs_avail
);
4085 __set_bit(VCPU_EXREG_PDPTR
,
4086 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4089 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4091 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4092 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4093 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4095 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4096 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4097 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4098 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4100 return fixed_bits_valid(val
, fixed0
, fixed1
);
4103 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4105 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4106 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4108 return fixed_bits_valid(val
, fixed0
, fixed1
);
4111 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4113 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4114 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4116 return fixed_bits_valid(val
, fixed0
, fixed1
);
4119 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4120 #define nested_guest_cr4_valid nested_cr4_valid
4121 #define nested_host_cr4_valid nested_cr4_valid
4123 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4125 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4127 struct kvm_vcpu
*vcpu
)
4129 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4130 vmx_decache_cr3(vcpu
);
4131 if (!(cr0
& X86_CR0_PG
)) {
4132 /* From paging/starting to nonpaging */
4133 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4134 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4135 (CPU_BASED_CR3_LOAD_EXITING
|
4136 CPU_BASED_CR3_STORE_EXITING
));
4137 vcpu
->arch
.cr0
= cr0
;
4138 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4139 } else if (!is_paging(vcpu
)) {
4140 /* From nonpaging to paging */
4141 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4142 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4143 ~(CPU_BASED_CR3_LOAD_EXITING
|
4144 CPU_BASED_CR3_STORE_EXITING
));
4145 vcpu
->arch
.cr0
= cr0
;
4146 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4149 if (!(cr0
& X86_CR0_WP
))
4150 *hw_cr0
&= ~X86_CR0_WP
;
4153 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4155 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4156 unsigned long hw_cr0
;
4158 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4159 if (enable_unrestricted_guest
)
4160 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4162 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4164 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4167 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4171 #ifdef CONFIG_X86_64
4172 if (vcpu
->arch
.efer
& EFER_LME
) {
4173 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4175 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4181 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4183 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4184 vmcs_writel(GUEST_CR0
, hw_cr0
);
4185 vcpu
->arch
.cr0
= cr0
;
4187 /* depends on vcpu->arch.cr0 to be set to a new value */
4188 vmx
->emulation_required
= emulation_required(vcpu
);
4191 static u64
construct_eptp(unsigned long root_hpa
)
4195 /* TODO write the value reading from MSR */
4196 eptp
= VMX_EPT_DEFAULT_MT
|
4197 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
4198 if (enable_ept_ad_bits
)
4199 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
4200 eptp
|= (root_hpa
& PAGE_MASK
);
4205 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4207 unsigned long guest_cr3
;
4212 eptp
= construct_eptp(cr3
);
4213 vmcs_write64(EPT_POINTER
, eptp
);
4214 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4215 guest_cr3
= kvm_read_cr3(vcpu
);
4217 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4218 ept_load_pdptrs(vcpu
);
4221 vmx_flush_tlb(vcpu
);
4222 vmcs_writel(GUEST_CR3
, guest_cr3
);
4225 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4228 * Pass through host's Machine Check Enable value to hw_cr4, which
4229 * is in force while we are in guest mode. Do not let guests control
4230 * this bit, even if host CR4.MCE == 0.
4232 unsigned long hw_cr4
=
4233 (cr4_read_shadow() & X86_CR4_MCE
) |
4234 (cr4
& ~X86_CR4_MCE
) |
4235 (to_vmx(vcpu
)->rmode
.vm86_active
?
4236 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4238 if (cr4
& X86_CR4_VMXE
) {
4240 * To use VMXON (and later other VMX instructions), a guest
4241 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4242 * So basically the check on whether to allow nested VMX
4245 if (!nested_vmx_allowed(vcpu
))
4249 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4252 vcpu
->arch
.cr4
= cr4
;
4254 if (!is_paging(vcpu
)) {
4255 hw_cr4
&= ~X86_CR4_PAE
;
4256 hw_cr4
|= X86_CR4_PSE
;
4257 } else if (!(cr4
& X86_CR4_PAE
)) {
4258 hw_cr4
&= ~X86_CR4_PAE
;
4262 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4264 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4265 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4266 * to be manually disabled when guest switches to non-paging
4269 * If !enable_unrestricted_guest, the CPU is always running
4270 * with CR0.PG=1 and CR4 needs to be modified.
4271 * If enable_unrestricted_guest, the CPU automatically
4272 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4274 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4276 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4277 vmcs_writel(GUEST_CR4
, hw_cr4
);
4281 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4282 struct kvm_segment
*var
, int seg
)
4284 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4287 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4288 *var
= vmx
->rmode
.segs
[seg
];
4289 if (seg
== VCPU_SREG_TR
4290 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4292 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4293 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4296 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4297 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4298 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4299 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4300 var
->unusable
= (ar
>> 16) & 1;
4301 var
->type
= ar
& 15;
4302 var
->s
= (ar
>> 4) & 1;
4303 var
->dpl
= (ar
>> 5) & 3;
4305 * Some userspaces do not preserve unusable property. Since usable
4306 * segment has to be present according to VMX spec we can use present
4307 * property to amend userspace bug by making unusable segment always
4308 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4309 * segment as unusable.
4311 var
->present
= !var
->unusable
;
4312 var
->avl
= (ar
>> 12) & 1;
4313 var
->l
= (ar
>> 13) & 1;
4314 var
->db
= (ar
>> 14) & 1;
4315 var
->g
= (ar
>> 15) & 1;
4318 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4320 struct kvm_segment s
;
4322 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4323 vmx_get_segment(vcpu
, &s
, seg
);
4326 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4329 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4331 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4333 if (unlikely(vmx
->rmode
.vm86_active
))
4336 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4337 return VMX_AR_DPL(ar
);
4341 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4345 if (var
->unusable
|| !var
->present
)
4348 ar
= var
->type
& 15;
4349 ar
|= (var
->s
& 1) << 4;
4350 ar
|= (var
->dpl
& 3) << 5;
4351 ar
|= (var
->present
& 1) << 7;
4352 ar
|= (var
->avl
& 1) << 12;
4353 ar
|= (var
->l
& 1) << 13;
4354 ar
|= (var
->db
& 1) << 14;
4355 ar
|= (var
->g
& 1) << 15;
4361 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4362 struct kvm_segment
*var
, int seg
)
4364 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4365 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4367 vmx_segment_cache_clear(vmx
);
4369 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4370 vmx
->rmode
.segs
[seg
] = *var
;
4371 if (seg
== VCPU_SREG_TR
)
4372 vmcs_write16(sf
->selector
, var
->selector
);
4374 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4378 vmcs_writel(sf
->base
, var
->base
);
4379 vmcs_write32(sf
->limit
, var
->limit
);
4380 vmcs_write16(sf
->selector
, var
->selector
);
4383 * Fix the "Accessed" bit in AR field of segment registers for older
4385 * IA32 arch specifies that at the time of processor reset the
4386 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4387 * is setting it to 0 in the userland code. This causes invalid guest
4388 * state vmexit when "unrestricted guest" mode is turned on.
4389 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4390 * tree. Newer qemu binaries with that qemu fix would not need this
4393 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4394 var
->type
|= 0x1; /* Accessed */
4396 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4399 vmx
->emulation_required
= emulation_required(vcpu
);
4402 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4404 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4406 *db
= (ar
>> 14) & 1;
4407 *l
= (ar
>> 13) & 1;
4410 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4412 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4413 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4416 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4418 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4419 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4422 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4424 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4425 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4428 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4430 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4431 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4434 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4436 struct kvm_segment var
;
4439 vmx_get_segment(vcpu
, &var
, seg
);
4441 if (seg
== VCPU_SREG_CS
)
4443 ar
= vmx_segment_access_rights(&var
);
4445 if (var
.base
!= (var
.selector
<< 4))
4447 if (var
.limit
!= 0xffff)
4455 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4457 struct kvm_segment cs
;
4458 unsigned int cs_rpl
;
4460 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4461 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4465 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4469 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4470 if (cs
.dpl
> cs_rpl
)
4473 if (cs
.dpl
!= cs_rpl
)
4479 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4483 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4485 struct kvm_segment ss
;
4486 unsigned int ss_rpl
;
4488 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4489 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4493 if (ss
.type
!= 3 && ss
.type
!= 7)
4497 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4505 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4507 struct kvm_segment var
;
4510 vmx_get_segment(vcpu
, &var
, seg
);
4511 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4519 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4520 if (var
.dpl
< rpl
) /* DPL < RPL */
4524 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4530 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4532 struct kvm_segment tr
;
4534 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4538 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4540 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4548 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4550 struct kvm_segment ldtr
;
4552 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4556 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4566 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4568 struct kvm_segment cs
, ss
;
4570 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4571 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4573 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4574 (ss
.selector
& SEGMENT_RPL_MASK
));
4578 * Check if guest state is valid. Returns true if valid, false if
4580 * We assume that registers are always usable
4582 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4584 if (enable_unrestricted_guest
)
4587 /* real mode guest state checks */
4588 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4589 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4591 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4593 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4595 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4597 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4599 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4602 /* protected mode guest state checks */
4603 if (!cs_ss_rpl_check(vcpu
))
4605 if (!code_segment_valid(vcpu
))
4607 if (!stack_segment_valid(vcpu
))
4609 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4611 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4613 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4615 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4617 if (!tr_valid(vcpu
))
4619 if (!ldtr_valid(vcpu
))
4623 * - Add checks on RIP
4624 * - Add checks on RFLAGS
4630 static int init_rmode_tss(struct kvm
*kvm
)
4636 idx
= srcu_read_lock(&kvm
->srcu
);
4637 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4638 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4641 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4642 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4643 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4646 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4649 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4653 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4654 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4657 srcu_read_unlock(&kvm
->srcu
, idx
);
4661 static int init_rmode_identity_map(struct kvm
*kvm
)
4664 kvm_pfn_t identity_map_pfn
;
4670 /* Protect kvm->arch.ept_identity_pagetable_done. */
4671 mutex_lock(&kvm
->slots_lock
);
4673 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4676 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4678 r
= alloc_identity_pagetable(kvm
);
4682 idx
= srcu_read_lock(&kvm
->srcu
);
4683 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4686 /* Set up identity-mapping pagetable for EPT in real mode */
4687 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4688 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4689 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4690 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4691 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4695 kvm
->arch
.ept_identity_pagetable_done
= true;
4698 srcu_read_unlock(&kvm
->srcu
, idx
);
4701 mutex_unlock(&kvm
->slots_lock
);
4705 static void seg_setup(int seg
)
4707 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4710 vmcs_write16(sf
->selector
, 0);
4711 vmcs_writel(sf
->base
, 0);
4712 vmcs_write32(sf
->limit
, 0xffff);
4714 if (seg
== VCPU_SREG_CS
)
4715 ar
|= 0x08; /* code segment */
4717 vmcs_write32(sf
->ar_bytes
, ar
);
4720 static int alloc_apic_access_page(struct kvm
*kvm
)
4725 mutex_lock(&kvm
->slots_lock
);
4726 if (kvm
->arch
.apic_access_page_done
)
4728 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4729 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4733 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4734 if (is_error_page(page
)) {
4740 * Do not pin the page in memory, so that memory hot-unplug
4741 * is able to migrate it.
4744 kvm
->arch
.apic_access_page_done
= true;
4746 mutex_unlock(&kvm
->slots_lock
);
4750 static int alloc_identity_pagetable(struct kvm
*kvm
)
4752 /* Called with kvm->slots_lock held. */
4756 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4758 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4759 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4764 static int allocate_vpid(void)
4770 spin_lock(&vmx_vpid_lock
);
4771 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4772 if (vpid
< VMX_NR_VPIDS
)
4773 __set_bit(vpid
, vmx_vpid_bitmap
);
4776 spin_unlock(&vmx_vpid_lock
);
4780 static void free_vpid(int vpid
)
4782 if (!enable_vpid
|| vpid
== 0)
4784 spin_lock(&vmx_vpid_lock
);
4785 __clear_bit(vpid
, vmx_vpid_bitmap
);
4786 spin_unlock(&vmx_vpid_lock
);
4789 #define MSR_TYPE_R 1
4790 #define MSR_TYPE_W 2
4791 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4794 int f
= sizeof(unsigned long);
4796 if (!cpu_has_vmx_msr_bitmap())
4800 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4801 * have the write-low and read-high bitmap offsets the wrong way round.
4802 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4804 if (msr
<= 0x1fff) {
4805 if (type
& MSR_TYPE_R
)
4807 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4809 if (type
& MSR_TYPE_W
)
4811 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4813 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4815 if (type
& MSR_TYPE_R
)
4817 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4819 if (type
& MSR_TYPE_W
)
4821 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4827 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4828 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4830 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4831 unsigned long *msr_bitmap_nested
,
4834 int f
= sizeof(unsigned long);
4836 if (!cpu_has_vmx_msr_bitmap()) {
4842 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4843 * have the write-low and read-high bitmap offsets the wrong way round.
4844 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4846 if (msr
<= 0x1fff) {
4847 if (type
& MSR_TYPE_R
&&
4848 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4850 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4852 if (type
& MSR_TYPE_W
&&
4853 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4855 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4857 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4859 if (type
& MSR_TYPE_R
&&
4860 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4862 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4864 if (type
& MSR_TYPE_W
&&
4865 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4867 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4872 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4875 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4876 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4877 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4878 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4881 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
4884 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
4886 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
4889 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4891 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4896 static bool vmx_get_enable_apicv(void)
4898 return enable_apicv
;
4901 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4903 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4908 if (vmx
->nested
.pi_desc
&&
4909 vmx
->nested
.pi_pending
) {
4910 vmx
->nested
.pi_pending
= false;
4911 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4914 max_irr
= find_last_bit(
4915 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4920 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4921 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4922 kunmap(vmx
->nested
.virtual_apic_page
);
4924 status
= vmcs_read16(GUEST_INTR_STATUS
);
4925 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4927 status
|= (u8
)max_irr
;
4928 vmcs_write16(GUEST_INTR_STATUS
, status
);
4933 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4936 if (vcpu
->mode
== IN_GUEST_MODE
) {
4937 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4940 * Currently, we don't support urgent interrupt,
4941 * all interrupts are recognized as non-urgent
4942 * interrupt, so we cannot post interrupts when
4945 * If the vcpu is in guest mode, it means it is
4946 * running instead of being scheduled out and
4947 * waiting in the run queue, and that's the only
4948 * case when 'SN' is set currently, warning if
4951 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4953 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4954 POSTED_INTR_VECTOR
);
4961 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4964 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4966 if (is_guest_mode(vcpu
) &&
4967 vector
== vmx
->nested
.posted_intr_nv
) {
4968 /* the PIR and ON have been set by L1. */
4969 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4971 * If a posted intr is not recognized by hardware,
4972 * we will accomplish it in the next vmentry.
4974 vmx
->nested
.pi_pending
= true;
4975 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4981 * Send interrupt to vcpu via posted interrupt way.
4982 * 1. If target vcpu is running(non-root mode), send posted interrupt
4983 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4984 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4985 * interrupt from PIR in next vmentry.
4987 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4989 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4992 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4996 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4999 /* If a previous notification has sent the IPI, nothing to do. */
5000 if (pi_test_and_set_on(&vmx
->pi_desc
))
5003 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
))
5004 kvm_vcpu_kick(vcpu
);
5008 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5009 * will not change in the lifetime of the guest.
5010 * Note that host-state that does change is set elsewhere. E.g., host-state
5011 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5013 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5018 unsigned long cr0
, cr3
, cr4
;
5021 WARN_ON(cr0
& X86_CR0_TS
);
5022 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5025 * Save the most likely value for this task's CR3 in the VMCS.
5026 * We can't use __get_current_cr3_fast() because we're not atomic.
5029 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5030 vmx
->host_state
.vmcs_host_cr3
= cr3
;
5032 /* Save the most likely value for this task's CR4 in the VMCS. */
5033 cr4
= cr4_read_shadow();
5034 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5035 vmx
->host_state
.vmcs_host_cr4
= cr4
;
5037 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5038 #ifdef CONFIG_X86_64
5040 * Load null selectors, so we can avoid reloading them in
5041 * __vmx_load_host_state(), in case userspace uses the null selectors
5042 * too (the expected case).
5044 vmcs_write16(HOST_DS_SELECTOR
, 0);
5045 vmcs_write16(HOST_ES_SELECTOR
, 0);
5047 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5048 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5050 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5051 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5053 native_store_idt(&dt
);
5054 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5055 vmx
->host_idt_base
= dt
.address
;
5057 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5059 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5060 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5061 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5062 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5064 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5065 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5066 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5070 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5072 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5074 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5075 if (is_guest_mode(&vmx
->vcpu
))
5076 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5077 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5078 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5081 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5083 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5085 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5086 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5087 /* Enable the preemption timer dynamically */
5088 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5089 return pin_based_exec_ctrl
;
5092 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5094 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5096 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5097 if (cpu_has_secondary_exec_ctrls()) {
5098 if (kvm_vcpu_apicv_active(vcpu
))
5099 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5100 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5101 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5103 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5104 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5105 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5108 if (cpu_has_vmx_msr_bitmap())
5109 vmx_set_msr_bitmap(vcpu
);
5112 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5114 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5116 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5117 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5119 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5120 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5121 #ifdef CONFIG_X86_64
5122 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5123 CPU_BASED_CR8_LOAD_EXITING
;
5127 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5128 CPU_BASED_CR3_LOAD_EXITING
|
5129 CPU_BASED_INVLPG_EXITING
;
5130 return exec_control
;
5133 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
5135 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5136 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
5137 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5139 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5141 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5142 enable_unrestricted_guest
= 0;
5143 /* Enable INVPCID for non-ept guests may cause performance regression. */
5144 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5146 if (!enable_unrestricted_guest
)
5147 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5149 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5150 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5151 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5152 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5153 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5154 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5156 We can NOT enable shadow_vmcs here because we don't have yet
5159 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5162 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5164 return exec_control
;
5167 static void ept_set_mmio_spte_mask(void)
5170 * EPT Misconfigurations can be generated if the value of bits 2:0
5171 * of an EPT paging-structure entry is 110b (write/execute).
5173 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE
);
5176 #define VMX_XSS_EXIT_BITMAP 0
5178 * Sets up the vmcs for emulated real mode.
5180 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5182 #ifdef CONFIG_X86_64
5188 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5189 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5191 if (enable_shadow_vmcs
) {
5192 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5193 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5195 if (cpu_has_vmx_msr_bitmap())
5196 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5198 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5201 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5202 vmx
->hv_deadline_tsc
= -1;
5204 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5206 if (cpu_has_secondary_exec_ctrls()) {
5207 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5208 vmx_secondary_exec_control(vmx
));
5211 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5212 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5213 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5214 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5215 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5217 vmcs_write16(GUEST_INTR_STATUS
, 0);
5219 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5220 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5224 vmcs_write32(PLE_GAP
, ple_gap
);
5225 vmx
->ple_window
= ple_window
;
5226 vmx
->ple_window_dirty
= true;
5229 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5230 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5231 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5233 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5234 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5235 vmx_set_constant_host_state(vmx
);
5236 #ifdef CONFIG_X86_64
5237 rdmsrl(MSR_FS_BASE
, a
);
5238 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5239 rdmsrl(MSR_GS_BASE
, a
);
5240 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5242 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5243 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5246 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5247 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5248 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5249 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5250 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5252 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5253 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5255 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5256 u32 index
= vmx_msr_index
[i
];
5257 u32 data_low
, data_high
;
5260 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5262 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5264 vmx
->guest_msrs
[j
].index
= i
;
5265 vmx
->guest_msrs
[j
].data
= 0;
5266 vmx
->guest_msrs
[j
].mask
= -1ull;
5271 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5273 /* 22.2.1, 20.8.1 */
5274 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5276 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5277 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5279 set_cr4_guest_host_mask(vmx
);
5281 if (vmx_xsaves_supported())
5282 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5285 ASSERT(vmx
->pml_pg
);
5286 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5287 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5293 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5295 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5296 struct msr_data apic_base_msr
;
5299 vmx
->rmode
.vm86_active
= 0;
5301 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5302 kvm_set_cr8(vcpu
, 0);
5305 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5306 MSR_IA32_APICBASE_ENABLE
;
5307 if (kvm_vcpu_is_reset_bsp(vcpu
))
5308 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5309 apic_base_msr
.host_initiated
= true;
5310 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5313 vmx_segment_cache_clear(vmx
);
5315 seg_setup(VCPU_SREG_CS
);
5316 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5317 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5319 seg_setup(VCPU_SREG_DS
);
5320 seg_setup(VCPU_SREG_ES
);
5321 seg_setup(VCPU_SREG_FS
);
5322 seg_setup(VCPU_SREG_GS
);
5323 seg_setup(VCPU_SREG_SS
);
5325 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5326 vmcs_writel(GUEST_TR_BASE
, 0);
5327 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5328 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5330 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5331 vmcs_writel(GUEST_LDTR_BASE
, 0);
5332 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5333 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5336 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5337 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5338 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5339 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5342 vmcs_writel(GUEST_RFLAGS
, 0x02);
5343 kvm_rip_write(vcpu
, 0xfff0);
5345 vmcs_writel(GUEST_GDTR_BASE
, 0);
5346 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5348 vmcs_writel(GUEST_IDTR_BASE
, 0);
5349 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5351 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5352 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5353 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5357 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5359 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5360 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5361 if (cpu_need_tpr_shadow(vcpu
))
5362 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5363 __pa(vcpu
->arch
.apic
->regs
));
5364 vmcs_write32(TPR_THRESHOLD
, 0);
5367 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5369 if (kvm_vcpu_apicv_active(vcpu
))
5370 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5373 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5375 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5376 vmx
->vcpu
.arch
.cr0
= cr0
;
5377 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5378 vmx_set_cr4(vcpu
, 0);
5379 vmx_set_efer(vcpu
, 0);
5381 update_exception_bitmap(vcpu
);
5383 vpid_sync_context(vmx
->vpid
);
5387 * In nested virtualization, check if L1 asked to exit on external interrupts.
5388 * For most existing hypervisors, this will always return true.
5390 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5392 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5393 PIN_BASED_EXT_INTR_MASK
;
5397 * In nested virtualization, check if L1 has set
5398 * VM_EXIT_ACK_INTR_ON_EXIT
5400 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5402 return get_vmcs12(vcpu
)->vm_exit_controls
&
5403 VM_EXIT_ACK_INTR_ON_EXIT
;
5406 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5408 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5409 PIN_BASED_NMI_EXITING
;
5412 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5414 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5415 CPU_BASED_VIRTUAL_INTR_PENDING
);
5418 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5420 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5421 enable_irq_window(vcpu
);
5425 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5426 CPU_BASED_VIRTUAL_NMI_PENDING
);
5429 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5431 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5433 int irq
= vcpu
->arch
.interrupt
.nr
;
5435 trace_kvm_inj_virq(irq
);
5437 ++vcpu
->stat
.irq_injections
;
5438 if (vmx
->rmode
.vm86_active
) {
5440 if (vcpu
->arch
.interrupt
.soft
)
5441 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5442 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5443 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5446 intr
= irq
| INTR_INFO_VALID_MASK
;
5447 if (vcpu
->arch
.interrupt
.soft
) {
5448 intr
|= INTR_TYPE_SOFT_INTR
;
5449 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5450 vmx
->vcpu
.arch
.event_exit_inst_len
);
5452 intr
|= INTR_TYPE_EXT_INTR
;
5453 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5456 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5458 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5460 if (!is_guest_mode(vcpu
)) {
5461 ++vcpu
->stat
.nmi_injections
;
5462 vmx
->nmi_known_unmasked
= false;
5465 if (vmx
->rmode
.vm86_active
) {
5466 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5467 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5471 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5472 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5475 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5477 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5479 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5482 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5484 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5486 vmx
->nmi_known_unmasked
= !masked
;
5488 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5489 GUEST_INTR_STATE_NMI
);
5491 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5492 GUEST_INTR_STATE_NMI
);
5495 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5497 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5500 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5501 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5502 | GUEST_INTR_STATE_NMI
));
5505 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5507 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5508 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5509 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5510 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5513 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5517 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5521 kvm
->arch
.tss_addr
= addr
;
5522 return init_rmode_tss(kvm
);
5525 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5530 * Update instruction length as we may reinject the exception
5531 * from user space while in guest debugging mode.
5533 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5534 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5535 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5539 if (vcpu
->guest_debug
&
5540 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5557 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5558 int vec
, u32 err_code
)
5561 * Instruction with address size override prefix opcode 0x67
5562 * Cause the #SS fault with 0 error code in VM86 mode.
5564 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5565 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5566 if (vcpu
->arch
.halt_request
) {
5567 vcpu
->arch
.halt_request
= 0;
5568 return kvm_vcpu_halt(vcpu
);
5576 * Forward all other exceptions that are valid in real mode.
5577 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5578 * the required debugging infrastructure rework.
5580 kvm_queue_exception(vcpu
, vec
);
5585 * Trigger machine check on the host. We assume all the MSRs are already set up
5586 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5587 * We pass a fake environment to the machine check handler because we want
5588 * the guest to be always treated like user space, no matter what context
5589 * it used internally.
5591 static void kvm_machine_check(void)
5593 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5594 struct pt_regs regs
= {
5595 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5596 .flags
= X86_EFLAGS_IF
,
5599 do_machine_check(®s
, 0);
5603 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5605 /* already handled by vcpu_run */
5609 static int handle_exception(struct kvm_vcpu
*vcpu
)
5611 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5612 struct kvm_run
*kvm_run
= vcpu
->run
;
5613 u32 intr_info
, ex_no
, error_code
;
5614 unsigned long cr2
, rip
, dr6
;
5616 enum emulation_result er
;
5618 vect_info
= vmx
->idt_vectoring_info
;
5619 intr_info
= vmx
->exit_intr_info
;
5621 if (is_machine_check(intr_info
))
5622 return handle_machine_check(vcpu
);
5624 if (is_nmi(intr_info
))
5625 return 1; /* already handled by vmx_vcpu_run() */
5627 if (is_invalid_opcode(intr_info
)) {
5628 if (is_guest_mode(vcpu
)) {
5629 kvm_queue_exception(vcpu
, UD_VECTOR
);
5632 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5633 if (er
!= EMULATE_DONE
)
5634 kvm_queue_exception(vcpu
, UD_VECTOR
);
5639 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5640 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5643 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5644 * MMIO, it is better to report an internal error.
5645 * See the comments in vmx_handle_exit.
5647 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5648 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5649 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5650 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5651 vcpu
->run
->internal
.ndata
= 3;
5652 vcpu
->run
->internal
.data
[0] = vect_info
;
5653 vcpu
->run
->internal
.data
[1] = intr_info
;
5654 vcpu
->run
->internal
.data
[2] = error_code
;
5658 if (is_page_fault(intr_info
)) {
5659 /* EPT won't cause page fault directly */
5661 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5662 trace_kvm_page_fault(cr2
, error_code
);
5664 if (kvm_event_needs_reinjection(vcpu
))
5665 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5666 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5669 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5671 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5672 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5676 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5679 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5680 if (!(vcpu
->guest_debug
&
5681 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5682 vcpu
->arch
.dr6
&= ~15;
5683 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5684 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5685 skip_emulated_instruction(vcpu
);
5687 kvm_queue_exception(vcpu
, DB_VECTOR
);
5690 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5691 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5695 * Update instruction length as we may reinject #BP from
5696 * user space while in guest debugging mode. Reading it for
5697 * #DB as well causes no harm, it is not used in that case.
5699 vmx
->vcpu
.arch
.event_exit_inst_len
=
5700 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5701 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5702 rip
= kvm_rip_read(vcpu
);
5703 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5704 kvm_run
->debug
.arch
.exception
= ex_no
;
5707 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5708 kvm_run
->ex
.exception
= ex_no
;
5709 kvm_run
->ex
.error_code
= error_code
;
5715 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5717 ++vcpu
->stat
.irq_exits
;
5721 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5723 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5727 static int handle_io(struct kvm_vcpu
*vcpu
)
5729 unsigned long exit_qualification
;
5730 int size
, in
, string
, ret
;
5733 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5734 string
= (exit_qualification
& 16) != 0;
5735 in
= (exit_qualification
& 8) != 0;
5737 ++vcpu
->stat
.io_exits
;
5740 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5742 port
= exit_qualification
>> 16;
5743 size
= (exit_qualification
& 7) + 1;
5745 ret
= kvm_skip_emulated_instruction(vcpu
);
5748 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5749 * KVM_EXIT_DEBUG here.
5751 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
5755 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5758 * Patch in the VMCALL instruction:
5760 hypercall
[0] = 0x0f;
5761 hypercall
[1] = 0x01;
5762 hypercall
[2] = 0xc1;
5765 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5766 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5768 if (is_guest_mode(vcpu
)) {
5769 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5770 unsigned long orig_val
= val
;
5773 * We get here when L2 changed cr0 in a way that did not change
5774 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5775 * but did change L0 shadowed bits. So we first calculate the
5776 * effective cr0 value that L1 would like to write into the
5777 * hardware. It consists of the L2-owned bits from the new
5778 * value combined with the L1-owned bits from L1's guest_cr0.
5780 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5781 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5783 if (!nested_guest_cr0_valid(vcpu
, val
))
5786 if (kvm_set_cr0(vcpu
, val
))
5788 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5791 if (to_vmx(vcpu
)->nested
.vmxon
&&
5792 !nested_host_cr0_valid(vcpu
, val
))
5795 return kvm_set_cr0(vcpu
, val
);
5799 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5801 if (is_guest_mode(vcpu
)) {
5802 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5803 unsigned long orig_val
= val
;
5805 /* analogously to handle_set_cr0 */
5806 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5807 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5808 if (kvm_set_cr4(vcpu
, val
))
5810 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5813 return kvm_set_cr4(vcpu
, val
);
5816 static int handle_cr(struct kvm_vcpu
*vcpu
)
5818 unsigned long exit_qualification
, val
;
5824 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5825 cr
= exit_qualification
& 15;
5826 reg
= (exit_qualification
>> 8) & 15;
5827 switch ((exit_qualification
>> 4) & 3) {
5828 case 0: /* mov to cr */
5829 val
= kvm_register_readl(vcpu
, reg
);
5830 trace_kvm_cr_write(cr
, val
);
5833 err
= handle_set_cr0(vcpu
, val
);
5834 return kvm_complete_insn_gp(vcpu
, err
);
5836 err
= kvm_set_cr3(vcpu
, val
);
5837 return kvm_complete_insn_gp(vcpu
, err
);
5839 err
= handle_set_cr4(vcpu
, val
);
5840 return kvm_complete_insn_gp(vcpu
, err
);
5842 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5844 err
= kvm_set_cr8(vcpu
, cr8
);
5845 ret
= kvm_complete_insn_gp(vcpu
, err
);
5846 if (lapic_in_kernel(vcpu
))
5848 if (cr8_prev
<= cr8
)
5851 * TODO: we might be squashing a
5852 * KVM_GUESTDBG_SINGLESTEP-triggered
5853 * KVM_EXIT_DEBUG here.
5855 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5861 WARN_ONCE(1, "Guest should always own CR0.TS");
5862 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5863 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5864 return kvm_skip_emulated_instruction(vcpu
);
5865 case 1: /*mov from cr*/
5868 val
= kvm_read_cr3(vcpu
);
5869 kvm_register_write(vcpu
, reg
, val
);
5870 trace_kvm_cr_read(cr
, val
);
5871 return kvm_skip_emulated_instruction(vcpu
);
5873 val
= kvm_get_cr8(vcpu
);
5874 kvm_register_write(vcpu
, reg
, val
);
5875 trace_kvm_cr_read(cr
, val
);
5876 return kvm_skip_emulated_instruction(vcpu
);
5880 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5881 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5882 kvm_lmsw(vcpu
, val
);
5884 return kvm_skip_emulated_instruction(vcpu
);
5888 vcpu
->run
->exit_reason
= 0;
5889 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5890 (int)(exit_qualification
>> 4) & 3, cr
);
5894 static int handle_dr(struct kvm_vcpu
*vcpu
)
5896 unsigned long exit_qualification
;
5899 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5900 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5902 /* First, if DR does not exist, trigger UD */
5903 if (!kvm_require_dr(vcpu
, dr
))
5906 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5907 if (!kvm_require_cpl(vcpu
, 0))
5909 dr7
= vmcs_readl(GUEST_DR7
);
5912 * As the vm-exit takes precedence over the debug trap, we
5913 * need to emulate the latter, either for the host or the
5914 * guest debugging itself.
5916 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5917 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5918 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5919 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5920 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5921 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5924 vcpu
->arch
.dr6
&= ~15;
5925 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5926 kvm_queue_exception(vcpu
, DB_VECTOR
);
5931 if (vcpu
->guest_debug
== 0) {
5932 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5933 CPU_BASED_MOV_DR_EXITING
);
5936 * No more DR vmexits; force a reload of the debug registers
5937 * and reenter on this instruction. The next vmexit will
5938 * retrieve the full state of the debug registers.
5940 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5944 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5945 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5948 if (kvm_get_dr(vcpu
, dr
, &val
))
5950 kvm_register_write(vcpu
, reg
, val
);
5952 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5955 return kvm_skip_emulated_instruction(vcpu
);
5958 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5960 return vcpu
->arch
.dr6
;
5963 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5967 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5969 get_debugreg(vcpu
->arch
.db
[0], 0);
5970 get_debugreg(vcpu
->arch
.db
[1], 1);
5971 get_debugreg(vcpu
->arch
.db
[2], 2);
5972 get_debugreg(vcpu
->arch
.db
[3], 3);
5973 get_debugreg(vcpu
->arch
.dr6
, 6);
5974 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5976 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5977 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
5980 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5982 vmcs_writel(GUEST_DR7
, val
);
5985 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5987 return kvm_emulate_cpuid(vcpu
);
5990 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5992 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5993 struct msr_data msr_info
;
5995 msr_info
.index
= ecx
;
5996 msr_info
.host_initiated
= false;
5997 if (vmx_get_msr(vcpu
, &msr_info
)) {
5998 trace_kvm_msr_read_ex(ecx
);
5999 kvm_inject_gp(vcpu
, 0);
6003 trace_kvm_msr_read(ecx
, msr_info
.data
);
6005 /* FIXME: handling of bits 32:63 of rax, rdx */
6006 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6007 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6008 return kvm_skip_emulated_instruction(vcpu
);
6011 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6013 struct msr_data msr
;
6014 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6015 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6016 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6020 msr
.host_initiated
= false;
6021 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6022 trace_kvm_msr_write_ex(ecx
, data
);
6023 kvm_inject_gp(vcpu
, 0);
6027 trace_kvm_msr_write(ecx
, data
);
6028 return kvm_skip_emulated_instruction(vcpu
);
6031 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6033 kvm_apic_update_ppr(vcpu
);
6037 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6039 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6040 CPU_BASED_VIRTUAL_INTR_PENDING
);
6042 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6044 ++vcpu
->stat
.irq_window_exits
;
6048 static int handle_halt(struct kvm_vcpu
*vcpu
)
6050 return kvm_emulate_halt(vcpu
);
6053 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6055 return kvm_emulate_hypercall(vcpu
);
6058 static int handle_invd(struct kvm_vcpu
*vcpu
)
6060 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6063 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6065 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6067 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6068 return kvm_skip_emulated_instruction(vcpu
);
6071 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6075 err
= kvm_rdpmc(vcpu
);
6076 return kvm_complete_insn_gp(vcpu
, err
);
6079 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6081 return kvm_emulate_wbinvd(vcpu
);
6084 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6086 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6087 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6089 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6090 return kvm_skip_emulated_instruction(vcpu
);
6094 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6096 kvm_skip_emulated_instruction(vcpu
);
6097 WARN(1, "this should never happen\n");
6101 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6103 kvm_skip_emulated_instruction(vcpu
);
6104 WARN(1, "this should never happen\n");
6108 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6110 if (likely(fasteoi
)) {
6111 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6112 int access_type
, offset
;
6114 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6115 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6117 * Sane guest uses MOV to write EOI, with written value
6118 * not cared. So make a short-circuit here by avoiding
6119 * heavy instruction emulation.
6121 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6122 (offset
== APIC_EOI
)) {
6123 kvm_lapic_set_eoi(vcpu
);
6124 return kvm_skip_emulated_instruction(vcpu
);
6127 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6130 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6132 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6133 int vector
= exit_qualification
& 0xff;
6135 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6136 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6140 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6142 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6143 u32 offset
= exit_qualification
& 0xfff;
6145 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6146 kvm_apic_write_nodecode(vcpu
, offset
);
6150 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6152 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6153 unsigned long exit_qualification
;
6154 bool has_error_code
= false;
6157 int reason
, type
, idt_v
, idt_index
;
6159 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6160 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6161 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6163 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6165 reason
= (u32
)exit_qualification
>> 30;
6166 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6168 case INTR_TYPE_NMI_INTR
:
6169 vcpu
->arch
.nmi_injected
= false;
6170 vmx_set_nmi_mask(vcpu
, true);
6172 case INTR_TYPE_EXT_INTR
:
6173 case INTR_TYPE_SOFT_INTR
:
6174 kvm_clear_interrupt_queue(vcpu
);
6176 case INTR_TYPE_HARD_EXCEPTION
:
6177 if (vmx
->idt_vectoring_info
&
6178 VECTORING_INFO_DELIVER_CODE_MASK
) {
6179 has_error_code
= true;
6181 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6184 case INTR_TYPE_SOFT_EXCEPTION
:
6185 kvm_clear_exception_queue(vcpu
);
6191 tss_selector
= exit_qualification
;
6193 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6194 type
!= INTR_TYPE_EXT_INTR
&&
6195 type
!= INTR_TYPE_NMI_INTR
))
6196 skip_emulated_instruction(vcpu
);
6198 if (kvm_task_switch(vcpu
, tss_selector
,
6199 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6200 has_error_code
, error_code
) == EMULATE_FAIL
) {
6201 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6202 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6203 vcpu
->run
->internal
.ndata
= 0;
6208 * TODO: What about debug traps on tss switch?
6209 * Are we supposed to inject them and update dr6?
6215 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6217 unsigned long exit_qualification
;
6221 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6223 if (is_guest_mode(vcpu
)
6224 && !(exit_qualification
& EPT_VIOLATION_GVA_TRANSLATED
)) {
6226 * Fix up exit_qualification according to whether guest
6227 * page table accesses are reads or writes.
6229 u64 eptp
= nested_ept_get_cr3(vcpu
);
6230 if (!(eptp
& VMX_EPT_AD_ENABLE_BIT
))
6231 exit_qualification
&= ~EPT_VIOLATION_ACC_WRITE
;
6235 * EPT violation happened while executing iret from NMI,
6236 * "blocked by NMI" bit has to be set before next VM entry.
6237 * There are errata that may cause this bit to not be set:
6240 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6241 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6242 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6244 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6245 trace_kvm_page_fault(gpa
, exit_qualification
);
6247 /* Is it a read fault? */
6248 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6249 ? PFERR_USER_MASK
: 0;
6250 /* Is it a write fault? */
6251 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6252 ? PFERR_WRITE_MASK
: 0;
6253 /* Is it a fetch fault? */
6254 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6255 ? PFERR_FETCH_MASK
: 0;
6256 /* ept page table entry is present? */
6257 error_code
|= (exit_qualification
&
6258 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6259 EPT_VIOLATION_EXECUTABLE
))
6260 ? PFERR_PRESENT_MASK
: 0;
6262 vcpu
->arch
.gpa_available
= true;
6263 vcpu
->arch
.exit_qualification
= exit_qualification
;
6265 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6268 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6273 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6274 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6275 trace_kvm_fast_mmio(gpa
);
6276 return kvm_skip_emulated_instruction(vcpu
);
6279 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6280 vcpu
->arch
.gpa_available
= true;
6281 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6282 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6285 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6286 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6288 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6291 /* It is the real ept misconfig */
6294 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6295 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6300 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6302 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6303 CPU_BASED_VIRTUAL_NMI_PENDING
);
6304 ++vcpu
->stat
.nmi_window_exits
;
6305 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6310 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6312 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6313 enum emulation_result err
= EMULATE_DONE
;
6316 bool intr_window_requested
;
6317 unsigned count
= 130;
6319 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6320 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6322 while (vmx
->emulation_required
&& count
-- != 0) {
6323 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6324 return handle_interrupt_window(&vmx
->vcpu
);
6326 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6329 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6331 if (err
== EMULATE_USER_EXIT
) {
6332 ++vcpu
->stat
.mmio_exits
;
6337 if (err
!= EMULATE_DONE
) {
6338 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6339 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6340 vcpu
->run
->internal
.ndata
= 0;
6344 if (vcpu
->arch
.halt_request
) {
6345 vcpu
->arch
.halt_request
= 0;
6346 ret
= kvm_vcpu_halt(vcpu
);
6350 if (signal_pending(current
))
6360 static int __grow_ple_window(int val
)
6362 if (ple_window_grow
< 1)
6365 val
= min(val
, ple_window_actual_max
);
6367 if (ple_window_grow
< ple_window
)
6368 val
*= ple_window_grow
;
6370 val
+= ple_window_grow
;
6375 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6380 if (modifier
< ple_window
)
6385 return max(val
, minimum
);
6388 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6390 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6391 int old
= vmx
->ple_window
;
6393 vmx
->ple_window
= __grow_ple_window(old
);
6395 if (vmx
->ple_window
!= old
)
6396 vmx
->ple_window_dirty
= true;
6398 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6401 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6403 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6404 int old
= vmx
->ple_window
;
6406 vmx
->ple_window
= __shrink_ple_window(old
,
6407 ple_window_shrink
, ple_window
);
6409 if (vmx
->ple_window
!= old
)
6410 vmx
->ple_window_dirty
= true;
6412 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6416 * ple_window_actual_max is computed to be one grow_ple_window() below
6417 * ple_window_max. (See __grow_ple_window for the reason.)
6418 * This prevents overflows, because ple_window_max is int.
6419 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6421 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6423 static void update_ple_window_actual_max(void)
6425 ple_window_actual_max
=
6426 __shrink_ple_window(max(ple_window_max
, ple_window
),
6427 ple_window_grow
, INT_MIN
);
6431 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6433 static void wakeup_handler(void)
6435 struct kvm_vcpu
*vcpu
;
6436 int cpu
= smp_processor_id();
6438 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6439 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6440 blocked_vcpu_list
) {
6441 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6443 if (pi_test_on(pi_desc
) == 1)
6444 kvm_vcpu_kick(vcpu
);
6446 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6449 void vmx_enable_tdp(void)
6451 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6452 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6453 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6454 0ull, VMX_EPT_EXECUTABLE_MASK
,
6455 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6456 enable_ept_ad_bits
? 0ull : VMX_EPT_RWX_MASK
);
6458 ept_set_mmio_spte_mask();
6462 static __init
int hardware_setup(void)
6464 int r
= -ENOMEM
, i
, msr
;
6466 rdmsrl_safe(MSR_EFER
, &host_efer
);
6468 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6469 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6471 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6472 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6477 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6478 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6479 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6482 * Allow direct access to the PC debug port (it is often used for I/O
6483 * delays, but the vmexits simply slow things down).
6485 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6486 clear_bit(0x80, vmx_io_bitmap_a
);
6488 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6490 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6491 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6493 if (setup_vmcs_config(&vmcs_config
) < 0) {
6498 if (boot_cpu_has(X86_FEATURE_NX
))
6499 kvm_enable_efer_bits(EFER_NX
);
6501 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6502 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6505 if (!cpu_has_vmx_shadow_vmcs())
6506 enable_shadow_vmcs
= 0;
6507 if (enable_shadow_vmcs
)
6508 init_vmcs_shadow_fields();
6510 if (!cpu_has_vmx_ept() ||
6511 !cpu_has_vmx_ept_4levels()) {
6513 enable_unrestricted_guest
= 0;
6514 enable_ept_ad_bits
= 0;
6517 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6518 enable_ept_ad_bits
= 0;
6520 if (!cpu_has_vmx_unrestricted_guest())
6521 enable_unrestricted_guest
= 0;
6523 if (!cpu_has_vmx_flexpriority())
6524 flexpriority_enabled
= 0;
6527 * set_apic_access_page_addr() is used to reload apic access
6528 * page upon invalidation. No need to do anything if not
6529 * using the APIC_ACCESS_ADDR VMCS field.
6531 if (!flexpriority_enabled
)
6532 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6534 if (!cpu_has_vmx_tpr_shadow())
6535 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6537 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6538 kvm_disable_largepages();
6540 if (!cpu_has_vmx_ple())
6543 if (!cpu_has_vmx_apicv()) {
6545 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6548 if (cpu_has_vmx_tsc_scaling()) {
6549 kvm_has_tsc_control
= true;
6550 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6551 kvm_tsc_scaling_ratio_frac_bits
= 48;
6554 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6555 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6556 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6557 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6558 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6559 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6560 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6562 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6563 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6564 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6565 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6566 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6567 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6568 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6569 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6571 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6573 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6574 if (msr
== 0x839 /* TMCCT */)
6576 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6580 * TPR reads and writes can be virtualized even if virtual interrupt
6581 * delivery is not in use.
6583 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6584 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6587 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6589 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6596 update_ple_window_actual_max();
6599 * Only enable PML when hardware supports PML feature, and both EPT
6600 * and EPT A/D bit features are enabled -- PML depends on them to work.
6602 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6606 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6607 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6608 kvm_x86_ops
->flush_log_dirty
= NULL
;
6609 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6612 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6615 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6616 cpu_preemption_timer_multi
=
6617 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6619 kvm_x86_ops
->set_hv_timer
= NULL
;
6620 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6623 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6625 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6627 return alloc_kvm_area();
6630 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6631 free_page((unsigned long)vmx_bitmap
[i
]);
6636 static __exit
void hardware_unsetup(void)
6640 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6641 free_page((unsigned long)vmx_bitmap
[i
]);
6647 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6648 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6650 static int handle_pause(struct kvm_vcpu
*vcpu
)
6653 grow_ple_window(vcpu
);
6655 kvm_vcpu_on_spin(vcpu
);
6656 return kvm_skip_emulated_instruction(vcpu
);
6659 static int handle_nop(struct kvm_vcpu
*vcpu
)
6661 return kvm_skip_emulated_instruction(vcpu
);
6664 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6666 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6667 return handle_nop(vcpu
);
6670 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6675 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6677 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6678 return handle_nop(vcpu
);
6682 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6683 * We could reuse a single VMCS for all the L2 guests, but we also want the
6684 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6685 * allows keeping them loaded on the processor, and in the future will allow
6686 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6687 * every entry if they never change.
6688 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6689 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6691 * The following functions allocate and free a vmcs02 in this pool.
6694 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6695 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6697 struct vmcs02_list
*item
;
6698 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6699 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6700 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6701 return &item
->vmcs02
;
6704 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6705 /* Recycle the least recently used VMCS. */
6706 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6707 struct vmcs02_list
, list
);
6708 item
->vmptr
= vmx
->nested
.current_vmptr
;
6709 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6710 return &item
->vmcs02
;
6713 /* Create a new VMCS */
6714 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6717 item
->vmcs02
.vmcs
= alloc_vmcs();
6718 item
->vmcs02
.shadow_vmcs
= NULL
;
6719 if (!item
->vmcs02
.vmcs
) {
6723 loaded_vmcs_init(&item
->vmcs02
);
6724 item
->vmptr
= vmx
->nested
.current_vmptr
;
6725 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6726 vmx
->nested
.vmcs02_num
++;
6727 return &item
->vmcs02
;
6730 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6731 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6733 struct vmcs02_list
*item
;
6734 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6735 if (item
->vmptr
== vmptr
) {
6736 free_loaded_vmcs(&item
->vmcs02
);
6737 list_del(&item
->list
);
6739 vmx
->nested
.vmcs02_num
--;
6745 * Free all VMCSs saved for this vcpu, except the one pointed by
6746 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6747 * must be &vmx->vmcs01.
6749 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6751 struct vmcs02_list
*item
, *n
;
6753 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6754 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6756 * Something will leak if the above WARN triggers. Better than
6759 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6762 free_loaded_vmcs(&item
->vmcs02
);
6763 list_del(&item
->list
);
6765 vmx
->nested
.vmcs02_num
--;
6770 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6771 * set the success or error code of an emulated VMX instruction, as specified
6772 * by Vol 2B, VMX Instruction Reference, "Conventions".
6774 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6776 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6777 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6778 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6781 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6783 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6784 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6785 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6789 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6790 u32 vm_instruction_error
)
6792 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6794 * failValid writes the error number to the current VMCS, which
6795 * can't be done there isn't a current VMCS.
6797 nested_vmx_failInvalid(vcpu
);
6800 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6801 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6802 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6804 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6806 * We don't need to force a shadow sync because
6807 * VM_INSTRUCTION_ERROR is not shadowed
6811 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6813 /* TODO: not to reset guest simply here. */
6814 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6815 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6818 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6820 struct vcpu_vmx
*vmx
=
6821 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6823 vmx
->nested
.preemption_timer_expired
= true;
6824 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6825 kvm_vcpu_kick(&vmx
->vcpu
);
6827 return HRTIMER_NORESTART
;
6831 * Decode the memory-address operand of a vmx instruction, as recorded on an
6832 * exit caused by such an instruction (run by a guest hypervisor).
6833 * On success, returns 0. When the operand is invalid, returns 1 and throws
6836 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6837 unsigned long exit_qualification
,
6838 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6842 struct kvm_segment s
;
6845 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6846 * Execution", on an exit, vmx_instruction_info holds most of the
6847 * addressing components of the operand. Only the displacement part
6848 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6849 * For how an actual address is calculated from all these components,
6850 * refer to Vol. 1, "Operand Addressing".
6852 int scaling
= vmx_instruction_info
& 3;
6853 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6854 bool is_reg
= vmx_instruction_info
& (1u << 10);
6855 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6856 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6857 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6858 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6859 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6862 kvm_queue_exception(vcpu
, UD_VECTOR
);
6866 /* Addr = segment_base + offset */
6867 /* offset = base + [index * scale] + displacement */
6868 off
= exit_qualification
; /* holds the displacement */
6870 off
+= kvm_register_read(vcpu
, base_reg
);
6872 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6873 vmx_get_segment(vcpu
, &s
, seg_reg
);
6874 *ret
= s
.base
+ off
;
6876 if (addr_size
== 1) /* 32 bit */
6879 /* Checks for #GP/#SS exceptions. */
6881 if (is_long_mode(vcpu
)) {
6882 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6883 * non-canonical form. This is the only check on the memory
6884 * destination for long mode!
6886 exn
= is_noncanonical_address(*ret
);
6887 } else if (is_protmode(vcpu
)) {
6888 /* Protected mode: apply checks for segment validity in the
6890 * - segment type check (#GP(0) may be thrown)
6891 * - usability check (#GP(0)/#SS(0))
6892 * - limit check (#GP(0)/#SS(0))
6895 /* #GP(0) if the destination operand is located in a
6896 * read-only data segment or any code segment.
6898 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6900 /* #GP(0) if the source operand is located in an
6901 * execute-only code segment
6903 exn
= ((s
.type
& 0xa) == 8);
6905 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6908 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6910 exn
= (s
.unusable
!= 0);
6911 /* Protected mode: #GP(0)/#SS(0) if the memory
6912 * operand is outside the segment limit.
6914 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6917 kvm_queue_exception_e(vcpu
,
6918 seg_reg
== VCPU_SREG_SS
?
6919 SS_VECTOR
: GP_VECTOR
,
6927 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
6930 struct x86_exception e
;
6932 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6933 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6936 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
6937 sizeof(*vmpointer
), &e
)) {
6938 kvm_inject_page_fault(vcpu
, &e
);
6945 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
6947 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6948 struct vmcs
*shadow_vmcs
;
6950 if (cpu_has_vmx_msr_bitmap()) {
6951 vmx
->nested
.msr_bitmap
=
6952 (unsigned long *)__get_free_page(GFP_KERNEL
);
6953 if (!vmx
->nested
.msr_bitmap
)
6954 goto out_msr_bitmap
;
6957 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
6958 if (!vmx
->nested
.cached_vmcs12
)
6959 goto out_cached_vmcs12
;
6961 if (enable_shadow_vmcs
) {
6962 shadow_vmcs
= alloc_vmcs();
6964 goto out_shadow_vmcs
;
6965 /* mark vmcs as shadow */
6966 shadow_vmcs
->revision_id
|= (1u << 31);
6967 /* init shadow vmcs */
6968 vmcs_clear(shadow_vmcs
);
6969 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
6972 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6973 vmx
->nested
.vmcs02_num
= 0;
6975 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6976 HRTIMER_MODE_REL_PINNED
);
6977 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6979 vmx
->nested
.vmxon
= true;
6983 kfree(vmx
->nested
.cached_vmcs12
);
6986 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
6993 * Emulate the VMXON instruction.
6994 * Currently, we just remember that VMX is active, and do not save or even
6995 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6996 * do not currently need to store anything in that guest-allocated memory
6997 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6998 * argument is different from the VMXON pointer (which the spec says they do).
7000 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7005 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7006 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7007 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7010 * The Intel VMX Instruction Reference lists a bunch of bits that are
7011 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7012 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7013 * Otherwise, we should fail with #UD. But most faulting conditions
7014 * have already been checked by hardware, prior to the VM-exit for
7015 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7016 * that bit set to 1 in non-root mode.
7018 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7019 kvm_queue_exception(vcpu
, UD_VECTOR
);
7023 if (vmx
->nested
.vmxon
) {
7024 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7025 return kvm_skip_emulated_instruction(vcpu
);
7028 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7029 != VMXON_NEEDED_FEATURES
) {
7030 kvm_inject_gp(vcpu
, 0);
7034 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7039 * The first 4 bytes of VMXON region contain the supported
7040 * VMCS revision identifier
7042 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7043 * which replaces physical address width with 32
7045 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7046 nested_vmx_failInvalid(vcpu
);
7047 return kvm_skip_emulated_instruction(vcpu
);
7050 page
= nested_get_page(vcpu
, vmptr
);
7052 nested_vmx_failInvalid(vcpu
);
7053 return kvm_skip_emulated_instruction(vcpu
);
7055 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7057 nested_release_page_clean(page
);
7058 nested_vmx_failInvalid(vcpu
);
7059 return kvm_skip_emulated_instruction(vcpu
);
7062 nested_release_page_clean(page
);
7064 vmx
->nested
.vmxon_ptr
= vmptr
;
7065 ret
= enter_vmx_operation(vcpu
);
7069 nested_vmx_succeed(vcpu
);
7070 return kvm_skip_emulated_instruction(vcpu
);
7074 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7075 * for running VMX instructions (except VMXON, whose prerequisites are
7076 * slightly different). It also specifies what exception to inject otherwise.
7077 * Note that many of these exceptions have priority over VM exits, so they
7078 * don't have to be checked again here.
7080 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7082 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7083 kvm_queue_exception(vcpu
, UD_VECTOR
);
7089 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7091 if (vmx
->nested
.current_vmptr
== -1ull)
7094 /* current_vmptr and current_vmcs12 are always set/reset together */
7095 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
7098 if (enable_shadow_vmcs
) {
7099 /* copy to memory all shadowed fields in case
7100 they were modified */
7101 copy_shadow_to_vmcs12(vmx
);
7102 vmx
->nested
.sync_shadow_vmcs
= false;
7103 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
7104 SECONDARY_EXEC_SHADOW_VMCS
);
7105 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7107 vmx
->nested
.posted_intr_nv
= -1;
7109 /* Flush VMCS12 to guest memory */
7110 memcpy(vmx
->nested
.current_vmcs12
, vmx
->nested
.cached_vmcs12
,
7113 kunmap(vmx
->nested
.current_vmcs12_page
);
7114 nested_release_page(vmx
->nested
.current_vmcs12_page
);
7115 vmx
->nested
.current_vmptr
= -1ull;
7116 vmx
->nested
.current_vmcs12
= NULL
;
7120 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7121 * just stops using VMX.
7123 static void free_nested(struct vcpu_vmx
*vmx
)
7125 if (!vmx
->nested
.vmxon
)
7128 vmx
->nested
.vmxon
= false;
7129 free_vpid(vmx
->nested
.vpid02
);
7130 nested_release_vmcs12(vmx
);
7131 if (vmx
->nested
.msr_bitmap
) {
7132 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7133 vmx
->nested
.msr_bitmap
= NULL
;
7135 if (enable_shadow_vmcs
) {
7136 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7137 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7138 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7140 kfree(vmx
->nested
.cached_vmcs12
);
7141 /* Unpin physical memory we referred to in current vmcs02 */
7142 if (vmx
->nested
.apic_access_page
) {
7143 nested_release_page(vmx
->nested
.apic_access_page
);
7144 vmx
->nested
.apic_access_page
= NULL
;
7146 if (vmx
->nested
.virtual_apic_page
) {
7147 nested_release_page(vmx
->nested
.virtual_apic_page
);
7148 vmx
->nested
.virtual_apic_page
= NULL
;
7150 if (vmx
->nested
.pi_desc_page
) {
7151 kunmap(vmx
->nested
.pi_desc_page
);
7152 nested_release_page(vmx
->nested
.pi_desc_page
);
7153 vmx
->nested
.pi_desc_page
= NULL
;
7154 vmx
->nested
.pi_desc
= NULL
;
7157 nested_free_all_saved_vmcss(vmx
);
7160 /* Emulate the VMXOFF instruction */
7161 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7163 if (!nested_vmx_check_permission(vcpu
))
7165 free_nested(to_vmx(vcpu
));
7166 nested_vmx_succeed(vcpu
);
7167 return kvm_skip_emulated_instruction(vcpu
);
7170 /* Emulate the VMCLEAR instruction */
7171 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7173 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7177 if (!nested_vmx_check_permission(vcpu
))
7180 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7183 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7184 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7185 return kvm_skip_emulated_instruction(vcpu
);
7188 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7189 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7190 return kvm_skip_emulated_instruction(vcpu
);
7193 if (vmptr
== vmx
->nested
.current_vmptr
)
7194 nested_release_vmcs12(vmx
);
7196 kvm_vcpu_write_guest(vcpu
,
7197 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7198 &zero
, sizeof(zero
));
7200 nested_free_vmcs02(vmx
, vmptr
);
7202 nested_vmx_succeed(vcpu
);
7203 return kvm_skip_emulated_instruction(vcpu
);
7206 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7208 /* Emulate the VMLAUNCH instruction */
7209 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7211 return nested_vmx_run(vcpu
, true);
7214 /* Emulate the VMRESUME instruction */
7215 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7218 return nested_vmx_run(vcpu
, false);
7221 enum vmcs_field_type
{
7222 VMCS_FIELD_TYPE_U16
= 0,
7223 VMCS_FIELD_TYPE_U64
= 1,
7224 VMCS_FIELD_TYPE_U32
= 2,
7225 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
7228 static inline int vmcs_field_type(unsigned long field
)
7230 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
7231 return VMCS_FIELD_TYPE_U32
;
7232 return (field
>> 13) & 0x3 ;
7235 static inline int vmcs_field_readonly(unsigned long field
)
7237 return (((field
>> 10) & 0x3) == 1);
7241 * Read a vmcs12 field. Since these can have varying lengths and we return
7242 * one type, we chose the biggest type (u64) and zero-extend the return value
7243 * to that size. Note that the caller, handle_vmread, might need to use only
7244 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7245 * 64-bit fields are to be returned).
7247 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7248 unsigned long field
, u64
*ret
)
7250 short offset
= vmcs_field_to_offset(field
);
7256 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7258 switch (vmcs_field_type(field
)) {
7259 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7260 *ret
= *((natural_width
*)p
);
7262 case VMCS_FIELD_TYPE_U16
:
7265 case VMCS_FIELD_TYPE_U32
:
7268 case VMCS_FIELD_TYPE_U64
:
7278 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7279 unsigned long field
, u64 field_value
){
7280 short offset
= vmcs_field_to_offset(field
);
7281 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7285 switch (vmcs_field_type(field
)) {
7286 case VMCS_FIELD_TYPE_U16
:
7287 *(u16
*)p
= field_value
;
7289 case VMCS_FIELD_TYPE_U32
:
7290 *(u32
*)p
= field_value
;
7292 case VMCS_FIELD_TYPE_U64
:
7293 *(u64
*)p
= field_value
;
7295 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7296 *(natural_width
*)p
= field_value
;
7305 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7308 unsigned long field
;
7310 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7311 const unsigned long *fields
= shadow_read_write_fields
;
7312 const int num_fields
= max_shadow_read_write_fields
;
7316 vmcs_load(shadow_vmcs
);
7318 for (i
= 0; i
< num_fields
; i
++) {
7320 switch (vmcs_field_type(field
)) {
7321 case VMCS_FIELD_TYPE_U16
:
7322 field_value
= vmcs_read16(field
);
7324 case VMCS_FIELD_TYPE_U32
:
7325 field_value
= vmcs_read32(field
);
7327 case VMCS_FIELD_TYPE_U64
:
7328 field_value
= vmcs_read64(field
);
7330 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7331 field_value
= vmcs_readl(field
);
7337 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7340 vmcs_clear(shadow_vmcs
);
7341 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7346 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7348 const unsigned long *fields
[] = {
7349 shadow_read_write_fields
,
7350 shadow_read_only_fields
7352 const int max_fields
[] = {
7353 max_shadow_read_write_fields
,
7354 max_shadow_read_only_fields
7357 unsigned long field
;
7358 u64 field_value
= 0;
7359 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7361 vmcs_load(shadow_vmcs
);
7363 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7364 for (i
= 0; i
< max_fields
[q
]; i
++) {
7365 field
= fields
[q
][i
];
7366 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7368 switch (vmcs_field_type(field
)) {
7369 case VMCS_FIELD_TYPE_U16
:
7370 vmcs_write16(field
, (u16
)field_value
);
7372 case VMCS_FIELD_TYPE_U32
:
7373 vmcs_write32(field
, (u32
)field_value
);
7375 case VMCS_FIELD_TYPE_U64
:
7376 vmcs_write64(field
, (u64
)field_value
);
7378 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7379 vmcs_writel(field
, (long)field_value
);
7388 vmcs_clear(shadow_vmcs
);
7389 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7393 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7394 * used before) all generate the same failure when it is missing.
7396 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7398 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7399 if (vmx
->nested
.current_vmptr
== -1ull) {
7400 nested_vmx_failInvalid(vcpu
);
7406 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7408 unsigned long field
;
7410 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7411 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7414 if (!nested_vmx_check_permission(vcpu
))
7417 if (!nested_vmx_check_vmcs12(vcpu
))
7418 return kvm_skip_emulated_instruction(vcpu
);
7420 /* Decode instruction info and find the field to read */
7421 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7422 /* Read the field, zero-extended to a u64 field_value */
7423 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7424 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7425 return kvm_skip_emulated_instruction(vcpu
);
7428 * Now copy part of this value to register or memory, as requested.
7429 * Note that the number of bits actually copied is 32 or 64 depending
7430 * on the guest's mode (32 or 64 bit), not on the given field's length.
7432 if (vmx_instruction_info
& (1u << 10)) {
7433 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7436 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7437 vmx_instruction_info
, true, &gva
))
7439 /* _system ok, as hardware has verified cpl=0 */
7440 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7441 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7444 nested_vmx_succeed(vcpu
);
7445 return kvm_skip_emulated_instruction(vcpu
);
7449 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7451 unsigned long field
;
7453 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7454 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7455 /* The value to write might be 32 or 64 bits, depending on L1's long
7456 * mode, and eventually we need to write that into a field of several
7457 * possible lengths. The code below first zero-extends the value to 64
7458 * bit (field_value), and then copies only the appropriate number of
7459 * bits into the vmcs12 field.
7461 u64 field_value
= 0;
7462 struct x86_exception e
;
7464 if (!nested_vmx_check_permission(vcpu
))
7467 if (!nested_vmx_check_vmcs12(vcpu
))
7468 return kvm_skip_emulated_instruction(vcpu
);
7470 if (vmx_instruction_info
& (1u << 10))
7471 field_value
= kvm_register_readl(vcpu
,
7472 (((vmx_instruction_info
) >> 3) & 0xf));
7474 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7475 vmx_instruction_info
, false, &gva
))
7477 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7478 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7479 kvm_inject_page_fault(vcpu
, &e
);
7485 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7486 if (vmcs_field_readonly(field
)) {
7487 nested_vmx_failValid(vcpu
,
7488 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7489 return kvm_skip_emulated_instruction(vcpu
);
7492 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7493 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7494 return kvm_skip_emulated_instruction(vcpu
);
7497 nested_vmx_succeed(vcpu
);
7498 return kvm_skip_emulated_instruction(vcpu
);
7501 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7503 vmx
->nested
.current_vmptr
= vmptr
;
7504 if (enable_shadow_vmcs
) {
7505 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7506 SECONDARY_EXEC_SHADOW_VMCS
);
7507 vmcs_write64(VMCS_LINK_POINTER
,
7508 __pa(vmx
->vmcs01
.shadow_vmcs
));
7509 vmx
->nested
.sync_shadow_vmcs
= true;
7513 /* Emulate the VMPTRLD instruction */
7514 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7516 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7519 if (!nested_vmx_check_permission(vcpu
))
7522 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7525 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7526 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7527 return kvm_skip_emulated_instruction(vcpu
);
7530 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7531 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7532 return kvm_skip_emulated_instruction(vcpu
);
7535 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7536 struct vmcs12
*new_vmcs12
;
7538 page
= nested_get_page(vcpu
, vmptr
);
7540 nested_vmx_failInvalid(vcpu
);
7541 return kvm_skip_emulated_instruction(vcpu
);
7543 new_vmcs12
= kmap(page
);
7544 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7546 nested_release_page_clean(page
);
7547 nested_vmx_failValid(vcpu
,
7548 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7549 return kvm_skip_emulated_instruction(vcpu
);
7552 nested_release_vmcs12(vmx
);
7553 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7554 vmx
->nested
.current_vmcs12_page
= page
;
7556 * Load VMCS12 from guest memory since it is not already
7559 memcpy(vmx
->nested
.cached_vmcs12
,
7560 vmx
->nested
.current_vmcs12
, VMCS12_SIZE
);
7561 set_current_vmptr(vmx
, vmptr
);
7564 nested_vmx_succeed(vcpu
);
7565 return kvm_skip_emulated_instruction(vcpu
);
7568 /* Emulate the VMPTRST instruction */
7569 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7571 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7572 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7574 struct x86_exception e
;
7576 if (!nested_vmx_check_permission(vcpu
))
7579 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7580 vmx_instruction_info
, true, &vmcs_gva
))
7582 /* ok to use *_system, as hardware has verified cpl=0 */
7583 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7584 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7586 kvm_inject_page_fault(vcpu
, &e
);
7589 nested_vmx_succeed(vcpu
);
7590 return kvm_skip_emulated_instruction(vcpu
);
7593 /* Emulate the INVEPT instruction */
7594 static int handle_invept(struct kvm_vcpu
*vcpu
)
7596 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7597 u32 vmx_instruction_info
, types
;
7600 struct x86_exception e
;
7605 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7606 SECONDARY_EXEC_ENABLE_EPT
) ||
7607 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7608 kvm_queue_exception(vcpu
, UD_VECTOR
);
7612 if (!nested_vmx_check_permission(vcpu
))
7615 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7616 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7618 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7620 if (type
>= 32 || !(types
& (1 << type
))) {
7621 nested_vmx_failValid(vcpu
,
7622 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7623 return kvm_skip_emulated_instruction(vcpu
);
7626 /* According to the Intel VMX instruction reference, the memory
7627 * operand is read even if it isn't needed (e.g., for type==global)
7629 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7630 vmx_instruction_info
, false, &gva
))
7632 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7633 sizeof(operand
), &e
)) {
7634 kvm_inject_page_fault(vcpu
, &e
);
7639 case VMX_EPT_EXTENT_GLOBAL
:
7641 * TODO: track mappings and invalidate
7642 * single context requests appropriately
7644 case VMX_EPT_EXTENT_CONTEXT
:
7645 kvm_mmu_sync_roots(vcpu
);
7646 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7647 nested_vmx_succeed(vcpu
);
7654 return kvm_skip_emulated_instruction(vcpu
);
7657 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7659 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7660 u32 vmx_instruction_info
;
7661 unsigned long type
, types
;
7663 struct x86_exception e
;
7666 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7667 SECONDARY_EXEC_ENABLE_VPID
) ||
7668 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7669 kvm_queue_exception(vcpu
, UD_VECTOR
);
7673 if (!nested_vmx_check_permission(vcpu
))
7676 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7677 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7679 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7680 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7682 if (type
>= 32 || !(types
& (1 << type
))) {
7683 nested_vmx_failValid(vcpu
,
7684 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7685 return kvm_skip_emulated_instruction(vcpu
);
7688 /* according to the intel vmx instruction reference, the memory
7689 * operand is read even if it isn't needed (e.g., for type==global)
7691 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7692 vmx_instruction_info
, false, &gva
))
7694 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7696 kvm_inject_page_fault(vcpu
, &e
);
7701 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7702 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7703 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7705 nested_vmx_failValid(vcpu
,
7706 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7707 return kvm_skip_emulated_instruction(vcpu
);
7710 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7714 return kvm_skip_emulated_instruction(vcpu
);
7717 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7718 nested_vmx_succeed(vcpu
);
7720 return kvm_skip_emulated_instruction(vcpu
);
7723 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7725 unsigned long exit_qualification
;
7727 trace_kvm_pml_full(vcpu
->vcpu_id
);
7729 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7732 * PML buffer FULL happened while executing iret from NMI,
7733 * "blocked by NMI" bit has to be set before next VM entry.
7735 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7736 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7737 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7738 GUEST_INTR_STATE_NMI
);
7741 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7742 * here.., and there's no userspace involvement needed for PML.
7747 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7749 kvm_lapic_expired_hv_timer(vcpu
);
7754 * The exit handlers return 1 if the exit was handled fully and guest execution
7755 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7756 * to be done to userspace and return 0.
7758 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7759 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7760 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7761 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7762 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7763 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7764 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7765 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7766 [EXIT_REASON_CPUID
] = handle_cpuid
,
7767 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7768 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7769 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7770 [EXIT_REASON_HLT
] = handle_halt
,
7771 [EXIT_REASON_INVD
] = handle_invd
,
7772 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7773 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7774 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7775 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7776 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7777 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7778 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7779 [EXIT_REASON_VMREAD
] = handle_vmread
,
7780 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7781 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7782 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7783 [EXIT_REASON_VMON
] = handle_vmon
,
7784 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7785 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7786 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7787 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7788 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7789 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7790 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7791 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7792 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7793 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7794 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7795 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7796 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7797 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7798 [EXIT_REASON_INVEPT
] = handle_invept
,
7799 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7800 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7801 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7802 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7803 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7806 static const int kvm_vmx_max_exit_handlers
=
7807 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7809 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7810 struct vmcs12
*vmcs12
)
7812 unsigned long exit_qualification
;
7813 gpa_t bitmap
, last_bitmap
;
7818 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7819 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7821 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7823 port
= exit_qualification
>> 16;
7824 size
= (exit_qualification
& 7) + 1;
7826 last_bitmap
= (gpa_t
)-1;
7831 bitmap
= vmcs12
->io_bitmap_a
;
7832 else if (port
< 0x10000)
7833 bitmap
= vmcs12
->io_bitmap_b
;
7836 bitmap
+= (port
& 0x7fff) / 8;
7838 if (last_bitmap
!= bitmap
)
7839 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7841 if (b
& (1 << (port
& 7)))
7846 last_bitmap
= bitmap
;
7853 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7854 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7855 * disinterest in the current event (read or write a specific MSR) by using an
7856 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7858 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7859 struct vmcs12
*vmcs12
, u32 exit_reason
)
7861 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7864 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7868 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7869 * for the four combinations of read/write and low/high MSR numbers.
7870 * First we need to figure out which of the four to use:
7872 bitmap
= vmcs12
->msr_bitmap
;
7873 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7875 if (msr_index
>= 0xc0000000) {
7876 msr_index
-= 0xc0000000;
7880 /* Then read the msr_index'th bit from this bitmap: */
7881 if (msr_index
< 1024*8) {
7883 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7885 return 1 & (b
>> (msr_index
& 7));
7887 return true; /* let L1 handle the wrong parameter */
7891 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7892 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7893 * intercept (via guest_host_mask etc.) the current event.
7895 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7896 struct vmcs12
*vmcs12
)
7898 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7899 int cr
= exit_qualification
& 15;
7903 switch ((exit_qualification
>> 4) & 3) {
7904 case 0: /* mov to cr */
7905 reg
= (exit_qualification
>> 8) & 15;
7906 val
= kvm_register_readl(vcpu
, reg
);
7909 if (vmcs12
->cr0_guest_host_mask
&
7910 (val
^ vmcs12
->cr0_read_shadow
))
7914 if ((vmcs12
->cr3_target_count
>= 1 &&
7915 vmcs12
->cr3_target_value0
== val
) ||
7916 (vmcs12
->cr3_target_count
>= 2 &&
7917 vmcs12
->cr3_target_value1
== val
) ||
7918 (vmcs12
->cr3_target_count
>= 3 &&
7919 vmcs12
->cr3_target_value2
== val
) ||
7920 (vmcs12
->cr3_target_count
>= 4 &&
7921 vmcs12
->cr3_target_value3
== val
))
7923 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7927 if (vmcs12
->cr4_guest_host_mask
&
7928 (vmcs12
->cr4_read_shadow
^ val
))
7932 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7938 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7939 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7942 case 1: /* mov from cr */
7945 if (vmcs12
->cpu_based_vm_exec_control
&
7946 CPU_BASED_CR3_STORE_EXITING
)
7950 if (vmcs12
->cpu_based_vm_exec_control
&
7951 CPU_BASED_CR8_STORE_EXITING
)
7958 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7959 * cr0. Other attempted changes are ignored, with no exit.
7961 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
7962 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7963 (val
^ vmcs12
->cr0_read_shadow
))
7965 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7966 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7975 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7976 * should handle it ourselves in L0 (and then continue L2). Only call this
7977 * when in is_guest_mode (L2).
7979 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7981 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7982 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7983 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7984 u32 exit_reason
= vmx
->exit_reason
;
7986 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7987 vmcs_readl(EXIT_QUALIFICATION
),
7988 vmx
->idt_vectoring_info
,
7990 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7993 if (vmx
->nested
.nested_run_pending
)
7996 if (unlikely(vmx
->fail
)) {
7997 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7998 vmcs_read32(VM_INSTRUCTION_ERROR
));
8002 switch (exit_reason
) {
8003 case EXIT_REASON_EXCEPTION_NMI
:
8004 if (is_nmi(intr_info
))
8006 else if (is_page_fault(intr_info
))
8008 else if (is_no_device(intr_info
) &&
8009 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8011 else if (is_debug(intr_info
) &&
8013 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8015 else if (is_breakpoint(intr_info
) &&
8016 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8018 return vmcs12
->exception_bitmap
&
8019 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8020 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8022 case EXIT_REASON_TRIPLE_FAULT
:
8024 case EXIT_REASON_PENDING_INTERRUPT
:
8025 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8026 case EXIT_REASON_NMI_WINDOW
:
8027 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8028 case EXIT_REASON_TASK_SWITCH
:
8030 case EXIT_REASON_CPUID
:
8032 case EXIT_REASON_HLT
:
8033 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8034 case EXIT_REASON_INVD
:
8036 case EXIT_REASON_INVLPG
:
8037 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8038 case EXIT_REASON_RDPMC
:
8039 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8040 case EXIT_REASON_RDRAND
:
8041 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND
);
8042 case EXIT_REASON_RDSEED
:
8043 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED
);
8044 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8045 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8046 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8047 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8048 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8049 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8050 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8051 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8053 * VMX instructions trap unconditionally. This allows L1 to
8054 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8057 case EXIT_REASON_CR_ACCESS
:
8058 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8059 case EXIT_REASON_DR_ACCESS
:
8060 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8061 case EXIT_REASON_IO_INSTRUCTION
:
8062 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8063 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8064 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8065 case EXIT_REASON_MSR_READ
:
8066 case EXIT_REASON_MSR_WRITE
:
8067 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8068 case EXIT_REASON_INVALID_STATE
:
8070 case EXIT_REASON_MWAIT_INSTRUCTION
:
8071 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8072 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8073 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8074 case EXIT_REASON_MONITOR_INSTRUCTION
:
8075 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8076 case EXIT_REASON_PAUSE_INSTRUCTION
:
8077 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8078 nested_cpu_has2(vmcs12
,
8079 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8080 case EXIT_REASON_MCE_DURING_VMENTRY
:
8082 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8083 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8084 case EXIT_REASON_APIC_ACCESS
:
8085 return nested_cpu_has2(vmcs12
,
8086 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8087 case EXIT_REASON_APIC_WRITE
:
8088 case EXIT_REASON_EOI_INDUCED
:
8089 /* apic_write and eoi_induced should exit unconditionally. */
8091 case EXIT_REASON_EPT_VIOLATION
:
8093 * L0 always deals with the EPT violation. If nested EPT is
8094 * used, and the nested mmu code discovers that the address is
8095 * missing in the guest EPT table (EPT12), the EPT violation
8096 * will be injected with nested_ept_inject_page_fault()
8099 case EXIT_REASON_EPT_MISCONFIG
:
8101 * L2 never uses directly L1's EPT, but rather L0's own EPT
8102 * table (shadow on EPT) or a merged EPT table that L0 built
8103 * (EPT on EPT). So any problems with the structure of the
8104 * table is L0's fault.
8107 case EXIT_REASON_WBINVD
:
8108 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8109 case EXIT_REASON_XSETBV
:
8111 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8113 * This should never happen, since it is not possible to
8114 * set XSS to a non-zero value---neither in L1 nor in L2.
8115 * If if it were, XSS would have to be checked against
8116 * the XSS exit bitmap in vmcs12.
8118 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8119 case EXIT_REASON_PREEMPTION_TIMER
:
8121 case EXIT_REASON_PML_FULL
:
8122 /* We emulate PML support to L1. */
8129 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8131 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8132 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8135 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8138 __free_page(vmx
->pml_pg
);
8143 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8145 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8149 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8151 /* Do nothing if PML buffer is empty */
8152 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8155 /* PML index always points to next available PML buffer entity */
8156 if (pml_idx
>= PML_ENTITY_NUM
)
8161 pml_buf
= page_address(vmx
->pml_pg
);
8162 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8165 gpa
= pml_buf
[pml_idx
];
8166 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8167 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8170 /* reset PML index */
8171 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8175 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8176 * Called before reporting dirty_bitmap to userspace.
8178 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8181 struct kvm_vcpu
*vcpu
;
8183 * We only need to kick vcpu out of guest mode here, as PML buffer
8184 * is flushed at beginning of all VMEXITs, and it's obvious that only
8185 * vcpus running in guest are possible to have unflushed GPAs in PML
8188 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8189 kvm_vcpu_kick(vcpu
);
8192 static void vmx_dump_sel(char *name
, uint32_t sel
)
8194 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8195 name
, vmcs_read16(sel
),
8196 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8197 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8198 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8201 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8203 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8204 name
, vmcs_read32(limit
),
8205 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8208 static void dump_vmcs(void)
8210 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8211 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8212 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8213 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8214 u32 secondary_exec_control
= 0;
8215 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8216 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8219 if (cpu_has_secondary_exec_ctrls())
8220 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8222 pr_err("*** Guest State ***\n");
8223 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8224 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8225 vmcs_readl(CR0_GUEST_HOST_MASK
));
8226 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8227 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8228 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8229 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8230 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8232 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8233 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8234 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8235 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8237 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8238 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8239 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8240 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8241 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8242 vmcs_readl(GUEST_SYSENTER_ESP
),
8243 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8244 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8245 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8246 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8247 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8248 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8249 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8250 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8251 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8252 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8253 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8254 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8255 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8256 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8257 efer
, vmcs_read64(GUEST_IA32_PAT
));
8258 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8259 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8260 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8261 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8262 pr_err("PerfGlobCtl = 0x%016llx\n",
8263 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8264 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8265 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8266 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8267 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8268 vmcs_read32(GUEST_ACTIVITY_STATE
));
8269 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8270 pr_err("InterruptStatus = %04x\n",
8271 vmcs_read16(GUEST_INTR_STATUS
));
8273 pr_err("*** Host State ***\n");
8274 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8275 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8276 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8277 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8278 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8279 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8280 vmcs_read16(HOST_TR_SELECTOR
));
8281 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8282 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8283 vmcs_readl(HOST_TR_BASE
));
8284 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8285 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8286 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8287 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8288 vmcs_readl(HOST_CR4
));
8289 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8290 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8291 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8292 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8293 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8294 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8295 vmcs_read64(HOST_IA32_EFER
),
8296 vmcs_read64(HOST_IA32_PAT
));
8297 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8298 pr_err("PerfGlobCtl = 0x%016llx\n",
8299 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8301 pr_err("*** Control State ***\n");
8302 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8303 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8304 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8305 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8306 vmcs_read32(EXCEPTION_BITMAP
),
8307 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8308 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8309 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8310 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8311 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8312 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8313 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8314 vmcs_read32(VM_EXIT_INTR_INFO
),
8315 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8316 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8317 pr_err(" reason=%08x qualification=%016lx\n",
8318 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8319 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8320 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8321 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8322 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8323 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8324 pr_err("TSC Multiplier = 0x%016llx\n",
8325 vmcs_read64(TSC_MULTIPLIER
));
8326 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8327 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8328 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8329 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8330 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8331 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8332 n
= vmcs_read32(CR3_TARGET_COUNT
);
8333 for (i
= 0; i
+ 1 < n
; i
+= 4)
8334 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8335 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8336 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8338 pr_err("CR3 target%u=%016lx\n",
8339 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8340 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8341 pr_err("PLE Gap=%08x Window=%08x\n",
8342 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8343 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8344 pr_err("Virtual processor ID = 0x%04x\n",
8345 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8349 * The guest has exited. See if we can fix it or if we need userspace
8352 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8354 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8355 u32 exit_reason
= vmx
->exit_reason
;
8356 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8358 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8359 vcpu
->arch
.gpa_available
= false;
8362 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8363 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8364 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8365 * mode as if vcpus is in root mode, the PML buffer must has been
8369 vmx_flush_pml_buffer(vcpu
);
8371 /* If guest state is invalid, start emulating */
8372 if (vmx
->emulation_required
)
8373 return handle_invalid_guest_state(vcpu
);
8375 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8376 nested_vmx_vmexit(vcpu
, exit_reason
,
8377 vmcs_read32(VM_EXIT_INTR_INFO
),
8378 vmcs_readl(EXIT_QUALIFICATION
));
8382 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8384 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8385 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8390 if (unlikely(vmx
->fail
)) {
8391 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8392 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8393 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8399 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8400 * delivery event since it indicates guest is accessing MMIO.
8401 * The vm-exit can be triggered again after return to guest that
8402 * will cause infinite loop.
8404 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8405 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8406 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8407 exit_reason
!= EXIT_REASON_PML_FULL
&&
8408 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8409 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8410 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8411 vcpu
->run
->internal
.ndata
= 2;
8412 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8413 vcpu
->run
->internal
.data
[1] = exit_reason
;
8417 if (exit_reason
< kvm_vmx_max_exit_handlers
8418 && kvm_vmx_exit_handlers
[exit_reason
])
8419 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8421 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8423 kvm_queue_exception(vcpu
, UD_VECTOR
);
8428 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8430 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8432 if (is_guest_mode(vcpu
) &&
8433 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8436 if (irr
== -1 || tpr
< irr
) {
8437 vmcs_write32(TPR_THRESHOLD
, 0);
8441 vmcs_write32(TPR_THRESHOLD
, irr
);
8444 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8446 u32 sec_exec_control
;
8448 /* Postpone execution until vmcs01 is the current VMCS. */
8449 if (is_guest_mode(vcpu
)) {
8450 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8454 if (!cpu_has_vmx_virtualize_x2apic_mode())
8457 if (!cpu_need_tpr_shadow(vcpu
))
8460 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8463 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8464 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8466 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8467 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8468 vmx_flush_tlb_ept_only(vcpu
);
8470 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8472 vmx_set_msr_bitmap(vcpu
);
8475 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8477 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8480 * Currently we do not handle the nested case where L2 has an
8481 * APIC access page of its own; that page is still pinned.
8482 * Hence, we skip the case where the VCPU is in guest mode _and_
8483 * L1 prepared an APIC access page for L2.
8485 * For the case where L1 and L2 share the same APIC access page
8486 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8487 * in the vmcs12), this function will only update either the vmcs01
8488 * or the vmcs02. If the former, the vmcs02 will be updated by
8489 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8490 * the next L2->L1 exit.
8492 if (!is_guest_mode(vcpu
) ||
8493 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8494 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8495 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8496 vmx_flush_tlb_ept_only(vcpu
);
8500 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8508 status
= vmcs_read16(GUEST_INTR_STATUS
);
8510 if (max_isr
!= old
) {
8512 status
|= max_isr
<< 8;
8513 vmcs_write16(GUEST_INTR_STATUS
, status
);
8517 static void vmx_set_rvi(int vector
)
8525 status
= vmcs_read16(GUEST_INTR_STATUS
);
8526 old
= (u8
)status
& 0xff;
8527 if ((u8
)vector
!= old
) {
8529 status
|= (u8
)vector
;
8530 vmcs_write16(GUEST_INTR_STATUS
, status
);
8534 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8536 if (!is_guest_mode(vcpu
)) {
8537 vmx_set_rvi(max_irr
);
8545 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8548 if (nested_exit_on_intr(vcpu
))
8552 * Else, fall back to pre-APICv interrupt injection since L2
8553 * is run without virtual interrupt delivery.
8555 if (!kvm_event_needs_reinjection(vcpu
) &&
8556 vmx_interrupt_allowed(vcpu
)) {
8557 kvm_queue_interrupt(vcpu
, max_irr
, false);
8558 vmx_inject_irq(vcpu
);
8562 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8564 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8567 WARN_ON(!vcpu
->arch
.apicv_active
);
8568 if (pi_test_on(&vmx
->pi_desc
)) {
8569 pi_clear_on(&vmx
->pi_desc
);
8571 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8572 * But on x86 this is just a compiler barrier anyway.
8574 smp_mb__after_atomic();
8575 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8577 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8579 vmx_hwapic_irr_update(vcpu
, max_irr
);
8583 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8585 if (!kvm_vcpu_apicv_active(vcpu
))
8588 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8589 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8590 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8591 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8594 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
8596 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8598 pi_clear_on(&vmx
->pi_desc
);
8599 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
8602 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8606 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8607 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8610 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8611 exit_intr_info
= vmx
->exit_intr_info
;
8613 /* Handle machine checks before interrupts are enabled */
8614 if (is_machine_check(exit_intr_info
))
8615 kvm_machine_check();
8617 /* We need to handle NMIs before interrupts are enabled */
8618 if (is_nmi(exit_intr_info
)) {
8619 kvm_before_handle_nmi(&vmx
->vcpu
);
8621 kvm_after_handle_nmi(&vmx
->vcpu
);
8625 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8627 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8628 register void *__sp
asm(_ASM_SP
);
8630 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8631 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8632 unsigned int vector
;
8633 unsigned long entry
;
8635 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8636 #ifdef CONFIG_X86_64
8640 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8641 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8642 entry
= gate_offset(*desc
);
8644 #ifdef CONFIG_X86_64
8645 "mov %%" _ASM_SP
", %[sp]\n\t"
8646 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8651 __ASM_SIZE(push
) " $%c[cs]\n\t"
8652 "call *%[entry]\n\t"
8654 #ifdef CONFIG_X86_64
8660 [ss
]"i"(__KERNEL_DS
),
8661 [cs
]"i"(__KERNEL_CS
)
8665 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
8667 static bool vmx_has_high_real_mode_segbase(void)
8669 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8672 static bool vmx_mpx_supported(void)
8674 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8675 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8678 static bool vmx_xsaves_supported(void)
8680 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8681 SECONDARY_EXEC_XSAVES
;
8684 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8689 bool idtv_info_valid
;
8691 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8693 if (vmx
->nmi_known_unmasked
)
8696 * Can't use vmx->exit_intr_info since we're not sure what
8697 * the exit reason is.
8699 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8700 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8701 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8703 * SDM 3: 27.7.1.2 (September 2008)
8704 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8705 * a guest IRET fault.
8706 * SDM 3: 23.2.2 (September 2008)
8707 * Bit 12 is undefined in any of the following cases:
8708 * If the VM exit sets the valid bit in the IDT-vectoring
8709 * information field.
8710 * If the VM exit is due to a double fault.
8712 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8713 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8714 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8715 GUEST_INTR_STATE_NMI
);
8717 vmx
->nmi_known_unmasked
=
8718 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8719 & GUEST_INTR_STATE_NMI
);
8722 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8723 u32 idt_vectoring_info
,
8724 int instr_len_field
,
8725 int error_code_field
)
8729 bool idtv_info_valid
;
8731 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8733 vcpu
->arch
.nmi_injected
= false;
8734 kvm_clear_exception_queue(vcpu
);
8735 kvm_clear_interrupt_queue(vcpu
);
8737 if (!idtv_info_valid
)
8740 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8742 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8743 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8746 case INTR_TYPE_NMI_INTR
:
8747 vcpu
->arch
.nmi_injected
= true;
8749 * SDM 3: 27.7.1.2 (September 2008)
8750 * Clear bit "block by NMI" before VM entry if a NMI
8753 vmx_set_nmi_mask(vcpu
, false);
8755 case INTR_TYPE_SOFT_EXCEPTION
:
8756 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8758 case INTR_TYPE_HARD_EXCEPTION
:
8759 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8760 u32 err
= vmcs_read32(error_code_field
);
8761 kvm_requeue_exception_e(vcpu
, vector
, err
);
8763 kvm_requeue_exception(vcpu
, vector
);
8765 case INTR_TYPE_SOFT_INTR
:
8766 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8768 case INTR_TYPE_EXT_INTR
:
8769 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8776 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8778 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8779 VM_EXIT_INSTRUCTION_LEN
,
8780 IDT_VECTORING_ERROR_CODE
);
8783 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8785 __vmx_complete_interrupts(vcpu
,
8786 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8787 VM_ENTRY_INSTRUCTION_LEN
,
8788 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8790 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8793 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8796 struct perf_guest_switch_msr
*msrs
;
8798 msrs
= perf_guest_get_msrs(&nr_msrs
);
8803 for (i
= 0; i
< nr_msrs
; i
++)
8804 if (msrs
[i
].host
== msrs
[i
].guest
)
8805 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8807 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8811 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8813 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8817 if (vmx
->hv_deadline_tsc
== -1)
8821 if (vmx
->hv_deadline_tsc
> tscl
)
8822 /* sure to be 32 bit only because checked on set_hv_timer */
8823 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8824 cpu_preemption_timer_multi
);
8828 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8831 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8833 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8834 unsigned long debugctlmsr
, cr3
, cr4
;
8836 /* Don't enter VMX if guest state is invalid, let the exit handler
8837 start emulation until we arrive back to a valid state */
8838 if (vmx
->emulation_required
)
8841 if (vmx
->ple_window_dirty
) {
8842 vmx
->ple_window_dirty
= false;
8843 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8846 if (vmx
->nested
.sync_shadow_vmcs
) {
8847 copy_vmcs12_to_shadow(vmx
);
8848 vmx
->nested
.sync_shadow_vmcs
= false;
8851 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8852 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8853 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8854 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8856 cr3
= __get_current_cr3_fast();
8857 if (unlikely(cr3
!= vmx
->host_state
.vmcs_host_cr3
)) {
8858 vmcs_writel(HOST_CR3
, cr3
);
8859 vmx
->host_state
.vmcs_host_cr3
= cr3
;
8862 cr4
= cr4_read_shadow();
8863 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8864 vmcs_writel(HOST_CR4
, cr4
);
8865 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8868 /* When single-stepping over STI and MOV SS, we must clear the
8869 * corresponding interruptibility bits in the guest state. Otherwise
8870 * vmentry fails as it then expects bit 14 (BS) in pending debug
8871 * exceptions being set, but that's not correct for the guest debugging
8873 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8874 vmx_set_interrupt_shadow(vcpu
, 0);
8876 if (vmx
->guest_pkru_valid
)
8877 __write_pkru(vmx
->guest_pkru
);
8879 atomic_switch_perf_msrs(vmx
);
8880 debugctlmsr
= get_debugctlmsr();
8882 vmx_arm_hv_timer(vcpu
);
8884 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8886 /* Store host registers */
8887 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8888 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8889 "push %%" _ASM_CX
" \n\t"
8890 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8892 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8893 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8895 /* Reload cr2 if changed */
8896 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8897 "mov %%cr2, %%" _ASM_DX
" \n\t"
8898 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8900 "mov %%" _ASM_AX
", %%cr2 \n\t"
8902 /* Check if vmlaunch of vmresume is needed */
8903 "cmpl $0, %c[launched](%0) \n\t"
8904 /* Load guest registers. Don't clobber flags. */
8905 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8906 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8907 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8908 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8909 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8910 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8911 #ifdef CONFIG_X86_64
8912 "mov %c[r8](%0), %%r8 \n\t"
8913 "mov %c[r9](%0), %%r9 \n\t"
8914 "mov %c[r10](%0), %%r10 \n\t"
8915 "mov %c[r11](%0), %%r11 \n\t"
8916 "mov %c[r12](%0), %%r12 \n\t"
8917 "mov %c[r13](%0), %%r13 \n\t"
8918 "mov %c[r14](%0), %%r14 \n\t"
8919 "mov %c[r15](%0), %%r15 \n\t"
8921 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8923 /* Enter guest mode */
8925 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8927 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8929 /* Save guest registers, load host registers, keep flags */
8930 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8932 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8933 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8934 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8935 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8936 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8937 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8938 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8939 #ifdef CONFIG_X86_64
8940 "mov %%r8, %c[r8](%0) \n\t"
8941 "mov %%r9, %c[r9](%0) \n\t"
8942 "mov %%r10, %c[r10](%0) \n\t"
8943 "mov %%r11, %c[r11](%0) \n\t"
8944 "mov %%r12, %c[r12](%0) \n\t"
8945 "mov %%r13, %c[r13](%0) \n\t"
8946 "mov %%r14, %c[r14](%0) \n\t"
8947 "mov %%r15, %c[r15](%0) \n\t"
8949 "mov %%cr2, %%" _ASM_AX
" \n\t"
8950 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8952 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8953 "setbe %c[fail](%0) \n\t"
8954 ".pushsection .rodata \n\t"
8955 ".global vmx_return \n\t"
8956 "vmx_return: " _ASM_PTR
" 2b \n\t"
8958 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8959 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8960 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8961 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8962 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8963 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8964 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8965 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8966 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8967 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8968 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8969 #ifdef CONFIG_X86_64
8970 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8971 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8972 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8973 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8974 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8975 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8976 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8977 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8979 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8980 [wordsize
]"i"(sizeof(ulong
))
8982 #ifdef CONFIG_X86_64
8983 , "rax", "rbx", "rdi", "rsi"
8984 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8986 , "eax", "ebx", "edi", "esi"
8990 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8992 update_debugctlmsr(debugctlmsr
);
8994 #ifndef CONFIG_X86_64
8996 * The sysexit path does not restore ds/es, so we must set them to
8997 * a reasonable value ourselves.
8999 * We can't defer this to vmx_load_host_state() since that function
9000 * may be executed in interrupt context, which saves and restore segments
9001 * around it, nullifying its effect.
9003 loadsegment(ds
, __USER_DS
);
9004 loadsegment(es
, __USER_DS
);
9007 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9008 | (1 << VCPU_EXREG_RFLAGS
)
9009 | (1 << VCPU_EXREG_PDPTR
)
9010 | (1 << VCPU_EXREG_SEGMENTS
)
9011 | (1 << VCPU_EXREG_CR3
));
9012 vcpu
->arch
.regs_dirty
= 0;
9014 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9016 vmx
->loaded_vmcs
->launched
= 1;
9018 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
9021 * eager fpu is enabled if PKEY is supported and CR4 is switched
9022 * back on host, so it is safe to read guest PKRU from current
9025 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
9026 vmx
->guest_pkru
= __read_pkru();
9027 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
9028 vmx
->guest_pkru_valid
= true;
9029 __write_pkru(vmx
->host_pkru
);
9031 vmx
->guest_pkru_valid
= false;
9035 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9036 * we did not inject a still-pending event to L1 now because of
9037 * nested_run_pending, we need to re-enable this bit.
9039 if (vmx
->nested
.nested_run_pending
)
9040 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9042 vmx
->nested
.nested_run_pending
= 0;
9044 vmx_complete_atomic_exit(vmx
);
9045 vmx_recover_nmi_blocking(vmx
);
9046 vmx_complete_interrupts(vmx
);
9048 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9050 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9052 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9055 if (vmx
->loaded_vmcs
== vmcs
)
9059 vmx
->loaded_vmcs
= vmcs
;
9061 vmx_vcpu_load(vcpu
, cpu
);
9067 * Ensure that the current vmcs of the logical processor is the
9068 * vmcs01 of the vcpu before calling free_nested().
9070 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9072 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9075 r
= vcpu_load(vcpu
);
9077 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9082 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9084 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9087 vmx_destroy_pml_buffer(vmx
);
9088 free_vpid(vmx
->vpid
);
9089 leave_guest_mode(vcpu
);
9090 vmx_free_vcpu_nested(vcpu
);
9091 free_loaded_vmcs(vmx
->loaded_vmcs
);
9092 kfree(vmx
->guest_msrs
);
9093 kvm_vcpu_uninit(vcpu
);
9094 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9097 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9100 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9104 return ERR_PTR(-ENOMEM
);
9106 vmx
->vpid
= allocate_vpid();
9108 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9115 * If PML is turned on, failure on enabling PML just results in failure
9116 * of creating the vcpu, therefore we can simplify PML logic (by
9117 * avoiding dealing with cases, such as enabling PML partially on vcpus
9118 * for the guest, etc.
9121 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9126 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9127 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9130 if (!vmx
->guest_msrs
)
9133 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9134 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9135 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9136 if (!vmx
->loaded_vmcs
->vmcs
)
9138 loaded_vmcs_init(vmx
->loaded_vmcs
);
9141 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9142 vmx
->vcpu
.cpu
= cpu
;
9143 err
= vmx_vcpu_setup(vmx
);
9144 vmx_vcpu_put(&vmx
->vcpu
);
9148 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9149 err
= alloc_apic_access_page(kvm
);
9155 if (!kvm
->arch
.ept_identity_map_addr
)
9156 kvm
->arch
.ept_identity_map_addr
=
9157 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9158 err
= init_rmode_identity_map(kvm
);
9164 nested_vmx_setup_ctls_msrs(vmx
);
9165 vmx
->nested
.vpid02
= allocate_vpid();
9168 vmx
->nested
.posted_intr_nv
= -1;
9169 vmx
->nested
.current_vmptr
= -1ull;
9170 vmx
->nested
.current_vmcs12
= NULL
;
9172 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9177 free_vpid(vmx
->nested
.vpid02
);
9178 free_loaded_vmcs(vmx
->loaded_vmcs
);
9180 kfree(vmx
->guest_msrs
);
9182 vmx_destroy_pml_buffer(vmx
);
9184 kvm_vcpu_uninit(&vmx
->vcpu
);
9186 free_vpid(vmx
->vpid
);
9187 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9188 return ERR_PTR(err
);
9191 static void __init
vmx_check_processor_compat(void *rtn
)
9193 struct vmcs_config vmcs_conf
;
9196 if (setup_vmcs_config(&vmcs_conf
) < 0)
9198 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9199 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9200 smp_processor_id());
9205 static int get_ept_level(void)
9207 return VMX_EPT_DEFAULT_GAW
+ 1;
9210 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9215 /* For VT-d and EPT combination
9216 * 1. MMIO: always map as UC
9218 * a. VT-d without snooping control feature: can't guarantee the
9219 * result, try to trust guest.
9220 * b. VT-d with snooping control feature: snooping control feature of
9221 * VT-d engine can guarantee the cache correctness. Just set it
9222 * to WB to keep consistent with host. So the same as item 3.
9223 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9224 * consistent with host MTRR
9227 cache
= MTRR_TYPE_UNCACHABLE
;
9231 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9232 ipat
= VMX_EPT_IPAT_BIT
;
9233 cache
= MTRR_TYPE_WRBACK
;
9237 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9238 ipat
= VMX_EPT_IPAT_BIT
;
9239 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9240 cache
= MTRR_TYPE_WRBACK
;
9242 cache
= MTRR_TYPE_UNCACHABLE
;
9246 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9249 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9252 static int vmx_get_lpage_level(void)
9254 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9255 return PT_DIRECTORY_LEVEL
;
9257 /* For shadow and EPT supported 1GB page */
9258 return PT_PDPE_LEVEL
;
9261 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9264 * These bits in the secondary execution controls field
9265 * are dynamic, the others are mostly based on the hypervisor
9266 * architecture and the guest's CPUID. Do not touch the
9270 SECONDARY_EXEC_SHADOW_VMCS
|
9271 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9272 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9274 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9276 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9277 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9281 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9282 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9284 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9286 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9287 struct kvm_cpuid_entry2
*entry
;
9289 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9290 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9292 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9293 if (entry && (entry->_reg & (_cpuid_mask))) \
9294 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9297 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9298 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9299 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9300 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9301 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9302 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9303 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9304 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9305 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9306 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9307 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9308 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9309 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9310 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9311 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9313 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9314 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9315 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9316 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9317 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9318 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9319 cr4_fixed1_update(bit(11), ecx
, bit(2));
9321 #undef cr4_fixed1_update
9324 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9326 struct kvm_cpuid_entry2
*best
;
9327 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9328 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9330 if (vmx_rdtscp_supported()) {
9331 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9332 if (!rdtscp_enabled
)
9333 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9337 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9338 SECONDARY_EXEC_RDTSCP
;
9340 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9341 ~SECONDARY_EXEC_RDTSCP
;
9345 /* Exposing INVPCID only when PCID is exposed */
9346 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9347 if (vmx_invpcid_supported() &&
9348 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9349 !guest_cpuid_has_pcid(vcpu
))) {
9350 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9353 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9356 if (cpu_has_secondary_exec_ctrls())
9357 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9359 if (nested_vmx_allowed(vcpu
))
9360 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9361 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9363 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9364 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9366 if (nested_vmx_allowed(vcpu
))
9367 nested_vmx_cr_fixed1_bits_update(vcpu
);
9370 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9372 if (func
== 1 && nested
)
9373 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9376 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9377 struct x86_exception
*fault
)
9379 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9380 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9382 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9384 if (vmx
->nested
.pml_full
) {
9385 exit_reason
= EXIT_REASON_PML_FULL
;
9386 vmx
->nested
.pml_full
= false;
9387 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9388 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9389 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9391 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9393 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9394 vmcs12
->guest_physical_address
= fault
->address
;
9397 /* Callbacks for nested_ept_init_mmu_context: */
9399 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9401 /* return the page table to be shadowed - in our case, EPT12 */
9402 return get_vmcs12(vcpu
)->ept_pointer
;
9405 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9409 WARN_ON(mmu_is_nested(vcpu
));
9410 eptp
= nested_ept_get_cr3(vcpu
);
9411 if ((eptp
& VMX_EPT_AD_ENABLE_BIT
) && !enable_ept_ad_bits
)
9414 kvm_mmu_unload(vcpu
);
9415 kvm_init_shadow_ept_mmu(vcpu
,
9416 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9417 VMX_EPT_EXECUTE_ONLY_BIT
,
9418 eptp
& VMX_EPT_AD_ENABLE_BIT
);
9419 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9420 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9421 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9423 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9427 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9429 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9432 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9435 bool inequality
, bit
;
9437 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9439 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9440 vmcs12
->page_fault_error_code_match
;
9441 return inequality
^ bit
;
9444 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9445 struct x86_exception
*fault
)
9447 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9449 WARN_ON(!is_guest_mode(vcpu
));
9451 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9452 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9453 vmcs_read32(VM_EXIT_INTR_INFO
),
9454 vmcs_readl(EXIT_QUALIFICATION
));
9456 kvm_inject_page_fault(vcpu
, fault
);
9459 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9460 struct vmcs12
*vmcs12
);
9462 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9463 struct vmcs12
*vmcs12
)
9465 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9468 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9470 * Translate L1 physical address to host physical
9471 * address for vmcs02. Keep the page pinned, so this
9472 * physical address remains valid. We keep a reference
9473 * to it so we can release it later.
9475 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9476 nested_release_page(vmx
->nested
.apic_access_page
);
9477 vmx
->nested
.apic_access_page
=
9478 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9480 * If translation failed, no matter: This feature asks
9481 * to exit when accessing the given address, and if it
9482 * can never be accessed, this feature won't do
9485 if (vmx
->nested
.apic_access_page
) {
9486 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9487 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9489 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9490 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9492 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9493 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9494 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9495 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9496 kvm_vcpu_reload_apic_access_page(vcpu
);
9499 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9500 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9501 nested_release_page(vmx
->nested
.virtual_apic_page
);
9502 vmx
->nested
.virtual_apic_page
=
9503 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9506 * If translation failed, VM entry will fail because
9507 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9508 * Failing the vm entry is _not_ what the processor
9509 * does but it's basically the only possibility we
9510 * have. We could still enter the guest if CR8 load
9511 * exits are enabled, CR8 store exits are enabled, and
9512 * virtualize APIC access is disabled; in this case
9513 * the processor would never use the TPR shadow and we
9514 * could simply clear the bit from the execution
9515 * control. But such a configuration is useless, so
9516 * let's keep the code simple.
9518 if (vmx
->nested
.virtual_apic_page
) {
9519 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9520 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9524 if (nested_cpu_has_posted_intr(vmcs12
)) {
9525 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9526 kunmap(vmx
->nested
.pi_desc_page
);
9527 nested_release_page(vmx
->nested
.pi_desc_page
);
9529 vmx
->nested
.pi_desc_page
=
9530 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9531 vmx
->nested
.pi_desc
=
9532 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9533 if (!vmx
->nested
.pi_desc
) {
9534 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9537 vmx
->nested
.pi_desc
=
9538 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9539 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9541 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9542 page_to_phys(vmx
->nested
.pi_desc_page
) +
9543 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9546 if (cpu_has_vmx_msr_bitmap() &&
9547 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9548 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9551 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9552 CPU_BASED_USE_MSR_BITMAPS
);
9555 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9557 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9558 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9560 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9563 /* Make sure short timeouts reliably trigger an immediate vmexit.
9564 * hrtimer_start does not guarantee this. */
9565 if (preemption_timeout
<= 1) {
9566 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9570 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9571 preemption_timeout
*= 1000000;
9572 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9573 hrtimer_start(&vmx
->nested
.preemption_timer
,
9574 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9577 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9578 struct vmcs12
*vmcs12
)
9583 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9586 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9590 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9592 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9593 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9600 * Merge L0's and L1's MSR bitmap, return false to indicate that
9601 * we do not use the hardware.
9603 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9604 struct vmcs12
*vmcs12
)
9608 unsigned long *msr_bitmap_l1
;
9609 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
9611 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9612 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9615 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9618 msr_bitmap_l1
= (unsigned long *)kmap(page
);
9620 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
9622 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9623 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9624 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9625 nested_vmx_disable_intercept_for_msr(
9626 msr_bitmap_l1
, msr_bitmap_l0
,
9629 nested_vmx_disable_intercept_for_msr(
9630 msr_bitmap_l1
, msr_bitmap_l0
,
9631 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9632 MSR_TYPE_R
| MSR_TYPE_W
);
9634 if (nested_cpu_has_vid(vmcs12
)) {
9635 nested_vmx_disable_intercept_for_msr(
9636 msr_bitmap_l1
, msr_bitmap_l0
,
9637 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9639 nested_vmx_disable_intercept_for_msr(
9640 msr_bitmap_l1
, msr_bitmap_l0
,
9641 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9646 nested_release_page_clean(page
);
9651 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9652 struct vmcs12
*vmcs12
)
9654 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9655 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9656 !nested_cpu_has_vid(vmcs12
) &&
9657 !nested_cpu_has_posted_intr(vmcs12
))
9661 * If virtualize x2apic mode is enabled,
9662 * virtualize apic access must be disabled.
9664 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9665 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9669 * If virtual interrupt delivery is enabled,
9670 * we must exit on external interrupts.
9672 if (nested_cpu_has_vid(vmcs12
) &&
9673 !nested_exit_on_intr(vcpu
))
9677 * bits 15:8 should be zero in posted_intr_nv,
9678 * the descriptor address has been already checked
9679 * in nested_get_vmcs12_pages.
9681 if (nested_cpu_has_posted_intr(vmcs12
) &&
9682 (!nested_cpu_has_vid(vmcs12
) ||
9683 !nested_exit_intr_ack_set(vcpu
) ||
9684 vmcs12
->posted_intr_nv
& 0xff00))
9687 /* tpr shadow is needed by all apicv features. */
9688 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9694 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9695 unsigned long count_field
,
9696 unsigned long addr_field
)
9701 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9702 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9708 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9709 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9710 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9711 pr_debug_ratelimited(
9712 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9713 addr_field
, maxphyaddr
, count
, addr
);
9719 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9720 struct vmcs12
*vmcs12
)
9722 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9723 vmcs12
->vm_exit_msr_store_count
== 0 &&
9724 vmcs12
->vm_entry_msr_load_count
== 0)
9725 return 0; /* Fast path */
9726 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9727 VM_EXIT_MSR_LOAD_ADDR
) ||
9728 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9729 VM_EXIT_MSR_STORE_ADDR
) ||
9730 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9731 VM_ENTRY_MSR_LOAD_ADDR
))
9736 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
9737 struct vmcs12
*vmcs12
)
9739 u64 address
= vmcs12
->pml_address
;
9740 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9742 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
9743 if (!nested_cpu_has_ept(vmcs12
) ||
9744 !IS_ALIGNED(address
, 4096) ||
9745 address
>> maxphyaddr
)
9752 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9753 struct vmx_msr_entry
*e
)
9755 /* x2APIC MSR accesses are not allowed */
9756 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9758 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9759 e
->index
== MSR_IA32_UCODE_REV
)
9761 if (e
->reserved
!= 0)
9766 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9767 struct vmx_msr_entry
*e
)
9769 if (e
->index
== MSR_FS_BASE
||
9770 e
->index
== MSR_GS_BASE
||
9771 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9772 nested_vmx_msr_check_common(vcpu
, e
))
9777 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9778 struct vmx_msr_entry
*e
)
9780 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9781 nested_vmx_msr_check_common(vcpu
, e
))
9787 * Load guest's/host's msr at nested entry/exit.
9788 * return 0 for success, entry index for failure.
9790 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9793 struct vmx_msr_entry e
;
9794 struct msr_data msr
;
9796 msr
.host_initiated
= false;
9797 for (i
= 0; i
< count
; i
++) {
9798 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9800 pr_debug_ratelimited(
9801 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9802 __func__
, i
, gpa
+ i
* sizeof(e
));
9805 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9806 pr_debug_ratelimited(
9807 "%s check failed (%u, 0x%x, 0x%x)\n",
9808 __func__
, i
, e
.index
, e
.reserved
);
9811 msr
.index
= e
.index
;
9813 if (kvm_set_msr(vcpu
, &msr
)) {
9814 pr_debug_ratelimited(
9815 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9816 __func__
, i
, e
.index
, e
.value
);
9825 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9828 struct vmx_msr_entry e
;
9830 for (i
= 0; i
< count
; i
++) {
9831 struct msr_data msr_info
;
9832 if (kvm_vcpu_read_guest(vcpu
,
9833 gpa
+ i
* sizeof(e
),
9834 &e
, 2 * sizeof(u32
))) {
9835 pr_debug_ratelimited(
9836 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9837 __func__
, i
, gpa
+ i
* sizeof(e
));
9840 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9841 pr_debug_ratelimited(
9842 "%s check failed (%u, 0x%x, 0x%x)\n",
9843 __func__
, i
, e
.index
, e
.reserved
);
9846 msr_info
.host_initiated
= false;
9847 msr_info
.index
= e
.index
;
9848 if (kvm_get_msr(vcpu
, &msr_info
)) {
9849 pr_debug_ratelimited(
9850 "%s cannot read MSR (%u, 0x%x)\n",
9851 __func__
, i
, e
.index
);
9854 if (kvm_vcpu_write_guest(vcpu
,
9855 gpa
+ i
* sizeof(e
) +
9856 offsetof(struct vmx_msr_entry
, value
),
9857 &msr_info
.data
, sizeof(msr_info
.data
))) {
9858 pr_debug_ratelimited(
9859 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9860 __func__
, i
, e
.index
, msr_info
.data
);
9867 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
9869 unsigned long invalid_mask
;
9871 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
9872 return (val
& invalid_mask
) == 0;
9876 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9877 * emulating VM entry into a guest with EPT enabled.
9878 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9879 * is assigned to entry_failure_code on failure.
9881 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
9882 u32
*entry_failure_code
)
9884 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
9885 if (!nested_cr3_valid(vcpu
, cr3
)) {
9886 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
9891 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9892 * must not be dereferenced.
9894 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
9896 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
9897 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
9902 vcpu
->arch
.cr3
= cr3
;
9903 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
9906 kvm_mmu_reset_context(vcpu
);
9911 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9912 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9913 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9914 * guest in a way that will both be appropriate to L1's requests, and our
9915 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9916 * function also has additional necessary side-effects, like setting various
9917 * vcpu->arch fields.
9918 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9919 * is assigned to entry_failure_code on failure.
9921 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
9922 bool from_vmentry
, u32
*entry_failure_code
)
9924 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9925 u32 exec_control
, vmcs12_exec_ctrl
;
9927 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9928 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9929 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9930 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9931 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9932 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9933 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9934 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9935 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9936 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9937 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9938 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9939 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9940 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9941 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9942 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9943 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9944 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9945 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9946 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9947 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9948 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9949 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9950 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9951 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9952 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9953 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9954 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9955 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9956 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9957 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9958 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9959 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9960 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9961 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9962 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9965 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
9966 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9967 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9969 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9970 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9973 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9974 vmcs12
->vm_entry_intr_info_field
);
9975 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9976 vmcs12
->vm_entry_exception_error_code
);
9977 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9978 vmcs12
->vm_entry_instruction_len
);
9979 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9980 vmcs12
->guest_interruptibility_info
);
9982 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9984 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9985 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9986 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9987 vmcs12
->guest_pending_dbg_exceptions
);
9988 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9989 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9991 if (nested_cpu_has_xsaves(vmcs12
))
9992 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9993 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9995 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9997 /* Preemption timer setting is only taken from vmcs01. */
9998 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9999 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10000 if (vmx
->hv_deadline_tsc
== -1)
10001 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10003 /* Posted interrupts setting is only taken from vmcs12. */
10004 if (nested_cpu_has_posted_intr(vmcs12
)) {
10006 * Note that we use L0's vector here and in
10007 * vmx_deliver_nested_posted_interrupt.
10009 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10010 vmx
->nested
.pi_pending
= false;
10011 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
10013 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10016 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10018 vmx
->nested
.preemption_timer_expired
= false;
10019 if (nested_cpu_has_preemption_timer(vmcs12
))
10020 vmx_start_preemption_timer(vcpu
);
10023 * Whether page-faults are trapped is determined by a combination of
10024 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10025 * If enable_ept, L0 doesn't care about page faults and we should
10026 * set all of these to L1's desires. However, if !enable_ept, L0 does
10027 * care about (at least some) page faults, and because it is not easy
10028 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10029 * to exit on each and every L2 page fault. This is done by setting
10030 * MASK=MATCH=0 and (see below) EB.PF=1.
10031 * Note that below we don't need special code to set EB.PF beyond the
10032 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10033 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10034 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10036 * A problem with this approach (when !enable_ept) is that L1 may be
10037 * injected with more page faults than it asked for. This could have
10038 * caused problems, but in practice existing hypervisors don't care.
10039 * To fix this, we will need to emulate the PFEC checking (on the L1
10040 * page tables), using walk_addr(), when injecting PFs to L1.
10042 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10043 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10044 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10045 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10047 if (cpu_has_secondary_exec_ctrls()) {
10048 exec_control
= vmx_secondary_exec_control(vmx
);
10050 /* Take the following fields only from vmcs12 */
10051 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10052 SECONDARY_EXEC_RDTSCP
|
10053 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10054 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
10055 if (nested_cpu_has(vmcs12
,
10056 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10057 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10058 ~SECONDARY_EXEC_ENABLE_PML
;
10059 exec_control
|= vmcs12_exec_ctrl
;
10062 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10063 vmcs_write64(EOI_EXIT_BITMAP0
,
10064 vmcs12
->eoi_exit_bitmap0
);
10065 vmcs_write64(EOI_EXIT_BITMAP1
,
10066 vmcs12
->eoi_exit_bitmap1
);
10067 vmcs_write64(EOI_EXIT_BITMAP2
,
10068 vmcs12
->eoi_exit_bitmap2
);
10069 vmcs_write64(EOI_EXIT_BITMAP3
,
10070 vmcs12
->eoi_exit_bitmap3
);
10071 vmcs_write16(GUEST_INTR_STATUS
,
10072 vmcs12
->guest_intr_status
);
10076 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10077 * nested_get_vmcs12_pages will either fix it up or
10078 * remove the VM execution control.
10080 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10081 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10083 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10088 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10089 * Some constant fields are set here by vmx_set_constant_host_state().
10090 * Other fields are different per CPU, and will be set later when
10091 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10093 vmx_set_constant_host_state(vmx
);
10096 * Set the MSR load/store lists to match L0's settings.
10098 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10099 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10100 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10101 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10102 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10105 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10106 * entry, but only if the current (host) sp changed from the value
10107 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10108 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10109 * here we just force the write to happen on entry.
10113 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10114 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10115 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10116 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10117 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10120 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10121 * nested_get_vmcs12_pages can't fix it up, the illegal value
10122 * will result in a VM entry failure.
10124 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10125 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10126 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10130 * Merging of IO bitmap not currently supported.
10131 * Rather, exit every time.
10133 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10134 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10136 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10138 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10139 * bitwise-or of what L1 wants to trap for L2, and what we want to
10140 * trap. Note that CR0.TS also needs updating - we do this later.
10142 update_exception_bitmap(vcpu
);
10143 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10144 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10146 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10147 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10148 * bits are further modified by vmx_set_efer() below.
10150 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10152 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10153 * emulated by vmx_set_efer(), below.
10155 vm_entry_controls_init(vmx
,
10156 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10157 ~VM_ENTRY_IA32E_MODE
) |
10158 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10160 if (from_vmentry
&&
10161 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10162 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10163 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10164 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10165 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10168 set_cr4_guest_host_mask(vmx
);
10170 if (from_vmentry
&&
10171 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10172 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10174 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10175 vmcs_write64(TSC_OFFSET
,
10176 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10178 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10179 if (kvm_has_tsc_control
)
10180 decache_tsc_multiplier(vmx
);
10184 * There is no direct mapping between vpid02 and vpid12, the
10185 * vpid02 is per-vCPU for L0 and reused while the value of
10186 * vpid12 is changed w/ one invvpid during nested vmentry.
10187 * The vpid12 is allocated by L1 for L2, so it will not
10188 * influence global bitmap(for vpid01 and vpid02 allocation)
10189 * even if spawn a lot of nested vCPUs.
10191 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10192 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10193 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10194 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10195 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10198 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10199 vmx_flush_tlb(vcpu
);
10206 * Conceptually we want to copy the PML address and index from
10207 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10208 * since we always flush the log on each vmexit, this happens
10209 * to be equivalent to simply resetting the fields in vmcs02.
10211 ASSERT(vmx
->pml_pg
);
10212 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10213 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10216 if (nested_cpu_has_ept(vmcs12
)) {
10217 if (nested_ept_init_mmu_context(vcpu
)) {
10218 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10221 } else if (nested_cpu_has2(vmcs12
,
10222 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10223 vmx_flush_tlb_ept_only(vcpu
);
10227 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10228 * bits which we consider mandatory enabled.
10229 * The CR0_READ_SHADOW is what L2 should have expected to read given
10230 * the specifications by L1; It's not enough to take
10231 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10232 * have more bits than L1 expected.
10234 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10235 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10237 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10238 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10240 if (from_vmentry
&&
10241 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10242 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10243 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10244 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10246 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10247 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10248 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10250 /* Shadow page tables on either EPT or shadow page tables. */
10251 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10252 entry_failure_code
))
10256 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10259 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10262 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10263 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10264 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10265 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10268 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10269 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10273 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10275 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10277 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10278 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10279 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10281 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10282 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10284 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10285 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10287 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10288 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10290 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10291 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10293 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10294 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10295 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10296 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10297 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10298 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10299 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10300 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10301 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10302 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10303 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10304 vmx
->nested
.nested_vmx_exit_ctls_low
,
10305 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10306 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10307 vmx
->nested
.nested_vmx_entry_ctls_low
,
10308 vmx
->nested
.nested_vmx_entry_ctls_high
))
10309 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10311 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10312 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10314 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10315 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10316 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10317 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10322 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10327 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10329 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10330 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10333 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10334 vmcs12
->vmcs_link_pointer
!= -1ull) {
10335 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10340 * If the load IA32_EFER VM-entry control is 1, the following checks
10341 * are performed on the field for the IA32_EFER MSR:
10342 * - Bits reserved in the IA32_EFER MSR must be 0.
10343 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10344 * the IA-32e mode guest VM-exit control. It must also be identical
10345 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10348 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10349 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10350 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10351 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10352 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10353 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10354 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10359 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10360 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10361 * the values of the LMA and LME bits in the field must each be that of
10362 * the host address-space size VM-exit control.
10364 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10365 ia32e
= (vmcs12
->vm_exit_controls
&
10366 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10367 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10368 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10369 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10376 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10378 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10379 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10380 struct loaded_vmcs
*vmcs02
;
10384 vmcs02
= nested_get_current_vmcs02(vmx
);
10388 enter_guest_mode(vcpu
);
10390 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10391 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10393 vmx_switch_vmcs(vcpu
, vmcs02
);
10394 vmx_segment_cache_clear(vmx
);
10396 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10397 leave_guest_mode(vcpu
);
10398 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10399 nested_vmx_entry_failure(vcpu
, vmcs12
,
10400 EXIT_REASON_INVALID_STATE
, exit_qual
);
10404 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10406 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10407 vmcs12
->vm_entry_msr_load_addr
,
10408 vmcs12
->vm_entry_msr_load_count
);
10409 if (msr_entry_idx
) {
10410 leave_guest_mode(vcpu
);
10411 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10412 nested_vmx_entry_failure(vcpu
, vmcs12
,
10413 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10417 vmcs12
->launch_state
= 1;
10420 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10421 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10422 * returned as far as L1 is concerned. It will only return (and set
10423 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10429 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10430 * for running an L2 nested guest.
10432 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10434 struct vmcs12
*vmcs12
;
10435 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10439 if (!nested_vmx_check_permission(vcpu
))
10442 if (!nested_vmx_check_vmcs12(vcpu
))
10445 vmcs12
= get_vmcs12(vcpu
);
10447 if (enable_shadow_vmcs
)
10448 copy_shadow_to_vmcs12(vmx
);
10451 * The nested entry process starts with enforcing various prerequisites
10452 * on vmcs12 as required by the Intel SDM, and act appropriately when
10453 * they fail: As the SDM explains, some conditions should cause the
10454 * instruction to fail, while others will cause the instruction to seem
10455 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10456 * To speed up the normal (success) code path, we should avoid checking
10457 * for misconfigurations which will anyway be caught by the processor
10458 * when using the merged vmcs02.
10460 if (vmcs12
->launch_state
== launch
) {
10461 nested_vmx_failValid(vcpu
,
10462 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10463 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10467 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10469 nested_vmx_failValid(vcpu
, ret
);
10474 * After this point, the trap flag no longer triggers a singlestep trap
10475 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10476 * This is not 100% correct; for performance reasons, we delegate most
10477 * of the checks on host state to the processor. If those fail,
10478 * the singlestep trap is missed.
10480 skip_emulated_instruction(vcpu
);
10482 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10484 nested_vmx_entry_failure(vcpu
, vmcs12
,
10485 EXIT_REASON_INVALID_STATE
, exit_qual
);
10490 * We're finally done with prerequisite checking, and can start with
10491 * the nested entry.
10494 ret
= enter_vmx_non_root_mode(vcpu
, true);
10498 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10499 return kvm_vcpu_halt(vcpu
);
10501 vmx
->nested
.nested_run_pending
= 1;
10506 return kvm_skip_emulated_instruction(vcpu
);
10510 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10511 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10512 * This function returns the new value we should put in vmcs12.guest_cr0.
10513 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10514 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10515 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10516 * didn't trap the bit, because if L1 did, so would L0).
10517 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10518 * been modified by L2, and L1 knows it. So just leave the old value of
10519 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10520 * isn't relevant, because if L0 traps this bit it can set it to anything.
10521 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10522 * changed these bits, and therefore they need to be updated, but L0
10523 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10524 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10526 static inline unsigned long
10527 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10530 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10531 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10532 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10533 vcpu
->arch
.cr0_guest_owned_bits
));
10536 static inline unsigned long
10537 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10540 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10541 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10542 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10543 vcpu
->arch
.cr4_guest_owned_bits
));
10546 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10547 struct vmcs12
*vmcs12
)
10552 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10553 nr
= vcpu
->arch
.exception
.nr
;
10554 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10556 if (kvm_exception_is_soft(nr
)) {
10557 vmcs12
->vm_exit_instruction_len
=
10558 vcpu
->arch
.event_exit_inst_len
;
10559 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10561 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10563 if (vcpu
->arch
.exception
.has_error_code
) {
10564 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10565 vmcs12
->idt_vectoring_error_code
=
10566 vcpu
->arch
.exception
.error_code
;
10569 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10570 } else if (vcpu
->arch
.nmi_injected
) {
10571 vmcs12
->idt_vectoring_info_field
=
10572 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10573 } else if (vcpu
->arch
.interrupt
.pending
) {
10574 nr
= vcpu
->arch
.interrupt
.nr
;
10575 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10577 if (vcpu
->arch
.interrupt
.soft
) {
10578 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10579 vmcs12
->vm_entry_instruction_len
=
10580 vcpu
->arch
.event_exit_inst_len
;
10582 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10584 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10588 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10590 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10592 if (vcpu
->arch
.exception
.pending
||
10593 vcpu
->arch
.nmi_injected
||
10594 vcpu
->arch
.interrupt
.pending
)
10597 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10598 vmx
->nested
.preemption_timer_expired
) {
10599 if (vmx
->nested
.nested_run_pending
)
10601 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10605 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10606 if (vmx
->nested
.nested_run_pending
)
10608 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10609 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10610 INTR_INFO_VALID_MASK
, 0);
10612 * The NMI-triggered VM exit counts as injection:
10613 * clear this one and block further NMIs.
10615 vcpu
->arch
.nmi_pending
= 0;
10616 vmx_set_nmi_mask(vcpu
, true);
10620 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10621 nested_exit_on_intr(vcpu
)) {
10622 if (vmx
->nested
.nested_run_pending
)
10624 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10628 vmx_complete_nested_posted_interrupt(vcpu
);
10632 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10634 ktime_t remaining
=
10635 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10638 if (ktime_to_ns(remaining
) <= 0)
10641 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10642 do_div(value
, 1000000);
10643 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10647 * Update the guest state fields of vmcs12 to reflect changes that
10648 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10649 * VM-entry controls is also updated, since this is really a guest
10652 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10654 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10655 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10657 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10658 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10659 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10661 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10662 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10663 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10664 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10665 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10666 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10667 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10668 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10669 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10670 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10671 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10672 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10673 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10674 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10675 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10676 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10677 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10678 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10679 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10680 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10681 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10682 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10683 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10684 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10685 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10686 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10687 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10688 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10689 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10690 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10691 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10692 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10693 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10694 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10695 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10696 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10698 vmcs12
->guest_interruptibility_info
=
10699 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10700 vmcs12
->guest_pending_dbg_exceptions
=
10701 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10702 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10703 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10705 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10707 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10708 if (vmcs12
->vm_exit_controls
&
10709 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10710 vmcs12
->vmx_preemption_timer_value
=
10711 vmx_get_preemption_timer_value(vcpu
);
10712 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10716 * In some cases (usually, nested EPT), L2 is allowed to change its
10717 * own CR3 without exiting. If it has changed it, we must keep it.
10718 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10719 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10721 * Additionally, restore L2's PDPTR to vmcs12.
10724 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10725 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10726 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10727 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10728 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10731 if (nested_cpu_has_ept(vmcs12
))
10732 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
10734 if (nested_cpu_has_vid(vmcs12
))
10735 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10737 vmcs12
->vm_entry_controls
=
10738 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10739 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10741 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10742 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10743 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10746 /* TODO: These cannot have changed unless we have MSR bitmaps and
10747 * the relevant bit asks not to trap the change */
10748 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10749 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10750 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10751 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10752 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10753 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10754 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10755 if (kvm_mpx_supported())
10756 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10757 if (nested_cpu_has_xsaves(vmcs12
))
10758 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10762 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10763 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10764 * and this function updates it to reflect the changes to the guest state while
10765 * L2 was running (and perhaps made some exits which were handled directly by L0
10766 * without going back to L1), and to reflect the exit reason.
10767 * Note that we do not have to copy here all VMCS fields, just those that
10768 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10769 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10770 * which already writes to vmcs12 directly.
10772 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10773 u32 exit_reason
, u32 exit_intr_info
,
10774 unsigned long exit_qualification
)
10776 /* update guest state fields: */
10777 sync_vmcs12(vcpu
, vmcs12
);
10779 /* update exit information fields: */
10781 vmcs12
->vm_exit_reason
= exit_reason
;
10782 vmcs12
->exit_qualification
= exit_qualification
;
10784 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10785 if ((vmcs12
->vm_exit_intr_info
&
10786 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10787 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10788 vmcs12
->vm_exit_intr_error_code
=
10789 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10790 vmcs12
->idt_vectoring_info_field
= 0;
10791 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10792 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10794 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10795 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10796 * instead of reading the real value. */
10797 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10800 * Transfer the event that L0 or L1 may wanted to inject into
10801 * L2 to IDT_VECTORING_INFO_FIELD.
10803 vmcs12_save_pending_event(vcpu
, vmcs12
);
10807 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10808 * preserved above and would only end up incorrectly in L1.
10810 vcpu
->arch
.nmi_injected
= false;
10811 kvm_clear_exception_queue(vcpu
);
10812 kvm_clear_interrupt_queue(vcpu
);
10816 * A part of what we need to when the nested L2 guest exits and we want to
10817 * run its L1 parent, is to reset L1's guest state to the host state specified
10819 * This function is to be called not only on normal nested exit, but also on
10820 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10821 * Failures During or After Loading Guest State").
10822 * This function should be called when the active VMCS is L1's (vmcs01).
10824 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10825 struct vmcs12
*vmcs12
)
10827 struct kvm_segment seg
;
10828 u32 entry_failure_code
;
10830 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10831 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10832 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10833 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10835 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10836 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10838 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10839 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10840 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10842 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10843 * actually changed, because vmx_set_cr0 refers to efer set above.
10845 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10846 * (KVM doesn't change it);
10848 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
10849 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10851 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
10852 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10853 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10855 nested_ept_uninit_mmu_context(vcpu
);
10858 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10859 * couldn't have changed.
10861 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
10862 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
10865 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10869 * Trivially support vpid by letting L2s share their parent
10870 * L1's vpid. TODO: move to a more elaborate solution, giving
10871 * each L2 its own vpid and exposing the vpid feature to L1.
10873 vmx_flush_tlb(vcpu
);
10877 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10878 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10879 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10880 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10881 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10883 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10884 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10885 vmcs_write64(GUEST_BNDCFGS
, 0);
10887 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10888 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10889 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10891 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10892 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10893 vmcs12
->host_ia32_perf_global_ctrl
);
10895 /* Set L1 segment info according to Intel SDM
10896 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10897 seg
= (struct kvm_segment
) {
10899 .limit
= 0xFFFFFFFF,
10900 .selector
= vmcs12
->host_cs_selector
,
10906 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10910 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10911 seg
= (struct kvm_segment
) {
10913 .limit
= 0xFFFFFFFF,
10920 seg
.selector
= vmcs12
->host_ds_selector
;
10921 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10922 seg
.selector
= vmcs12
->host_es_selector
;
10923 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10924 seg
.selector
= vmcs12
->host_ss_selector
;
10925 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10926 seg
.selector
= vmcs12
->host_fs_selector
;
10927 seg
.base
= vmcs12
->host_fs_base
;
10928 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10929 seg
.selector
= vmcs12
->host_gs_selector
;
10930 seg
.base
= vmcs12
->host_gs_base
;
10931 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10932 seg
= (struct kvm_segment
) {
10933 .base
= vmcs12
->host_tr_base
,
10935 .selector
= vmcs12
->host_tr_selector
,
10939 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10941 kvm_set_dr(vcpu
, 7, 0x400);
10942 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10944 if (cpu_has_vmx_msr_bitmap())
10945 vmx_set_msr_bitmap(vcpu
);
10947 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10948 vmcs12
->vm_exit_msr_load_count
))
10949 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10953 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10954 * and modify vmcs12 to make it see what it would expect to see there if
10955 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10957 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10958 u32 exit_intr_info
,
10959 unsigned long exit_qualification
)
10961 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10962 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10963 u32 vm_inst_error
= 0;
10965 /* trying to cancel vmlaunch/vmresume is a bug */
10966 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10968 leave_guest_mode(vcpu
);
10969 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10970 exit_qualification
);
10972 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10973 vmcs12
->vm_exit_msr_store_count
))
10974 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10976 if (unlikely(vmx
->fail
))
10977 vm_inst_error
= vmcs_read32(VM_INSTRUCTION_ERROR
);
10979 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10981 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10982 && nested_exit_intr_ack_set(vcpu
)) {
10983 int irq
= kvm_cpu_get_interrupt(vcpu
);
10985 vmcs12
->vm_exit_intr_info
= irq
|
10986 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10989 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10990 vmcs12
->exit_qualification
,
10991 vmcs12
->idt_vectoring_info_field
,
10992 vmcs12
->vm_exit_intr_info
,
10993 vmcs12
->vm_exit_intr_error_code
,
10996 vm_entry_controls_reset_shadow(vmx
);
10997 vm_exit_controls_reset_shadow(vmx
);
10998 vmx_segment_cache_clear(vmx
);
11000 /* if no vmcs02 cache requested, remove the one we used */
11001 if (VMCS02_POOL_SIZE
== 0)
11002 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11004 load_vmcs12_host_state(vcpu
, vmcs12
);
11006 /* Update any VMCS fields that might have changed while L2 ran */
11007 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11008 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11009 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11010 if (vmx
->hv_deadline_tsc
== -1)
11011 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11012 PIN_BASED_VMX_PREEMPTION_TIMER
);
11014 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11015 PIN_BASED_VMX_PREEMPTION_TIMER
);
11016 if (kvm_has_tsc_control
)
11017 decache_tsc_multiplier(vmx
);
11019 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11020 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11021 vmx_set_virtual_x2apic_mode(vcpu
,
11022 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11023 } else if (!nested_cpu_has_ept(vmcs12
) &&
11024 nested_cpu_has2(vmcs12
,
11025 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11026 vmx_flush_tlb_ept_only(vcpu
);
11029 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11032 /* Unpin physical memory we referred to in vmcs02 */
11033 if (vmx
->nested
.apic_access_page
) {
11034 nested_release_page(vmx
->nested
.apic_access_page
);
11035 vmx
->nested
.apic_access_page
= NULL
;
11037 if (vmx
->nested
.virtual_apic_page
) {
11038 nested_release_page(vmx
->nested
.virtual_apic_page
);
11039 vmx
->nested
.virtual_apic_page
= NULL
;
11041 if (vmx
->nested
.pi_desc_page
) {
11042 kunmap(vmx
->nested
.pi_desc_page
);
11043 nested_release_page(vmx
->nested
.pi_desc_page
);
11044 vmx
->nested
.pi_desc_page
= NULL
;
11045 vmx
->nested
.pi_desc
= NULL
;
11049 * We are now running in L2, mmu_notifier will force to reload the
11050 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11052 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11055 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11056 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11057 * success or failure flag accordingly.
11059 if (unlikely(vmx
->fail
)) {
11061 nested_vmx_failValid(vcpu
, vm_inst_error
);
11063 nested_vmx_succeed(vcpu
);
11064 if (enable_shadow_vmcs
)
11065 vmx
->nested
.sync_shadow_vmcs
= true;
11067 /* in case we halted in L2 */
11068 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11072 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11074 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11076 if (is_guest_mode(vcpu
)) {
11077 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11078 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11080 free_nested(to_vmx(vcpu
));
11084 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11085 * 23.7 "VM-entry failures during or after loading guest state" (this also
11086 * lists the acceptable exit-reason and exit-qualification parameters).
11087 * It should only be called before L2 actually succeeded to run, and when
11088 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11090 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11091 struct vmcs12
*vmcs12
,
11092 u32 reason
, unsigned long qualification
)
11094 load_vmcs12_host_state(vcpu
, vmcs12
);
11095 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11096 vmcs12
->exit_qualification
= qualification
;
11097 nested_vmx_succeed(vcpu
);
11098 if (enable_shadow_vmcs
)
11099 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11102 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11103 struct x86_instruction_info
*info
,
11104 enum x86_intercept_stage stage
)
11106 return X86EMUL_CONTINUE
;
11109 #ifdef CONFIG_X86_64
11110 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11111 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11112 u64 divisor
, u64
*result
)
11114 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11116 /* To avoid the overflow on divq */
11117 if (high
>= divisor
)
11120 /* Low hold the result, high hold rem which is discarded */
11121 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11122 "rm" (divisor
), "0" (low
), "1" (high
));
11128 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11130 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11131 u64 tscl
= rdtsc();
11132 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11133 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11135 /* Convert to host delta tsc if tsc scaling is enabled */
11136 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11137 u64_shl_div_u64(delta_tsc
,
11138 kvm_tsc_scaling_ratio_frac_bits
,
11139 vcpu
->arch
.tsc_scaling_ratio
,
11144 * If the delta tsc can't fit in the 32 bit after the multi shift,
11145 * we can't use the preemption timer.
11146 * It's possible that it fits on later vmentries, but checking
11147 * on every vmentry is costly so we just use an hrtimer.
11149 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11152 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11153 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11154 PIN_BASED_VMX_PREEMPTION_TIMER
);
11158 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11160 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11161 vmx
->hv_deadline_tsc
= -1;
11162 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11163 PIN_BASED_VMX_PREEMPTION_TIMER
);
11167 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11170 shrink_ple_window(vcpu
);
11173 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11174 struct kvm_memory_slot
*slot
)
11176 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11177 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11180 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11181 struct kvm_memory_slot
*slot
)
11183 kvm_mmu_slot_set_dirty(kvm
, slot
);
11186 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11188 kvm_flush_pml_buffers(kvm
);
11191 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11193 struct vmcs12
*vmcs12
;
11194 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11196 struct page
*page
= NULL
;
11199 if (is_guest_mode(vcpu
)) {
11200 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11203 * Check if PML is enabled for the nested guest.
11204 * Whether eptp bit 6 is set is already checked
11205 * as part of A/D emulation.
11207 vmcs12
= get_vmcs12(vcpu
);
11208 if (!nested_cpu_has_pml(vmcs12
))
11211 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11212 vmx
->nested
.pml_full
= true;
11216 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11218 page
= nested_get_page(vcpu
, vmcs12
->pml_address
);
11222 pml_address
= kmap(page
);
11223 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11225 nested_release_page_clean(page
);
11231 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11232 struct kvm_memory_slot
*memslot
,
11233 gfn_t offset
, unsigned long mask
)
11235 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11239 * This routine does the following things for vCPU which is going
11240 * to be blocked if VT-d PI is enabled.
11241 * - Store the vCPU to the wakeup list, so when interrupts happen
11242 * we can find the right vCPU to wake up.
11243 * - Change the Posted-interrupt descriptor as below:
11244 * 'NDST' <-- vcpu->pre_pcpu
11245 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11246 * - If 'ON' is set during this process, which means at least one
11247 * interrupt is posted for this vCPU, we cannot block it, in
11248 * this case, return 1, otherwise, return 0.
11251 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11253 unsigned long flags
;
11255 struct pi_desc old
, new;
11256 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11258 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11259 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11260 !kvm_vcpu_apicv_active(vcpu
))
11263 vcpu
->pre_pcpu
= vcpu
->cpu
;
11264 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11265 vcpu
->pre_pcpu
), flags
);
11266 list_add_tail(&vcpu
->blocked_vcpu_list
,
11267 &per_cpu(blocked_vcpu_on_cpu
,
11269 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
11270 vcpu
->pre_pcpu
), flags
);
11273 old
.control
= new.control
= pi_desc
->control
;
11276 * We should not block the vCPU if
11277 * an interrupt is posted for it.
11279 if (pi_test_on(pi_desc
) == 1) {
11280 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11281 vcpu
->pre_pcpu
), flags
);
11282 list_del(&vcpu
->blocked_vcpu_list
);
11283 spin_unlock_irqrestore(
11284 &per_cpu(blocked_vcpu_on_cpu_lock
,
11285 vcpu
->pre_pcpu
), flags
);
11286 vcpu
->pre_pcpu
= -1;
11291 WARN((pi_desc
->sn
== 1),
11292 "Warning: SN field of posted-interrupts "
11293 "is set before blocking\n");
11296 * Since vCPU can be preempted during this process,
11297 * vcpu->cpu could be different with pre_pcpu, we
11298 * need to set pre_pcpu as the destination of wakeup
11299 * notification event, then we can find the right vCPU
11300 * to wakeup in wakeup handler if interrupts happen
11301 * when the vCPU is in blocked state.
11303 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11305 if (x2apic_enabled())
11308 new.ndst
= (dest
<< 8) & 0xFF00;
11310 /* set 'NV' to 'wakeup vector' */
11311 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11312 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11313 new.control
) != old
.control
);
11318 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11320 if (pi_pre_block(vcpu
))
11323 if (kvm_lapic_hv_timer_in_use(vcpu
))
11324 kvm_lapic_switch_to_sw_timer(vcpu
);
11329 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11331 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11332 struct pi_desc old
, new;
11334 unsigned long flags
;
11336 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11337 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11338 !kvm_vcpu_apicv_active(vcpu
))
11342 old
.control
= new.control
= pi_desc
->control
;
11344 dest
= cpu_physical_id(vcpu
->cpu
);
11346 if (x2apic_enabled())
11349 new.ndst
= (dest
<< 8) & 0xFF00;
11351 /* Allow posting non-urgent interrupts */
11354 /* set 'NV' to 'notification vector' */
11355 new.nv
= POSTED_INTR_VECTOR
;
11356 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11357 new.control
) != old
.control
);
11359 if(vcpu
->pre_pcpu
!= -1) {
11361 &per_cpu(blocked_vcpu_on_cpu_lock
,
11362 vcpu
->pre_pcpu
), flags
);
11363 list_del(&vcpu
->blocked_vcpu_list
);
11364 spin_unlock_irqrestore(
11365 &per_cpu(blocked_vcpu_on_cpu_lock
,
11366 vcpu
->pre_pcpu
), flags
);
11367 vcpu
->pre_pcpu
= -1;
11371 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11373 if (kvm_x86_ops
->set_hv_timer
)
11374 kvm_lapic_switch_to_hv_timer(vcpu
);
11376 pi_post_block(vcpu
);
11380 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11383 * @host_irq: host irq of the interrupt
11384 * @guest_irq: gsi of the interrupt
11385 * @set: set or unset PI
11386 * returns 0 on success, < 0 on failure
11388 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11389 uint32_t guest_irq
, bool set
)
11391 struct kvm_kernel_irq_routing_entry
*e
;
11392 struct kvm_irq_routing_table
*irq_rt
;
11393 struct kvm_lapic_irq irq
;
11394 struct kvm_vcpu
*vcpu
;
11395 struct vcpu_data vcpu_info
;
11396 int idx
, ret
= -EINVAL
;
11398 if (!kvm_arch_has_assigned_device(kvm
) ||
11399 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11400 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11403 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11404 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11405 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
11407 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11408 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11411 * VT-d PI cannot support posting multicast/broadcast
11412 * interrupts to a vCPU, we still use interrupt remapping
11413 * for these kind of interrupts.
11415 * For lowest-priority interrupts, we only support
11416 * those with single CPU as the destination, e.g. user
11417 * configures the interrupts via /proc/irq or uses
11418 * irqbalance to make the interrupts single-CPU.
11420 * We will support full lowest-priority interrupt later.
11423 kvm_set_msi_irq(kvm
, e
, &irq
);
11424 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11426 * Make sure the IRTE is in remapped mode if
11427 * we don't handle it in posted mode.
11429 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11432 "failed to back to remapped mode, irq: %u\n",
11440 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11441 vcpu_info
.vector
= irq
.vector
;
11443 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11444 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11447 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11449 /* suppress notification event before unposting */
11450 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11451 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11452 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11456 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11464 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11468 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11470 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11471 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11472 FEATURE_CONTROL_LMCE
;
11474 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11475 ~FEATURE_CONTROL_LMCE
;
11478 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11479 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11480 .disabled_by_bios
= vmx_disabled_by_bios
,
11481 .hardware_setup
= hardware_setup
,
11482 .hardware_unsetup
= hardware_unsetup
,
11483 .check_processor_compatibility
= vmx_check_processor_compat
,
11484 .hardware_enable
= hardware_enable
,
11485 .hardware_disable
= hardware_disable
,
11486 .cpu_has_accelerated_tpr
= report_flexpriority
,
11487 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11489 .vcpu_create
= vmx_create_vcpu
,
11490 .vcpu_free
= vmx_free_vcpu
,
11491 .vcpu_reset
= vmx_vcpu_reset
,
11493 .prepare_guest_switch
= vmx_save_host_state
,
11494 .vcpu_load
= vmx_vcpu_load
,
11495 .vcpu_put
= vmx_vcpu_put
,
11497 .update_bp_intercept
= update_exception_bitmap
,
11498 .get_msr
= vmx_get_msr
,
11499 .set_msr
= vmx_set_msr
,
11500 .get_segment_base
= vmx_get_segment_base
,
11501 .get_segment
= vmx_get_segment
,
11502 .set_segment
= vmx_set_segment
,
11503 .get_cpl
= vmx_get_cpl
,
11504 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11505 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11506 .decache_cr3
= vmx_decache_cr3
,
11507 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11508 .set_cr0
= vmx_set_cr0
,
11509 .set_cr3
= vmx_set_cr3
,
11510 .set_cr4
= vmx_set_cr4
,
11511 .set_efer
= vmx_set_efer
,
11512 .get_idt
= vmx_get_idt
,
11513 .set_idt
= vmx_set_idt
,
11514 .get_gdt
= vmx_get_gdt
,
11515 .set_gdt
= vmx_set_gdt
,
11516 .get_dr6
= vmx_get_dr6
,
11517 .set_dr6
= vmx_set_dr6
,
11518 .set_dr7
= vmx_set_dr7
,
11519 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11520 .cache_reg
= vmx_cache_reg
,
11521 .get_rflags
= vmx_get_rflags
,
11522 .set_rflags
= vmx_set_rflags
,
11524 .get_pkru
= vmx_get_pkru
,
11526 .tlb_flush
= vmx_flush_tlb
,
11528 .run
= vmx_vcpu_run
,
11529 .handle_exit
= vmx_handle_exit
,
11530 .skip_emulated_instruction
= skip_emulated_instruction
,
11531 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11532 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11533 .patch_hypercall
= vmx_patch_hypercall
,
11534 .set_irq
= vmx_inject_irq
,
11535 .set_nmi
= vmx_inject_nmi
,
11536 .queue_exception
= vmx_queue_exception
,
11537 .cancel_injection
= vmx_cancel_injection
,
11538 .interrupt_allowed
= vmx_interrupt_allowed
,
11539 .nmi_allowed
= vmx_nmi_allowed
,
11540 .get_nmi_mask
= vmx_get_nmi_mask
,
11541 .set_nmi_mask
= vmx_set_nmi_mask
,
11542 .enable_nmi_window
= enable_nmi_window
,
11543 .enable_irq_window
= enable_irq_window
,
11544 .update_cr8_intercept
= update_cr8_intercept
,
11545 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11546 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11547 .get_enable_apicv
= vmx_get_enable_apicv
,
11548 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11549 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11550 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
11551 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11552 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11553 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11554 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11556 .set_tss_addr
= vmx_set_tss_addr
,
11557 .get_tdp_level
= get_ept_level
,
11558 .get_mt_mask
= vmx_get_mt_mask
,
11560 .get_exit_info
= vmx_get_exit_info
,
11562 .get_lpage_level
= vmx_get_lpage_level
,
11564 .cpuid_update
= vmx_cpuid_update
,
11566 .rdtscp_supported
= vmx_rdtscp_supported
,
11567 .invpcid_supported
= vmx_invpcid_supported
,
11569 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11571 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11573 .write_tsc_offset
= vmx_write_tsc_offset
,
11575 .set_tdp_cr3
= vmx_set_cr3
,
11577 .check_intercept
= vmx_check_intercept
,
11578 .handle_external_intr
= vmx_handle_external_intr
,
11579 .mpx_supported
= vmx_mpx_supported
,
11580 .xsaves_supported
= vmx_xsaves_supported
,
11582 .check_nested_events
= vmx_check_nested_events
,
11584 .sched_in
= vmx_sched_in
,
11586 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11587 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11588 .flush_log_dirty
= vmx_flush_log_dirty
,
11589 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11590 .write_log_dirty
= vmx_write_pml_buffer
,
11592 .pre_block
= vmx_pre_block
,
11593 .post_block
= vmx_post_block
,
11595 .pmu_ops
= &intel_pmu_ops
,
11597 .update_pi_irte
= vmx_update_pi_irte
,
11599 #ifdef CONFIG_X86_64
11600 .set_hv_timer
= vmx_set_hv_timer
,
11601 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11604 .setup_mce
= vmx_setup_mce
,
11607 static int __init
vmx_init(void)
11609 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11610 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11614 #ifdef CONFIG_KEXEC_CORE
11615 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11616 crash_vmclear_local_loaded_vmcss
);
11622 static void __exit
vmx_exit(void)
11624 #ifdef CONFIG_KEXEC_CORE
11625 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11632 module_init(vmx_init
)
11633 module_exit(vmx_exit
)