ceph/src/seastar/dpdk/lib/librte_eal/common/include/arch/x86/rte_atomic.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2014 Intel Corporation
   3  */
   4
   5 #ifndef _RTE_ATOMIC_X86_H_
   6 #define _RTE_ATOMIC_X86_H_
   7
   8 #ifdef __cplusplus
   9 extern "C" {
  10 #endif
  11
  12 #include <stdint.h>
  13 #include <rte_common.h>
  14 #include <rte_config.h>
  15 #include <emmintrin.h>
  16 #include "generic/rte_atomic.h"
  17
  18 #if RTE_MAX_LCORE == 1
  19 #define MPLOCKED                        /**< No need to insert MP lock prefix. */
  20 #else
  21 #define MPLOCKED        "lock ; "       /**< Insert MP lock prefix. */
  22 #endif
  23
  24 #define rte_mb() _mm_mfence()
  25
  26 #define rte_wmb() _mm_sfence()
  27
  28 #define rte_rmb() _mm_lfence()
  29
  30 #define rte_smp_wmb() rte_compiler_barrier()
  31
  32 #define rte_smp_rmb() rte_compiler_barrier()
  33
  34 /*
  35  * From Intel Software Development Manual; Vol 3;
  36  * 8.2.2 Memory Ordering in P6 and More Recent Processor Families:
  37  * ...
  38  * . Reads are not reordered with other reads.
  39  * . Writes are not reordered with older reads.
  40  * . Writes to memory are not reordered with other writes,
  41  *   with the following exceptions:
  42  *   . streaming stores (writes) executed with the non-temporal move
  43  *     instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD); and
  44  *   . string operations (see Section 8.2.4.1).
  45  *  ...
  46  * . Reads may be reordered with older writes to different locations but not
  47  * with older writes to the same location.
  48  * . Reads or writes cannot be reordered with I/O instructions,
  49  * locked instructions, or serializing instructions.
  50  * . Reads cannot pass earlier LFENCE and MFENCE instructions.
  51  * . Writes ... cannot pass earlier LFENCE, SFENCE, and MFENCE instructions.
  52  * . LFENCE instructions cannot pass earlier reads.
  53  * . SFENCE instructions cannot pass earlier writes ...
  54  * . MFENCE instructions cannot pass earlier reads, writes ...
  55  *
  56  * As pointed by Java guys, that makes possible to use lock-prefixed
  57  * instructions to get the same effect as mfence and on most modern HW
  58  * that gives a better perfomance then using mfence:
  59  * https://shipilev.net/blog/2014/on-the-fence-with-dependencies/
  60  * Basic idea is to use lock prefixed add with some dummy memory location
  61  * as the destination. From their experiments 128B(2 cache lines) below
  62  * current stack pointer looks like a good candidate.
  63  * So below we use that techinque for rte_smp_mb() implementation.
  64  */
  65
  66 static __rte_always_inline void
  67 rte_smp_mb(void)
  68 {
  69 #ifdef RTE_ARCH_I686
  70         asm volatile("lock addl $0, -128(%%esp); " ::: "memory");
  71 #else
  72         asm volatile("lock addl $0, -128(%%rsp); " ::: "memory");
  73 #endif
  74 }
  75
  76 #define rte_io_mb() rte_mb()
  77
  78 #define rte_io_wmb() rte_compiler_barrier()
  79
  80 #define rte_io_rmb() rte_compiler_barrier()
  81
  82 #define rte_cio_wmb() rte_compiler_barrier()
  83
  84 #define rte_cio_rmb() rte_compiler_barrier()
  85
  86 /*------------------------- 16 bit atomic operations -------------------------*/
  87
  88 #ifndef RTE_FORCE_INTRINSICS
  89 static inline int
  90 rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
  91 {
  92         uint8_t res;
  93
  94         asm volatile(
  95                         MPLOCKED
  96                         "cmpxchgw %[src], %[dst];"
  97                         "sete %[res];"
  98                         : [res] "=a" (res),     /* output */
  99                           [dst] "=m" (*dst)
 100                         : [src] "r" (src),      /* input */
 101                           "a" (exp),
 102                           "m" (*dst)
 103                         : "memory");            /* no-clobber list */
 104         return res;
 105 }
 106
 107 static inline uint16_t
 108 rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
 109 {
 110         asm volatile(
 111                         MPLOCKED
 112                         "xchgw %0, %1;"
 113                         : "=r" (val), "=m" (*dst)
 114                         : "0" (val),  "m" (*dst)
 115                         : "memory");         /* no-clobber list */
 116         return val;
 117 }
 118
 119 static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
 120 {
 121         return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
 122 }
 123
 124 static inline void
 125 rte_atomic16_inc(rte_atomic16_t *v)
 126 {
 127         asm volatile(
 128                         MPLOCKED
 129                         "incw %[cnt]"
 130                         : [cnt] "=m" (v->cnt)   /* output */
 131                         : "m" (v->cnt)          /* input */
 132                         );
 133 }
 134
 135 static inline void
 136 rte_atomic16_dec(rte_atomic16_t *v)
 137 {
 138         asm volatile(
 139                         MPLOCKED
 140                         "decw %[cnt]"
 141                         : [cnt] "=m" (v->cnt)   /* output */
 142                         : "m" (v->cnt)          /* input */
 143                         );
 144 }
 145
 146 static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
 147 {
 148         uint8_t ret;
 149
 150         asm volatile(
 151                         MPLOCKED
 152                         "incw %[cnt] ; "
 153                         "sete %[ret]"
 154                         : [cnt] "+m" (v->cnt),  /* output */
 155                           [ret] "=qm" (ret)
 156                         );
 157         return ret != 0;
 158 }
 159
 160 static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
 161 {
 162         uint8_t ret;
 163
 164         asm volatile(MPLOCKED
 165                         "decw %[cnt] ; "
 166                         "sete %[ret]"
 167                         : [cnt] "+m" (v->cnt),  /* output */
 168                           [ret] "=qm" (ret)
 169                         );
 170         return ret != 0;
 171 }
 172
 173 /*------------------------- 32 bit atomic operations -------------------------*/
 174
 175 static inline int
 176 rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
 177 {
 178         uint8_t res;
 179
 180         asm volatile(
 181                         MPLOCKED
 182                         "cmpxchgl %[src], %[dst];"
 183                         "sete %[res];"
 184                         : [res] "=a" (res),     /* output */
 185                           [dst] "=m" (*dst)
 186                         : [src] "r" (src),      /* input */
 187                           "a" (exp),
 188                           "m" (*dst)
 189                         : "memory");            /* no-clobber list */
 190         return res;
 191 }
 192
 193 static inline uint32_t
 194 rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
 195 {
 196         asm volatile(
 197                         MPLOCKED
 198                         "xchgl %0, %1;"
 199                         : "=r" (val), "=m" (*dst)
 200                         : "0" (val),  "m" (*dst)
 201                         : "memory");         /* no-clobber list */
 202         return val;
 203 }
 204
 205 static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
 206 {
 207         return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
 208 }
 209
 210 static inline void
 211 rte_atomic32_inc(rte_atomic32_t *v)
 212 {
 213         asm volatile(
 214                         MPLOCKED
 215                         "incl %[cnt]"
 216                         : [cnt] "=m" (v->cnt)   /* output */
 217                         : "m" (v->cnt)          /* input */
 218                         );
 219 }
 220
 221 static inline void
 222 rte_atomic32_dec(rte_atomic32_t *v)
 223 {
 224         asm volatile(
 225                         MPLOCKED
 226                         "decl %[cnt]"
 227                         : [cnt] "=m" (v->cnt)   /* output */
 228                         : "m" (v->cnt)          /* input */
 229                         );
 230 }
 231
 232 static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
 233 {
 234         uint8_t ret;
 235
 236         asm volatile(
 237                         MPLOCKED
 238                         "incl %[cnt] ; "
 239                         "sete %[ret]"
 240                         : [cnt] "+m" (v->cnt),  /* output */
 241                           [ret] "=qm" (ret)
 242                         );
 243         return ret != 0;
 244 }
 245
 246 static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
 247 {
 248         uint8_t ret;
 249
 250         asm volatile(MPLOCKED
 251                         "decl %[cnt] ; "
 252                         "sete %[ret]"
 253                         : [cnt] "+m" (v->cnt),  /* output */
 254                           [ret] "=qm" (ret)
 255                         );
 256         return ret != 0;
 257 }
 258 #endif
 259
 260 #ifdef RTE_ARCH_I686
 261 #include "rte_atomic_32.h"
 262 #else
 263 #include "rte_atomic_64.h"
 264 #endif
 265
 266 #ifdef __cplusplus
 267 }
 268 #endif
 269
 270 #endif /* _RTE_ATOMIC_X86_H_ */