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[ceph.git] / ceph / src / spdk / dpdk / drivers / net / i40e / base / i40e_adminq_cmd.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
3 */
4
5 #ifndef _I40E_ADMINQ_CMD_H_
6 #define _I40E_ADMINQ_CMD_H_
7
8 /* This header file defines the i40e Admin Queue commands and is shared between
9 * i40e Firmware and Software.
10 *
11 * This file needs to comply with the Linux Kernel coding style.
12 */
13
14 #define I40E_FW_API_VERSION_MAJOR 0x0001
15 #define I40E_FW_API_VERSION_MINOR_X722 0x0006
16 #define I40E_FW_API_VERSION_MINOR_X710 0x0007
17
18 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
19 I40E_FW_API_VERSION_MINOR_X710 : \
20 I40E_FW_API_VERSION_MINOR_X722)
21
22 /* API version 1.7 implements additional link and PHY-specific APIs */
23 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
24 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
25 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
26
27 struct i40e_aq_desc {
28 __le16 flags;
29 __le16 opcode;
30 __le16 datalen;
31 __le16 retval;
32 __le32 cookie_high;
33 __le32 cookie_low;
34 union {
35 struct {
36 __le32 param0;
37 __le32 param1;
38 __le32 param2;
39 __le32 param3;
40 } internal;
41 struct {
42 __le32 param0;
43 __le32 param1;
44 __le32 addr_high;
45 __le32 addr_low;
46 } external;
47 u8 raw[16];
48 } params;
49 };
50
51 /* Flags sub-structure
52 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
53 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
54 */
55
56 /* command flags and offsets*/
57 #define I40E_AQ_FLAG_DD_SHIFT 0
58 #define I40E_AQ_FLAG_CMP_SHIFT 1
59 #define I40E_AQ_FLAG_ERR_SHIFT 2
60 #define I40E_AQ_FLAG_VFE_SHIFT 3
61 #define I40E_AQ_FLAG_LB_SHIFT 9
62 #define I40E_AQ_FLAG_RD_SHIFT 10
63 #define I40E_AQ_FLAG_VFC_SHIFT 11
64 #define I40E_AQ_FLAG_BUF_SHIFT 12
65 #define I40E_AQ_FLAG_SI_SHIFT 13
66 #define I40E_AQ_FLAG_EI_SHIFT 14
67 #define I40E_AQ_FLAG_FE_SHIFT 15
68
69 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
70 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
71 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
72 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
73 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
74 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
75 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
76 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
77 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
78 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
79 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
80
81 /* error codes */
82 enum i40e_admin_queue_err {
83 I40E_AQ_RC_OK = 0, /* success */
84 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
85 I40E_AQ_RC_ENOENT = 2, /* No such element */
86 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
87 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
88 I40E_AQ_RC_EIO = 5, /* I/O error */
89 I40E_AQ_RC_ENXIO = 6, /* No such resource */
90 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
91 I40E_AQ_RC_EAGAIN = 8, /* Try again */
92 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
93 I40E_AQ_RC_EACCES = 10, /* Permission denied */
94 I40E_AQ_RC_EFAULT = 11, /* Bad address */
95 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
96 I40E_AQ_RC_EEXIST = 13, /* object already exists */
97 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
98 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
99 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
100 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
101 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
102 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
103 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
104 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
105 I40E_AQ_RC_EFBIG = 22, /* File too large */
106 };
107
108 /* Admin Queue command opcodes */
109 enum i40e_admin_queue_opc {
110 /* aq commands */
111 i40e_aqc_opc_get_version = 0x0001,
112 i40e_aqc_opc_driver_version = 0x0002,
113 i40e_aqc_opc_queue_shutdown = 0x0003,
114 i40e_aqc_opc_set_pf_context = 0x0004,
115
116 /* resource ownership */
117 i40e_aqc_opc_request_resource = 0x0008,
118 i40e_aqc_opc_release_resource = 0x0009,
119
120 i40e_aqc_opc_list_func_capabilities = 0x000A,
121 i40e_aqc_opc_list_dev_capabilities = 0x000B,
122
123 /* Proxy commands */
124 i40e_aqc_opc_set_proxy_config = 0x0104,
125 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
126
127 /* LAA */
128 i40e_aqc_opc_mac_address_read = 0x0107,
129 i40e_aqc_opc_mac_address_write = 0x0108,
130
131 /* PXE */
132 i40e_aqc_opc_clear_pxe_mode = 0x0110,
133
134 /* WoL commands */
135 i40e_aqc_opc_set_wol_filter = 0x0120,
136 i40e_aqc_opc_get_wake_reason = 0x0121,
137 i40e_aqc_opc_clear_all_wol_filters = 0x025E,
138
139 /* internal switch commands */
140 i40e_aqc_opc_get_switch_config = 0x0200,
141 i40e_aqc_opc_add_statistics = 0x0201,
142 i40e_aqc_opc_remove_statistics = 0x0202,
143 i40e_aqc_opc_set_port_parameters = 0x0203,
144 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
145 i40e_aqc_opc_set_switch_config = 0x0205,
146 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
147 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
148
149 i40e_aqc_opc_add_vsi = 0x0210,
150 i40e_aqc_opc_update_vsi_parameters = 0x0211,
151 i40e_aqc_opc_get_vsi_parameters = 0x0212,
152
153 i40e_aqc_opc_add_pv = 0x0220,
154 i40e_aqc_opc_update_pv_parameters = 0x0221,
155 i40e_aqc_opc_get_pv_parameters = 0x0222,
156
157 i40e_aqc_opc_add_veb = 0x0230,
158 i40e_aqc_opc_update_veb_parameters = 0x0231,
159 i40e_aqc_opc_get_veb_parameters = 0x0232,
160
161 i40e_aqc_opc_delete_element = 0x0243,
162
163 i40e_aqc_opc_add_macvlan = 0x0250,
164 i40e_aqc_opc_remove_macvlan = 0x0251,
165 i40e_aqc_opc_add_vlan = 0x0252,
166 i40e_aqc_opc_remove_vlan = 0x0253,
167 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
168 i40e_aqc_opc_add_tag = 0x0255,
169 i40e_aqc_opc_remove_tag = 0x0256,
170 i40e_aqc_opc_add_multicast_etag = 0x0257,
171 i40e_aqc_opc_remove_multicast_etag = 0x0258,
172 i40e_aqc_opc_update_tag = 0x0259,
173 i40e_aqc_opc_add_control_packet_filter = 0x025A,
174 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
175 i40e_aqc_opc_add_cloud_filters = 0x025C,
176 i40e_aqc_opc_remove_cloud_filters = 0x025D,
177 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
178 i40e_aqc_opc_replace_cloud_filters = 0x025F,
179
180 i40e_aqc_opc_add_mirror_rule = 0x0260,
181 i40e_aqc_opc_delete_mirror_rule = 0x0261,
182
183 /* Dynamic Device Personalization */
184 i40e_aqc_opc_write_personalization_profile = 0x0270,
185 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
186
187 /* DCB commands */
188 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
189 i40e_aqc_opc_dcb_updated = 0x0302,
190 i40e_aqc_opc_set_dcb_parameters = 0x0303,
191
192 /* TX scheduler */
193 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
194 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
195 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
196 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
197 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
198 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
199
200 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
201 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
202 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
203 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
204 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
205 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
206 i40e_aqc_opc_query_port_ets_config = 0x0419,
207 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
208 i40e_aqc_opc_suspend_port_tx = 0x041B,
209 i40e_aqc_opc_resume_port_tx = 0x041C,
210 i40e_aqc_opc_configure_partition_bw = 0x041D,
211 /* hmc */
212 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
213 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
214
215 /* phy commands*/
216 i40e_aqc_opc_get_phy_abilities = 0x0600,
217 i40e_aqc_opc_set_phy_config = 0x0601,
218 i40e_aqc_opc_set_mac_config = 0x0603,
219 i40e_aqc_opc_set_link_restart_an = 0x0605,
220 i40e_aqc_opc_get_link_status = 0x0607,
221 i40e_aqc_opc_set_phy_int_mask = 0x0613,
222 i40e_aqc_opc_get_local_advt_reg = 0x0614,
223 i40e_aqc_opc_set_local_advt_reg = 0x0615,
224 i40e_aqc_opc_get_partner_advt = 0x0616,
225 i40e_aqc_opc_set_lb_modes = 0x0618,
226 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
227 i40e_aqc_opc_set_phy_debug = 0x0622,
228 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
229 i40e_aqc_opc_run_phy_activity = 0x0626,
230 i40e_aqc_opc_set_phy_register = 0x0628,
231 i40e_aqc_opc_get_phy_register = 0x0629,
232
233 /* NVM commands */
234 i40e_aqc_opc_nvm_read = 0x0701,
235 i40e_aqc_opc_nvm_erase = 0x0702,
236 i40e_aqc_opc_nvm_update = 0x0703,
237 i40e_aqc_opc_nvm_config_read = 0x0704,
238 i40e_aqc_opc_nvm_config_write = 0x0705,
239 i40e_aqc_opc_nvm_progress = 0x0706,
240 i40e_aqc_opc_oem_post_update = 0x0720,
241 i40e_aqc_opc_thermal_sensor = 0x0721,
242
243 /* virtualization commands */
244 i40e_aqc_opc_send_msg_to_pf = 0x0801,
245 i40e_aqc_opc_send_msg_to_vf = 0x0802,
246 i40e_aqc_opc_send_msg_to_peer = 0x0803,
247
248 /* alternate structure */
249 i40e_aqc_opc_alternate_write = 0x0900,
250 i40e_aqc_opc_alternate_write_indirect = 0x0901,
251 i40e_aqc_opc_alternate_read = 0x0902,
252 i40e_aqc_opc_alternate_read_indirect = 0x0903,
253 i40e_aqc_opc_alternate_write_done = 0x0904,
254 i40e_aqc_opc_alternate_set_mode = 0x0905,
255 i40e_aqc_opc_alternate_clear_port = 0x0906,
256
257 /* LLDP commands */
258 i40e_aqc_opc_lldp_get_mib = 0x0A00,
259 i40e_aqc_opc_lldp_update_mib = 0x0A01,
260 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
261 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
262 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
263 i40e_aqc_opc_lldp_stop = 0x0A05,
264 i40e_aqc_opc_lldp_start = 0x0A06,
265 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
266 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
267 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
268
269 /* Tunnel commands */
270 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
271 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
272 i40e_aqc_opc_set_rss_key = 0x0B02,
273 i40e_aqc_opc_set_rss_lut = 0x0B03,
274 i40e_aqc_opc_get_rss_key = 0x0B04,
275 i40e_aqc_opc_get_rss_lut = 0x0B05,
276
277 /* Async Events */
278 i40e_aqc_opc_event_lan_overflow = 0x1001,
279
280 /* OEM commands */
281 i40e_aqc_opc_oem_parameter_change = 0xFE00,
282 i40e_aqc_opc_oem_device_status_change = 0xFE01,
283 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
284 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
285
286 /* debug commands */
287 i40e_aqc_opc_debug_read_reg = 0xFF03,
288 i40e_aqc_opc_debug_write_reg = 0xFF04,
289 i40e_aqc_opc_debug_modify_reg = 0xFF07,
290 i40e_aqc_opc_debug_dump_internals = 0xFF08,
291 };
292
293 /* command structures and indirect data structures */
294
295 /* Structure naming conventions:
296 * - no suffix for direct command descriptor structures
297 * - _data for indirect sent data
298 * - _resp for indirect return data (data which is both will use _data)
299 * - _completion for direct return data
300 * - _element_ for repeated elements (may also be _data or _resp)
301 *
302 * Command structures are expected to overlay the params.raw member of the basic
303 * descriptor, and as such cannot exceed 16 bytes in length.
304 */
305
306 /* This macro is used to generate a compilation error if a structure
307 * is not exactly the correct length. It gives a divide by zero error if the
308 * structure is not of the correct size, otherwise it creates an enum that is
309 * never used.
310 */
311 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
312 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
313
314 /* This macro is used extensively to ensure that command structures are 16
315 * bytes in length as they have to map to the raw array of that size.
316 */
317 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
318
319 /* internal (0x00XX) commands */
320
321 /* Get version (direct 0x0001) */
322 struct i40e_aqc_get_version {
323 __le32 rom_ver;
324 __le32 fw_build;
325 __le16 fw_major;
326 __le16 fw_minor;
327 __le16 api_major;
328 __le16 api_minor;
329 };
330
331 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
332
333 /* Send driver version (indirect 0x0002) */
334 struct i40e_aqc_driver_version {
335 u8 driver_major_ver;
336 u8 driver_minor_ver;
337 u8 driver_build_ver;
338 u8 driver_subbuild_ver;
339 u8 reserved[4];
340 __le32 address_high;
341 __le32 address_low;
342 };
343
344 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
345
346 /* Queue Shutdown (direct 0x0003) */
347 struct i40e_aqc_queue_shutdown {
348 __le32 driver_unloading;
349 #define I40E_AQ_DRIVER_UNLOADING 0x1
350 u8 reserved[12];
351 };
352
353 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
354
355 /* Set PF context (0x0004, direct) */
356 struct i40e_aqc_set_pf_context {
357 u8 pf_id;
358 u8 reserved[15];
359 };
360
361 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
362
363 /* Request resource ownership (direct 0x0008)
364 * Release resource ownership (direct 0x0009)
365 */
366 #define I40E_AQ_RESOURCE_NVM 1
367 #define I40E_AQ_RESOURCE_SDP 2
368 #define I40E_AQ_RESOURCE_ACCESS_READ 1
369 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
370 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
371 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
372
373 struct i40e_aqc_request_resource {
374 __le16 resource_id;
375 __le16 access_type;
376 __le32 timeout;
377 __le32 resource_number;
378 u8 reserved[4];
379 };
380
381 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
382
383 /* Get function capabilities (indirect 0x000A)
384 * Get device capabilities (indirect 0x000B)
385 */
386 struct i40e_aqc_list_capabilites {
387 u8 command_flags;
388 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
389 u8 pf_index;
390 u8 reserved[2];
391 __le32 count;
392 __le32 addr_high;
393 __le32 addr_low;
394 };
395
396 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
397
398 struct i40e_aqc_list_capabilities_element_resp {
399 __le16 id;
400 u8 major_rev;
401 u8 minor_rev;
402 __le32 number;
403 __le32 logical_id;
404 __le32 phys_id;
405 u8 reserved[16];
406 };
407
408 /* list of caps */
409
410 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
411 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
412 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
413 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
414 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
415 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
416 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
417 #define I40E_AQ_CAP_ID_SRIOV 0x0012
418 #define I40E_AQ_CAP_ID_VF 0x0013
419 #define I40E_AQ_CAP_ID_VMDQ 0x0014
420 #define I40E_AQ_CAP_ID_8021QBG 0x0015
421 #define I40E_AQ_CAP_ID_8021QBR 0x0016
422 #define I40E_AQ_CAP_ID_VSI 0x0017
423 #define I40E_AQ_CAP_ID_DCB 0x0018
424 #define I40E_AQ_CAP_ID_FCOE 0x0021
425 #define I40E_AQ_CAP_ID_ISCSI 0x0022
426 #define I40E_AQ_CAP_ID_RSS 0x0040
427 #define I40E_AQ_CAP_ID_RXQ 0x0041
428 #define I40E_AQ_CAP_ID_TXQ 0x0042
429 #define I40E_AQ_CAP_ID_MSIX 0x0043
430 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
431 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
432 #define I40E_AQ_CAP_ID_1588 0x0046
433 #define I40E_AQ_CAP_ID_IWARP 0x0051
434 #define I40E_AQ_CAP_ID_LED 0x0061
435 #define I40E_AQ_CAP_ID_SDP 0x0062
436 #define I40E_AQ_CAP_ID_MDIO 0x0063
437 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
438 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
439 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
440 #define I40E_AQ_CAP_ID_CEM 0x00F2
441
442 /* Set CPPM Configuration (direct 0x0103) */
443 struct i40e_aqc_cppm_configuration {
444 __le16 command_flags;
445 #define I40E_AQ_CPPM_EN_LTRC 0x0800
446 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
447 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
448 #define I40E_AQ_CPPM_EN_HPTC 0x4000
449 #define I40E_AQ_CPPM_EN_DMARC 0x8000
450 __le16 ttlx;
451 __le32 dmacr;
452 __le16 dmcth;
453 u8 hptc;
454 u8 reserved;
455 __le32 pfltrc;
456 };
457
458 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
459
460 /* Set ARP Proxy command / response (indirect 0x0104) */
461 struct i40e_aqc_arp_proxy_data {
462 __le16 command_flags;
463 #define I40E_AQ_ARP_INIT_IPV4 0x0800
464 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
465 #define I40E_AQ_ARP_ENA 0x2000
466 #define I40E_AQ_ARP_ADD_IPV4 0x4000
467 #define I40E_AQ_ARP_DEL_IPV4 0x8000
468 __le16 table_id;
469 __le32 enabled_offloads;
470 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
471 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
472 __le32 ip_addr;
473 u8 mac_addr[6];
474 u8 reserved[2];
475 };
476
477 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
478
479 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
480 struct i40e_aqc_ns_proxy_data {
481 __le16 table_idx_mac_addr_0;
482 __le16 table_idx_mac_addr_1;
483 __le16 table_idx_ipv6_0;
484 __le16 table_idx_ipv6_1;
485 __le16 control;
486 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
487 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
488 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
489 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
490 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
491 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
492 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
493 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
494 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
495 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
496 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
497 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
498 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
499 u8 mac_addr_0[6];
500 u8 mac_addr_1[6];
501 u8 local_mac_addr[6];
502 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
503 u8 ipv6_addr_1[16];
504 };
505
506 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
507
508 /* Manage LAA Command (0x0106) - obsolete */
509 struct i40e_aqc_mng_laa {
510 __le16 command_flags;
511 #define I40E_AQ_LAA_FLAG_WR 0x8000
512 u8 reserved[2];
513 __le32 sal;
514 __le16 sah;
515 u8 reserved2[6];
516 };
517
518 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
519
520 /* Manage MAC Address Read Command (indirect 0x0107) */
521 struct i40e_aqc_mac_address_read {
522 __le16 command_flags;
523 #define I40E_AQC_LAN_ADDR_VALID 0x10
524 #define I40E_AQC_SAN_ADDR_VALID 0x20
525 #define I40E_AQC_PORT_ADDR_VALID 0x40
526 #define I40E_AQC_WOL_ADDR_VALID 0x80
527 #define I40E_AQC_MC_MAG_EN_VALID 0x100
528 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200
529 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
530 u8 reserved[6];
531 __le32 addr_high;
532 __le32 addr_low;
533 };
534
535 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
536
537 struct i40e_aqc_mac_address_read_data {
538 u8 pf_lan_mac[6];
539 u8 pf_san_mac[6];
540 u8 port_mac[6];
541 u8 pf_wol_mac[6];
542 };
543
544 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
545
546 /* Manage MAC Address Write Command (0x0108) */
547 struct i40e_aqc_mac_address_write {
548 __le16 command_flags;
549 #define I40E_AQC_MC_MAG_EN 0x0100
550 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
551 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
552 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
553 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
554 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
555 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
556
557 __le16 mac_sah;
558 __le32 mac_sal;
559 u8 reserved[8];
560 };
561
562 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
563
564 /* PXE commands (0x011x) */
565
566 /* Clear PXE Command and response (direct 0x0110) */
567 struct i40e_aqc_clear_pxe {
568 u8 rx_cnt;
569 u8 reserved[15];
570 };
571
572 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
573
574 /* Set WoL Filter (0x0120) */
575
576 struct i40e_aqc_set_wol_filter {
577 __le16 filter_index;
578 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
579 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
580 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
581 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
582
583 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
584 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
585 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
586 __le16 cmd_flags;
587 #define I40E_AQC_SET_WOL_FILTER 0x8000
588 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
589 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
590 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
591 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
592 __le16 valid_flags;
593 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
594 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
595 u8 reserved[2];
596 __le32 address_high;
597 __le32 address_low;
598 };
599
600 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
601
602 struct i40e_aqc_set_wol_filter_data {
603 u8 filter[128];
604 u8 mask[16];
605 };
606
607 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
608
609 /* Get Wake Reason (0x0121) */
610
611 struct i40e_aqc_get_wake_reason_completion {
612 u8 reserved_1[2];
613 __le16 wake_reason;
614 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
615 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
616 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
617 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
618 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
619 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
620 u8 reserved_2[12];
621 };
622
623 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
624
625 /* Switch configuration commands (0x02xx) */
626
627 /* Used by many indirect commands that only pass an seid and a buffer in the
628 * command
629 */
630 struct i40e_aqc_switch_seid {
631 __le16 seid;
632 u8 reserved[6];
633 __le32 addr_high;
634 __le32 addr_low;
635 };
636
637 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
638
639 /* Get Switch Configuration command (indirect 0x0200)
640 * uses i40e_aqc_switch_seid for the descriptor
641 */
642 struct i40e_aqc_get_switch_config_header_resp {
643 __le16 num_reported;
644 __le16 num_total;
645 u8 reserved[12];
646 };
647
648 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
649
650 struct i40e_aqc_switch_config_element_resp {
651 u8 element_type;
652 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
653 #define I40E_AQ_SW_ELEM_TYPE_PF 2
654 #define I40E_AQ_SW_ELEM_TYPE_VF 3
655 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
656 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
657 #define I40E_AQ_SW_ELEM_TYPE_PV 16
658 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
659 #define I40E_AQ_SW_ELEM_TYPE_PA 18
660 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
661 u8 revision;
662 #define I40E_AQ_SW_ELEM_REV_1 1
663 __le16 seid;
664 __le16 uplink_seid;
665 __le16 downlink_seid;
666 u8 reserved[3];
667 u8 connection_type;
668 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
669 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
670 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
671 __le16 scheduler_id;
672 __le16 element_info;
673 };
674
675 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
676
677 /* Get Switch Configuration (indirect 0x0200)
678 * an array of elements are returned in the response buffer
679 * the first in the array is the header, remainder are elements
680 */
681 struct i40e_aqc_get_switch_config_resp {
682 struct i40e_aqc_get_switch_config_header_resp header;
683 struct i40e_aqc_switch_config_element_resp element[1];
684 };
685
686 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
687
688 /* Add Statistics (direct 0x0201)
689 * Remove Statistics (direct 0x0202)
690 */
691 struct i40e_aqc_add_remove_statistics {
692 __le16 seid;
693 __le16 vlan;
694 __le16 stat_index;
695 u8 reserved[10];
696 };
697
698 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
699
700 /* Set Port Parameters command (direct 0x0203) */
701 struct i40e_aqc_set_port_parameters {
702 __le16 command_flags;
703 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
704 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
705 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
706 __le16 bad_frame_vsi;
707 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
708 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
709 __le16 default_seid; /* reserved for command */
710 u8 reserved[10];
711 };
712
713 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
714
715 /* Get Switch Resource Allocation (indirect 0x0204) */
716 struct i40e_aqc_get_switch_resource_alloc {
717 u8 num_entries; /* reserved for command */
718 u8 reserved[7];
719 __le32 addr_high;
720 __le32 addr_low;
721 };
722
723 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
724
725 /* expect an array of these structs in the response buffer */
726 struct i40e_aqc_switch_resource_alloc_element_resp {
727 u8 resource_type;
728 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
729 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
730 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
731 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
732 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
733 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
734 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
735 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
736 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
737 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
738 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
739 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
740 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
741 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
742 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
743 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
744 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
745 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
746 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
747 u8 reserved1;
748 __le16 guaranteed;
749 __le16 total;
750 __le16 used;
751 __le16 total_unalloced;
752 u8 reserved2[6];
753 };
754
755 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
756
757 /* Set Switch Configuration (direct 0x0205) */
758 struct i40e_aqc_set_switch_config {
759 __le16 flags;
760 /* flags used for both fields below */
761 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
762 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
763 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
764 __le16 valid_flags;
765 /* The ethertype in switch_tag is dropped on ingress and used
766 * internally by the switch. Set this to zero for the default
767 * of 0x88a8 (802.1ad). Should be zero for firmware API
768 * versions lower than 1.7.
769 */
770 __le16 switch_tag;
771 /* The ethertypes in first_tag and second_tag are used to
772 * match the outer and inner VLAN tags (respectively) when HW
773 * double VLAN tagging is enabled via the set port parameters
774 * AQ command. Otherwise these are both ignored. Set them to
775 * zero for their defaults of 0x8100 (802.1Q). Should be zero
776 * for firmware API versions lower than 1.7.
777 */
778 __le16 first_tag;
779 __le16 second_tag;
780 /* Next byte is split into following:
781 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0
782 * Bit 6 : 0 : Destination Port, 1: source port
783 * Bit 5..4 : L4 type
784 * 0: rsvd
785 * 1: TCP
786 * 2: UDP
787 * 3: Both TCP and UDP
788 * Bits 3:0 Mode
789 * 0: default mode
790 * 1: L4 port only mode
791 * 2: non-tunneled mode
792 * 3: tunneled mode
793 */
794 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
795
796 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40
797
798 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00
799 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
800 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20
801 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30
802
803 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00
804 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01
805 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
806 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03
807 u8 mode;
808 u8 rsvd5[5];
809 };
810
811 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
812
813 /* Read Receive control registers (direct 0x0206)
814 * Write Receive control registers (direct 0x0207)
815 * used for accessing Rx control registers that can be
816 * slow and need special handling when under high Rx load
817 */
818 struct i40e_aqc_rx_ctl_reg_read_write {
819 __le32 reserved1;
820 __le32 address;
821 __le32 reserved2;
822 __le32 value;
823 };
824
825 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
826
827 /* Add VSI (indirect 0x0210)
828 * this indirect command uses struct i40e_aqc_vsi_properties_data
829 * as the indirect buffer (128 bytes)
830 *
831 * Update VSI (indirect 0x211)
832 * uses the same data structure as Add VSI
833 *
834 * Get VSI (indirect 0x0212)
835 * uses the same completion and data structure as Add VSI
836 */
837 struct i40e_aqc_add_get_update_vsi {
838 __le16 uplink_seid;
839 u8 connection_type;
840 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
841 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
842 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
843 u8 reserved1;
844 u8 vf_id;
845 u8 reserved2;
846 __le16 vsi_flags;
847 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
848 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
849 #define I40E_AQ_VSI_TYPE_VF 0x0
850 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
851 #define I40E_AQ_VSI_TYPE_PF 0x2
852 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
853 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
854 __le32 addr_high;
855 __le32 addr_low;
856 };
857
858 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
859
860 struct i40e_aqc_add_get_update_vsi_completion {
861 __le16 seid;
862 __le16 vsi_number;
863 __le16 vsi_used;
864 __le16 vsi_free;
865 __le32 addr_high;
866 __le32 addr_low;
867 };
868
869 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
870
871 struct i40e_aqc_vsi_properties_data {
872 /* first 96 byte are written by SW */
873 __le16 valid_sections;
874 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
875 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
876 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
877 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
878 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
879 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
880 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
881 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
882 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
883 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
884 /* switch section */
885 __le16 switch_id; /* 12bit id combined with flags below */
886 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
887 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
888 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
889 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
890 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
891 u8 sw_reserved[2];
892 /* security section */
893 u8 sec_flags;
894 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
895 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
896 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
897 u8 sec_reserved;
898 /* VLAN section */
899 __le16 pvid; /* VLANS include priority bits */
900 __le16 fcoe_pvid;
901 u8 port_vlan_flags;
902 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
903 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
904 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
905 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
906 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
907 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
908 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
909 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
910 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
911 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
912 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
913 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
914 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
915 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
916 u8 pvlan_reserved[3];
917 /* ingress egress up sections */
918 __le32 ingress_table; /* bitmap, 3 bits per up */
919 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
920 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
921 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
922 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
923 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
924 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
925 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
926 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
927 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
928 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
929 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
930 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
931 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
932 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
933 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
934 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
935 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
936 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
937 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
938 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
939 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
940 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
941 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
942 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
943 __le32 egress_table; /* same defines as for ingress table */
944 /* cascaded PV section */
945 __le16 cas_pv_tag;
946 u8 cas_pv_flags;
947 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
948 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
949 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
950 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
951 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
952 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
953 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
954 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
955 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
956 u8 cas_pv_reserved;
957 /* queue mapping section */
958 __le16 mapping_flags;
959 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
960 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
961 __le16 queue_mapping[16];
962 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
963 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
964 __le16 tc_mapping[8];
965 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
966 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
967 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
968 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
969 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
970 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
971 /* queueing option section */
972 u8 queueing_opt_flags;
973 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
974 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
975 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
976 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
977 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
978 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
979 u8 queueing_opt_reserved[3];
980 /* scheduler section */
981 u8 up_enable_bits;
982 u8 sched_reserved;
983 /* outer up section */
984 __le32 outer_up_table; /* same structure and defines as ingress tbl */
985 u8 cmd_reserved[8];
986 /* last 32 bytes are written by FW */
987 __le16 qs_handle[8];
988 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
989 __le16 stat_counter_idx;
990 __le16 sched_id;
991 u8 resp_reserved[12];
992 };
993
994 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
995
996 /* Add Port Virtualizer (direct 0x0220)
997 * also used for update PV (direct 0x0221) but only flags are used
998 * (IS_CTRL_PORT only works on add PV)
999 */
1000 struct i40e_aqc_add_update_pv {
1001 __le16 command_flags;
1002 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
1003 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
1004 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
1005 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
1006 __le16 uplink_seid;
1007 __le16 connected_seid;
1008 u8 reserved[10];
1009 };
1010
1011 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
1012
1013 struct i40e_aqc_add_update_pv_completion {
1014 /* reserved for update; for add also encodes error if rc == ENOSPC */
1015 __le16 pv_seid;
1016 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
1017 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
1018 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1019 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
1020 u8 reserved[14];
1021 };
1022
1023 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
1024
1025 /* Get PV Params (direct 0x0222)
1026 * uses i40e_aqc_switch_seid for the descriptor
1027 */
1028
1029 struct i40e_aqc_get_pv_params_completion {
1030 __le16 seid;
1031 __le16 default_stag;
1032 __le16 pv_flags; /* same flags as add_pv */
1033 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1034 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1035 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1036 u8 reserved[8];
1037 __le16 default_port_seid;
1038 };
1039
1040 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1041
1042 /* Add VEB (direct 0x0230) */
1043 struct i40e_aqc_add_veb {
1044 __le16 uplink_seid;
1045 __le16 downlink_seid;
1046 __le16 veb_flags;
1047 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1048 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1049 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1050 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1051 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1052 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1053 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1054 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1055 u8 enable_tcs;
1056 u8 reserved[9];
1057 };
1058
1059 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1060
1061 struct i40e_aqc_add_veb_completion {
1062 u8 reserved[6];
1063 __le16 switch_seid;
1064 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1065 __le16 veb_seid;
1066 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1067 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1068 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1069 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1070 __le16 statistic_index;
1071 __le16 vebs_used;
1072 __le16 vebs_free;
1073 };
1074
1075 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1076
1077 /* Get VEB Parameters (direct 0x0232)
1078 * uses i40e_aqc_switch_seid for the descriptor
1079 */
1080 struct i40e_aqc_get_veb_parameters_completion {
1081 __le16 seid;
1082 __le16 switch_id;
1083 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1084 __le16 statistic_index;
1085 __le16 vebs_used;
1086 __le16 vebs_free;
1087 u8 reserved[4];
1088 };
1089
1090 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1091
1092 /* Delete Element (direct 0x0243)
1093 * uses the generic i40e_aqc_switch_seid
1094 */
1095
1096 /* Add MAC-VLAN (indirect 0x0250) */
1097
1098 /* used for the command for most vlan commands */
1099 struct i40e_aqc_macvlan {
1100 __le16 num_addresses;
1101 __le16 seid[3];
1102 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1103 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1104 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1105 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1106 __le32 addr_high;
1107 __le32 addr_low;
1108 };
1109
1110 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1111
1112 /* indirect data for command and response */
1113 struct i40e_aqc_add_macvlan_element_data {
1114 u8 mac_addr[6];
1115 __le16 vlan_tag;
1116 __le16 flags;
1117 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1118 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1119 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1120 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1121 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1122 __le16 queue_number;
1123 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1124 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1125 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1126 /* response section */
1127 u8 match_method;
1128 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1129 #define I40E_AQC_MM_HASH_MATCH 0x02
1130 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1131 u8 reserved1[3];
1132 };
1133
1134 struct i40e_aqc_add_remove_macvlan_completion {
1135 __le16 perfect_mac_used;
1136 __le16 perfect_mac_free;
1137 __le16 unicast_hash_free;
1138 __le16 multicast_hash_free;
1139 __le32 addr_high;
1140 __le32 addr_low;
1141 };
1142
1143 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1144
1145 /* Remove MAC-VLAN (indirect 0x0251)
1146 * uses i40e_aqc_macvlan for the descriptor
1147 * data points to an array of num_addresses of elements
1148 */
1149
1150 struct i40e_aqc_remove_macvlan_element_data {
1151 u8 mac_addr[6];
1152 __le16 vlan_tag;
1153 u8 flags;
1154 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1155 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1156 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1157 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1158 u8 reserved[3];
1159 /* reply section */
1160 u8 error_code;
1161 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1162 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1163 u8 reply_reserved[3];
1164 };
1165
1166 /* Add VLAN (indirect 0x0252)
1167 * Remove VLAN (indirect 0x0253)
1168 * use the generic i40e_aqc_macvlan for the command
1169 */
1170 struct i40e_aqc_add_remove_vlan_element_data {
1171 __le16 vlan_tag;
1172 u8 vlan_flags;
1173 /* flags for add VLAN */
1174 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1175 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1176 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1177 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1178 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1179 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1180 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1181 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1182 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1183 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1184 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1185 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1186 /* flags for remove VLAN */
1187 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1188 u8 reserved;
1189 u8 result;
1190 /* flags for add VLAN */
1191 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1192 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1193 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1194 /* flags for remove VLAN */
1195 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1196 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1197 u8 reserved1[3];
1198 };
1199
1200 struct i40e_aqc_add_remove_vlan_completion {
1201 u8 reserved[4];
1202 __le16 vlans_used;
1203 __le16 vlans_free;
1204 __le32 addr_high;
1205 __le32 addr_low;
1206 };
1207
1208 /* Set VSI Promiscuous Modes (direct 0x0254) */
1209 struct i40e_aqc_set_vsi_promiscuous_modes {
1210 __le16 promiscuous_flags;
1211 __le16 valid_flags;
1212 /* flags used for both fields above */
1213 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1214 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1215 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1216 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1217 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1218 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1219 __le16 seid;
1220 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1221 __le16 vlan_tag;
1222 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1223 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1224 u8 reserved[8];
1225 };
1226
1227 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1228
1229 /* Add S/E-tag command (direct 0x0255)
1230 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1231 */
1232 struct i40e_aqc_add_tag {
1233 __le16 flags;
1234 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1235 __le16 seid;
1236 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1237 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1238 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1239 __le16 tag;
1240 __le16 queue_number;
1241 u8 reserved[8];
1242 };
1243
1244 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1245
1246 struct i40e_aqc_add_remove_tag_completion {
1247 u8 reserved[12];
1248 __le16 tags_used;
1249 __le16 tags_free;
1250 };
1251
1252 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1253
1254 /* Remove S/E-tag command (direct 0x0256)
1255 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1256 */
1257 struct i40e_aqc_remove_tag {
1258 __le16 seid;
1259 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1260 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1261 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1262 __le16 tag;
1263 u8 reserved[12];
1264 };
1265
1266 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1267
1268 /* Add multicast E-Tag (direct 0x0257)
1269 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1270 * and no external data
1271 */
1272 struct i40e_aqc_add_remove_mcast_etag {
1273 __le16 pv_seid;
1274 __le16 etag;
1275 u8 num_unicast_etags;
1276 u8 reserved[3];
1277 __le32 addr_high; /* address of array of 2-byte s-tags */
1278 __le32 addr_low;
1279 };
1280
1281 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1282
1283 struct i40e_aqc_add_remove_mcast_etag_completion {
1284 u8 reserved[4];
1285 __le16 mcast_etags_used;
1286 __le16 mcast_etags_free;
1287 __le32 addr_high;
1288 __le32 addr_low;
1289
1290 };
1291
1292 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1293
1294 /* Update S/E-Tag (direct 0x0259) */
1295 struct i40e_aqc_update_tag {
1296 __le16 seid;
1297 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1298 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1299 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1300 __le16 old_tag;
1301 __le16 new_tag;
1302 u8 reserved[10];
1303 };
1304
1305 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1306
1307 struct i40e_aqc_update_tag_completion {
1308 u8 reserved[12];
1309 __le16 tags_used;
1310 __le16 tags_free;
1311 };
1312
1313 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1314
1315 /* Add Control Packet filter (direct 0x025A)
1316 * Remove Control Packet filter (direct 0x025B)
1317 * uses the i40e_aqc_add_oveb_cloud,
1318 * and the generic direct completion structure
1319 */
1320 struct i40e_aqc_add_remove_control_packet_filter {
1321 u8 mac[6];
1322 __le16 etype;
1323 __le16 flags;
1324 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1325 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1326 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1327 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1328 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1329 __le16 seid;
1330 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1331 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1332 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1333 __le16 queue;
1334 u8 reserved[2];
1335 };
1336
1337 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1338
1339 struct i40e_aqc_add_remove_control_packet_filter_completion {
1340 __le16 mac_etype_used;
1341 __le16 etype_used;
1342 __le16 mac_etype_free;
1343 __le16 etype_free;
1344 u8 reserved[8];
1345 };
1346
1347 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1348
1349 /* Add Cloud filters (indirect 0x025C)
1350 * Remove Cloud filters (indirect 0x025D)
1351 * uses the i40e_aqc_add_remove_cloud_filters,
1352 * and the generic indirect completion structure
1353 */
1354 struct i40e_aqc_add_remove_cloud_filters {
1355 u8 num_filters;
1356 u8 reserved;
1357 __le16 seid;
1358 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1359 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1360 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1361 u8 big_buffer_flag;
1362 #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1
1363 #define I40E_AQC_ADD_CLOUD_CMD_BB 1
1364 u8 reserved2[3];
1365 __le32 addr_high;
1366 __le32 addr_low;
1367 };
1368
1369 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1370
1371 struct i40e_aqc_cloud_filters_element_data {
1372 u8 outer_mac[6];
1373 u8 inner_mac[6];
1374 __le16 inner_vlan;
1375 union {
1376 struct {
1377 u8 reserved[12];
1378 u8 data[4];
1379 } v4;
1380 struct {
1381 u8 data[16];
1382 } v6;
1383 struct {
1384 __le16 data[8];
1385 } raw_v6;
1386 } ipaddr;
1387 __le16 flags;
1388 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1389 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1390 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1391 /* 0x0000 reserved */
1392 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1393 /* 0x0002 reserved */
1394 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1395 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1396 /* 0x0005 reserved */
1397 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1398 /* 0x0007 reserved */
1399 /* 0x0008 reserved */
1400 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1401 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1402 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1403 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1404 /* 0x0010 to 0x0017 is for custom filters */
1405 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
1406 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
1407 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */
1408
1409 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1410 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1411 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1412 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1413 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1414
1415 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1416 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1417 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1418 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1419 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1420 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1421 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1422 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1423
1424 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1425 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1426 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1427
1428 __le32 tenant_id;
1429 u8 reserved[4];
1430 __le16 queue_number;
1431 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1432 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1433 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1434 u8 reserved2[14];
1435 /* response section */
1436 u8 allocation_result;
1437 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1438 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1439 u8 response_reserved[7];
1440 };
1441
1442 /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when
1443 * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set.
1444 */
1445 struct i40e_aqc_add_rm_cloud_filt_elem_ext {
1446 struct i40e_aqc_cloud_filters_element_data element;
1447 u16 general_fields[32];
1448 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1449 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1450 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1451 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1452 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1453 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1454 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1455 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1456 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1457 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1458 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1459 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1460 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1461 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1471 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1472 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1473 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1474 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1475 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1476 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1477 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1478 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1479 };
1480
1481 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1482
1483 /* i40e_aqc_cloud_filters_element_bb is used when
1484 * I40E_AQC_CLOUD_CMD_BB flag is set.
1485 */
1486 struct i40e_aqc_cloud_filters_element_bb {
1487 struct i40e_aqc_cloud_filters_element_data element;
1488 u16 general_fields[32];
1489 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1490 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1491 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1492 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1493 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1494 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1495 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1496 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1497 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1498 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1499 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1500 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1501 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1502 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1503 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1504 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1505 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1506 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1507 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1508 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1509 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1510 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1511 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1512 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1513 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1514 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1515 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1516 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1517 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1518 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1519 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1520 };
1521
1522 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1523
1524 struct i40e_aqc_remove_cloud_filters_completion {
1525 __le16 perfect_ovlan_used;
1526 __le16 perfect_ovlan_free;
1527 __le16 vlan_used;
1528 __le16 vlan_free;
1529 __le32 addr_high;
1530 __le32 addr_low;
1531 };
1532
1533 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1534
1535 /* Replace filter Command 0x025F
1536 * uses the i40e_aqc_replace_cloud_filters,
1537 * and the generic indirect completion structure
1538 */
1539 struct i40e_filter_data {
1540 u8 filter_type;
1541 u8 input[3];
1542 };
1543
1544 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1545
1546 struct i40e_aqc_replace_cloud_filters_cmd {
1547 u8 valid_flags;
1548 #define I40E_AQC_REPLACE_L1_FILTER 0x0
1549 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1
1550 #define I40E_AQC_GET_CLOUD_FILTERS 0x2
1551 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4
1552 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
1553 u8 old_filter_type;
1554 u8 new_filter_type;
1555 u8 tr_bit;
1556 u8 tr_bit2;
1557 u8 reserved[3];
1558 __le32 addr_high;
1559 __le32 addr_low;
1560 };
1561
1562 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1563
1564 struct i40e_aqc_replace_cloud_filters_cmd_buf {
1565 u8 data[32];
1566 /* Filter type INPUT codes*/
1567 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3
1568 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL)
1569
1570 /* Field Vector offsets */
1571 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
1572 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6
1573 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7
1574 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8
1575 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9
1576 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10
1577 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11
1578 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12
1579 /* big FLU */
1580 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14
1581 /* big FLU */
1582 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15
1583
1584 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37
1585 struct i40e_filter_data filters[8];
1586 };
1587
1588 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1589
1590 /* Add Mirror Rule (indirect or direct 0x0260)
1591 * Delete Mirror Rule (indirect or direct 0x0261)
1592 * note: some rule types (4,5) do not use an external buffer.
1593 * take care to set the flags correctly.
1594 */
1595 struct i40e_aqc_add_delete_mirror_rule {
1596 __le16 seid;
1597 __le16 rule_type;
1598 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1599 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1600 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1601 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1602 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1603 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1604 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1605 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1606 __le16 num_entries;
1607 __le16 destination; /* VSI for add, rule id for delete */
1608 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1609 __le32 addr_low;
1610 };
1611
1612 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1613
1614 struct i40e_aqc_add_delete_mirror_rule_completion {
1615 u8 reserved[2];
1616 __le16 rule_id; /* only used on add */
1617 __le16 mirror_rules_used;
1618 __le16 mirror_rules_free;
1619 __le32 addr_high;
1620 __le32 addr_low;
1621 };
1622
1623 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1624
1625 /* Dynamic Device Personalization */
1626 struct i40e_aqc_write_personalization_profile {
1627 u8 flags;
1628 u8 reserved[3];
1629 __le32 profile_track_id;
1630 __le32 addr_high;
1631 __le32 addr_low;
1632 };
1633
1634 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1635
1636 struct i40e_aqc_write_ddp_resp {
1637 __le32 error_offset;
1638 __le32 error_info;
1639 __le32 addr_high;
1640 __le32 addr_low;
1641 };
1642
1643 struct i40e_aqc_get_applied_profiles {
1644 u8 flags;
1645 #define I40E_AQC_GET_DDP_GET_CONF 0x1
1646 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2
1647 u8 rsv[3];
1648 __le32 reserved;
1649 __le32 addr_high;
1650 __le32 addr_low;
1651 };
1652
1653 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1654
1655 /* DCB 0x03xx*/
1656
1657 /* PFC Ignore (direct 0x0301)
1658 * the command and response use the same descriptor structure
1659 */
1660 struct i40e_aqc_pfc_ignore {
1661 u8 tc_bitmap;
1662 u8 command_flags; /* unused on response */
1663 #define I40E_AQC_PFC_IGNORE_SET 0x80
1664 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1665 u8 reserved[14];
1666 };
1667
1668 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1669
1670 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1671 * with no parameters
1672 */
1673
1674 /* TX scheduler 0x04xx */
1675
1676 /* Almost all the indirect commands use
1677 * this generic struct to pass the SEID in param0
1678 */
1679 struct i40e_aqc_tx_sched_ind {
1680 __le16 vsi_seid;
1681 u8 reserved[6];
1682 __le32 addr_high;
1683 __le32 addr_low;
1684 };
1685
1686 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1687
1688 /* Several commands respond with a set of queue set handles */
1689 struct i40e_aqc_qs_handles_resp {
1690 __le16 qs_handles[8];
1691 };
1692
1693 /* Configure VSI BW limits (direct 0x0400) */
1694 struct i40e_aqc_configure_vsi_bw_limit {
1695 __le16 vsi_seid;
1696 u8 reserved[2];
1697 __le16 credit;
1698 u8 reserved1[2];
1699 u8 max_credit; /* 0-3, limit = 2^max */
1700 u8 reserved2[7];
1701 };
1702
1703 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1704
1705 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1706 * responds with i40e_aqc_qs_handles_resp
1707 */
1708 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1709 u8 tc_valid_bits;
1710 u8 reserved[15];
1711 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1712
1713 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1714 __le16 tc_bw_max[2];
1715 u8 reserved1[28];
1716 };
1717
1718 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1719
1720 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1721 * responds with i40e_aqc_qs_handles_resp
1722 */
1723 struct i40e_aqc_configure_vsi_tc_bw_data {
1724 u8 tc_valid_bits;
1725 u8 reserved[3];
1726 u8 tc_bw_credits[8];
1727 u8 reserved1[4];
1728 __le16 qs_handles[8];
1729 };
1730
1731 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1732
1733 /* Query vsi bw configuration (indirect 0x0408) */
1734 struct i40e_aqc_query_vsi_bw_config_resp {
1735 u8 tc_valid_bits;
1736 u8 tc_suspended_bits;
1737 u8 reserved[14];
1738 __le16 qs_handles[8];
1739 u8 reserved1[4];
1740 __le16 port_bw_limit;
1741 u8 reserved2[2];
1742 u8 max_bw; /* 0-3, limit = 2^max */
1743 u8 reserved3[23];
1744 };
1745
1746 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1747
1748 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1749 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1750 u8 tc_valid_bits;
1751 u8 reserved[3];
1752 u8 share_credits[8];
1753 __le16 credits[8];
1754
1755 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1756 __le16 tc_bw_max[2];
1757 };
1758
1759 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1760
1761 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1762 struct i40e_aqc_configure_switching_comp_bw_limit {
1763 __le16 seid;
1764 u8 reserved[2];
1765 __le16 credit;
1766 u8 reserved1[2];
1767 u8 max_bw; /* 0-3, limit = 2^max */
1768 u8 reserved2[7];
1769 };
1770
1771 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1772
1773 /* Enable Physical Port ETS (indirect 0x0413)
1774 * Modify Physical Port ETS (indirect 0x0414)
1775 * Disable Physical Port ETS (indirect 0x0415)
1776 */
1777 struct i40e_aqc_configure_switching_comp_ets_data {
1778 u8 reserved[4];
1779 u8 tc_valid_bits;
1780 u8 seepage;
1781 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1782 u8 tc_strict_priority_flags;
1783 u8 reserved1[17];
1784 u8 tc_bw_share_credits[8];
1785 u8 reserved2[96];
1786 };
1787
1788 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1789
1790 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1791 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1792 u8 tc_valid_bits;
1793 u8 reserved[15];
1794 __le16 tc_bw_credit[8];
1795
1796 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1797 __le16 tc_bw_max[2];
1798 u8 reserved1[28];
1799 };
1800
1801 I40E_CHECK_STRUCT_LEN(0x40,
1802 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1803
1804 /* Configure Switching Component Bandwidth Allocation per Tc
1805 * (indirect 0x0417)
1806 */
1807 struct i40e_aqc_configure_switching_comp_bw_config_data {
1808 u8 tc_valid_bits;
1809 u8 reserved[2];
1810 u8 absolute_credits; /* bool */
1811 u8 tc_bw_share_credits[8];
1812 u8 reserved1[20];
1813 };
1814
1815 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1816
1817 /* Query Switching Component Configuration (indirect 0x0418) */
1818 struct i40e_aqc_query_switching_comp_ets_config_resp {
1819 u8 tc_valid_bits;
1820 u8 reserved[35];
1821 __le16 port_bw_limit;
1822 u8 reserved1[2];
1823 u8 tc_bw_max; /* 0-3, limit = 2^max */
1824 u8 reserved2[23];
1825 };
1826
1827 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1828
1829 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1830 struct i40e_aqc_query_port_ets_config_resp {
1831 u8 reserved[4];
1832 u8 tc_valid_bits;
1833 u8 reserved1;
1834 u8 tc_strict_priority_bits;
1835 u8 reserved2;
1836 u8 tc_bw_share_credits[8];
1837 __le16 tc_bw_limits[8];
1838
1839 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1840 __le16 tc_bw_max[2];
1841 u8 reserved3[32];
1842 };
1843
1844 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1845
1846 /* Query Switching Component Bandwidth Allocation per Traffic Type
1847 * (indirect 0x041A)
1848 */
1849 struct i40e_aqc_query_switching_comp_bw_config_resp {
1850 u8 tc_valid_bits;
1851 u8 reserved[2];
1852 u8 absolute_credits_enable; /* bool */
1853 u8 tc_bw_share_credits[8];
1854 __le16 tc_bw_limits[8];
1855
1856 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1857 __le16 tc_bw_max[2];
1858 };
1859
1860 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1861
1862 /* Suspend/resume port TX traffic
1863 * (direct 0x041B and 0x041C) uses the generic SEID struct
1864 */
1865
1866 /* Configure partition BW
1867 * (indirect 0x041D)
1868 */
1869 struct i40e_aqc_configure_partition_bw_data {
1870 __le16 pf_valid_bits;
1871 u8 min_bw[16]; /* guaranteed bandwidth */
1872 u8 max_bw[16]; /* bandwidth limit */
1873 };
1874
1875 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1876
1877 /* Get and set the active HMC resource profile and status.
1878 * (direct 0x0500) and (direct 0x0501)
1879 */
1880 struct i40e_aq_get_set_hmc_resource_profile {
1881 u8 pm_profile;
1882 u8 pe_vf_enabled;
1883 u8 reserved[14];
1884 };
1885
1886 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1887
1888 enum i40e_aq_hmc_profile {
1889 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1890 I40E_HMC_PROFILE_DEFAULT = 1,
1891 I40E_HMC_PROFILE_FAVOR_VF = 2,
1892 I40E_HMC_PROFILE_EQUAL = 3,
1893 };
1894
1895 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1896
1897 /* set in param0 for get phy abilities to report qualified modules */
1898 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1899 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1900
1901 enum i40e_aq_phy_type {
1902 I40E_PHY_TYPE_SGMII = 0x0,
1903 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1904 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1905 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1906 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1907 I40E_PHY_TYPE_XAUI = 0x5,
1908 I40E_PHY_TYPE_XFI = 0x6,
1909 I40E_PHY_TYPE_SFI = 0x7,
1910 I40E_PHY_TYPE_XLAUI = 0x8,
1911 I40E_PHY_TYPE_XLPPI = 0x9,
1912 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1913 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1914 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1915 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1916 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1917 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1918 I40E_PHY_TYPE_100BASE_TX = 0x11,
1919 I40E_PHY_TYPE_1000BASE_T = 0x12,
1920 I40E_PHY_TYPE_10GBASE_T = 0x13,
1921 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1922 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1923 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1924 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1925 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1926 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1927 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1928 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1929 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1930 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1931 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1932 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1933 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1934 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1935 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1936 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1937 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1938 #ifdef CARLSVILLE_HW
1939 I40E_PHY_TYPE_2_5GBASE_T = 0x30,
1940 I40E_PHY_TYPE_5GBASE_T = 0x31,
1941 #endif
1942 I40E_PHY_TYPE_MAX,
1943 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1944 I40E_PHY_TYPE_EMPTY = 0xFE,
1945 I40E_PHY_TYPE_DEFAULT = 0xFF,
1946 };
1947
1948 #ifdef CARLSVILLE_HW
1949 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1950 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1951 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1952 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1953 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1954 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1955 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1956 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1957 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1958 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1959 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1960 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1961 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1962 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1963 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1964 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1965 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1966 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1967 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1968 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1969 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1970 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1971 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1972 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1973 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1974 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1975 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1976 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1977 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1978 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1979 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1980 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1981 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1982 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1983 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1984 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
1985 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
1986 BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
1987 #else
1988 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1989 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1990 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1991 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1992 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1993 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1994 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1995 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1996 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1997 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1998 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1999 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
2000 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
2001 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
2002 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
2003 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
2004 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
2005 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
2006 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
2007 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
2008 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
2009 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
2010 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
2011 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
2012 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
2013 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
2014 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
2015 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
2016 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
2017 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
2018 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
2019 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
2020 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
2021 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
2022 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
2023 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC))
2024 #endif
2025
2026 #ifdef CARLSVILLE_HW
2027 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0
2028 #endif
2029 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
2030 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
2031 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
2032 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
2033 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
2034 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
2035 #ifdef CARLSVILLE_HW
2036 #define I40E_LINK_SPEED_5GB_SHIFT 0x7
2037 #endif
2038
2039 enum i40e_aq_link_speed {
2040 I40E_LINK_SPEED_UNKNOWN = 0,
2041 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
2042 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
2043 #ifdef CARLSVILLE_HW
2044 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
2045 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT),
2046 #endif
2047 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
2048 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
2049 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT),
2050 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT),
2051 };
2052
2053 struct i40e_aqc_module_desc {
2054 u8 oui[3];
2055 u8 reserved1;
2056 u8 part_number[16];
2057 u8 revision[4];
2058 u8 reserved2[8];
2059 };
2060
2061 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
2062
2063 struct i40e_aq_get_phy_abilities_resp {
2064 __le32 phy_type; /* bitmap using the above enum for offsets */
2065 u8 link_speed; /* bitmap using the above enum bit patterns */
2066 u8 abilities;
2067 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
2068 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
2069 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
2070 #define I40E_AQ_PHY_LINK_ENABLED 0x08
2071 #define I40E_AQ_PHY_AN_ENABLED 0x10
2072 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
2073 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
2074 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
2075 __le16 eee_capability;
2076 #define I40E_AQ_EEE_100BASE_TX 0x0002
2077 #define I40E_AQ_EEE_1000BASE_T 0x0004
2078 #define I40E_AQ_EEE_10GBASE_T 0x0008
2079 #define I40E_AQ_EEE_1000BASE_KX 0x0010
2080 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
2081 #define I40E_AQ_EEE_10GBASE_KR 0x0040
2082 __le32 eeer_val;
2083 u8 d3_lpan;
2084 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
2085 u8 phy_type_ext;
2086 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01
2087 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02
2088 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
2089 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
2090 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10
2091 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20
2092 #ifdef CARLSVILLE_HW
2093 #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40
2094 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80
2095 #endif
2096 u8 fec_cfg_curr_mod_ext_info;
2097 #define I40E_AQ_ENABLE_FEC_KR 0x01
2098 #define I40E_AQ_ENABLE_FEC_RS 0x02
2099 #define I40E_AQ_REQUEST_FEC_KR 0x04
2100 #define I40E_AQ_REQUEST_FEC_RS 0x08
2101 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
2102 #define I40E_AQ_FEC
2103 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
2104 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
2105
2106 u8 ext_comp_code;
2107 u8 phy_id[4];
2108 u8 module_type[3];
2109 u8 qualified_module_count;
2110 #define I40E_AQ_PHY_MAX_QMS 16
2111 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
2112 };
2113
2114 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
2115
2116 /* Set PHY Config (direct 0x0601) */
2117 struct i40e_aq_set_phy_config { /* same bits as above in all */
2118 __le32 phy_type;
2119 u8 link_speed;
2120 u8 abilities;
2121 /* bits 0-2 use the values from get_phy_abilities_resp */
2122 #define I40E_AQ_PHY_ENABLE_LINK 0x08
2123 #define I40E_AQ_PHY_ENABLE_AN 0x10
2124 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
2125 __le16 eee_capability;
2126 __le32 eeer;
2127 u8 low_power_ctrl;
2128 u8 phy_type_ext;
2129 u8 fec_config;
2130 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
2131 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
2132 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
2133 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
2134 #define I40E_AQ_SET_FEC_AUTO BIT(4)
2135 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
2136 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
2137 u8 reserved;
2138 };
2139
2140 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
2141
2142 /* Set MAC Config command data structure (direct 0x0603) */
2143 struct i40e_aq_set_mac_config {
2144 __le16 max_frame_size;
2145 u8 params;
2146 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
2147 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
2148 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
2149 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
2150 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
2151 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
2152 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
2153 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
2154 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
2155 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
2156 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
2157 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
2158 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
2159 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
2160 u8 tx_timer_priority; /* bitmap */
2161 __le16 tx_timer_value;
2162 __le16 fc_refresh_threshold;
2163 u8 reserved[8];
2164 };
2165
2166 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
2167
2168 /* Restart Auto-Negotiation (direct 0x605) */
2169 struct i40e_aqc_set_link_restart_an {
2170 u8 command;
2171 #define I40E_AQ_PHY_RESTART_AN 0x02
2172 #define I40E_AQ_PHY_LINK_ENABLE 0x04
2173 u8 reserved[15];
2174 };
2175
2176 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
2177
2178 /* Get Link Status cmd & response data structure (direct 0x0607) */
2179 struct i40e_aqc_get_link_status {
2180 __le16 command_flags; /* only field set on command */
2181 #define I40E_AQ_LSE_MASK 0x3
2182 #define I40E_AQ_LSE_NOP 0x0
2183 #define I40E_AQ_LSE_DISABLE 0x2
2184 #define I40E_AQ_LSE_ENABLE 0x3
2185 /* only response uses this flag */
2186 #define I40E_AQ_LSE_IS_ENABLED 0x1
2187 u8 phy_type; /* i40e_aq_phy_type */
2188 u8 link_speed; /* i40e_aq_link_speed */
2189 u8 link_info;
2190 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
2191 #define I40E_AQ_LINK_UP_FUNCTION 0x01
2192 #define I40E_AQ_LINK_FAULT 0x02
2193 #define I40E_AQ_LINK_FAULT_TX 0x04
2194 #define I40E_AQ_LINK_FAULT_RX 0x08
2195 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
2196 #define I40E_AQ_LINK_UP_PORT 0x20
2197 #define I40E_AQ_MEDIA_AVAILABLE 0x40
2198 #define I40E_AQ_SIGNAL_DETECT 0x80
2199 u8 an_info;
2200 #define I40E_AQ_AN_COMPLETED 0x01
2201 #define I40E_AQ_LP_AN_ABILITY 0x02
2202 #define I40E_AQ_PD_FAULT 0x04
2203 #define I40E_AQ_FEC_EN 0x08
2204 #define I40E_AQ_PHY_LOW_POWER 0x10
2205 #define I40E_AQ_LINK_PAUSE_TX 0x20
2206 #define I40E_AQ_LINK_PAUSE_RX 0x40
2207 #define I40E_AQ_QUALIFIED_MODULE 0x80
2208 u8 ext_info;
2209 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
2210 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
2211 #define I40E_AQ_LINK_TX_SHIFT 0x02
2212 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
2213 #define I40E_AQ_LINK_TX_ACTIVE 0x00
2214 #define I40E_AQ_LINK_TX_DRAINED 0x01
2215 #define I40E_AQ_LINK_TX_FLUSHED 0x03
2216 #define I40E_AQ_LINK_FORCED_40G 0x10
2217 /* 25G Error Codes */
2218 #define I40E_AQ_25G_NO_ERR 0X00
2219 #define I40E_AQ_25G_NOT_PRESENT 0X01
2220 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
2221 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
2222 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
2223 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
2224 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
2225 /* Since firmware API 1.7 loopback field keeps power class info as well */
2226 #define I40E_AQ_LOOPBACK_MASK 0x07
2227 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6
2228 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2229 __le16 max_frame_size;
2230 u8 config;
2231 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
2232 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
2233 #define I40E_AQ_CONFIG_CRC_ENA 0x04
2234 #define I40E_AQ_CONFIG_PACING_MASK 0x78
2235 union {
2236 struct {
2237 u8 power_desc;
2238 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
2239 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
2240 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
2241 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
2242 #define I40E_AQ_PWR_CLASS_MASK 0x03
2243 u8 reserved[4];
2244 };
2245 struct {
2246 u8 link_type[4];
2247 u8 link_type_ext;
2248 };
2249 };
2250 };
2251
2252 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
2253
2254 /* Set event mask command (direct 0x613) */
2255 struct i40e_aqc_set_phy_int_mask {
2256 u8 reserved[8];
2257 __le16 event_mask;
2258 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
2259 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
2260 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
2261 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
2262 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
2263 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
2264 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
2265 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
2266 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2267 u8 reserved1[6];
2268 };
2269
2270 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
2271
2272 /* Get Local AN advt register (direct 0x0614)
2273 * Set Local AN advt register (direct 0x0615)
2274 * Get Link Partner AN advt register (direct 0x0616)
2275 */
2276 struct i40e_aqc_an_advt_reg {
2277 __le32 local_an_reg0;
2278 __le16 local_an_reg1;
2279 u8 reserved[10];
2280 };
2281
2282 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
2283
2284 /* Set Loopback mode (0x0618) */
2285 struct i40e_aqc_set_lb_mode {
2286 __le16 lb_mode;
2287 #define I40E_AQ_LB_PHY_LOCAL 0x01
2288 #define I40E_AQ_LB_PHY_REMOTE 0x02
2289 #define I40E_AQ_LB_MAC_LOCAL 0x04
2290 u8 reserved[14];
2291 };
2292
2293 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
2294
2295 /* Set PHY Debug command (0x0622) */
2296 struct i40e_aqc_set_phy_debug {
2297 u8 command_flags;
2298 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
2299 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
2300 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2301 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2302 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2303 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2304 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2305 /* Disable link manageability on a single port */
2306 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2307 /* Disable link manageability on all ports needs both bits 4 and 5 */
2308 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
2309 u8 reserved[15];
2310 };
2311
2312 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2313
2314 enum i40e_aq_phy_reg_type {
2315 I40E_AQC_PHY_REG_INTERNAL = 0x1,
2316 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2317 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2318 };
2319
2320 /* Run PHY Activity (0x0626) */
2321 struct i40e_aqc_run_phy_activity {
2322 __le16 activity_id;
2323 u8 flags;
2324 u8 reserved1;
2325 __le32 control;
2326 __le32 data;
2327 u8 reserved2[4];
2328 };
2329
2330 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2331
2332 /* Set PHY Register command (0x0628) */
2333 /* Get PHY Register command (0x0629) */
2334 struct i40e_aqc_phy_register_access {
2335 u8 phy_interface;
2336 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2337 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
2338 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
2339 u8 dev_addres;
2340 u8 cmd_flags;
2341 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 1
2342 u8 reserved1;
2343 __le32 reg_address;
2344 __le32 reg_value;
2345 u8 reserved2[4];
2346 };
2347
2348 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
2349
2350 /* NVM Read command (indirect 0x0701)
2351 * NVM Erase commands (direct 0x0702)
2352 * NVM Update commands (indirect 0x0703)
2353 */
2354 struct i40e_aqc_nvm_update {
2355 u8 command_flags;
2356 #define I40E_AQ_NVM_LAST_CMD 0x01
2357 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20
2358 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40
2359 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2360 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
2361 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
2362 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2363 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
2364 u8 module_pointer;
2365 __le16 length;
2366 __le32 offset;
2367 __le32 addr_high;
2368 __le32 addr_low;
2369 };
2370
2371 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2372
2373 /* NVM Config Read (indirect 0x0704) */
2374 struct i40e_aqc_nvm_config_read {
2375 __le16 cmd_flags;
2376 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2377 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2378 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2379 __le16 element_count;
2380 __le16 element_id; /* Feature/field ID */
2381 __le16 element_id_msw; /* MSWord of field ID */
2382 __le32 address_high;
2383 __le32 address_low;
2384 };
2385
2386 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2387
2388 /* NVM Config Write (indirect 0x0705) */
2389 struct i40e_aqc_nvm_config_write {
2390 __le16 cmd_flags;
2391 __le16 element_count;
2392 u8 reserved[4];
2393 __le32 address_high;
2394 __le32 address_low;
2395 };
2396
2397 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2398
2399 /* Used for 0x0704 as well as for 0x0705 commands */
2400 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2401 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2402 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2403 #define I40E_AQ_ANVM_FEATURE 0
2404 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2405 struct i40e_aqc_nvm_config_data_feature {
2406 __le16 feature_id;
2407 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2408 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2409 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2410 __le16 feature_options;
2411 __le16 feature_selection;
2412 };
2413
2414 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2415
2416 struct i40e_aqc_nvm_config_data_immediate_field {
2417 __le32 field_id;
2418 __le32 field_value;
2419 __le16 field_options;
2420 __le16 reserved;
2421 };
2422
2423 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2424
2425 /* OEM Post Update (indirect 0x0720)
2426 * no command data struct used
2427 */
2428 struct i40e_aqc_nvm_oem_post_update {
2429 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2430 u8 sel_data;
2431 u8 reserved[7];
2432 };
2433
2434 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2435
2436 struct i40e_aqc_nvm_oem_post_update_buffer {
2437 u8 str_len;
2438 u8 dev_addr;
2439 __le16 eeprom_addr;
2440 u8 data[36];
2441 };
2442
2443 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2444
2445 /* Thermal Sensor (indirect 0x0721)
2446 * read or set thermal sensor configs and values
2447 * takes a sensor and command specific data buffer, not detailed here
2448 */
2449 struct i40e_aqc_thermal_sensor {
2450 u8 sensor_action;
2451 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2452 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2453 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2454 u8 reserved[7];
2455 __le32 addr_high;
2456 __le32 addr_low;
2457 };
2458
2459 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2460
2461 /* Send to PF command (indirect 0x0801) id is only used by PF
2462 * Send to VF command (indirect 0x0802) id is only used by PF
2463 * Send to Peer PF command (indirect 0x0803)
2464 */
2465 struct i40e_aqc_pf_vf_message {
2466 __le32 id;
2467 u8 reserved[4];
2468 __le32 addr_high;
2469 __le32 addr_low;
2470 };
2471
2472 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2473
2474 /* Alternate structure */
2475
2476 /* Direct write (direct 0x0900)
2477 * Direct read (direct 0x0902)
2478 */
2479 struct i40e_aqc_alternate_write {
2480 __le32 address0;
2481 __le32 data0;
2482 __le32 address1;
2483 __le32 data1;
2484 };
2485
2486 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2487
2488 /* Indirect write (indirect 0x0901)
2489 * Indirect read (indirect 0x0903)
2490 */
2491
2492 struct i40e_aqc_alternate_ind_write {
2493 __le32 address;
2494 __le32 length;
2495 __le32 addr_high;
2496 __le32 addr_low;
2497 };
2498
2499 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2500
2501 /* Done alternate write (direct 0x0904)
2502 * uses i40e_aq_desc
2503 */
2504 struct i40e_aqc_alternate_write_done {
2505 __le16 cmd_flags;
2506 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2507 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2508 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2509 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2510 u8 reserved[14];
2511 };
2512
2513 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2514
2515 /* Set OEM mode (direct 0x0905) */
2516 struct i40e_aqc_alternate_set_mode {
2517 __le32 mode;
2518 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2519 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2520 u8 reserved[12];
2521 };
2522
2523 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2524
2525 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2526
2527 /* async events 0x10xx */
2528
2529 /* Lan Queue Overflow Event (direct, 0x1001) */
2530 struct i40e_aqc_lan_overflow {
2531 __le32 prtdcb_rupto;
2532 __le32 otx_ctl;
2533 u8 reserved[8];
2534 };
2535
2536 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2537
2538 /* Get LLDP MIB (indirect 0x0A00) */
2539 struct i40e_aqc_lldp_get_mib {
2540 u8 type;
2541 u8 reserved1;
2542 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2543 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2544 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2545 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2546 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2547 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2548 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2549 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2550 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2551 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2552 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2553 __le16 local_len;
2554 __le16 remote_len;
2555 u8 reserved2[2];
2556 __le32 addr_high;
2557 __le32 addr_low;
2558 };
2559
2560 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2561
2562 /* Configure LLDP MIB Change Event (direct 0x0A01)
2563 * also used for the event (with type in the command field)
2564 */
2565 struct i40e_aqc_lldp_update_mib {
2566 u8 command;
2567 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2568 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2569 u8 reserved[7];
2570 __le32 addr_high;
2571 __le32 addr_low;
2572 };
2573
2574 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2575
2576 /* Add LLDP TLV (indirect 0x0A02)
2577 * Delete LLDP TLV (indirect 0x0A04)
2578 */
2579 struct i40e_aqc_lldp_add_tlv {
2580 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2581 u8 reserved1[1];
2582 __le16 len;
2583 u8 reserved2[4];
2584 __le32 addr_high;
2585 __le32 addr_low;
2586 };
2587
2588 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2589
2590 /* Update LLDP TLV (indirect 0x0A03) */
2591 struct i40e_aqc_lldp_update_tlv {
2592 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2593 u8 reserved;
2594 __le16 old_len;
2595 __le16 new_offset;
2596 __le16 new_len;
2597 __le32 addr_high;
2598 __le32 addr_low;
2599 };
2600
2601 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2602
2603 /* Stop LLDP (direct 0x0A05) */
2604 struct i40e_aqc_lldp_stop {
2605 u8 command;
2606 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2607 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2608 u8 reserved[15];
2609 };
2610
2611 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2612
2613 /* Start LLDP (direct 0x0A06) */
2614
2615 struct i40e_aqc_lldp_start {
2616 u8 command;
2617 #define I40E_AQ_LLDP_AGENT_START 0x1
2618 u8 reserved[15];
2619 };
2620
2621 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2622
2623 /* Set DCB (direct 0x0303) */
2624 struct i40e_aqc_set_dcb_parameters {
2625 u8 command;
2626 #define I40E_AQ_DCB_SET_AGENT 0x1
2627 #define I40E_DCB_VALID 0x1
2628 u8 valid_flags;
2629 u8 reserved[14];
2630 };
2631
2632 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2633
2634 /* Get CEE DCBX Oper Config (0x0A07)
2635 * uses the generic descriptor struct
2636 * returns below as indirect response
2637 */
2638
2639 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2640 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2641 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2642 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2643 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2644 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2645
2646 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2647 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2648 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2649 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2650 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2651 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2652 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2653 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2654 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2655 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2656 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2657 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2658
2659 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2660 * word boundary layout issues, which the Linux compilers silently deal
2661 * with by adding padding, making the actual struct larger than designed.
2662 * However, the FW compiler for the NIC is less lenient and complains
2663 * about the struct. Hence, the struct defined here has an extra byte in
2664 * fields reserved3 and reserved4 to directly acknowledge that padding,
2665 * and the new length is used in the length check macro.
2666 */
2667 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2668 u8 reserved1;
2669 u8 oper_num_tc;
2670 u8 oper_prio_tc[4];
2671 u8 reserved2;
2672 u8 oper_tc_bw[8];
2673 u8 oper_pfc_en;
2674 u8 reserved3[2];
2675 __le16 oper_app_prio;
2676 u8 reserved4[2];
2677 __le16 tlv_status;
2678 };
2679
2680 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2681
2682 struct i40e_aqc_get_cee_dcb_cfg_resp {
2683 u8 oper_num_tc;
2684 u8 oper_prio_tc[4];
2685 u8 oper_tc_bw[8];
2686 u8 oper_pfc_en;
2687 __le16 oper_app_prio;
2688 __le32 tlv_status;
2689 u8 reserved[12];
2690 };
2691
2692 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2693
2694 /* Set Local LLDP MIB (indirect 0x0A08)
2695 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2696 */
2697 struct i40e_aqc_lldp_set_local_mib {
2698 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2699 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2700 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2701 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2702 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2703 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2704 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2705 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2706 u8 type;
2707 u8 reserved0;
2708 __le16 length;
2709 u8 reserved1[4];
2710 __le32 address_high;
2711 __le32 address_low;
2712 };
2713
2714 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2715
2716 struct i40e_aqc_lldp_set_local_mib_resp {
2717 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2718 u8 status;
2719 u8 reserved[15];
2720 };
2721
2722 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2723
2724 /* Stop/Start LLDP Agent (direct 0x0A09)
2725 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2726 */
2727 struct i40e_aqc_lldp_stop_start_specific_agent {
2728 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2729 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2730 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2731 u8 command;
2732 u8 reserved[15];
2733 };
2734
2735 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2736
2737 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2738 struct i40e_aqc_add_udp_tunnel {
2739 __le16 udp_port;
2740 u8 reserved0[3];
2741 u8 protocol_type;
2742 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2743 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2744 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2745 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2746 u8 reserved1[10];
2747 };
2748
2749 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2750
2751 struct i40e_aqc_add_udp_tunnel_completion {
2752 __le16 udp_port;
2753 u8 filter_entry_index;
2754 u8 multiple_pfs;
2755 #define I40E_AQC_SINGLE_PF 0x0
2756 #define I40E_AQC_MULTIPLE_PFS 0x1
2757 u8 total_filters;
2758 u8 reserved[11];
2759 };
2760
2761 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2762
2763 /* remove UDP Tunnel command (0x0B01) */
2764 struct i40e_aqc_remove_udp_tunnel {
2765 u8 reserved[2];
2766 u8 index; /* 0 to 15 */
2767 u8 reserved2[13];
2768 };
2769
2770 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2771
2772 struct i40e_aqc_del_udp_tunnel_completion {
2773 __le16 udp_port;
2774 u8 index; /* 0 to 15 */
2775 u8 multiple_pfs;
2776 u8 total_filters_used;
2777 u8 reserved1[11];
2778 };
2779
2780 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2781
2782 struct i40e_aqc_get_set_rss_key {
2783 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2784 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2785 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2786 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2787 __le16 vsi_id;
2788 u8 reserved[6];
2789 __le32 addr_high;
2790 __le32 addr_low;
2791 };
2792
2793 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2794
2795 struct i40e_aqc_get_set_rss_key_data {
2796 u8 standard_rss_key[0x28];
2797 u8 extended_hash_key[0xc];
2798 };
2799
2800 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2801
2802 struct i40e_aqc_get_set_rss_lut {
2803 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2804 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2805 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2806 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2807 __le16 vsi_id;
2808 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2809 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2810 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2811
2812 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2813 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2814 __le16 flags;
2815 u8 reserved[4];
2816 __le32 addr_high;
2817 __le32 addr_low;
2818 };
2819
2820 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2821
2822 /* tunnel key structure 0x0B10 */
2823
2824 struct i40e_aqc_tunnel_key_structure {
2825 u8 key1_off;
2826 u8 key2_off;
2827 u8 key1_len; /* 0 to 15 */
2828 u8 key2_len; /* 0 to 15 */
2829 u8 flags;
2830 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2831 /* response flags */
2832 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2833 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2834 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2835 u8 network_key_index;
2836 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2837 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2838 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2839 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2840 u8 reserved[10];
2841 };
2842
2843 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2844
2845 /* OEM mode commands (direct 0xFE0x) */
2846 struct i40e_aqc_oem_param_change {
2847 __le32 param_type;
2848 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2849 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2850 #define I40E_AQ_OEM_PARAM_MAC 2
2851 __le32 param_value1;
2852 __le16 param_value2;
2853 u8 reserved[6];
2854 };
2855
2856 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2857
2858 struct i40e_aqc_oem_state_change {
2859 __le32 state;
2860 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2861 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2862 u8 reserved[12];
2863 };
2864
2865 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2866
2867 /* Initialize OCSD (0xFE02, direct) */
2868 struct i40e_aqc_opc_oem_ocsd_initialize {
2869 u8 type_status;
2870 u8 reserved1[3];
2871 __le32 ocsd_memory_block_addr_high;
2872 __le32 ocsd_memory_block_addr_low;
2873 __le32 requested_update_interval;
2874 };
2875
2876 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2877
2878 /* Initialize OCBB (0xFE03, direct) */
2879 struct i40e_aqc_opc_oem_ocbb_initialize {
2880 u8 type_status;
2881 u8 reserved1[3];
2882 __le32 ocbb_memory_block_addr_high;
2883 __le32 ocbb_memory_block_addr_low;
2884 u8 reserved2[4];
2885 };
2886
2887 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2888
2889 /* debug commands */
2890
2891 /* get device id (0xFF00) uses the generic structure */
2892
2893 /* set test more (0xFF01, internal) */
2894
2895 struct i40e_acq_set_test_mode {
2896 u8 mode;
2897 #define I40E_AQ_TEST_PARTIAL 0
2898 #define I40E_AQ_TEST_FULL 1
2899 #define I40E_AQ_TEST_NVM 2
2900 u8 reserved[3];
2901 u8 command;
2902 #define I40E_AQ_TEST_OPEN 0
2903 #define I40E_AQ_TEST_CLOSE 1
2904 #define I40E_AQ_TEST_INC 2
2905 u8 reserved2[3];
2906 __le32 address_high;
2907 __le32 address_low;
2908 };
2909
2910 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2911
2912 /* Debug Read Register command (0xFF03)
2913 * Debug Write Register command (0xFF04)
2914 */
2915 struct i40e_aqc_debug_reg_read_write {
2916 __le32 reserved;
2917 __le32 address;
2918 __le32 value_high;
2919 __le32 value_low;
2920 };
2921
2922 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2923
2924 /* Scatter/gather Reg Read (indirect 0xFF05)
2925 * Scatter/gather Reg Write (indirect 0xFF06)
2926 */
2927
2928 /* i40e_aq_desc is used for the command */
2929 struct i40e_aqc_debug_reg_sg_element_data {
2930 __le32 address;
2931 __le32 value;
2932 };
2933
2934 /* Debug Modify register (direct 0xFF07) */
2935 struct i40e_aqc_debug_modify_reg {
2936 __le32 address;
2937 __le32 value;
2938 __le32 clear_mask;
2939 __le32 set_mask;
2940 };
2941
2942 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2943
2944 /* dump internal data (0xFF08, indirect) */
2945
2946 #define I40E_AQ_CLUSTER_ID_AUX 0
2947 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2948 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2949 #define I40E_AQ_CLUSTER_ID_HMC 3
2950 #define I40E_AQ_CLUSTER_ID_MAC0 4
2951 #define I40E_AQ_CLUSTER_ID_MAC1 5
2952 #define I40E_AQ_CLUSTER_ID_MAC2 6
2953 #define I40E_AQ_CLUSTER_ID_MAC3 7
2954 #define I40E_AQ_CLUSTER_ID_DCB 8
2955 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2956 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2957 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2958
2959 struct i40e_aqc_debug_dump_internals {
2960 u8 cluster_id;
2961 u8 table_id;
2962 __le16 data_size;
2963 __le32 idx;
2964 __le32 address_high;
2965 __le32 address_low;
2966 };
2967
2968 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2969
2970 struct i40e_aqc_debug_modify_internals {
2971 u8 cluster_id;
2972 u8 cluster_specific_params[7];
2973 __le32 address_high;
2974 __le32 address_low;
2975 };
2976
2977 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2978
2979 #endif /* _I40E_ADMINQ_CMD_H_ */
Ceph