ceph/src/spdk/dpdk/drivers/net/ice/base/ice_nvm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2019
   3  */
   4
   5 #include "ice_common.h"
   6
   7
   8 /**
   9  * ice_aq_read_nvm
  10  * @hw: pointer to the HW struct
  11  * @module_typeid: module pointer location in words from the NVM beginning
  12  * @offset: byte offset from the module beginning
  13  * @length: length of the section to be read (in bytes from the offset)
  14  * @data: command buffer (size [bytes] = length)
  15  * @last_command: tells if this is the last command in a series
  16  * @cd: pointer to command details structure or NULL
  17  *
  18  * Read the NVM using the admin queue commands (0x0701)
  19  */
  20 static enum ice_status
  21 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
  22                 void *data, bool last_command, struct ice_sq_cd *cd)
  23 {
  24         struct ice_aq_desc desc;
  25         struct ice_aqc_nvm *cmd;
  26
  27         ice_debug(hw, ICE_DBG_TRACE, "ice_aq_read_nvm");
  28
  29         cmd = &desc.params.nvm;
  30
  31         /* In offset the highest byte must be zeroed. */
  32         if (offset & 0xFF000000)
  33                 return ICE_ERR_PARAM;
  34
  35         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
  36
  37         /* If this is the last command in a series, set the proper flag. */
  38         if (last_command)
  39                 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
  40         cmd->module_typeid = CPU_TO_LE16(module_typeid);
  41         cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
  42         cmd->offset_high = (offset >> 16) & 0xFF;
  43         cmd->length = CPU_TO_LE16(length);
  44
  45         return ice_aq_send_cmd(hw, &desc, data, length, cd);
  46 }
  47
  48 /**
  49  * ice_check_sr_access_params - verify params for Shadow RAM R/W operations.
  50  * @hw: pointer to the HW structure
  51  * @offset: offset in words from module start
  52  * @words: number of words to access
  53  */
  54 static enum ice_status
  55 ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words)
  56 {
  57         if ((offset + words) > hw->nvm.sr_words) {
  58                 ice_debug(hw, ICE_DBG_NVM,
  59                           "NVM error: offset beyond SR lmt.\n");
  60                 return ICE_ERR_PARAM;
  61         }
  62
  63         if (words > ICE_SR_SECTOR_SIZE_IN_WORDS) {
  64                 /* We can access only up to 4KB (one sector), in one AQ write */
  65                 ice_debug(hw, ICE_DBG_NVM,
  66                           "NVM error: tried to access %d words, limit is %d.\n",
  67                           words, ICE_SR_SECTOR_SIZE_IN_WORDS);
  68                 return ICE_ERR_PARAM;
  69         }
  70
  71         if (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) !=
  72             (offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) {
  73                 /* A single access cannot spread over two sectors */
  74                 ice_debug(hw, ICE_DBG_NVM,
  75                           "NVM error: cannot spread over two sectors.\n");
  76                 return ICE_ERR_PARAM;
  77         }
  78
  79         return ICE_SUCCESS;
  80 }
  81
  82 /**
  83  * ice_read_sr_aq - Read Shadow RAM.
  84  * @hw: pointer to the HW structure
  85  * @offset: offset in words from module start
  86  * @words: number of words to read
  87  * @data: buffer for words reads from Shadow RAM
  88  * @last_command: tells the AdminQ that this is the last command
  89  *
  90  * Reads 16-bit word buffers from the Shadow RAM using the admin command.
  91  */
  92 static enum ice_status
  93 ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,
  94                bool last_command)
  95 {
  96         enum ice_status status;
  97
  98         ice_debug(hw, ICE_DBG_TRACE, "ice_read_sr_aq");
  99
 100         status = ice_check_sr_access_params(hw, offset, words);
 101
 102         /* values in "offset" and "words" parameters are sized as words
 103          * (16 bits) but ice_aq_read_nvm expects these values in bytes.
 104          * So do this conversion while calling ice_aq_read_nvm.
 105          */
 106         if (!status)
 107                 status = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data,
 108                                          last_command, NULL);
 109
 110         return status;
 111 }
 112
 113 /**
 114  * ice_read_sr_word_aq - Reads Shadow RAM via AQ
 115  * @hw: pointer to the HW structure
 116  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 117  * @data: word read from the Shadow RAM
 118  *
 119  * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method.
 120  */
 121 static enum ice_status
 122 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
 123 {
 124         enum ice_status status;
 125
 126         ice_debug(hw, ICE_DBG_TRACE, "ice_read_sr_word_aq");
 127
 128         status = ice_read_sr_aq(hw, offset, 1, data, true);
 129         if (!status)
 130                 *data = LE16_TO_CPU(*(__le16 *)data);
 131
 132         return status;
 133 }
 134
 135
 136 /**
 137  * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
 138  * @hw: pointer to the HW structure
 139  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 140  * @words: (in) number of words to read; (out) number of words actually read
 141  * @data: words read from the Shadow RAM
 142  *
 143  * Reads 16 bit words (data buf) from the SR using the ice_read_sr_aq
 144  * method. Ownership of the NVM is taken before reading the buffer and later
 145  * released.
 146  */
 147 static enum ice_status
 148 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
 149 {
 150         enum ice_status status;
 151         bool last_cmd = false;
 152         u16 words_read = 0;
 153         u16 i = 0;
 154
 155         ice_debug(hw, ICE_DBG_TRACE, "ice_read_sr_buf_aq");
 156
 157         do {
 158                 u16 read_size, off_w;
 159
 160                 /* Calculate number of bytes we should read in this step.
 161                  * It's not allowed to read more than one page at a time or
 162                  * to cross page boundaries.
 163                  */
 164                 off_w = offset % ICE_SR_SECTOR_SIZE_IN_WORDS;
 165                 read_size = off_w ?
 166                         MIN_T(u16, *words,
 167                               (ICE_SR_SECTOR_SIZE_IN_WORDS - off_w)) :
 168                         MIN_T(u16, (*words - words_read),
 169                               ICE_SR_SECTOR_SIZE_IN_WORDS);
 170
 171                 /* Check if this is last command, if so set proper flag */
 172                 if ((words_read + read_size) >= *words)
 173                         last_cmd = true;
 174
 175                 status = ice_read_sr_aq(hw, offset, read_size,
 176                                         data + words_read, last_cmd);
 177                 if (status)
 178                         goto read_nvm_buf_aq_exit;
 179
 180                 /* Increment counter for words already read and move offset to
 181                  * new read location
 182                  */
 183                 words_read += read_size;
 184                 offset += read_size;
 185         } while (words_read < *words);
 186
 187         for (i = 0; i < *words; i++)
 188                 data[i] = LE16_TO_CPU(((__le16 *)data)[i]);
 189
 190 read_nvm_buf_aq_exit:
 191         *words = words_read;
 192         return status;
 193 }
 194
 195 /**
 196  * ice_acquire_nvm - Generic request for acquiring the NVM ownership
 197  * @hw: pointer to the HW structure
 198  * @access: NVM access type (read or write)
 199  *
 200  * This function will request NVM ownership.
 201  */
 202 static enum ice_status
 203 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
 204 {
 205         ice_debug(hw, ICE_DBG_TRACE, "ice_acquire_nvm");
 206
 207         if (hw->nvm.blank_nvm_mode)
 208                 return ICE_SUCCESS;
 209
 210         return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
 211 }
 212
 213 /**
 214  * ice_release_nvm - Generic request for releasing the NVM ownership
 215  * @hw: pointer to the HW structure
 216  *
 217  * This function will release NVM ownership.
 218  */
 219 static void ice_release_nvm(struct ice_hw *hw)
 220 {
 221         ice_debug(hw, ICE_DBG_TRACE, "ice_release_nvm");
 222
 223         if (hw->nvm.blank_nvm_mode)
 224                 return;
 225
 226         ice_release_res(hw, ICE_NVM_RES_ID);
 227 }
 228
 229 /**
 230  * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
 231  * @hw: pointer to the HW structure
 232  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 233  * @data: word read from the Shadow RAM
 234  *
 235  * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
 236  */
 237 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
 238 {
 239         enum ice_status status;
 240
 241         status = ice_acquire_nvm(hw, ICE_RES_READ);
 242         if (!status) {
 243                 status = ice_read_sr_word_aq(hw, offset, data);
 244                 ice_release_nvm(hw);
 245         }
 246
 247         return status;
 248 }
 249
 250 /**
 251  * ice_init_nvm - initializes NVM setting
 252  * @hw: pointer to the HW struct
 253  *
 254  * This function reads and populates NVM settings such as Shadow RAM size,
 255  * max_timeout, and blank_nvm_mode
 256  */
 257 enum ice_status ice_init_nvm(struct ice_hw *hw)
 258 {
 259         struct ice_nvm_info *nvm = &hw->nvm;
 260         u16 oem_hi, oem_lo, cfg_ptr;
 261         u16 eetrack_lo, eetrack_hi;
 262         enum ice_status status = ICE_SUCCESS;
 263         u32 fla, gens_stat;
 264         u8 sr_size;
 265
 266         ice_debug(hw, ICE_DBG_TRACE, "ice_init_nvm");
 267
 268         /* The SR size is stored regardless of the NVM programming mode
 269          * as the blank mode may be used in the factory line.
 270          */
 271         gens_stat = rd32(hw, GLNVM_GENS);
 272         sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
 273
 274         /* Switching to words (sr_size contains power of 2) */
 275         nvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
 276
 277         /* Check if we are in the normal or blank NVM programming mode */
 278         fla = rd32(hw, GLNVM_FLA);
 279         if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
 280                 nvm->blank_nvm_mode = false;
 281         } else { /* Blank programming mode */
 282                 nvm->blank_nvm_mode = true;
 283                 status = ICE_ERR_NVM_BLANK_MODE;
 284                 ice_debug(hw, ICE_DBG_NVM,
 285                           "NVM init error: unsupported blank mode.\n");
 286                 return status;
 287         }
 288
 289         status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &hw->nvm.ver);
 290         if (status) {
 291                 ice_debug(hw, ICE_DBG_INIT,
 292                           "Failed to read DEV starter version.\n");
 293                 return status;
 294         }
 295
 296         status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
 297         if (status) {
 298                 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK lo.\n");
 299                 return status;
 300         }
 301         status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
 302         if (status) {
 303                 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK hi.\n");
 304                 return status;
 305         }
 306
 307         hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
 308
 309         status = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);
 310         if (status) {
 311                 ice_debug(hw, ICE_DBG_INIT, "Failed to read BOOT_CONFIG_PTR.\n");
 312                 return status;
 313         }
 314
 315         status = ice_read_sr_word(hw, (cfg_ptr + ICE_NVM_OEM_VER_OFF), &oem_hi);
 316         if (status) {
 317                 ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER hi.\n");
 318                 return status;
 319         }
 320
 321         status = ice_read_sr_word(hw, (cfg_ptr + (ICE_NVM_OEM_VER_OFF + 1)),
 322                                   &oem_lo);
 323         if (status) {
 324                 ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER lo.\n");
 325                 return status;
 326         }
 327
 328         hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;
 329         return status;
 330 }
 331
 332
 333 /**
 334  * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
 335  * @hw: pointer to the HW structure
 336  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 337  * @words: (in) number of words to read; (out) number of words actually read
 338  * @data: words read from the Shadow RAM
 339  *
 340  * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
 341  * method. The buf read is preceded by the NVM ownership take
 342  * and followed by the release.
 343  */
 344 enum ice_status
 345 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
 346 {
 347         enum ice_status status;
 348
 349         status = ice_acquire_nvm(hw, ICE_RES_READ);
 350         if (!status) {
 351                 status = ice_read_sr_buf_aq(hw, offset, words, data);
 352                 ice_release_nvm(hw);
 353         }
 354
 355         return status;
 356 }
 357
 358
 359 /**
 360  * ice_nvm_validate_checksum
 361  * @hw: pointer to the HW struct
 362  *
 363  * Verify NVM PFA checksum validity (0x0706)
 364  */
 365 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
 366 {
 367         struct ice_aqc_nvm_checksum *cmd;
 368         struct ice_aq_desc desc;
 369         enum ice_status status;
 370
 371         status = ice_acquire_nvm(hw, ICE_RES_READ);
 372         if (status)
 373                 return status;
 374
 375         cmd = &desc.params.nvm_checksum;
 376
 377         ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
 378         cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
 379
 380         status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
 381         ice_release_nvm(hw);
 382
 383         if (!status)
 384                 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
 385                         status = ICE_ERR_NVM_CHECKSUM;
 386
 387         return status;
 388 }