compiler/rustc_codegen_llvm/src/asm.rs

   1 use crate::builder::Builder;
   2 use crate::common::Funclet;
   3 use crate::context::CodegenCx;
   4 use crate::llvm;
   5 use crate::llvm_util;
   6 use crate::type_::Type;
   7 use crate::type_of::LayoutLlvmExt;
   8 use crate::value::Value;
   9
  10 use rustc_ast::LlvmAsmDialect;
  11 use rustc_ast::{InlineAsmOptions, InlineAsmTemplatePiece};
  12 use rustc_codegen_ssa::mir::operand::OperandValue;
  13 use rustc_codegen_ssa::mir::place::PlaceRef;
  14 use rustc_codegen_ssa::traits::*;
  15 use rustc_data_structures::fx::FxHashMap;
  16 use rustc_hir as hir;
  17 use rustc_middle::ty::layout::TyAndLayout;
  18 use rustc_middle::{bug, span_bug, ty::Instance};
  19 use rustc_span::{Pos, Span, Symbol};
  20 use rustc_target::abi::*;
  21 use rustc_target::asm::*;
  22
  23 use libc::{c_char, c_uint};
  24 use tracing::debug;
  25
  26 impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
  27     fn codegen_llvm_inline_asm(
  28         &mut self,
  29         ia: &hir::LlvmInlineAsmInner,
  30         outputs: Vec<PlaceRef<'tcx, &'ll Value>>,
  31         mut inputs: Vec<&'ll Value>,
  32         span: Span,
  33     ) -> bool {
  34         let mut ext_constraints = vec![];
  35         let mut output_types = vec![];
  36
  37         // Prepare the output operands
  38         let mut indirect_outputs = vec![];
  39         for (i, (out, &place)) in ia.outputs.iter().zip(&outputs).enumerate() {
  40             if out.is_rw {
  41                 let operand = self.load_operand(place);
  42                 if let OperandValue::Immediate(_) = operand.val {
  43                     inputs.push(operand.immediate());
  44                 }
  45                 ext_constraints.push(i.to_string());
  46             }
  47             if out.is_indirect {
  48                 let operand = self.load_operand(place);
  49                 if let OperandValue::Immediate(_) = operand.val {
  50                     indirect_outputs.push(operand.immediate());
  51                 }
  52             } else {
  53                 output_types.push(place.layout.llvm_type(self.cx));
  54             }
  55         }
  56         if !indirect_outputs.is_empty() {
  57             indirect_outputs.extend_from_slice(&inputs);
  58             inputs = indirect_outputs;
  59         }
  60
  61         let clobbers = ia.clobbers.iter().map(|s| format!("~{{{}}}", &s));
  62
  63         // Default per-arch clobbers
  64         // Basically what clang does
  65         let arch_clobbers = match &self.sess().target.arch[..] {
  66             "x86" | "x86_64" => &["~{dirflag}", "~{fpsr}", "~{flags}"][..],
  67             "mips" | "mips64" => &["~{$1}"],
  68             _ => &[],
  69         };
  70
  71         let all_constraints = ia
  72             .outputs
  73             .iter()
  74             .map(|out| out.constraint.to_string())
  75             .chain(ia.inputs.iter().map(|s| s.to_string()))
  76             .chain(ext_constraints)
  77             .chain(clobbers)
  78             .chain(arch_clobbers.iter().map(|s| (*s).to_string()))
  79             .collect::<Vec<String>>()
  80             .join(",");
  81
  82         debug!("Asm Constraints: {}", &all_constraints);
  83
  84         // Depending on how many outputs we have, the return type is different
  85         let num_outputs = output_types.len();
  86         let output_type = match num_outputs {
  87             0 => self.type_void(),
  88             1 => output_types[0],
  89             _ => self.type_struct(&output_types, false),
  90         };
  91
  92         let asm = ia.asm.as_str();
  93         let r = inline_asm_call(
  94             self,
  95             &asm,
  96             &all_constraints,
  97             &inputs,
  98             output_type,
  99             ia.volatile,
 100             ia.alignstack,
 101             ia.dialect,
 102             &[span],
 103             false,
 104             None,
 105         );
 106         if r.is_none() {
 107             return false;
 108         }
 109         let r = r.unwrap();
 110
 111         // Again, based on how many outputs we have
 112         let outputs = ia.outputs.iter().zip(&outputs).filter(|&(o, _)| !o.is_indirect);
 113         for (i, (_, &place)) in outputs.enumerate() {
 114             let v = if num_outputs == 1 { r } else { self.extract_value(r, i as u64) };
 115             OperandValue::Immediate(v).store(self, place);
 116         }
 117
 118         true
 119     }
 120
 121     fn codegen_inline_asm(
 122         &mut self,
 123         template: &[InlineAsmTemplatePiece],
 124         operands: &[InlineAsmOperandRef<'tcx, Self>],
 125         options: InlineAsmOptions,
 126         line_spans: &[Span],
 127         instance: Instance<'_>,
 128         dest_catch_funclet: Option<(Self::BasicBlock, Self::BasicBlock, Option<&Self::Funclet>)>,
 129     ) {
 130         let asm_arch = self.tcx.sess.asm_arch.unwrap();
 131
 132         // Collect the types of output operands
 133         let mut constraints = vec![];
 134         let mut clobbers = vec![];
 135         let mut output_types = vec![];
 136         let mut op_idx = FxHashMap::default();
 137         let mut clobbered_x87 = false;
 138         for (idx, op) in operands.iter().enumerate() {
 139             match *op {
 140                 InlineAsmOperandRef::Out { reg, late, place } => {
 141                     let is_target_supported = |reg_class: InlineAsmRegClass| {
 142                         for &(_, feature) in reg_class.supported_types(asm_arch) {
 143                             if let Some(feature) = feature {
 144                                 let codegen_fn_attrs = self.tcx.codegen_fn_attrs(instance.def_id());
 145                                 let feature_name = Symbol::intern(feature);
 146                                 if self.tcx.sess.target_features.contains(&feature_name)
 147                                     || codegen_fn_attrs.target_features.contains(&feature_name)
 148                                 {
 149                                     return true;
 150                                 }
 151                             } else {
 152                                 // Register class is unconditionally supported
 153                                 return true;
 154                             }
 155                         }
 156                         false
 157                     };
 158
 159                     let mut layout = None;
 160                     let ty = if let Some(ref place) = place {
 161                         layout = Some(&place.layout);
 162                         llvm_fixup_output_type(self.cx, reg.reg_class(), &place.layout)
 163                     } else if matches!(
 164                         reg.reg_class(),
 165                         InlineAsmRegClass::X86(
 166                             X86InlineAsmRegClass::mmx_reg | X86InlineAsmRegClass::x87_reg
 167                         )
 168                     ) {
 169                         // Special handling for x87/mmx registers: we always
 170                         // clobber the whole set if one register is marked as
 171                         // clobbered. This is due to the way LLVM handles the
 172                         // FP stack in inline assembly.
 173                         if !clobbered_x87 {
 174                             clobbered_x87 = true;
 175                             clobbers.push("~{st}".to_string());
 176                             for i in 1..=7 {
 177                                 clobbers.push(format!("~{{st({})}}", i));
 178                             }
 179                         }
 180                         continue;
 181                     } else if !is_target_supported(reg.reg_class())
 182                         || reg.reg_class().is_clobber_only(asm_arch)
 183                     {
 184                         // We turn discarded outputs into clobber constraints
 185                         // if the target feature needed by the register class is
 186                         // disabled. This is necessary otherwise LLVM will try
 187                         // to actually allocate a register for the dummy output.
 188                         assert!(matches!(reg, InlineAsmRegOrRegClass::Reg(_)));
 189                         clobbers.push(format!("~{}", reg_to_llvm(reg, None)));
 190                         continue;
 191                     } else {
 192                         // If the output is discarded, we don't really care what
 193                         // type is used. We're just using this to tell LLVM to
 194                         // reserve the register.
 195                         dummy_output_type(self.cx, reg.reg_class())
 196                     };
 197                     output_types.push(ty);
 198                     op_idx.insert(idx, constraints.len());
 199                     let prefix = if late { "=" } else { "=&" };
 200                     constraints.push(format!("{}{}", prefix, reg_to_llvm(reg, layout)));
 201                 }
 202                 InlineAsmOperandRef::InOut { reg, late, in_value, out_place } => {
 203                     let layout = if let Some(ref out_place) = out_place {
 204                         &out_place.layout
 205                     } else {
 206                         // LLVM required tied operands to have the same type,
 207                         // so we just use the type of the input.
 208                         &in_value.layout
 209                     };
 210                     let ty = llvm_fixup_output_type(self.cx, reg.reg_class(), layout);
 211                     output_types.push(ty);
 212                     op_idx.insert(idx, constraints.len());
 213                     let prefix = if late { "=" } else { "=&" };
 214                     constraints.push(format!("{}{}", prefix, reg_to_llvm(reg, Some(layout))));
 215                 }
 216                 _ => {}
 217             }
 218         }
 219
 220         // Collect input operands
 221         let mut inputs = vec![];
 222         for (idx, op) in operands.iter().enumerate() {
 223             match *op {
 224                 InlineAsmOperandRef::In { reg, value } => {
 225                     let llval =
 226                         llvm_fixup_input(self, value.immediate(), reg.reg_class(), &value.layout);
 227                     inputs.push(llval);
 228                     op_idx.insert(idx, constraints.len());
 229                     constraints.push(reg_to_llvm(reg, Some(&value.layout)));
 230                 }
 231                 InlineAsmOperandRef::InOut { reg, late: _, in_value, out_place: _ } => {
 232                     let value = llvm_fixup_input(
 233                         self,
 234                         in_value.immediate(),
 235                         reg.reg_class(),
 236                         &in_value.layout,
 237                     );
 238                     inputs.push(value);
 239                     constraints.push(format!("{}", op_idx[&idx]));
 240                 }
 241                 InlineAsmOperandRef::SymFn { instance } => {
 242                     inputs.push(self.cx.get_fn(instance));
 243                     op_idx.insert(idx, constraints.len());
 244                     constraints.push("s".to_string());
 245                 }
 246                 InlineAsmOperandRef::SymStatic { def_id } => {
 247                     inputs.push(self.cx.get_static(def_id));
 248                     op_idx.insert(idx, constraints.len());
 249                     constraints.push("s".to_string());
 250                 }
 251                 _ => {}
 252             }
 253         }
 254
 255         // Build the template string
 256         let mut template_str = String::new();
 257         for piece in template {
 258             match *piece {
 259                 InlineAsmTemplatePiece::String(ref s) => {
 260                     if s.contains('$') {
 261                         for c in s.chars() {
 262                             if c == '$' {
 263                                 template_str.push_str("$$");
 264                             } else {
 265                                 template_str.push(c);
 266                             }
 267                         }
 268                     } else {
 269                         template_str.push_str(s)
 270                     }
 271                 }
 272                 InlineAsmTemplatePiece::Placeholder { operand_idx, modifier, span: _ } => {
 273                     match operands[operand_idx] {
 274                         InlineAsmOperandRef::In { reg, .. }
 275                         | InlineAsmOperandRef::Out { reg, .. }
 276                         | InlineAsmOperandRef::InOut { reg, .. } => {
 277                             let modifier = modifier_to_llvm(asm_arch, reg.reg_class(), modifier);
 278                             if let Some(modifier) = modifier {
 279                                 template_str.push_str(&format!(
 280                                     "${{{}:{}}}",
 281                                     op_idx[&operand_idx], modifier
 282                                 ));
 283                             } else {
 284                                 template_str.push_str(&format!("${{{}}}", op_idx[&operand_idx]));
 285                             }
 286                         }
 287                         InlineAsmOperandRef::Const { ref string } => {
 288                             // Const operands get injected directly into the template
 289                             template_str.push_str(string);
 290                         }
 291                         InlineAsmOperandRef::SymFn { .. }
 292                         | InlineAsmOperandRef::SymStatic { .. } => {
 293                             // Only emit the raw symbol name
 294                             template_str.push_str(&format!("${{{}:c}}", op_idx[&operand_idx]));
 295                         }
 296                     }
 297                 }
 298             }
 299         }
 300
 301         constraints.append(&mut clobbers);
 302         if !options.contains(InlineAsmOptions::PRESERVES_FLAGS) {
 303             match asm_arch {
 304                 InlineAsmArch::AArch64 | InlineAsmArch::Arm => {
 305                     constraints.push("~{cc}".to_string());
 306                 }
 307                 InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
 308                     constraints.extend_from_slice(&[
 309                         "~{dirflag}".to_string(),
 310                         "~{fpsr}".to_string(),
 311                         "~{flags}".to_string(),
 312                     ]);
 313                 }
 314                 InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
 315                     constraints.extend_from_slice(&[
 316                         "~{vtype}".to_string(),
 317                         "~{vl}".to_string(),
 318                         "~{vxsat}".to_string(),
 319                         "~{vxrm}".to_string(),
 320                     ]);
 321                 }
 322                 InlineAsmArch::Avr => {
 323                     constraints.push("~{sreg}".to_string());
 324                 }
 325                 InlineAsmArch::Nvptx64 => {}
 326                 InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {}
 327                 InlineAsmArch::Hexagon => {}
 328                 InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
 329                 InlineAsmArch::S390x => {}
 330                 InlineAsmArch::SpirV => {}
 331                 InlineAsmArch::Wasm32 | InlineAsmArch::Wasm64 => {}
 332                 InlineAsmArch::Bpf => {}
 333             }
 334         }
 335         if !options.contains(InlineAsmOptions::NOMEM) {
 336             // This is actually ignored by LLVM, but it's probably best to keep
 337             // it just in case. LLVM instead uses the ReadOnly/ReadNone
 338             // attributes on the call instruction to optimize.
 339             constraints.push("~{memory}".to_string());
 340         }
 341         let volatile = !options.contains(InlineAsmOptions::PURE);
 342         let alignstack = !options.contains(InlineAsmOptions::NOSTACK);
 343         let output_type = match &output_types[..] {
 344             [] => self.type_void(),
 345             [ty] => ty,
 346             tys => self.type_struct(tys, false),
 347         };
 348         let dialect = match asm_arch {
 349             InlineAsmArch::X86 | InlineAsmArch::X86_64
 350                 if !options.contains(InlineAsmOptions::ATT_SYNTAX) =>
 351             {
 352                 LlvmAsmDialect::Intel
 353             }
 354             _ => LlvmAsmDialect::Att,
 355         };
 356         let result = inline_asm_call(
 357             self,
 358             &template_str,
 359             &constraints.join(","),
 360             &inputs,
 361             output_type,
 362             volatile,
 363             alignstack,
 364             dialect,
 365             line_spans,
 366             options.contains(InlineAsmOptions::MAY_UNWIND),
 367             dest_catch_funclet,
 368         )
 369         .unwrap_or_else(|| span_bug!(line_spans[0], "LLVM asm constraint validation failed"));
 370
 371         if options.contains(InlineAsmOptions::PURE) {
 372             if options.contains(InlineAsmOptions::NOMEM) {
 373                 llvm::Attribute::ReadNone.apply_callsite(llvm::AttributePlace::Function, result);
 374             } else if options.contains(InlineAsmOptions::READONLY) {
 375                 llvm::Attribute::ReadOnly.apply_callsite(llvm::AttributePlace::Function, result);
 376             }
 377             llvm::Attribute::WillReturn.apply_callsite(llvm::AttributePlace::Function, result);
 378         } else if options.contains(InlineAsmOptions::NOMEM) {
 379             llvm::Attribute::InaccessibleMemOnly
 380                 .apply_callsite(llvm::AttributePlace::Function, result);
 381         } else {
 382             // LLVM doesn't have an attribute to represent ReadOnly + SideEffect
 383         }
 384
 385         // Write results to outputs
 386         for (idx, op) in operands.iter().enumerate() {
 387             if let InlineAsmOperandRef::Out { reg, place: Some(place), .. }
 388             | InlineAsmOperandRef::InOut { reg, out_place: Some(place), .. } = *op
 389             {
 390                 let value = if output_types.len() == 1 {
 391                     result
 392                 } else {
 393                     self.extract_value(result, op_idx[&idx] as u64)
 394                 };
 395                 let value = llvm_fixup_output(self, value, reg.reg_class(), &place.layout);
 396                 OperandValue::Immediate(value).store(self, place);
 397             }
 398         }
 399     }
 400 }
 401
 402 impl AsmMethods for CodegenCx<'_, '_> {
 403     fn codegen_global_asm(
 404         &self,
 405         template: &[InlineAsmTemplatePiece],
 406         operands: &[GlobalAsmOperandRef],
 407         options: InlineAsmOptions,
 408         _line_spans: &[Span],
 409     ) {
 410         let asm_arch = self.tcx.sess.asm_arch.unwrap();
 411
 412         // Default to Intel syntax on x86
 413         let intel_syntax = matches!(asm_arch, InlineAsmArch::X86 | InlineAsmArch::X86_64)
 414             && !options.contains(InlineAsmOptions::ATT_SYNTAX);
 415
 416         // Build the template string
 417         let mut template_str = String::new();
 418         if intel_syntax {
 419             template_str.push_str(".intel_syntax\n");
 420         }
 421         for piece in template {
 422             match *piece {
 423                 InlineAsmTemplatePiece::String(ref s) => template_str.push_str(s),
 424                 InlineAsmTemplatePiece::Placeholder { operand_idx, modifier: _, span: _ } => {
 425                     match operands[operand_idx] {
 426                         GlobalAsmOperandRef::Const { ref string } => {
 427                             // Const operands get injected directly into the
 428                             // template. Note that we don't need to escape $
 429                             // here unlike normal inline assembly.
 430                             template_str.push_str(string);
 431                         }
 432                     }
 433                 }
 434             }
 435         }
 436         if intel_syntax {
 437             template_str.push_str("\n.att_syntax\n");
 438         }
 439
 440         unsafe {
 441             llvm::LLVMRustAppendModuleInlineAsm(
 442                 self.llmod,
 443                 template_str.as_ptr().cast(),
 444                 template_str.len(),
 445             );
 446         }
 447     }
 448 }
 449
 450 pub(crate) fn inline_asm_call<'ll>(
 451     bx: &mut Builder<'_, 'll, '_>,
 452     asm: &str,
 453     cons: &str,
 454     inputs: &[&'ll Value],
 455     output: &'ll llvm::Type,
 456     volatile: bool,
 457     alignstack: bool,
 458     dia: LlvmAsmDialect,
 459     line_spans: &[Span],
 460     unwind: bool,
 461     dest_catch_funclet: Option<(
 462         &'ll llvm::BasicBlock,
 463         &'ll llvm::BasicBlock,
 464         Option<&Funclet<'ll>>,
 465     )>,
 466 ) -> Option<&'ll Value> {
 467     let volatile = if volatile { llvm::True } else { llvm::False };
 468     let alignstack = if alignstack { llvm::True } else { llvm::False };
 469     let can_throw = if unwind { llvm::True } else { llvm::False };
 470
 471     let argtys = inputs
 472         .iter()
 473         .map(|v| {
 474             debug!("Asm Input Type: {:?}", *v);
 475             bx.cx.val_ty(*v)
 476         })
 477         .collect::<Vec<_>>();
 478
 479     debug!("Asm Output Type: {:?}", output);
 480     let fty = bx.cx.type_func(&argtys, output);
 481     unsafe {
 482         // Ask LLVM to verify that the constraints are well-formed.
 483         let constraints_ok = llvm::LLVMRustInlineAsmVerify(fty, cons.as_ptr().cast(), cons.len());
 484         debug!("constraint verification result: {:?}", constraints_ok);
 485         if constraints_ok {
 486             if unwind && llvm_util::get_version() < (13, 0, 0) {
 487                 bx.cx.sess().span_fatal(
 488                     line_spans[0],
 489                     "unwinding from inline assembly is only supported on llvm >= 13.",
 490                 );
 491             }
 492
 493             let v = llvm::LLVMRustInlineAsm(
 494                 fty,
 495                 asm.as_ptr().cast(),
 496                 asm.len(),
 497                 cons.as_ptr().cast(),
 498                 cons.len(),
 499                 volatile,
 500                 alignstack,
 501                 llvm::AsmDialect::from_generic(dia),
 502                 can_throw,
 503             );
 504
 505             let call = if let Some((dest, catch, funclet)) = dest_catch_funclet {
 506                 bx.invoke(fty, v, inputs, dest, catch, funclet)
 507             } else {
 508                 bx.call(fty, v, inputs, None)
 509             };
 510
 511             // Store mark in a metadata node so we can map LLVM errors
 512             // back to source locations.  See #17552.
 513             let key = "srcloc";
 514             let kind = llvm::LLVMGetMDKindIDInContext(
 515                 bx.llcx,
 516                 key.as_ptr() as *const c_char,
 517                 key.len() as c_uint,
 518             );
 519
 520             // srcloc contains one integer for each line of assembly code.
 521             // Unfortunately this isn't enough to encode a full span so instead
 522             // we just encode the start position of each line.
 523             // FIXME: Figure out a way to pass the entire line spans.
 524             let mut srcloc = vec![];
 525             if dia == LlvmAsmDialect::Intel && line_spans.len() > 1 {
 526                 // LLVM inserts an extra line to add the ".intel_syntax", so add
 527                 // a dummy srcloc entry for it.
 528                 //
 529                 // Don't do this if we only have 1 line span since that may be
 530                 // due to the asm template string coming from a macro. LLVM will
 531                 // default to the first srcloc for lines that don't have an
 532                 // associated srcloc.
 533                 srcloc.push(bx.const_i32(0));
 534             }
 535             srcloc.extend(line_spans.iter().map(|span| bx.const_i32(span.lo().to_u32() as i32)));
 536             let md = llvm::LLVMMDNodeInContext(bx.llcx, srcloc.as_ptr(), srcloc.len() as u32);
 537             llvm::LLVMSetMetadata(call, kind, md);
 538
 539             Some(call)
 540         } else {
 541             // LLVM has detected an issue with our constraints, bail out
 542             None
 543         }
 544     }
 545 }
 546
 547 /// If the register is an xmm/ymm/zmm register then return its index.
 548 fn xmm_reg_index(reg: InlineAsmReg) -> Option<u32> {
 549     match reg {
 550         InlineAsmReg::X86(reg)
 551             if reg as u32 >= X86InlineAsmReg::xmm0 as u32
 552                 && reg as u32 <= X86InlineAsmReg::xmm15 as u32 =>
 553         {
 554             Some(reg as u32 - X86InlineAsmReg::xmm0 as u32)
 555         }
 556         InlineAsmReg::X86(reg)
 557             if reg as u32 >= X86InlineAsmReg::ymm0 as u32
 558                 && reg as u32 <= X86InlineAsmReg::ymm15 as u32 =>
 559         {
 560             Some(reg as u32 - X86InlineAsmReg::ymm0 as u32)
 561         }
 562         InlineAsmReg::X86(reg)
 563             if reg as u32 >= X86InlineAsmReg::zmm0 as u32
 564                 && reg as u32 <= X86InlineAsmReg::zmm31 as u32 =>
 565         {
 566             Some(reg as u32 - X86InlineAsmReg::zmm0 as u32)
 567         }
 568         _ => None,
 569     }
 570 }
 571
 572 /// If the register is an AArch64 vector register then return its index.
 573 fn a64_vreg_index(reg: InlineAsmReg) -> Option<u32> {
 574     match reg {
 575         InlineAsmReg::AArch64(reg)
 576             if reg as u32 >= AArch64InlineAsmReg::v0 as u32
 577                 && reg as u32 <= AArch64InlineAsmReg::v31 as u32 =>
 578         {
 579             Some(reg as u32 - AArch64InlineAsmReg::v0 as u32)
 580         }
 581         _ => None,
 582     }
 583 }
 584
 585 /// Converts a register class to an LLVM constraint code.
 586 fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) -> String {
 587     match reg {
 588         // For vector registers LLVM wants the register name to match the type size.
 589         InlineAsmRegOrRegClass::Reg(reg) => {
 590             if let Some(idx) = xmm_reg_index(reg) {
 591                 let class = if let Some(layout) = layout {
 592                     match layout.size.bytes() {
 593                         64 => 'z',
 594                         32 => 'y',
 595                         _ => 'x',
 596                     }
 597                 } else {
 598                     // We use f32 as the type for discarded outputs
 599                     'x'
 600                 };
 601                 format!("{{{}mm{}}}", class, idx)
 602             } else if let Some(idx) = a64_vreg_index(reg) {
 603                 let class = if let Some(layout) = layout {
 604                     match layout.size.bytes() {
 605                         16 => 'q',
 606                         8 => 'd',
 607                         4 => 's',
 608                         2 => 'h',
 609                         1 => 'd', // We fixup i8 to i8x8
 610                         _ => unreachable!(),
 611                     }
 612                 } else {
 613                     // We use i64x2 as the type for discarded outputs
 614                     'q'
 615                 };
 616                 format!("{{{}{}}}", class, idx)
 617             } else if reg == InlineAsmReg::AArch64(AArch64InlineAsmReg::x30) {
 618                 // LLVM doesn't recognize x30
 619                 "{lr}".to_string()
 620             } else if reg == InlineAsmReg::Arm(ArmInlineAsmReg::r14) {
 621                 // LLVM doesn't recognize r14
 622                 "{lr}".to_string()
 623             } else {
 624                 format!("{{{}}}", reg.name())
 625             }
 626         }
 627         InlineAsmRegOrRegClass::RegClass(reg) => match reg {
 628             InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => "r",
 629             InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg) => "w",
 630             InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => "x",
 631             InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
 632                 unreachable!("clobber-only")
 633             }
 634             InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => "r",
 635             InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
 636             | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
 637             | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8) => "t",
 638             InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16)
 639             | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8)
 640             | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => "x",
 641             InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
 642             | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
 643             InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
 644             InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "r",
 645             InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
 646             InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
 647             InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
 648             InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
 649             InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => "r",
 650             InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => "b",
 651             InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => "f",
 652             InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)
 653             | InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => {
 654                 unreachable!("clobber-only")
 655             }
 656             InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r",
 657             InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => "f",
 658             InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => {
 659                 unreachable!("clobber-only")
 660             }
 661             InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) => "r",
 662             InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => "Q",
 663             InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => "q",
 664             InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
 665             | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x",
 666             InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v",
 667             InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk",
 668             InlineAsmRegClass::X86(
 669                 X86InlineAsmRegClass::x87_reg | X86InlineAsmRegClass::mmx_reg,
 670             ) => unreachable!("clobber-only"),
 671             InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => "r",
 672             InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r",
 673             InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w",
 674             InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => "r",
 675             InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper) => "d",
 676             InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair) => "r",
 677             InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw) => "w",
 678             InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => "e",
 679             InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => "r",
 680             InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => "f",
 681             InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
 682                 bug!("LLVM backend does not support SPIR-V")
 683             }
 684             InlineAsmRegClass::Err => unreachable!(),
 685         }
 686         .to_string(),
 687     }
 688 }
 689
 690 /// Converts a modifier into LLVM's equivalent modifier.
 691 fn modifier_to_llvm(
 692     arch: InlineAsmArch,
 693     reg: InlineAsmRegClass,
 694     modifier: Option<char>,
 695 ) -> Option<char> {
 696     match reg {
 697         InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => modifier,
 698         InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg)
 699         | InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
 700             if modifier == Some('v') { None } else { modifier }
 701         }
 702         InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
 703             unreachable!("clobber-only")
 704         }
 705         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => None,
 706         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
 707         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => None,
 708         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
 709         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
 710         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) => Some('P'),
 711         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg)
 712         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8)
 713         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
 714             if modifier.is_none() {
 715                 Some('q')
 716             } else {
 717                 modifier
 718             }
 719         }
 720         InlineAsmRegClass::Hexagon(_) => None,
 721         InlineAsmRegClass::Mips(_) => None,
 722         InlineAsmRegClass::Nvptx(_) => None,
 723         InlineAsmRegClass::PowerPC(_) => None,
 724         InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
 725         | InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
 726         InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => {
 727             unreachable!("clobber-only")
 728         }
 729         InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
 730         | InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => match modifier {
 731             None if arch == InlineAsmArch::X86_64 => Some('q'),
 732             None => Some('k'),
 733             Some('l') => Some('b'),
 734             Some('h') => Some('h'),
 735             Some('x') => Some('w'),
 736             Some('e') => Some('k'),
 737             Some('r') => Some('q'),
 738             _ => unreachable!(),
 739         },
 740         InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => None,
 741         InlineAsmRegClass::X86(reg @ X86InlineAsmRegClass::xmm_reg)
 742         | InlineAsmRegClass::X86(reg @ X86InlineAsmRegClass::ymm_reg)
 743         | InlineAsmRegClass::X86(reg @ X86InlineAsmRegClass::zmm_reg) => match (reg, modifier) {
 744             (X86InlineAsmRegClass::xmm_reg, None) => Some('x'),
 745             (X86InlineAsmRegClass::ymm_reg, None) => Some('t'),
 746             (X86InlineAsmRegClass::zmm_reg, None) => Some('g'),
 747             (_, Some('x')) => Some('x'),
 748             (_, Some('y')) => Some('t'),
 749             (_, Some('z')) => Some('g'),
 750             _ => unreachable!(),
 751         },
 752         InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None,
 753         InlineAsmRegClass::X86(X86InlineAsmRegClass::x87_reg | X86InlineAsmRegClass::mmx_reg) => {
 754             unreachable!("clobber-only")
 755         }
 756         InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => None,
 757         InlineAsmRegClass::Bpf(_) => None,
 758         InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair)
 759         | InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw)
 760         | InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => match modifier {
 761             Some('h') => Some('B'),
 762             Some('l') => Some('A'),
 763             _ => None,
 764         },
 765         InlineAsmRegClass::Avr(_) => None,
 766         InlineAsmRegClass::S390x(_) => None,
 767         InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
 768             bug!("LLVM backend does not support SPIR-V")
 769         }
 770         InlineAsmRegClass::Err => unreachable!(),
 771     }
 772 }
 773
 774 /// Type to use for outputs that are discarded. It doesn't really matter what
 775 /// the type is, as long as it is valid for the constraint code.
 776 fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'ll Type {
 777     match reg {
 778         InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::reg) => cx.type_i32(),
 779         InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg)
 780         | InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
 781             cx.type_vector(cx.type_i64(), 2)
 782         }
 783         InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
 784             unreachable!("clobber-only")
 785         }
 786         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => cx.type_i32(),
 787         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
 788         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => cx.type_f32(),
 789         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
 790         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
 791         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low8) => cx.type_f64(),
 792         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg)
 793         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8)
 794         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
 795             cx.type_vector(cx.type_i64(), 2)
 796         }
 797         InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
 798         InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
 799         InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
 800         InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
 801         InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
 802         InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
 803         InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => cx.type_i32(),
 804         InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => cx.type_i32(),
 805         InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => cx.type_f64(),
 806         InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)
 807         | InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => {
 808             unreachable!("clobber-only")
 809         }
 810         InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),
 811         InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => cx.type_f32(),
 812         InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => {
 813             unreachable!("clobber-only")
 814         }
 815         InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
 816         | InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd) => cx.type_i32(),
 817         InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => cx.type_i8(),
 818         InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
 819         | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg)
 820         | InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(),
 821         InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(),
 822         InlineAsmRegClass::X86(X86InlineAsmRegClass::x87_reg | X86InlineAsmRegClass::mmx_reg) => {
 823             unreachable!("clobber-only")
 824         }
 825         InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => cx.type_i32(),
 826         InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => cx.type_i64(),
 827         InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => cx.type_i32(),
 828         InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => cx.type_i8(),
 829         InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper) => cx.type_i8(),
 830         InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair) => cx.type_i16(),
 831         InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw) => cx.type_i16(),
 832         InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => cx.type_i16(),
 833         InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => cx.type_i32(),
 834         InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => cx.type_f64(),
 835         InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
 836             bug!("LLVM backend does not support SPIR-V")
 837         }
 838         InlineAsmRegClass::Err => unreachable!(),
 839     }
 840 }
 841
 842 /// Helper function to get the LLVM type for a Scalar. Pointers are returned as
 843 /// the equivalent integer type.
 844 fn llvm_asm_scalar_type<'ll>(cx: &CodegenCx<'ll, '_>, scalar: Scalar) -> &'ll Type {
 845     match scalar.value {
 846         Primitive::Int(Integer::I8, _) => cx.type_i8(),
 847         Primitive::Int(Integer::I16, _) => cx.type_i16(),
 848         Primitive::Int(Integer::I32, _) => cx.type_i32(),
 849         Primitive::Int(Integer::I64, _) => cx.type_i64(),
 850         Primitive::F32 => cx.type_f32(),
 851         Primitive::F64 => cx.type_f64(),
 852         Primitive::Pointer => cx.type_isize(),
 853         _ => unreachable!(),
 854     }
 855 }
 856
 857 /// Fix up an input value to work around LLVM bugs.
 858 fn llvm_fixup_input<'ll, 'tcx>(
 859     bx: &mut Builder<'_, 'll, 'tcx>,
 860     mut value: &'ll Value,
 861     reg: InlineAsmRegClass,
 862     layout: &TyAndLayout<'tcx>,
 863 ) -> &'ll Value {
 864     match (reg, layout.abi) {
 865         (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
 866             if let Primitive::Int(Integer::I8, _) = s.value {
 867                 let vec_ty = bx.cx.type_vector(bx.cx.type_i8(), 8);
 868                 bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
 869             } else {
 870                 value
 871             }
 872         }
 873         (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
 874             let elem_ty = llvm_asm_scalar_type(bx.cx, s);
 875             let count = 16 / layout.size.bytes();
 876             let vec_ty = bx.cx.type_vector(elem_ty, count);
 877             if let Primitive::Pointer = s.value {
 878                 value = bx.ptrtoint(value, bx.cx.type_isize());
 879             }
 880             bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
 881         }
 882         (
 883             InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16),
 884             Abi::Vector { element, count },
 885         ) if layout.size.bytes() == 8 => {
 886             let elem_ty = llvm_asm_scalar_type(bx.cx, element);
 887             let vec_ty = bx.cx.type_vector(elem_ty, count);
 888             let indices: Vec<_> = (0..count * 2).map(|x| bx.const_i32(x as i32)).collect();
 889             bx.shuffle_vector(value, bx.const_undef(vec_ty), bx.const_vector(&indices))
 890         }
 891         (InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
 892             if s.value == Primitive::F64 =>
 893         {
 894             bx.bitcast(value, bx.cx.type_i64())
 895         }
 896         (
 897             InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
 898             Abi::Vector { .. },
 899         ) if layout.size.bytes() == 64 => bx.bitcast(value, bx.cx.type_vector(bx.cx.type_f64(), 8)),
 900         (
 901             InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
 902             Abi::Scalar(s),
 903         ) => {
 904             if let Primitive::Int(Integer::I32, _) = s.value {
 905                 bx.bitcast(value, bx.cx.type_f32())
 906             } else {
 907                 value
 908             }
 909         }
 910         (
 911             InlineAsmRegClass::Arm(
 912                 ArmInlineAsmRegClass::dreg
 913                 | ArmInlineAsmRegClass::dreg_low8
 914                 | ArmInlineAsmRegClass::dreg_low16,
 915             ),
 916             Abi::Scalar(s),
 917         ) => {
 918             if let Primitive::Int(Integer::I64, _) = s.value {
 919                 bx.bitcast(value, bx.cx.type_f64())
 920             } else {
 921                 value
 922             }
 923         }
 924         (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
 925             // MIPS only supports register-length arithmetics.
 926             Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
 927             Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
 928             Primitive::F64 => bx.bitcast(value, bx.cx.type_i64()),
 929             _ => value,
 930         },
 931         _ => value,
 932     }
 933 }
 934
 935 /// Fix up an output value to work around LLVM bugs.
 936 fn llvm_fixup_output<'ll, 'tcx>(
 937     bx: &mut Builder<'_, 'll, 'tcx>,
 938     mut value: &'ll Value,
 939     reg: InlineAsmRegClass,
 940     layout: &TyAndLayout<'tcx>,
 941 ) -> &'ll Value {
 942     match (reg, layout.abi) {
 943         (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
 944             if let Primitive::Int(Integer::I8, _) = s.value {
 945                 bx.extract_element(value, bx.const_i32(0))
 946             } else {
 947                 value
 948             }
 949         }
 950         (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
 951             value = bx.extract_element(value, bx.const_i32(0));
 952             if let Primitive::Pointer = s.value {
 953                 value = bx.inttoptr(value, layout.llvm_type(bx.cx));
 954             }
 955             value
 956         }
 957         (
 958             InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16),
 959             Abi::Vector { element, count },
 960         ) if layout.size.bytes() == 8 => {
 961             let elem_ty = llvm_asm_scalar_type(bx.cx, element);
 962             let vec_ty = bx.cx.type_vector(elem_ty, count * 2);
 963             let indices: Vec<_> = (0..count).map(|x| bx.const_i32(x as i32)).collect();
 964             bx.shuffle_vector(value, bx.const_undef(vec_ty), bx.const_vector(&indices))
 965         }
 966         (InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
 967             if s.value == Primitive::F64 =>
 968         {
 969             bx.bitcast(value, bx.cx.type_f64())
 970         }
 971         (
 972             InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
 973             Abi::Vector { .. },
 974         ) if layout.size.bytes() == 64 => bx.bitcast(value, layout.llvm_type(bx.cx)),
 975         (
 976             InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
 977             Abi::Scalar(s),
 978         ) => {
 979             if let Primitive::Int(Integer::I32, _) = s.value {
 980                 bx.bitcast(value, bx.cx.type_i32())
 981             } else {
 982                 value
 983             }
 984         }
 985         (
 986             InlineAsmRegClass::Arm(
 987                 ArmInlineAsmRegClass::dreg
 988                 | ArmInlineAsmRegClass::dreg_low8
 989                 | ArmInlineAsmRegClass::dreg_low16,
 990             ),
 991             Abi::Scalar(s),
 992         ) => {
 993             if let Primitive::Int(Integer::I64, _) = s.value {
 994                 bx.bitcast(value, bx.cx.type_i64())
 995             } else {
 996                 value
 997             }
 998         }
 999         (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
1000             // MIPS only supports register-length arithmetics.
1001             Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
1002             Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
1003             Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
1004             Primitive::F64 => bx.bitcast(value, bx.cx.type_f64()),
1005             _ => value,
1006         },
1007         _ => value,
1008     }
1009 }
1010
1011 /// Output type to use for llvm_fixup_output.
1012 fn llvm_fixup_output_type<'ll, 'tcx>(
1013     cx: &CodegenCx<'ll, 'tcx>,
1014     reg: InlineAsmRegClass,
1015     layout: &TyAndLayout<'tcx>,
1016 ) -> &'ll Type {
1017     match (reg, layout.abi) {
1018         (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
1019             if let Primitive::Int(Integer::I8, _) = s.value {
1020                 cx.type_vector(cx.type_i8(), 8)
1021             } else {
1022                 layout.llvm_type(cx)
1023             }
1024         }
1025         (InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
1026             let elem_ty = llvm_asm_scalar_type(cx, s);
1027             let count = 16 / layout.size.bytes();
1028             cx.type_vector(elem_ty, count)
1029         }
1030         (
1031             InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16),
1032             Abi::Vector { element, count },
1033         ) if layout.size.bytes() == 8 => {
1034             let elem_ty = llvm_asm_scalar_type(cx, element);
1035             cx.type_vector(elem_ty, count * 2)
1036         }
1037         (InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
1038             if s.value == Primitive::F64 =>
1039         {
1040             cx.type_i64()
1041         }
1042         (
1043             InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
1044             Abi::Vector { .. },
1045         ) if layout.size.bytes() == 64 => cx.type_vector(cx.type_f64(), 8),
1046         (
1047             InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
1048             Abi::Scalar(s),
1049         ) => {
1050             if let Primitive::Int(Integer::I32, _) = s.value {
1051                 cx.type_f32()
1052             } else {
1053                 layout.llvm_type(cx)
1054             }
1055         }
1056         (
1057             InlineAsmRegClass::Arm(
1058                 ArmInlineAsmRegClass::dreg
1059                 | ArmInlineAsmRegClass::dreg_low8
1060                 | ArmInlineAsmRegClass::dreg_low16,
1061             ),
1062             Abi::Scalar(s),
1063         ) => {
1064             if let Primitive::Int(Integer::I64, _) = s.value {
1065                 cx.type_f64()
1066             } else {
1067                 layout.llvm_type(cx)
1068             }
1069         }
1070         (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
1071             // MIPS only supports register-length arithmetics.
1072             Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
1073             Primitive::F32 => cx.type_i32(),
1074             Primitive::F64 => cx.type_i64(),
1075             _ => layout.llvm_type(cx),
1076         },
1077         _ => layout.llvm_type(cx),
1078     }
1079 }