cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #ifdef TARGET_I386
  22 #include "exec-i386.h"
  23 #endif
  24 #ifdef TARGET_ARM
  25 #include "exec-arm.h"
  26 #endif
  27
  28 #include "disas.h"
  29
  30 //#define DEBUG_EXEC
  31 //#define DEBUG_SIGNAL
  32 /* enable it to have a fully working x86 emulator for ring 0 */
  33 //#define RING0_HACKS
  34
  35 #if defined(TARGET_ARM)
  36 /* XXX: unify with i386 target */
  37 void cpu_loop_exit(void)
  38 {
  39     longjmp(env->jmp_env, 1);
  40 }
  41 #endif
  42
  43 /* main execution loop */
  44
  45 int cpu_exec(CPUState *env1)
  46 {
  47     int saved_T0, saved_T1, saved_T2;
  48     CPUState *saved_env;
  49 #ifdef reg_EAX
  50     int saved_EAX;
  51 #endif
  52 #ifdef reg_ECX
  53     int saved_ECX;
  54 #endif
  55 #ifdef reg_EDX
  56     int saved_EDX;
  57 #endif
  58 #ifdef reg_EBX
  59     int saved_EBX;
  60 #endif
  61 #ifdef reg_ESP
  62     int saved_ESP;
  63 #endif
  64 #ifdef reg_EBP
  65     int saved_EBP;
  66 #endif
  67 #ifdef reg_ESI
  68     int saved_ESI;
  69 #endif
  70 #ifdef reg_EDI
  71     int saved_EDI;
  72 #endif
  73 #ifdef __sparc__
  74     int saved_i7, tmp_T0;
  75 #endif
  76     int code_gen_size, ret;
  77     void (*gen_func)(void);
  78     TranslationBlock *tb, **ptb;
  79     uint8_t *tc_ptr, *cs_base, *pc;
  80     unsigned int flags;
  81
  82     /* first we save global registers */
  83     saved_T0 = T0;
  84     saved_T1 = T1;
  85     saved_T2 = T2;
  86     saved_env = env;
  87     env = env1;
  88 #ifdef __sparc__
  89     /* we also save i7 because longjmp may not restore it */
  90     asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
  91 #endif
  92
  93 #if defined(TARGET_I386)
  94 #ifdef reg_EAX
  95     saved_EAX = EAX;
  96     EAX = env->regs[R_EAX];
  97 #endif
  98 #ifdef reg_ECX
  99     saved_ECX = ECX;
 100     ECX = env->regs[R_ECX];
 101 #endif
 102 #ifdef reg_EDX
 103     saved_EDX = EDX;
 104     EDX = env->regs[R_EDX];
 105 #endif
 106 #ifdef reg_EBX
 107     saved_EBX = EBX;
 108     EBX = env->regs[R_EBX];
 109 #endif
 110 #ifdef reg_ESP
 111     saved_ESP = ESP;
 112     ESP = env->regs[R_ESP];
 113 #endif
 114 #ifdef reg_EBP
 115     saved_EBP = EBP;
 116     EBP = env->regs[R_EBP];
 117 #endif
 118 #ifdef reg_ESI
 119     saved_ESI = ESI;
 120     ESI = env->regs[R_ESI];
 121 #endif
 122 #ifdef reg_EDI
 123     saved_EDI = EDI;
 124     EDI = env->regs[R_EDI];
 125 #endif
 126
 127     /* put eflags in CPU temporary format */
 128     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 129     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 130     CC_OP = CC_OP_EFLAGS;
 131     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 132 #elif defined(TARGET_ARM)
 133     {
 134         unsigned int psr;
 135         psr = env->cpsr;
 136         env->CF = (psr >> 29) & 1;
 137         env->NZF = (psr & 0xc0000000) ^ 0x40000000;
 138         env->VF = (psr << 3) & 0x80000000;
 139         env->cpsr = psr & ~0xf0000000;
 140     }
 141 #else
 142 #error unsupported target CPU
 143 #endif
 144     env->interrupt_request = 0;
 145     env->exception_index = -1;
 146
 147     /* prepare setjmp context for exception handling */
 148     for(;;) {
 149         if (setjmp(env->jmp_env) == 0) {
 150             /* if an exception is pending, we execute it here */
 151             if (env->exception_index >= 0) {
 152                 if (env->exception_index >= EXCP_INTERRUPT) {
 153                     /* exit request from the cpu execution loop */
 154                     ret = env->exception_index;
 155                     break;
 156                 } else if (env->user_mode_only) {
 157                     /* if user mode only, we simulate a fake exception
 158                        which will be hanlded outside the cpu execution
 159                        loop */
 160                     do_interrupt_user(env->exception_index,
 161                                       env->exception_is_int,
 162                                       env->error_code,
 163                                       env->exception_next_eip);
 164                     ret = env->exception_index;
 165                     break;
 166                 } else {
 167                     /* simulate a real cpu exception. On i386, it can
 168                        trigger new exceptions, but we do not handle
 169                        double or triple faults yet. */
 170                     do_interrupt(env->exception_index,
 171                                  env->exception_is_int,
 172                                  env->error_code,
 173                                  env->exception_next_eip);
 174                 }
 175                 env->exception_index = -1;
 176             }
 177 #if defined(TARGET_I386)
 178             /* if hardware interrupt pending, we execute it */
 179             if (env->hard_interrupt_request &&
 180                 (env->eflags & IF_MASK)) {
 181                 int intno;
 182                 intno = cpu_x86_get_pic_interrupt(env);
 183                 if (loglevel) {
 184                     fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
 185                 }
 186                 do_interrupt(intno, 0, 0, 0);
 187                 env->hard_interrupt_request = 0;
 188             }
 189 #endif
 190             T0 = 0; /* force lookup of first TB */
 191             for(;;) {
 192 #ifdef __sparc__
 193                 /* g1 can be modified by some libc? functions */
 194                 tmp_T0 = T0;
 195 #endif
 196                 if (env->interrupt_request) {
 197                     env->exception_index = EXCP_INTERRUPT;
 198                     cpu_loop_exit();
 199                 }
 200 #ifdef DEBUG_EXEC
 201                 if (loglevel) {
 202 #if defined(TARGET_I386)
 203                     /* restore flags in standard format */
 204                     env->regs[R_EAX] = EAX;
 205                     env->regs[R_EBX] = EBX;
 206                     env->regs[R_ECX] = ECX;
 207                     env->regs[R_EDX] = EDX;
 208                     env->regs[R_ESI] = ESI;
 209                     env->regs[R_EDI] = EDI;
 210                     env->regs[R_EBP] = EBP;
 211                     env->regs[R_ESP] = ESP;
 212                     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 213                     cpu_x86_dump_state(env, logfile, 0);
 214                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 215 #elif defined(TARGET_ARM)
 216                     cpu_arm_dump_state(env, logfile, 0);
 217 #else
 218 #error unsupported target CPU
 219 #endif
 220                 }
 221 #endif
 222                 /* we compute the CPU state. We assume it will not
 223                    change during the whole generated block. */
 224 #if defined(TARGET_I386)
 225                 flags = (env->segs[R_CS].flags & DESC_B_MASK)
 226                     >> (DESC_B_SHIFT - GEN_FLAG_CODE32_SHIFT);
 227                 flags |= (env->segs[R_SS].flags & DESC_B_MASK)
 228                     >> (DESC_B_SHIFT - GEN_FLAG_SS32_SHIFT);
 229                 flags |= (((unsigned long)env->segs[R_DS].base |
 230                            (unsigned long)env->segs[R_ES].base |
 231                            (unsigned long)env->segs[R_SS].base) != 0) <<
 232                     GEN_FLAG_ADDSEG_SHIFT;
 233                 if (!(env->eflags & VM_MASK)) {
 234                     flags |= (env->segs[R_CS].selector & 3) << GEN_FLAG_CPL_SHIFT;
 235                 } else {
 236                     /* NOTE: a dummy CPL is kept */
 237                     flags |= (1 << GEN_FLAG_VM_SHIFT);
 238                     flags |= (3 << GEN_FLAG_CPL_SHIFT);
 239                 }
 240                 flags |= (env->eflags & (IOPL_MASK | TF_MASK));
 241                 cs_base = env->segs[R_CS].base;
 242                 pc = cs_base + env->eip;
 243 #elif defined(TARGET_ARM)
 244                 flags = 0;
 245                 cs_base = 0;
 246                 pc = (uint8_t *)env->regs[15];
 247 #else
 248 #error unsupported CPU
 249 #endif
 250                 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
 251                              flags);
 252                 if (!tb) {
 253                     spin_lock(&tb_lock);
 254                     /* if no translated code available, then translate it now */
 255                     tb = tb_alloc((unsigned long)pc);
 256                     if (!tb) {
 257                         /* flush must be done */
 258                         tb_flush();
 259                         /* cannot fail at this point */
 260                         tb = tb_alloc((unsigned long)pc);
 261                         /* don't forget to invalidate previous TB info */
 262                         ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
 263                         T0 = 0;
 264                     }
 265                     tc_ptr = code_gen_ptr;
 266                     tb->tc_ptr = tc_ptr;
 267                     tb->cs_base = (unsigned long)cs_base;
 268                     tb->flags = flags;
 269                     ret = cpu_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
 270 #if defined(TARGET_I386)
 271                     /* XXX: suppress that, this is incorrect */
 272                     /* if invalid instruction, signal it */
 273                     if (ret != 0) {
 274                         /* NOTE: the tb is allocated but not linked, so we
 275                            can leave it */
 276                         spin_unlock(&tb_lock);
 277                         raise_exception(EXCP06_ILLOP);
 278                     }
 279 #endif
 280                     *ptb = tb;
 281                     tb->hash_next = NULL;
 282                     tb_link(tb);
 283                     code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
 284                     spin_unlock(&tb_lock);
 285                 }
 286 #ifdef DEBUG_EXEC
 287                 if (loglevel) {
 288                     fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
 289                             (long)tb->tc_ptr, (long)tb->pc,
 290                             lookup_symbol((void *)tb->pc));
 291                 }
 292 #endif
 293 #ifdef __sparc__
 294                 T0 = tmp_T0;
 295 #endif
 296                 /* see if we can patch the calling TB. XXX: remove TF test */
 297 #ifndef RING0_HACKS
 298
 299                 if (T0 != 0
 300 #if defined(TARGET_I386)
 301                     && !(env->eflags & TF_MASK)
 302 #endif
 303                     ) {
 304                     spin_lock(&tb_lock);
 305                     tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
 306                     spin_unlock(&tb_lock);
 307                 }
 308 #endif
 309                 tc_ptr = tb->tc_ptr;
 310
 311                 /* execute the generated code */
 312                 gen_func = (void *)tc_ptr;
 313 #if defined(__sparc__)
 314                 __asm__ __volatile__("call      %0\n\t"
 315                                      "mov       %%o7,%%i0"
 316                                      : /* no outputs */
 317                                      : "r" (gen_func)
 318                                      : "i0", "i1", "i2", "i3", "i4", "i5");
 319 #elif defined(__arm__)
 320                 asm volatile ("mov pc, %0\n\t"
 321                               ".global exec_loop\n\t"
 322                               "exec_loop:\n\t"
 323                               : /* no outputs */
 324                               : "r" (gen_func)
 325                               : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
 326 #else
 327                 gen_func();
 328 #endif
 329             }
 330         } else {
 331         }
 332     } /* for(;;) */
 333
 334
 335 #if defined(TARGET_I386)
 336     /* restore flags in standard format */
 337     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 338
 339     /* restore global registers */
 340 #ifdef reg_EAX
 341     EAX = saved_EAX;
 342 #endif
 343 #ifdef reg_ECX
 344     ECX = saved_ECX;
 345 #endif
 346 #ifdef reg_EDX
 347     EDX = saved_EDX;
 348 #endif
 349 #ifdef reg_EBX
 350     EBX = saved_EBX;
 351 #endif
 352 #ifdef reg_ESP
 353     ESP = saved_ESP;
 354 #endif
 355 #ifdef reg_EBP
 356     EBP = saved_EBP;
 357 #endif
 358 #ifdef reg_ESI
 359     ESI = saved_ESI;
 360 #endif
 361 #ifdef reg_EDI
 362     EDI = saved_EDI;
 363 #endif
 364 #elif defined(TARGET_ARM)
 365     {
 366         int ZF;
 367         ZF = (env->NZF == 0);
 368         env->cpsr = env->cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
 369             (env->CF << 29) | ((env->VF & 0x80000000) >> 3);
 370     }
 371 #else
 372 #error unsupported target CPU
 373 #endif
 374 #ifdef __sparc__
 375     asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
 376 #endif
 377     T0 = saved_T0;
 378     T1 = saved_T1;
 379     T2 = saved_T2;
 380     env = saved_env;
 381     return ret;
 382 }
 383
 384 void cpu_interrupt(CPUState *s)
 385 {
 386     s->interrupt_request = 1;
 387 }
 388
 389
 390 #if defined(TARGET_I386)
 391
 392 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
 393 {
 394     CPUX86State *saved_env;
 395
 396     saved_env = env;
 397     env = s;
 398     if (env->eflags & VM_MASK) {
 399         SegmentCache *sc;
 400         selector &= 0xffff;
 401         sc = &env->segs[seg_reg];
 402         /* NOTE: in VM86 mode, limit and flags are never reloaded,
 403            so we must load them here */
 404         sc->base = (void *)(selector << 4);
 405         sc->limit = 0xffff;
 406         sc->flags = 0;
 407         sc->selector = selector;
 408     } else {
 409         load_seg(seg_reg, selector, 0);
 410     }
 411     env = saved_env;
 412 }
 413
 414 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
 415 {
 416     CPUX86State *saved_env;
 417
 418     saved_env = env;
 419     env = s;
 420
 421     helper_fsave(ptr, data32);
 422
 423     env = saved_env;
 424 }
 425
 426 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
 427 {
 428     CPUX86State *saved_env;
 429
 430     saved_env = env;
 431     env = s;
 432
 433     helper_frstor(ptr, data32);
 434
 435     env = saved_env;
 436 }
 437
 438 #endif /* TARGET_I386 */
 439
 440 #undef EAX
 441 #undef ECX
 442 #undef EDX
 443 #undef EBX
 444 #undef ESP
 445 #undef EBP
 446 #undef ESI
 447 #undef EDI
 448 #undef EIP
 449 #include <signal.h>
 450 #include <sys/ucontext.h>
 451
 452 #if defined(TARGET_I386)
 453
 454 /* 'pc' is the host PC at which the exception was raised. 'address' is
 455    the effective address of the memory exception. 'is_write' is 1 if a
 456    write caused the exception and otherwise 0'. 'old_set' is the
 457    signal set which should be restored */
 458 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 459                                     int is_write, sigset_t *old_set)
 460 {
 461     TranslationBlock *tb;
 462     int ret;
 463
 464 #ifdef RING0_HACKS
 465     env = global_env; /* XXX: find a better solution */
 466 #endif
 467 #if defined(DEBUG_SIGNAL)
 468     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 469            pc, address, is_write, *(unsigned long *)old_set);
 470 #endif
 471     /* XXX: locking issue */
 472     if (is_write && page_unprotect(address)) {
 473         return 1;
 474     }
 475     /* see if it is an MMU fault */
 476     ret = cpu_x86_handle_mmu_fault(env, address, is_write);
 477     if (ret < 0)
 478         return 0; /* not an MMU fault */
 479     if (ret == 0)
 480         return 1; /* the MMU fault was handled without causing real CPU fault */
 481     /* now we have a real cpu fault */
 482     tb = tb_find_pc(pc);
 483     if (tb) {
 484         /* the PC is inside the translated code. It means that we have
 485            a virtual CPU fault */
 486         cpu_restore_state(tb, env, pc);
 487     }
 488 #if 0
 489     printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
 490            env->eip, env->cr[2], env->error_code);
 491 #endif
 492     /* we restore the process signal mask as the sigreturn should
 493        do it (XXX: use sigsetjmp) */
 494     sigprocmask(SIG_SETMASK, old_set, NULL);
 495     raise_exception_err(EXCP0E_PAGE, env->error_code);
 496     /* never comes here */
 497     return 1;
 498 }
 499
 500 #elif defined(TARGET_ARM)
 501 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 502                                     int is_write, sigset_t *old_set)
 503 {
 504     /* XXX: do more */
 505     return 0;
 506 }
 507 #else
 508 #error unsupported target CPU
 509 #endif
 510
 511 #if defined(__i386__)
 512
 513 int cpu_signal_handler(int host_signum, struct siginfo *info,
 514                        void *puc)
 515 {
 516     struct ucontext *uc = puc;
 517     unsigned long pc;
 518
 519 #ifndef REG_EIP
 520 /* for glibc 2.1 */
 521 #define REG_EIP    EIP
 522 #define REG_ERR    ERR
 523 #define REG_TRAPNO TRAPNO
 524 #endif
 525     pc = uc->uc_mcontext.gregs[REG_EIP];
 526     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 527                              uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
 528                              (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
 529                              &uc->uc_sigmask);
 530 }
 531
 532 #elif defined(__powerpc)
 533
 534 int cpu_signal_handler(int host_signum, struct siginfo *info,
 535                        void *puc)
 536 {
 537     struct ucontext *uc = puc;
 538     struct pt_regs *regs = uc->uc_mcontext.regs;
 539     unsigned long pc;
 540     int is_write;
 541
 542     pc = regs->nip;
 543     is_write = 0;
 544 #if 0
 545     /* ppc 4xx case */
 546     if (regs->dsisr & 0x00800000)
 547         is_write = 1;
 548 #else
 549     if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
 550         is_write = 1;
 551 #endif
 552     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 553                              is_write, &uc->uc_sigmask);
 554 }
 555
 556 #elif defined(__alpha__)
 557
 558 int cpu_signal_handler(int host_signum, struct siginfo *info,
 559                            void *puc)
 560 {
 561     struct ucontext *uc = puc;
 562     uint32_t *pc = uc->uc_mcontext.sc_pc;
 563     uint32_t insn = *pc;
 564     int is_write = 0;
 565
 566     /* XXX: need kernel patch to get write flag faster */
 567     switch (insn >> 26) {
 568     case 0x0d: // stw
 569     case 0x0e: // stb
 570     case 0x0f: // stq_u
 571     case 0x24: // stf
 572     case 0x25: // stg
 573     case 0x26: // sts
 574     case 0x27: // stt
 575     case 0x2c: // stl
 576     case 0x2d: // stq
 577     case 0x2e: // stl_c
 578     case 0x2f: // stq_c
 579         is_write = 1;
 580     }
 581
 582     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 583                              is_write, &uc->uc_sigmask);
 584 }
 585 #elif defined(__sparc__)
 586
 587 int cpu_signal_handler(int host_signum, struct siginfo *info,
 588                        void *puc)
 589 {
 590     uint32_t *regs = (uint32_t *)(info + 1);
 591     void *sigmask = (regs + 20);
 592     unsigned long pc;
 593     int is_write;
 594     uint32_t insn;
 595
 596     /* XXX: is there a standard glibc define ? */
 597     pc = regs[1];
 598     /* XXX: need kernel patch to get write flag faster */
 599     is_write = 0;
 600     insn = *(uint32_t *)pc;
 601     if ((insn >> 30) == 3) {
 602       switch((insn >> 19) & 0x3f) {
 603       case 0x05: // stb
 604       case 0x06: // sth
 605       case 0x04: // st
 606       case 0x07: // std
 607       case 0x24: // stf
 608       case 0x27: // stdf
 609       case 0x25: // stfsr
 610         is_write = 1;
 611         break;
 612       }
 613     }
 614     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 615                              is_write, sigmask);
 616 }
 617
 618 #elif defined(__arm__)
 619
 620 int cpu_signal_handler(int host_signum, struct siginfo *info,
 621                        void *puc)
 622 {
 623     struct ucontext *uc = puc;
 624     unsigned long pc;
 625     int is_write;
 626
 627     pc = uc->uc_mcontext.gregs[R15];
 628     /* XXX: compute is_write */
 629     is_write = 0;
 630     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 631                              is_write,
 632                              &uc->uc_sigmask);
 633 }
 634
 635 #else
 636
 637 #error host CPU specific signal handler needed
 638
 639 #endif