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2 * i386 emulator main execution loop
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 //#define DEBUG_SIGNAL
27 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
28 /* XXX: unify with i386 target */
29 void cpu_loop_exit(void)
31 longjmp(env
->jmp_env
, 1);
35 /* main execution loop */
37 int cpu_exec(CPUState
*env1
)
39 int saved_T0
, saved_T1
, saved_T2
;
68 int code_gen_size
, ret
, interrupt_request
;
69 void (*gen_func
)(void);
70 TranslationBlock
*tb
, **ptb
;
71 uint8_t *tc_ptr
, *cs_base
, *pc
;
74 /* first we save global registers */
81 /* we also save i7 because longjmp may not restore it */
82 asm volatile ("mov %%i7, %0" : "=r" (saved_i7
));
85 #if defined(TARGET_I386)
88 EAX
= env
->regs
[R_EAX
];
92 ECX
= env
->regs
[R_ECX
];
96 EDX
= env
->regs
[R_EDX
];
100 EBX
= env
->regs
[R_EBX
];
104 ESP
= env
->regs
[R_ESP
];
108 EBP
= env
->regs
[R_EBP
];
112 ESI
= env
->regs
[R_ESI
];
116 EDI
= env
->regs
[R_EDI
];
119 /* put eflags in CPU temporary format */
120 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
121 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
122 CC_OP
= CC_OP_EFLAGS
;
123 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
124 #elif defined(TARGET_ARM)
128 env
->CF
= (psr
>> 29) & 1;
129 env
->NZF
= (psr
& 0xc0000000) ^ 0x40000000;
130 env
->VF
= (psr
<< 3) & 0x80000000;
131 env
->cpsr
= psr
& ~0xf0000000;
133 #elif defined(TARGET_SPARC)
135 #error unsupported target CPU
137 env
->exception_index
= -1;
139 /* prepare setjmp context for exception handling */
141 if (setjmp(env
->jmp_env
) == 0) {
142 /* if an exception is pending, we execute it here */
143 if (env
->exception_index
>= 0) {
144 if (env
->exception_index
>= EXCP_INTERRUPT
) {
145 /* exit request from the cpu execution loop */
146 ret
= env
->exception_index
;
148 } else if (env
->user_mode_only
) {
149 /* if user mode only, we simulate a fake exception
150 which will be hanlded outside the cpu execution
152 #if defined(TARGET_I386)
153 do_interrupt_user(env
->exception_index
,
154 env
->exception_is_int
,
156 env
->exception_next_eip
);
158 ret
= env
->exception_index
;
161 #if defined(TARGET_I386)
162 /* simulate a real cpu exception. On i386, it can
163 trigger new exceptions, but we do not handle
164 double or triple faults yet. */
165 do_interrupt(env
->exception_index
,
166 env
->exception_is_int
,
168 env
->exception_next_eip
, 0);
171 env
->exception_index
= -1;
173 T0
= 0; /* force lookup of first TB */
176 /* g1 can be modified by some libc? functions */
179 interrupt_request
= env
->interrupt_request
;
180 if (__builtin_expect(interrupt_request
, 0)) {
181 #if defined(TARGET_I386)
182 /* if hardware interrupt pending, we execute it */
183 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
184 (env
->eflags
& IF_MASK
) &&
185 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
187 intno
= cpu_x86_get_pic_interrupt(env
);
189 fprintf(logfile
, "Servicing hardware INT=0x%02x\n", intno
);
191 do_interrupt(intno
, 0, 0, 0, 1);
192 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
193 /* ensure that no TB jump will be modified as
194 the program flow was changed */
202 if (interrupt_request
& CPU_INTERRUPT_EXIT
) {
203 env
->interrupt_request
&= ~CPU_INTERRUPT_EXIT
;
204 env
->exception_index
= EXCP_INTERRUPT
;
210 #if defined(TARGET_I386)
211 /* restore flags in standard format */
212 env
->regs
[R_EAX
] = EAX
;
213 env
->regs
[R_EBX
] = EBX
;
214 env
->regs
[R_ECX
] = ECX
;
215 env
->regs
[R_EDX
] = EDX
;
216 env
->regs
[R_ESI
] = ESI
;
217 env
->regs
[R_EDI
] = EDI
;
218 env
->regs
[R_EBP
] = EBP
;
219 env
->regs
[R_ESP
] = ESP
;
220 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
221 cpu_x86_dump_state(env
, logfile
, X86_DUMP_CCOP
);
222 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
223 #elif defined(TARGET_ARM)
224 env
->cpsr
= compute_cpsr();
225 cpu_arm_dump_state(env
, logfile
, 0);
226 env
->cpsr
&= ~0xf0000000;
227 #elif defined(TARGET_SPARC)
228 cpu_sparc_dump_state (env
, logfile
, 0);
230 #error unsupported target CPU
234 /* we record a subset of the CPU state. It will
235 always be the same before a given translated block
237 #if defined(TARGET_I386)
239 flags
|= (env
->eflags
& (IOPL_MASK
| TF_MASK
| VM_MASK
));
240 cs_base
= env
->segs
[R_CS
].base
;
241 pc
= cs_base
+ env
->eip
;
242 #elif defined(TARGET_ARM)
245 pc
= (uint8_t *)env
->regs
[15];
246 #elif defined(TARGET_SPARC)
253 pc
= (uint8_t *) env
->pc
;
255 #error unsupported CPU
257 tb
= tb_find(&ptb
, (unsigned long)pc
, (unsigned long)cs_base
,
261 /* if no translated code available, then translate it now */
262 tb
= tb_alloc((unsigned long)pc
);
264 /* flush must be done */
266 /* cannot fail at this point */
267 tb
= tb_alloc((unsigned long)pc
);
268 /* don't forget to invalidate previous TB info */
269 ptb
= &tb_hash
[tb_hash_func((unsigned long)pc
)];
272 tc_ptr
= code_gen_ptr
;
274 tb
->cs_base
= (unsigned long)cs_base
;
276 /* XXX: an MMU exception can occur here */
277 cpu_gen_code(env
, tb
, CODE_GEN_MAX_SIZE
, &code_gen_size
);
279 tb
->hash_next
= NULL
;
281 code_gen_ptr
= (void *)(((unsigned long)code_gen_ptr
+ code_gen_size
+ CODE_GEN_ALIGN
- 1) & ~(CODE_GEN_ALIGN
- 1));
282 spin_unlock(&tb_lock
);
286 fprintf(logfile
, "Trace 0x%08lx [0x%08lx] %s\n",
287 (long)tb
->tc_ptr
, (long)tb
->pc
,
288 lookup_symbol((void *)tb
->pc
));
294 /* see if we can patch the calling TB. */
297 tb_add_jump((TranslationBlock
*)(T0
& ~3), T0
& 3, tb
);
298 spin_unlock(&tb_lock
);
301 env
->current_tb
= tb
;
302 /* execute the generated code */
303 gen_func
= (void *)tc_ptr
;
304 #if defined(__sparc__)
305 __asm__
__volatile__("call %0\n\t"
309 : "i0", "i1", "i2", "i3", "i4", "i5");
310 #elif defined(__arm__)
311 asm volatile ("mov pc, %0\n\t"
312 ".global exec_loop\n\t"
316 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
320 env
->current_tb
= NULL
;
321 /* reset soft MMU for next block (it can currently
322 only be set by a memory fault) */
323 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
324 if (env
->hflags
& HF_SOFTMMU_MASK
) {
325 env
->hflags
&= ~HF_SOFTMMU_MASK
;
326 /* do not allow linking to another block */
336 #if defined(TARGET_I386)
337 /* restore flags in standard format */
338 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
340 /* restore global registers */
365 #elif defined(TARGET_ARM)
366 env
->cpsr
= compute_cpsr();
367 #elif defined(TARGET_SPARC)
369 #error unsupported target CPU
372 asm volatile ("mov %0, %%i7" : : "r" (saved_i7
));
381 #if defined(TARGET_I386)
383 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
)
385 CPUX86State
*saved_env
;
389 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
391 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
392 (uint8_t *)(selector
<< 4), 0xffff, 0);
394 load_seg(seg_reg
, selector
, 0);
399 void cpu_x86_fsave(CPUX86State
*s
, uint8_t *ptr
, int data32
)
401 CPUX86State
*saved_env
;
406 helper_fsave(ptr
, data32
);
411 void cpu_x86_frstor(CPUX86State
*s
, uint8_t *ptr
, int data32
)
413 CPUX86State
*saved_env
;
418 helper_frstor(ptr
, data32
);
423 #endif /* TARGET_I386 */
435 #include <sys/ucontext.h>
437 #if defined(TARGET_I386)
439 /* 'pc' is the host PC at which the exception was raised. 'address' is
440 the effective address of the memory exception. 'is_write' is 1 if a
441 write caused the exception and otherwise 0'. 'old_set' is the
442 signal set which should be restored */
443 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
444 int is_write
, sigset_t
*old_set
)
446 TranslationBlock
*tb
;
450 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
451 #if defined(DEBUG_SIGNAL)
452 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
453 pc
, address
, is_write
, *(unsigned long *)old_set
);
455 /* XXX: locking issue */
456 if (is_write
&& page_unprotect(address
)) {
459 /* see if it is an MMU fault */
460 ret
= cpu_x86_handle_mmu_fault(env
, address
, is_write
,
461 ((env
->hflags
& HF_CPL_MASK
) == 3), 0);
463 return 0; /* not an MMU fault */
465 return 1; /* the MMU fault was handled without causing real CPU fault */
466 /* now we have a real cpu fault */
469 /* the PC is inside the translated code. It means that we have
470 a virtual CPU fault */
471 cpu_restore_state(tb
, env
, pc
);
475 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
476 env
->eip
, env
->cr
[2], env
->error_code
);
478 /* we restore the process signal mask as the sigreturn should
479 do it (XXX: use sigsetjmp) */
480 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
481 raise_exception_err(EXCP0E_PAGE
, env
->error_code
);
483 /* activate soft MMU for this block */
484 env
->hflags
|= HF_SOFTMMU_MASK
;
485 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
488 /* never comes here */
492 #elif defined(TARGET_ARM)
493 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
494 int is_write
, sigset_t
*old_set
)
499 #elif defined(TARGET_SPARC)
500 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
501 int is_write
, sigset_t
*old_set
)
506 #error unsupported target CPU
509 #if defined(__i386__)
511 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
514 struct ucontext
*uc
= puc
;
521 #define REG_TRAPNO TRAPNO
523 pc
= uc
->uc_mcontext
.gregs
[REG_EIP
];
524 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
525 uc
->uc_mcontext
.gregs
[REG_TRAPNO
] == 0xe ?
526 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
530 #elif defined(__powerpc)
532 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
535 struct ucontext
*uc
= puc
;
536 struct pt_regs
*regs
= uc
->uc_mcontext
.regs
;
544 if (regs
->dsisr
& 0x00800000)
547 if (regs
->trap
!= 0x400 && (regs
->dsisr
& 0x02000000))
550 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
551 is_write
, &uc
->uc_sigmask
);
554 #elif defined(__alpha__)
556 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
559 struct ucontext
*uc
= puc
;
560 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
564 /* XXX: need kernel patch to get write flag faster */
565 switch (insn
>> 26) {
580 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
581 is_write
, &uc
->uc_sigmask
);
583 #elif defined(__sparc__)
585 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
588 uint32_t *regs
= (uint32_t *)(info
+ 1);
589 void *sigmask
= (regs
+ 20);
594 /* XXX: is there a standard glibc define ? */
596 /* XXX: need kernel patch to get write flag faster */
598 insn
= *(uint32_t *)pc
;
599 if ((insn
>> 30) == 3) {
600 switch((insn
>> 19) & 0x3f) {
612 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
616 #elif defined(__arm__)
618 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
621 struct ucontext
*uc
= puc
;
625 pc
= uc
->uc_mcontext
.gregs
[R15
];
626 /* XXX: compute is_write */
628 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
633 #elif defined(__mc68000)
635 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
638 struct ucontext
*uc
= puc
;
642 pc
= uc
->uc_mcontext
.gregs
[16];
643 /* XXX: compute is_write */
645 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
652 #error host CPU specific signal handler needed