2 * Intel AGPGART routines.
5 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
13 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
17 #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
18 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
19 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
23 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
25 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
26 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
27 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
28 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
29 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
30 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
31 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
32 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
33 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
34 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
35 #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
36 #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
37 #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
38 #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
39 #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
40 #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
41 #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
42 #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
44 /* cover 915 and 945 variants */
45 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
46 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
47 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
48 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
49 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
50 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
52 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
53 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
54 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
55 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
56 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
57 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB || \
58 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB)
60 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
61 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
62 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
64 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
65 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB)
68 extern int agp_memory_reserved
;
71 /* Intel 815 register */
72 #define INTEL_815_APCONT 0x51
73 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
75 /* Intel i820 registers */
76 #define INTEL_I820_RDCR 0x51
77 #define INTEL_I820_ERRSTS 0xc8
79 /* Intel i840 registers */
80 #define INTEL_I840_MCHCFG 0x50
81 #define INTEL_I840_ERRSTS 0xc8
83 /* Intel i850 registers */
84 #define INTEL_I850_MCHCFG 0x50
85 #define INTEL_I850_ERRSTS 0xc8
87 /* intel 915G registers */
88 #define I915_GMADDR 0x18
89 #define I915_MMADDR 0x10
90 #define I915_PTEADDR 0x1C
91 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
92 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
93 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
94 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
95 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
96 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
97 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
98 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
100 #define I915_IFPADDR 0x60
102 /* Intel 965G registers */
103 #define I965_MSAC 0x62
104 #define I965_IFPADDR 0x70
106 /* Intel 7505 registers */
107 #define INTEL_I7505_APSIZE 0x74
108 #define INTEL_I7505_NCAPID 0x60
109 #define INTEL_I7505_NISTAT 0x6c
110 #define INTEL_I7505_ATTBASE 0x78
111 #define INTEL_I7505_ERRSTS 0x42
112 #define INTEL_I7505_AGPCTRL 0x70
113 #define INTEL_I7505_MCHCFG 0x50
115 static const struct aper_size_info_fixed intel_i810_sizes
[] =
118 /* The 32M mode still requires a 64k gatt */
122 #define AGP_DCACHE_MEMORY 1
123 #define AGP_PHYS_MEMORY 2
124 #define INTEL_AGP_CACHED_MEMORY 3
126 static struct gatt_mask intel_i810_masks
[] =
128 {.mask
= I810_PTE_VALID
, .type
= 0},
129 {.mask
= (I810_PTE_VALID
| I810_PTE_LOCAL
), .type
= AGP_DCACHE_MEMORY
},
130 {.mask
= I810_PTE_VALID
, .type
= 0},
131 {.mask
= I810_PTE_VALID
| I830_PTE_SYSTEM_CACHED
,
132 .type
= INTEL_AGP_CACHED_MEMORY
}
135 static struct _intel_private
{
136 struct pci_dev
*pcidev
; /* device one */
137 u8 __iomem
*registers
;
138 u32 __iomem
*gtt
; /* I915G */
139 int num_dcache_entries
;
140 /* gtt_entries is the number of gtt entries that are already mapped
141 * to stolen memory. Stolen memory is larger than the memory mapped
142 * through gtt_entries, as it includes some reserved space for the BIOS
143 * popup and for the GTT.
145 int gtt_entries
; /* i830+ */
147 void __iomem
*i9xx_flush_page
;
148 void *i8xx_flush_page
;
150 struct page
*i8xx_page
;
151 struct resource ifp_resource
;
155 static int intel_i810_fetch_size(void)
158 struct aper_size_info_fixed
*values
;
160 pci_read_config_dword(agp_bridge
->dev
, I810_SMRAM_MISCC
, &smram_miscc
);
161 values
= A_SIZE_FIX(agp_bridge
->driver
->aperture_sizes
);
163 if ((smram_miscc
& I810_GMS
) == I810_GMS_DISABLE
) {
164 dev_warn(&agp_bridge
->dev
->dev
, "i810 is disabled\n");
167 if ((smram_miscc
& I810_GFX_MEM_WIN_SIZE
) == I810_GFX_MEM_WIN_32M
) {
168 agp_bridge
->previous_size
=
169 agp_bridge
->current_size
= (void *) (values
+ 1);
170 agp_bridge
->aperture_size_idx
= 1;
171 return values
[1].size
;
173 agp_bridge
->previous_size
=
174 agp_bridge
->current_size
= (void *) (values
);
175 agp_bridge
->aperture_size_idx
= 0;
176 return values
[0].size
;
182 static int intel_i810_configure(void)
184 struct aper_size_info_fixed
*current_size
;
188 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
190 if (!intel_private
.registers
) {
191 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, &temp
);
194 intel_private
.registers
= ioremap(temp
, 128 * 4096);
195 if (!intel_private
.registers
) {
196 dev_err(&intel_private
.pcidev
->dev
,
197 "can't remap memory\n");
202 if ((readl(intel_private
.registers
+I810_DRAM_CTL
)
203 & I810_DRAM_ROW_0
) == I810_DRAM_ROW_0_SDRAM
) {
204 /* This will need to be dynamically assigned */
205 dev_info(&intel_private
.pcidev
->dev
,
206 "detected 4MB dedicated video ram\n");
207 intel_private
.num_dcache_entries
= 1024;
209 pci_read_config_dword(intel_private
.pcidev
, I810_GMADDR
, &temp
);
210 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
211 writel(agp_bridge
->gatt_bus_addr
| I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
212 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
214 if (agp_bridge
->driver
->needs_scratch_page
) {
215 for (i
= 0; i
< current_size
->num_entries
; i
++) {
216 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
217 readl(intel_private
.registers
+I810_PTE_BASE
+(i
*4)); /* PCI posting. */
220 global_cache_flush();
224 static void intel_i810_cleanup(void)
226 writel(0, intel_private
.registers
+I810_PGETBL_CTL
);
227 readl(intel_private
.registers
); /* PCI Posting. */
228 iounmap(intel_private
.registers
);
231 static void intel_i810_tlbflush(struct agp_memory
*mem
)
236 static void intel_i810_agp_enable(struct agp_bridge_data
*bridge
, u32 mode
)
241 /* Exists to support ARGB cursors */
242 static void *i8xx_alloc_pages(void)
246 page
= alloc_pages(GFP_KERNEL
| GFP_DMA32
, 2);
250 if (set_pages_uc(page
, 4) < 0) {
251 set_pages_wb(page
, 4);
252 __free_pages(page
, 2);
256 atomic_inc(&agp_bridge
->current_memory_agp
);
257 return page_address(page
);
260 static void i8xx_destroy_pages(void *addr
)
267 page
= virt_to_page(addr
);
268 set_pages_wb(page
, 4);
270 __free_pages(page
, 2);
271 atomic_dec(&agp_bridge
->current_memory_agp
);
274 static int intel_i830_type_to_mask_type(struct agp_bridge_data
*bridge
,
277 if (type
< AGP_USER_TYPES
)
279 else if (type
== AGP_USER_CACHED_MEMORY
)
280 return INTEL_AGP_CACHED_MEMORY
;
285 static int intel_i810_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
288 int i
, j
, num_entries
;
293 if (mem
->page_count
== 0)
296 temp
= agp_bridge
->current_size
;
297 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
299 if ((pg_start
+ mem
->page_count
) > num_entries
)
303 for (j
= pg_start
; j
< (pg_start
+ mem
->page_count
); j
++) {
304 if (!PGE_EMPTY(agp_bridge
, readl(agp_bridge
->gatt_table
+j
))) {
310 if (type
!= mem
->type
)
313 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
316 case AGP_DCACHE_MEMORY
:
317 if (!mem
->is_flushed
)
318 global_cache_flush();
319 for (i
= pg_start
; i
< (pg_start
+ mem
->page_count
); i
++) {
320 writel((i
*4096)|I810_PTE_LOCAL
|I810_PTE_VALID
,
321 intel_private
.registers
+I810_PTE_BASE
+(i
*4));
323 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
325 case AGP_PHYS_MEMORY
:
326 case AGP_NORMAL_MEMORY
:
327 if (!mem
->is_flushed
)
328 global_cache_flush();
329 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
330 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
333 intel_private
.registers
+I810_PTE_BASE
+(j
*4));
335 readl(intel_private
.registers
+I810_PTE_BASE
+((j
-1)*4));
341 agp_bridge
->driver
->tlb_flush(mem
);
345 mem
->is_flushed
= true;
349 static int intel_i810_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
354 if (mem
->page_count
== 0)
357 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++) {
358 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
360 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
362 agp_bridge
->driver
->tlb_flush(mem
);
367 * The i810/i830 requires a physical address to program its mouse
368 * pointer into hardware.
369 * However the Xserver still writes to it through the agp aperture.
371 static struct agp_memory
*alloc_agpphysmem_i8xx(size_t pg_count
, int type
)
373 struct agp_memory
*new;
377 case 1: addr
= agp_bridge
->driver
->agp_alloc_page(agp_bridge
);
380 /* kludge to get 4 physical pages for ARGB cursor */
381 addr
= i8xx_alloc_pages();
390 new = agp_create_memory(pg_count
);
394 new->memory
[0] = virt_to_gart(addr
);
396 /* kludge to get 4 physical pages for ARGB cursor */
397 new->memory
[1] = new->memory
[0] + PAGE_SIZE
;
398 new->memory
[2] = new->memory
[1] + PAGE_SIZE
;
399 new->memory
[3] = new->memory
[2] + PAGE_SIZE
;
401 new->page_count
= pg_count
;
402 new->num_scratch_pages
= pg_count
;
403 new->type
= AGP_PHYS_MEMORY
;
404 new->physical
= new->memory
[0];
408 static struct agp_memory
*intel_i810_alloc_by_type(size_t pg_count
, int type
)
410 struct agp_memory
*new;
412 if (type
== AGP_DCACHE_MEMORY
) {
413 if (pg_count
!= intel_private
.num_dcache_entries
)
416 new = agp_create_memory(1);
420 new->type
= AGP_DCACHE_MEMORY
;
421 new->page_count
= pg_count
;
422 new->num_scratch_pages
= 0;
423 agp_free_page_array(new);
426 if (type
== AGP_PHYS_MEMORY
)
427 return alloc_agpphysmem_i8xx(pg_count
, type
);
431 static void intel_i810_free_by_type(struct agp_memory
*curr
)
433 agp_free_key(curr
->key
);
434 if (curr
->type
== AGP_PHYS_MEMORY
) {
435 if (curr
->page_count
== 4)
436 i8xx_destroy_pages(gart_to_virt(curr
->memory
[0]));
438 void *va
= gart_to_virt(curr
->memory
[0]);
440 agp_bridge
->driver
->agp_destroy_page(va
,
441 AGP_PAGE_DESTROY_UNMAP
);
442 agp_bridge
->driver
->agp_destroy_page(va
,
443 AGP_PAGE_DESTROY_FREE
);
445 agp_free_page_array(curr
);
450 static unsigned long intel_i810_mask_memory(struct agp_bridge_data
*bridge
,
451 unsigned long addr
, int type
)
453 /* Type checking must be done elsewhere */
454 return addr
| bridge
->driver
->masks
[type
].mask
;
457 static struct aper_size_info_fixed intel_i830_sizes
[] =
460 /* The 64M mode still requires a 128k gatt */
466 static void intel_i830_init_gtt_entries(void)
472 static const int ddt
[4] = { 0, 16, 32, 64 };
473 int size
; /* reserved space (in kb) at the top of stolen memory */
475 pci_read_config_word(agp_bridge
->dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
479 pgetbl_ctl
= readl(intel_private
.registers
+I810_PGETBL_CTL
);
481 /* The 965 has a field telling us the size of the GTT,
482 * which may be larger than what is necessary to map the
485 switch (pgetbl_ctl
& I965_PGETBL_SIZE_MASK
) {
486 case I965_PGETBL_SIZE_128KB
:
489 case I965_PGETBL_SIZE_256KB
:
492 case I965_PGETBL_SIZE_512KB
:
495 case I965_PGETBL_SIZE_1MB
:
498 case I965_PGETBL_SIZE_2MB
:
501 case I965_PGETBL_SIZE_1_5MB
:
505 dev_info(&intel_private
.pcidev
->dev
,
506 "unknown page table size, assuming 512KB\n");
509 size
+= 4; /* add in BIOS popup space */
511 /* G33's GTT size defined in gmch_ctrl */
512 switch (gmch_ctrl
& G33_PGETBL_SIZE_MASK
) {
513 case G33_PGETBL_SIZE_1M
:
516 case G33_PGETBL_SIZE_2M
:
520 dev_info(&agp_bridge
->dev
->dev
,
521 "unknown page table size 0x%x, assuming 512KB\n",
522 (gmch_ctrl
& G33_PGETBL_SIZE_MASK
));
527 /* On 4 series hardware, GTT stolen is separate from graphics
528 * stolen, ignore it in stolen gtt entries counting */
531 /* On previous hardware, the GTT size was just what was
532 * required to map the aperture.
534 size
= agp_bridge
->driver
->fetch_size() + 4;
537 if (agp_bridge
->dev
->device
== PCI_DEVICE_ID_INTEL_82830_HB
||
538 agp_bridge
->dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
) {
539 switch (gmch_ctrl
& I830_GMCH_GMS_MASK
) {
540 case I830_GMCH_GMS_STOLEN_512
:
541 gtt_entries
= KB(512) - KB(size
);
543 case I830_GMCH_GMS_STOLEN_1024
:
544 gtt_entries
= MB(1) - KB(size
);
546 case I830_GMCH_GMS_STOLEN_8192
:
547 gtt_entries
= MB(8) - KB(size
);
549 case I830_GMCH_GMS_LOCAL
:
550 rdct
= readb(intel_private
.registers
+I830_RDRAM_CHANNEL_TYPE
);
551 gtt_entries
= (I830_RDRAM_ND(rdct
) + 1) *
552 MB(ddt
[I830_RDRAM_DDT(rdct
)]);
560 switch (gmch_ctrl
& I855_GMCH_GMS_MASK
) {
561 case I855_GMCH_GMS_STOLEN_1M
:
562 gtt_entries
= MB(1) - KB(size
);
564 case I855_GMCH_GMS_STOLEN_4M
:
565 gtt_entries
= MB(4) - KB(size
);
567 case I855_GMCH_GMS_STOLEN_8M
:
568 gtt_entries
= MB(8) - KB(size
);
570 case I855_GMCH_GMS_STOLEN_16M
:
571 gtt_entries
= MB(16) - KB(size
);
573 case I855_GMCH_GMS_STOLEN_32M
:
574 gtt_entries
= MB(32) - KB(size
);
576 case I915_GMCH_GMS_STOLEN_48M
:
577 /* Check it's really I915G */
578 if (IS_I915
|| IS_I965
|| IS_G33
|| IS_G4X
)
579 gtt_entries
= MB(48) - KB(size
);
583 case I915_GMCH_GMS_STOLEN_64M
:
584 /* Check it's really I915G */
585 if (IS_I915
|| IS_I965
|| IS_G33
|| IS_G4X
)
586 gtt_entries
= MB(64) - KB(size
);
590 case G33_GMCH_GMS_STOLEN_128M
:
591 if (IS_G33
|| IS_I965
|| IS_G4X
)
592 gtt_entries
= MB(128) - KB(size
);
596 case G33_GMCH_GMS_STOLEN_256M
:
597 if (IS_G33
|| IS_I965
|| IS_G4X
)
598 gtt_entries
= MB(256) - KB(size
);
602 case INTEL_GMCH_GMS_STOLEN_96M
:
603 if (IS_I965
|| IS_G4X
)
604 gtt_entries
= MB(96) - KB(size
);
608 case INTEL_GMCH_GMS_STOLEN_160M
:
609 if (IS_I965
|| IS_G4X
)
610 gtt_entries
= MB(160) - KB(size
);
614 case INTEL_GMCH_GMS_STOLEN_224M
:
615 if (IS_I965
|| IS_G4X
)
616 gtt_entries
= MB(224) - KB(size
);
620 case INTEL_GMCH_GMS_STOLEN_352M
:
621 if (IS_I965
|| IS_G4X
)
622 gtt_entries
= MB(352) - KB(size
);
632 dev_info(&agp_bridge
->dev
->dev
, "detected %dK %s memory\n",
633 gtt_entries
/ KB(1), local
? "local" : "stolen");
635 dev_info(&agp_bridge
->dev
->dev
,
636 "no pre-allocated video memory detected\n");
637 gtt_entries
/= KB(4);
639 intel_private
.gtt_entries
= gtt_entries
;
642 static void intel_i830_fini_flush(void)
644 kunmap(intel_private
.i8xx_page
);
645 intel_private
.i8xx_flush_page
= NULL
;
646 unmap_page_from_agp(intel_private
.i8xx_page
);
648 __free_page(intel_private
.i8xx_page
);
649 intel_private
.i8xx_page
= NULL
;
652 static void intel_i830_setup_flush(void)
654 /* return if we've already set the flush mechanism up */
655 if (intel_private
.i8xx_page
)
658 intel_private
.i8xx_page
= alloc_page(GFP_KERNEL
| __GFP_ZERO
| GFP_DMA32
);
659 if (!intel_private
.i8xx_page
)
662 /* make page uncached */
663 map_page_into_agp(intel_private
.i8xx_page
);
665 intel_private
.i8xx_flush_page
= kmap(intel_private
.i8xx_page
);
666 if (!intel_private
.i8xx_flush_page
)
667 intel_i830_fini_flush();
670 static void intel_i830_chipset_flush(struct agp_bridge_data
*bridge
)
672 unsigned int *pg
= intel_private
.i8xx_flush_page
;
675 for (i
= 0; i
< 256; i
+= 2)
681 /* The intel i830 automatically initializes the agp aperture during POST.
682 * Use the memory already set aside for in the GTT.
684 static int intel_i830_create_gatt_table(struct agp_bridge_data
*bridge
)
687 struct aper_size_info_fixed
*size
;
691 size
= agp_bridge
->current_size
;
692 page_order
= size
->page_order
;
693 num_entries
= size
->num_entries
;
694 agp_bridge
->gatt_table_real
= NULL
;
696 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, &temp
);
699 intel_private
.registers
= ioremap(temp
, 128 * 4096);
700 if (!intel_private
.registers
)
703 temp
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
704 global_cache_flush(); /* FIXME: ?? */
706 /* we have to call this as early as possible after the MMIO base address is known */
707 intel_i830_init_gtt_entries();
709 agp_bridge
->gatt_table
= NULL
;
711 agp_bridge
->gatt_bus_addr
= temp
;
716 /* Return the gatt table to a sane state. Use the top of stolen
717 * memory for the GTT.
719 static int intel_i830_free_gatt_table(struct agp_bridge_data
*bridge
)
724 static int intel_i830_fetch_size(void)
727 struct aper_size_info_fixed
*values
;
729 values
= A_SIZE_FIX(agp_bridge
->driver
->aperture_sizes
);
731 if (agp_bridge
->dev
->device
!= PCI_DEVICE_ID_INTEL_82830_HB
&&
732 agp_bridge
->dev
->device
!= PCI_DEVICE_ID_INTEL_82845G_HB
) {
733 /* 855GM/852GM/865G has 128MB aperture size */
734 agp_bridge
->previous_size
= agp_bridge
->current_size
= (void *) values
;
735 agp_bridge
->aperture_size_idx
= 0;
736 return values
[0].size
;
739 pci_read_config_word(agp_bridge
->dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
741 if ((gmch_ctrl
& I830_GMCH_MEM_MASK
) == I830_GMCH_MEM_128M
) {
742 agp_bridge
->previous_size
= agp_bridge
->current_size
= (void *) values
;
743 agp_bridge
->aperture_size_idx
= 0;
744 return values
[0].size
;
746 agp_bridge
->previous_size
= agp_bridge
->current_size
= (void *) (values
+ 1);
747 agp_bridge
->aperture_size_idx
= 1;
748 return values
[1].size
;
754 static int intel_i830_configure(void)
756 struct aper_size_info_fixed
*current_size
;
761 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
763 pci_read_config_dword(intel_private
.pcidev
, I810_GMADDR
, &temp
);
764 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
766 pci_read_config_word(agp_bridge
->dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
767 gmch_ctrl
|= I830_GMCH_ENABLED
;
768 pci_write_config_word(agp_bridge
->dev
, I830_GMCH_CTRL
, gmch_ctrl
);
770 writel(agp_bridge
->gatt_bus_addr
|I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
771 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
773 if (agp_bridge
->driver
->needs_scratch_page
) {
774 for (i
= intel_private
.gtt_entries
; i
< current_size
->num_entries
; i
++) {
775 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
776 readl(intel_private
.registers
+I810_PTE_BASE
+(i
*4)); /* PCI Posting. */
780 global_cache_flush();
782 intel_i830_setup_flush();
786 static void intel_i830_cleanup(void)
788 iounmap(intel_private
.registers
);
791 static int intel_i830_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
794 int i
, j
, num_entries
;
799 if (mem
->page_count
== 0)
802 temp
= agp_bridge
->current_size
;
803 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
805 if (pg_start
< intel_private
.gtt_entries
) {
806 dev_printk(KERN_DEBUG
, &intel_private
.pcidev
->dev
,
807 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
808 pg_start
, intel_private
.gtt_entries
);
810 dev_info(&intel_private
.pcidev
->dev
,
811 "trying to insert into local/stolen memory\n");
815 if ((pg_start
+ mem
->page_count
) > num_entries
)
818 /* The i830 can't check the GTT for entries since its read only,
819 * depend on the caller to make the correct offset decisions.
822 if (type
!= mem
->type
)
825 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
827 if (mask_type
!= 0 && mask_type
!= AGP_PHYS_MEMORY
&&
828 mask_type
!= INTEL_AGP_CACHED_MEMORY
)
831 if (!mem
->is_flushed
)
832 global_cache_flush();
834 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
835 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
836 mem
->memory
[i
], mask_type
),
837 intel_private
.registers
+I810_PTE_BASE
+(j
*4));
839 readl(intel_private
.registers
+I810_PTE_BASE
+((j
-1)*4));
840 agp_bridge
->driver
->tlb_flush(mem
);
845 mem
->is_flushed
= true;
849 static int intel_i830_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
854 if (mem
->page_count
== 0)
857 if (pg_start
< intel_private
.gtt_entries
) {
858 dev_info(&intel_private
.pcidev
->dev
,
859 "trying to disable local/stolen memory\n");
863 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++) {
864 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
866 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
868 agp_bridge
->driver
->tlb_flush(mem
);
872 static struct agp_memory
*intel_i830_alloc_by_type(size_t pg_count
, int type
)
874 if (type
== AGP_PHYS_MEMORY
)
875 return alloc_agpphysmem_i8xx(pg_count
, type
);
876 /* always return NULL for other allocation types for now */
880 static int intel_alloc_chipset_flush_resource(void)
883 ret
= pci_bus_alloc_resource(agp_bridge
->dev
->bus
, &intel_private
.ifp_resource
, PAGE_SIZE
,
884 PAGE_SIZE
, PCIBIOS_MIN_MEM
, 0,
885 pcibios_align_resource
, agp_bridge
->dev
);
890 static void intel_i915_setup_chipset_flush(void)
895 pci_read_config_dword(agp_bridge
->dev
, I915_IFPADDR
, &temp
);
897 intel_alloc_chipset_flush_resource();
898 intel_private
.resource_valid
= 1;
899 pci_write_config_dword(agp_bridge
->dev
, I915_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
903 intel_private
.resource_valid
= 1;
904 intel_private
.ifp_resource
.start
= temp
;
905 intel_private
.ifp_resource
.end
= temp
+ PAGE_SIZE
;
906 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
907 /* some BIOSes reserve this area in a pnp some don't */
909 intel_private
.resource_valid
= 0;
913 static void intel_i965_g33_setup_chipset_flush(void)
915 u32 temp_hi
, temp_lo
;
918 pci_read_config_dword(agp_bridge
->dev
, I965_IFPADDR
+ 4, &temp_hi
);
919 pci_read_config_dword(agp_bridge
->dev
, I965_IFPADDR
, &temp_lo
);
921 if (!(temp_lo
& 0x1)) {
923 intel_alloc_chipset_flush_resource();
925 intel_private
.resource_valid
= 1;
926 pci_write_config_dword(agp_bridge
->dev
, I965_IFPADDR
+ 4,
927 upper_32_bits(intel_private
.ifp_resource
.start
));
928 pci_write_config_dword(agp_bridge
->dev
, I965_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
933 l64
= ((u64
)temp_hi
<< 32) | temp_lo
;
935 intel_private
.resource_valid
= 1;
936 intel_private
.ifp_resource
.start
= l64
;
937 intel_private
.ifp_resource
.end
= l64
+ PAGE_SIZE
;
938 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
939 /* some BIOSes reserve this area in a pnp some don't */
941 intel_private
.resource_valid
= 0;
945 static void intel_i9xx_setup_flush(void)
947 /* return if already configured */
948 if (intel_private
.ifp_resource
.start
)
951 /* setup a resource for this object */
952 intel_private
.ifp_resource
.name
= "Intel Flush Page";
953 intel_private
.ifp_resource
.flags
= IORESOURCE_MEM
;
955 /* Setup chipset flush for 915 */
956 if (IS_I965
|| IS_G33
|| IS_G4X
) {
957 intel_i965_g33_setup_chipset_flush();
959 intel_i915_setup_chipset_flush();
962 if (intel_private
.ifp_resource
.start
) {
963 intel_private
.i9xx_flush_page
= ioremap_nocache(intel_private
.ifp_resource
.start
, PAGE_SIZE
);
964 if (!intel_private
.i9xx_flush_page
)
965 dev_info(&intel_private
.pcidev
->dev
, "can't ioremap flush page - no chipset flushing");
969 static int intel_i915_configure(void)
971 struct aper_size_info_fixed
*current_size
;
976 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
978 pci_read_config_dword(intel_private
.pcidev
, I915_GMADDR
, &temp
);
980 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
982 pci_read_config_word(agp_bridge
->dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
983 gmch_ctrl
|= I830_GMCH_ENABLED
;
984 pci_write_config_word(agp_bridge
->dev
, I830_GMCH_CTRL
, gmch_ctrl
);
986 writel(agp_bridge
->gatt_bus_addr
|I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
987 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
989 if (agp_bridge
->driver
->needs_scratch_page
) {
990 for (i
= intel_private
.gtt_entries
; i
< current_size
->num_entries
; i
++) {
991 writel(agp_bridge
->scratch_page
, intel_private
.gtt
+i
);
992 readl(intel_private
.gtt
+i
); /* PCI Posting. */
996 global_cache_flush();
998 intel_i9xx_setup_flush();
1003 static void intel_i915_cleanup(void)
1005 if (intel_private
.i9xx_flush_page
)
1006 iounmap(intel_private
.i9xx_flush_page
);
1007 if (intel_private
.resource_valid
)
1008 release_resource(&intel_private
.ifp_resource
);
1009 intel_private
.ifp_resource
.start
= 0;
1010 intel_private
.resource_valid
= 0;
1011 iounmap(intel_private
.gtt
);
1012 iounmap(intel_private
.registers
);
1015 static void intel_i915_chipset_flush(struct agp_bridge_data
*bridge
)
1017 if (intel_private
.i9xx_flush_page
)
1018 writel(1, intel_private
.i9xx_flush_page
);
1021 static int intel_i915_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
1024 int i
, j
, num_entries
;
1029 if (mem
->page_count
== 0)
1032 temp
= agp_bridge
->current_size
;
1033 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
1035 if (pg_start
< intel_private
.gtt_entries
) {
1036 dev_printk(KERN_DEBUG
, &intel_private
.pcidev
->dev
,
1037 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1038 pg_start
, intel_private
.gtt_entries
);
1040 dev_info(&intel_private
.pcidev
->dev
,
1041 "trying to insert into local/stolen memory\n");
1045 if ((pg_start
+ mem
->page_count
) > num_entries
)
1048 /* The i915 can't check the GTT for entries since its read only,
1049 * depend on the caller to make the correct offset decisions.
1052 if (type
!= mem
->type
)
1055 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
1057 if (mask_type
!= 0 && mask_type
!= AGP_PHYS_MEMORY
&&
1058 mask_type
!= INTEL_AGP_CACHED_MEMORY
)
1061 if (!mem
->is_flushed
)
1062 global_cache_flush();
1064 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
1065 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
1066 mem
->memory
[i
], mask_type
), intel_private
.gtt
+j
);
1069 readl(intel_private
.gtt
+j
-1);
1070 agp_bridge
->driver
->tlb_flush(mem
);
1075 mem
->is_flushed
= true;
1079 static int intel_i915_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
1084 if (mem
->page_count
== 0)
1087 if (pg_start
< intel_private
.gtt_entries
) {
1088 dev_info(&intel_private
.pcidev
->dev
,
1089 "trying to disable local/stolen memory\n");
1093 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++)
1094 writel(agp_bridge
->scratch_page
, intel_private
.gtt
+i
);
1096 readl(intel_private
.gtt
+i
-1);
1098 agp_bridge
->driver
->tlb_flush(mem
);
1102 /* Return the aperture size by just checking the resource length. The effect
1103 * described in the spec of the MSAC registers is just changing of the
1106 static int intel_i9xx_fetch_size(void)
1108 int num_sizes
= ARRAY_SIZE(intel_i830_sizes
);
1109 int aper_size
; /* size in megabytes */
1112 aper_size
= pci_resource_len(intel_private
.pcidev
, 2) / MB(1);
1114 for (i
= 0; i
< num_sizes
; i
++) {
1115 if (aper_size
== intel_i830_sizes
[i
].size
) {
1116 agp_bridge
->current_size
= intel_i830_sizes
+ i
;
1117 agp_bridge
->previous_size
= agp_bridge
->current_size
;
1125 /* The intel i915 automatically initializes the agp aperture during POST.
1126 * Use the memory already set aside for in the GTT.
1128 static int intel_i915_create_gatt_table(struct agp_bridge_data
*bridge
)
1131 struct aper_size_info_fixed
*size
;
1134 int gtt_map_size
= 256 * 1024;
1136 size
= agp_bridge
->current_size
;
1137 page_order
= size
->page_order
;
1138 num_entries
= size
->num_entries
;
1139 agp_bridge
->gatt_table_real
= NULL
;
1141 pci_read_config_dword(intel_private
.pcidev
, I915_MMADDR
, &temp
);
1142 pci_read_config_dword(intel_private
.pcidev
, I915_PTEADDR
, &temp2
);
1145 gtt_map_size
= 1024 * 1024; /* 1M on G33 */
1146 intel_private
.gtt
= ioremap(temp2
, gtt_map_size
);
1147 if (!intel_private
.gtt
)
1152 intel_private
.registers
= ioremap(temp
, 128 * 4096);
1153 if (!intel_private
.registers
) {
1154 iounmap(intel_private
.gtt
);
1158 temp
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
1159 global_cache_flush(); /* FIXME: ? */
1161 /* we have to call this as early as possible after the MMIO base address is known */
1162 intel_i830_init_gtt_entries();
1164 agp_bridge
->gatt_table
= NULL
;
1166 agp_bridge
->gatt_bus_addr
= temp
;
1172 * The i965 supports 36-bit physical addresses, but to keep
1173 * the format of the GTT the same, the bits that don't fit
1174 * in a 32-bit word are shifted down to bits 4..7.
1176 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1177 * is always zero on 32-bit architectures, so no need to make
1180 static unsigned long intel_i965_mask_memory(struct agp_bridge_data
*bridge
,
1181 unsigned long addr
, int type
)
1183 /* Shift high bits down */
1184 addr
|= (addr
>> 28) & 0xf0;
1186 /* Type checking must be done elsewhere */
1187 return addr
| bridge
->driver
->masks
[type
].mask
;
1190 static void intel_i965_get_gtt_range(int *gtt_offset
, int *gtt_size
)
1192 switch (agp_bridge
->dev
->device
) {
1193 case PCI_DEVICE_ID_INTEL_GM45_HB
:
1194 case PCI_DEVICE_ID_INTEL_IGD_E_HB
:
1195 case PCI_DEVICE_ID_INTEL_Q45_HB
:
1196 case PCI_DEVICE_ID_INTEL_G45_HB
:
1197 *gtt_offset
= *gtt_size
= MB(2);
1200 *gtt_offset
= *gtt_size
= KB(512);
1204 /* The intel i965 automatically initializes the agp aperture during POST.
1205 * Use the memory already set aside for in the GTT.
1207 static int intel_i965_create_gatt_table(struct agp_bridge_data
*bridge
)
1210 struct aper_size_info_fixed
*size
;
1213 int gtt_offset
, gtt_size
;
1215 size
= agp_bridge
->current_size
;
1216 page_order
= size
->page_order
;
1217 num_entries
= size
->num_entries
;
1218 agp_bridge
->gatt_table_real
= NULL
;
1220 pci_read_config_dword(intel_private
.pcidev
, I915_MMADDR
, &temp
);
1224 intel_i965_get_gtt_range(>t_offset
, >t_size
);
1226 intel_private
.gtt
= ioremap((temp
+ gtt_offset
) , gtt_size
);
1228 if (!intel_private
.gtt
)
1231 intel_private
.registers
= ioremap(temp
, 128 * 4096);
1232 if (!intel_private
.registers
) {
1233 iounmap(intel_private
.gtt
);
1237 temp
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
1238 global_cache_flush(); /* FIXME: ? */
1240 /* we have to call this as early as possible after the MMIO base address is known */
1241 intel_i830_init_gtt_entries();
1243 agp_bridge
->gatt_table
= NULL
;
1245 agp_bridge
->gatt_bus_addr
= temp
;
1251 static int intel_fetch_size(void)
1255 struct aper_size_info_16
*values
;
1257 pci_read_config_word(agp_bridge
->dev
, INTEL_APSIZE
, &temp
);
1258 values
= A_SIZE_16(agp_bridge
->driver
->aperture_sizes
);
1260 for (i
= 0; i
< agp_bridge
->driver
->num_aperture_sizes
; i
++) {
1261 if (temp
== values
[i
].size_value
) {
1262 agp_bridge
->previous_size
= agp_bridge
->current_size
= (void *) (values
+ i
);
1263 agp_bridge
->aperture_size_idx
= i
;
1264 return values
[i
].size
;
1271 static int __intel_8xx_fetch_size(u8 temp
)
1274 struct aper_size_info_8
*values
;
1276 values
= A_SIZE_8(agp_bridge
->driver
->aperture_sizes
);
1278 for (i
= 0; i
< agp_bridge
->driver
->num_aperture_sizes
; i
++) {
1279 if (temp
== values
[i
].size_value
) {
1280 agp_bridge
->previous_size
=
1281 agp_bridge
->current_size
= (void *) (values
+ i
);
1282 agp_bridge
->aperture_size_idx
= i
;
1283 return values
[i
].size
;
1289 static int intel_8xx_fetch_size(void)
1293 pci_read_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, &temp
);
1294 return __intel_8xx_fetch_size(temp
);
1297 static int intel_815_fetch_size(void)
1301 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1302 * one non-reserved bit, so mask the others out ... */
1303 pci_read_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, &temp
);
1306 return __intel_8xx_fetch_size(temp
);
1309 static void intel_tlbflush(struct agp_memory
*mem
)
1311 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x2200);
1312 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x2280);
1316 static void intel_8xx_tlbflush(struct agp_memory
*mem
)
1319 pci_read_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, &temp
);
1320 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, temp
& ~(1 << 7));
1321 pci_read_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, &temp
);
1322 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, temp
| (1 << 7));
1326 static void intel_cleanup(void)
1329 struct aper_size_info_16
*previous_size
;
1331 previous_size
= A_SIZE_16(agp_bridge
->previous_size
);
1332 pci_read_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, &temp
);
1333 pci_write_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, temp
& ~(1 << 9));
1334 pci_write_config_word(agp_bridge
->dev
, INTEL_APSIZE
, previous_size
->size_value
);
1338 static void intel_8xx_cleanup(void)
1341 struct aper_size_info_8
*previous_size
;
1343 previous_size
= A_SIZE_8(agp_bridge
->previous_size
);
1344 pci_read_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, &temp
);
1345 pci_write_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, temp
& ~(1 << 9));
1346 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, previous_size
->size_value
);
1350 static int intel_configure(void)
1354 struct aper_size_info_16
*current_size
;
1356 current_size
= A_SIZE_16(agp_bridge
->current_size
);
1359 pci_write_config_word(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1361 /* address to map to */
1362 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1363 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1365 /* attbase - aperture base */
1366 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1369 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x2280);
1372 pci_read_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, &temp2
);
1373 pci_write_config_word(agp_bridge
->dev
, INTEL_NBXCFG
,
1374 (temp2
& ~(1 << 10)) | (1 << 9));
1375 /* clear any possible error conditions */
1376 pci_write_config_byte(agp_bridge
->dev
, INTEL_ERRSTS
+ 1, 7);
1380 static int intel_815_configure(void)
1384 struct aper_size_info_8
*current_size
;
1386 /* attbase - aperture base */
1387 /* the Intel 815 chipset spec. says that bits 29-31 in the
1388 * ATTBASE register are reserved -> try not to write them */
1389 if (agp_bridge
->gatt_bus_addr
& INTEL_815_ATTBASE_MASK
) {
1390 dev_emerg(&agp_bridge
->dev
->dev
, "gatt bus addr too high");
1394 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1397 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
,
1398 current_size
->size_value
);
1400 /* address to map to */
1401 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1402 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1404 pci_read_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, &addr
);
1405 addr
&= INTEL_815_ATTBASE_MASK
;
1406 addr
|= agp_bridge
->gatt_bus_addr
;
1407 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, addr
);
1410 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1413 pci_read_config_byte(agp_bridge
->dev
, INTEL_815_APCONT
, &temp2
);
1414 pci_write_config_byte(agp_bridge
->dev
, INTEL_815_APCONT
, temp2
| (1 << 1));
1416 /* clear any possible error conditions */
1417 /* Oddness : this chipset seems to have no ERRSTS register ! */
1421 static void intel_820_tlbflush(struct agp_memory
*mem
)
1426 static void intel_820_cleanup(void)
1429 struct aper_size_info_8
*previous_size
;
1431 previous_size
= A_SIZE_8(agp_bridge
->previous_size
);
1432 pci_read_config_byte(agp_bridge
->dev
, INTEL_I820_RDCR
, &temp
);
1433 pci_write_config_byte(agp_bridge
->dev
, INTEL_I820_RDCR
,
1435 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
,
1436 previous_size
->size_value
);
1440 static int intel_820_configure(void)
1444 struct aper_size_info_8
*current_size
;
1446 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1449 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1451 /* address to map to */
1452 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1453 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1455 /* attbase - aperture base */
1456 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1459 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1461 /* global enable aperture access */
1462 /* This flag is not accessed through MCHCFG register as in */
1464 pci_read_config_byte(agp_bridge
->dev
, INTEL_I820_RDCR
, &temp2
);
1465 pci_write_config_byte(agp_bridge
->dev
, INTEL_I820_RDCR
, temp2
| (1 << 1));
1466 /* clear any possible AGP-related error conditions */
1467 pci_write_config_word(agp_bridge
->dev
, INTEL_I820_ERRSTS
, 0x001c);
1471 static int intel_840_configure(void)
1475 struct aper_size_info_8
*current_size
;
1477 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1480 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1482 /* address to map to */
1483 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1484 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1486 /* attbase - aperture base */
1487 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1490 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1493 pci_read_config_word(agp_bridge
->dev
, INTEL_I840_MCHCFG
, &temp2
);
1494 pci_write_config_word(agp_bridge
->dev
, INTEL_I840_MCHCFG
, temp2
| (1 << 9));
1495 /* clear any possible error conditions */
1496 pci_write_config_word(agp_bridge
->dev
, INTEL_I840_ERRSTS
, 0xc000);
1500 static int intel_845_configure(void)
1504 struct aper_size_info_8
*current_size
;
1506 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1509 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1511 if (agp_bridge
->apbase_config
!= 0) {
1512 pci_write_config_dword(agp_bridge
->dev
, AGP_APBASE
,
1513 agp_bridge
->apbase_config
);
1515 /* address to map to */
1516 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1517 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1518 agp_bridge
->apbase_config
= temp
;
1521 /* attbase - aperture base */
1522 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1525 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1528 pci_read_config_byte(agp_bridge
->dev
, INTEL_I845_AGPM
, &temp2
);
1529 pci_write_config_byte(agp_bridge
->dev
, INTEL_I845_AGPM
, temp2
| (1 << 1));
1530 /* clear any possible error conditions */
1531 pci_write_config_word(agp_bridge
->dev
, INTEL_I845_ERRSTS
, 0x001c);
1533 intel_i830_setup_flush();
1537 static int intel_850_configure(void)
1541 struct aper_size_info_8
*current_size
;
1543 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1546 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1548 /* address to map to */
1549 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1550 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1552 /* attbase - aperture base */
1553 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1556 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1559 pci_read_config_word(agp_bridge
->dev
, INTEL_I850_MCHCFG
, &temp2
);
1560 pci_write_config_word(agp_bridge
->dev
, INTEL_I850_MCHCFG
, temp2
| (1 << 9));
1561 /* clear any possible AGP-related error conditions */
1562 pci_write_config_word(agp_bridge
->dev
, INTEL_I850_ERRSTS
, 0x001c);
1566 static int intel_860_configure(void)
1570 struct aper_size_info_8
*current_size
;
1572 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1575 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1577 /* address to map to */
1578 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1579 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1581 /* attbase - aperture base */
1582 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1585 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1588 pci_read_config_word(agp_bridge
->dev
, INTEL_I860_MCHCFG
, &temp2
);
1589 pci_write_config_word(agp_bridge
->dev
, INTEL_I860_MCHCFG
, temp2
| (1 << 9));
1590 /* clear any possible AGP-related error conditions */
1591 pci_write_config_word(agp_bridge
->dev
, INTEL_I860_ERRSTS
, 0xf700);
1595 static int intel_830mp_configure(void)
1599 struct aper_size_info_8
*current_size
;
1601 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1604 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1606 /* address to map to */
1607 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1608 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1610 /* attbase - aperture base */
1611 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1614 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1617 pci_read_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, &temp2
);
1618 pci_write_config_word(agp_bridge
->dev
, INTEL_NBXCFG
, temp2
| (1 << 9));
1619 /* clear any possible AGP-related error conditions */
1620 pci_write_config_word(agp_bridge
->dev
, INTEL_I830_ERRSTS
, 0x1c);
1624 static int intel_7505_configure(void)
1628 struct aper_size_info_8
*current_size
;
1630 current_size
= A_SIZE_8(agp_bridge
->current_size
);
1633 pci_write_config_byte(agp_bridge
->dev
, INTEL_APSIZE
, current_size
->size_value
);
1635 /* address to map to */
1636 pci_read_config_dword(agp_bridge
->dev
, AGP_APBASE
, &temp
);
1637 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1639 /* attbase - aperture base */
1640 pci_write_config_dword(agp_bridge
->dev
, INTEL_ATTBASE
, agp_bridge
->gatt_bus_addr
);
1643 pci_write_config_dword(agp_bridge
->dev
, INTEL_AGPCTRL
, 0x0000);
1646 pci_read_config_word(agp_bridge
->dev
, INTEL_I7505_MCHCFG
, &temp2
);
1647 pci_write_config_word(agp_bridge
->dev
, INTEL_I7505_MCHCFG
, temp2
| (1 << 9));
1652 /* Setup function */
1653 static const struct gatt_mask intel_generic_masks
[] =
1655 {.mask
= 0x00000017, .type
= 0}
1658 static const struct aper_size_info_8 intel_815_sizes
[2] =
1664 static const struct aper_size_info_8 intel_8xx_sizes
[7] =
1667 {128, 32768, 5, 32},
1675 static const struct aper_size_info_16 intel_generic_sizes
[7] =
1678 {128, 32768, 5, 32},
1686 static const struct aper_size_info_8 intel_830mp_sizes
[4] =
1689 {128, 32768, 5, 32},
1694 static const struct agp_bridge_driver intel_generic_driver
= {
1695 .owner
= THIS_MODULE
,
1696 .aperture_sizes
= intel_generic_sizes
,
1697 .size_type
= U16_APER_SIZE
,
1698 .num_aperture_sizes
= 7,
1699 .configure
= intel_configure
,
1700 .fetch_size
= intel_fetch_size
,
1701 .cleanup
= intel_cleanup
,
1702 .tlb_flush
= intel_tlbflush
,
1703 .mask_memory
= agp_generic_mask_memory
,
1704 .masks
= intel_generic_masks
,
1705 .agp_enable
= agp_generic_enable
,
1706 .cache_flush
= global_cache_flush
,
1707 .create_gatt_table
= agp_generic_create_gatt_table
,
1708 .free_gatt_table
= agp_generic_free_gatt_table
,
1709 .insert_memory
= agp_generic_insert_memory
,
1710 .remove_memory
= agp_generic_remove_memory
,
1711 .alloc_by_type
= agp_generic_alloc_by_type
,
1712 .free_by_type
= agp_generic_free_by_type
,
1713 .agp_alloc_page
= agp_generic_alloc_page
,
1714 .agp_alloc_pages
= agp_generic_alloc_pages
,
1715 .agp_destroy_page
= agp_generic_destroy_page
,
1716 .agp_destroy_pages
= agp_generic_destroy_pages
,
1717 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1720 static const struct agp_bridge_driver intel_810_driver
= {
1721 .owner
= THIS_MODULE
,
1722 .aperture_sizes
= intel_i810_sizes
,
1723 .size_type
= FIXED_APER_SIZE
,
1724 .num_aperture_sizes
= 2,
1725 .needs_scratch_page
= true,
1726 .configure
= intel_i810_configure
,
1727 .fetch_size
= intel_i810_fetch_size
,
1728 .cleanup
= intel_i810_cleanup
,
1729 .tlb_flush
= intel_i810_tlbflush
,
1730 .mask_memory
= intel_i810_mask_memory
,
1731 .masks
= intel_i810_masks
,
1732 .agp_enable
= intel_i810_agp_enable
,
1733 .cache_flush
= global_cache_flush
,
1734 .create_gatt_table
= agp_generic_create_gatt_table
,
1735 .free_gatt_table
= agp_generic_free_gatt_table
,
1736 .insert_memory
= intel_i810_insert_entries
,
1737 .remove_memory
= intel_i810_remove_entries
,
1738 .alloc_by_type
= intel_i810_alloc_by_type
,
1739 .free_by_type
= intel_i810_free_by_type
,
1740 .agp_alloc_page
= agp_generic_alloc_page
,
1741 .agp_alloc_pages
= agp_generic_alloc_pages
,
1742 .agp_destroy_page
= agp_generic_destroy_page
,
1743 .agp_destroy_pages
= agp_generic_destroy_pages
,
1744 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1747 static const struct agp_bridge_driver intel_815_driver
= {
1748 .owner
= THIS_MODULE
,
1749 .aperture_sizes
= intel_815_sizes
,
1750 .size_type
= U8_APER_SIZE
,
1751 .num_aperture_sizes
= 2,
1752 .configure
= intel_815_configure
,
1753 .fetch_size
= intel_815_fetch_size
,
1754 .cleanup
= intel_8xx_cleanup
,
1755 .tlb_flush
= intel_8xx_tlbflush
,
1756 .mask_memory
= agp_generic_mask_memory
,
1757 .masks
= intel_generic_masks
,
1758 .agp_enable
= agp_generic_enable
,
1759 .cache_flush
= global_cache_flush
,
1760 .create_gatt_table
= agp_generic_create_gatt_table
,
1761 .free_gatt_table
= agp_generic_free_gatt_table
,
1762 .insert_memory
= agp_generic_insert_memory
,
1763 .remove_memory
= agp_generic_remove_memory
,
1764 .alloc_by_type
= agp_generic_alloc_by_type
,
1765 .free_by_type
= agp_generic_free_by_type
,
1766 .agp_alloc_page
= agp_generic_alloc_page
,
1767 .agp_alloc_pages
= agp_generic_alloc_pages
,
1768 .agp_destroy_page
= agp_generic_destroy_page
,
1769 .agp_destroy_pages
= agp_generic_destroy_pages
,
1770 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1773 static const struct agp_bridge_driver intel_830_driver
= {
1774 .owner
= THIS_MODULE
,
1775 .aperture_sizes
= intel_i830_sizes
,
1776 .size_type
= FIXED_APER_SIZE
,
1777 .num_aperture_sizes
= 4,
1778 .needs_scratch_page
= true,
1779 .configure
= intel_i830_configure
,
1780 .fetch_size
= intel_i830_fetch_size
,
1781 .cleanup
= intel_i830_cleanup
,
1782 .tlb_flush
= intel_i810_tlbflush
,
1783 .mask_memory
= intel_i810_mask_memory
,
1784 .masks
= intel_i810_masks
,
1785 .agp_enable
= intel_i810_agp_enable
,
1786 .cache_flush
= global_cache_flush
,
1787 .create_gatt_table
= intel_i830_create_gatt_table
,
1788 .free_gatt_table
= intel_i830_free_gatt_table
,
1789 .insert_memory
= intel_i830_insert_entries
,
1790 .remove_memory
= intel_i830_remove_entries
,
1791 .alloc_by_type
= intel_i830_alloc_by_type
,
1792 .free_by_type
= intel_i810_free_by_type
,
1793 .agp_alloc_page
= agp_generic_alloc_page
,
1794 .agp_alloc_pages
= agp_generic_alloc_pages
,
1795 .agp_destroy_page
= agp_generic_destroy_page
,
1796 .agp_destroy_pages
= agp_generic_destroy_pages
,
1797 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1798 .chipset_flush
= intel_i830_chipset_flush
,
1801 static const struct agp_bridge_driver intel_820_driver
= {
1802 .owner
= THIS_MODULE
,
1803 .aperture_sizes
= intel_8xx_sizes
,
1804 .size_type
= U8_APER_SIZE
,
1805 .num_aperture_sizes
= 7,
1806 .configure
= intel_820_configure
,
1807 .fetch_size
= intel_8xx_fetch_size
,
1808 .cleanup
= intel_820_cleanup
,
1809 .tlb_flush
= intel_820_tlbflush
,
1810 .mask_memory
= agp_generic_mask_memory
,
1811 .masks
= intel_generic_masks
,
1812 .agp_enable
= agp_generic_enable
,
1813 .cache_flush
= global_cache_flush
,
1814 .create_gatt_table
= agp_generic_create_gatt_table
,
1815 .free_gatt_table
= agp_generic_free_gatt_table
,
1816 .insert_memory
= agp_generic_insert_memory
,
1817 .remove_memory
= agp_generic_remove_memory
,
1818 .alloc_by_type
= agp_generic_alloc_by_type
,
1819 .free_by_type
= agp_generic_free_by_type
,
1820 .agp_alloc_page
= agp_generic_alloc_page
,
1821 .agp_alloc_pages
= agp_generic_alloc_pages
,
1822 .agp_destroy_page
= agp_generic_destroy_page
,
1823 .agp_destroy_pages
= agp_generic_destroy_pages
,
1824 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1827 static const struct agp_bridge_driver intel_830mp_driver
= {
1828 .owner
= THIS_MODULE
,
1829 .aperture_sizes
= intel_830mp_sizes
,
1830 .size_type
= U8_APER_SIZE
,
1831 .num_aperture_sizes
= 4,
1832 .configure
= intel_830mp_configure
,
1833 .fetch_size
= intel_8xx_fetch_size
,
1834 .cleanup
= intel_8xx_cleanup
,
1835 .tlb_flush
= intel_8xx_tlbflush
,
1836 .mask_memory
= agp_generic_mask_memory
,
1837 .masks
= intel_generic_masks
,
1838 .agp_enable
= agp_generic_enable
,
1839 .cache_flush
= global_cache_flush
,
1840 .create_gatt_table
= agp_generic_create_gatt_table
,
1841 .free_gatt_table
= agp_generic_free_gatt_table
,
1842 .insert_memory
= agp_generic_insert_memory
,
1843 .remove_memory
= agp_generic_remove_memory
,
1844 .alloc_by_type
= agp_generic_alloc_by_type
,
1845 .free_by_type
= agp_generic_free_by_type
,
1846 .agp_alloc_page
= agp_generic_alloc_page
,
1847 .agp_alloc_pages
= agp_generic_alloc_pages
,
1848 .agp_destroy_page
= agp_generic_destroy_page
,
1849 .agp_destroy_pages
= agp_generic_destroy_pages
,
1850 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1853 static const struct agp_bridge_driver intel_840_driver
= {
1854 .owner
= THIS_MODULE
,
1855 .aperture_sizes
= intel_8xx_sizes
,
1856 .size_type
= U8_APER_SIZE
,
1857 .num_aperture_sizes
= 7,
1858 .configure
= intel_840_configure
,
1859 .fetch_size
= intel_8xx_fetch_size
,
1860 .cleanup
= intel_8xx_cleanup
,
1861 .tlb_flush
= intel_8xx_tlbflush
,
1862 .mask_memory
= agp_generic_mask_memory
,
1863 .masks
= intel_generic_masks
,
1864 .agp_enable
= agp_generic_enable
,
1865 .cache_flush
= global_cache_flush
,
1866 .create_gatt_table
= agp_generic_create_gatt_table
,
1867 .free_gatt_table
= agp_generic_free_gatt_table
,
1868 .insert_memory
= agp_generic_insert_memory
,
1869 .remove_memory
= agp_generic_remove_memory
,
1870 .alloc_by_type
= agp_generic_alloc_by_type
,
1871 .free_by_type
= agp_generic_free_by_type
,
1872 .agp_alloc_page
= agp_generic_alloc_page
,
1873 .agp_alloc_pages
= agp_generic_alloc_pages
,
1874 .agp_destroy_page
= agp_generic_destroy_page
,
1875 .agp_destroy_pages
= agp_generic_destroy_pages
,
1876 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1879 static const struct agp_bridge_driver intel_845_driver
= {
1880 .owner
= THIS_MODULE
,
1881 .aperture_sizes
= intel_8xx_sizes
,
1882 .size_type
= U8_APER_SIZE
,
1883 .num_aperture_sizes
= 7,
1884 .configure
= intel_845_configure
,
1885 .fetch_size
= intel_8xx_fetch_size
,
1886 .cleanup
= intel_8xx_cleanup
,
1887 .tlb_flush
= intel_8xx_tlbflush
,
1888 .mask_memory
= agp_generic_mask_memory
,
1889 .masks
= intel_generic_masks
,
1890 .agp_enable
= agp_generic_enable
,
1891 .cache_flush
= global_cache_flush
,
1892 .create_gatt_table
= agp_generic_create_gatt_table
,
1893 .free_gatt_table
= agp_generic_free_gatt_table
,
1894 .insert_memory
= agp_generic_insert_memory
,
1895 .remove_memory
= agp_generic_remove_memory
,
1896 .alloc_by_type
= agp_generic_alloc_by_type
,
1897 .free_by_type
= agp_generic_free_by_type
,
1898 .agp_alloc_page
= agp_generic_alloc_page
,
1899 .agp_alloc_pages
= agp_generic_alloc_pages
,
1900 .agp_destroy_page
= agp_generic_destroy_page
,
1901 .agp_destroy_pages
= agp_generic_destroy_pages
,
1902 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1903 .chipset_flush
= intel_i830_chipset_flush
,
1906 static const struct agp_bridge_driver intel_850_driver
= {
1907 .owner
= THIS_MODULE
,
1908 .aperture_sizes
= intel_8xx_sizes
,
1909 .size_type
= U8_APER_SIZE
,
1910 .num_aperture_sizes
= 7,
1911 .configure
= intel_850_configure
,
1912 .fetch_size
= intel_8xx_fetch_size
,
1913 .cleanup
= intel_8xx_cleanup
,
1914 .tlb_flush
= intel_8xx_tlbflush
,
1915 .mask_memory
= agp_generic_mask_memory
,
1916 .masks
= intel_generic_masks
,
1917 .agp_enable
= agp_generic_enable
,
1918 .cache_flush
= global_cache_flush
,
1919 .create_gatt_table
= agp_generic_create_gatt_table
,
1920 .free_gatt_table
= agp_generic_free_gatt_table
,
1921 .insert_memory
= agp_generic_insert_memory
,
1922 .remove_memory
= agp_generic_remove_memory
,
1923 .alloc_by_type
= agp_generic_alloc_by_type
,
1924 .free_by_type
= agp_generic_free_by_type
,
1925 .agp_alloc_page
= agp_generic_alloc_page
,
1926 .agp_alloc_pages
= agp_generic_alloc_pages
,
1927 .agp_destroy_page
= agp_generic_destroy_page
,
1928 .agp_destroy_pages
= agp_generic_destroy_pages
,
1929 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1932 static const struct agp_bridge_driver intel_860_driver
= {
1933 .owner
= THIS_MODULE
,
1934 .aperture_sizes
= intel_8xx_sizes
,
1935 .size_type
= U8_APER_SIZE
,
1936 .num_aperture_sizes
= 7,
1937 .configure
= intel_860_configure
,
1938 .fetch_size
= intel_8xx_fetch_size
,
1939 .cleanup
= intel_8xx_cleanup
,
1940 .tlb_flush
= intel_8xx_tlbflush
,
1941 .mask_memory
= agp_generic_mask_memory
,
1942 .masks
= intel_generic_masks
,
1943 .agp_enable
= agp_generic_enable
,
1944 .cache_flush
= global_cache_flush
,
1945 .create_gatt_table
= agp_generic_create_gatt_table
,
1946 .free_gatt_table
= agp_generic_free_gatt_table
,
1947 .insert_memory
= agp_generic_insert_memory
,
1948 .remove_memory
= agp_generic_remove_memory
,
1949 .alloc_by_type
= agp_generic_alloc_by_type
,
1950 .free_by_type
= agp_generic_free_by_type
,
1951 .agp_alloc_page
= agp_generic_alloc_page
,
1952 .agp_alloc_pages
= agp_generic_alloc_pages
,
1953 .agp_destroy_page
= agp_generic_destroy_page
,
1954 .agp_destroy_pages
= agp_generic_destroy_pages
,
1955 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1958 static const struct agp_bridge_driver intel_915_driver
= {
1959 .owner
= THIS_MODULE
,
1960 .aperture_sizes
= intel_i830_sizes
,
1961 .size_type
= FIXED_APER_SIZE
,
1962 .num_aperture_sizes
= 4,
1963 .needs_scratch_page
= true,
1964 .configure
= intel_i915_configure
,
1965 .fetch_size
= intel_i9xx_fetch_size
,
1966 .cleanup
= intel_i915_cleanup
,
1967 .tlb_flush
= intel_i810_tlbflush
,
1968 .mask_memory
= intel_i810_mask_memory
,
1969 .masks
= intel_i810_masks
,
1970 .agp_enable
= intel_i810_agp_enable
,
1971 .cache_flush
= global_cache_flush
,
1972 .create_gatt_table
= intel_i915_create_gatt_table
,
1973 .free_gatt_table
= intel_i830_free_gatt_table
,
1974 .insert_memory
= intel_i915_insert_entries
,
1975 .remove_memory
= intel_i915_remove_entries
,
1976 .alloc_by_type
= intel_i830_alloc_by_type
,
1977 .free_by_type
= intel_i810_free_by_type
,
1978 .agp_alloc_page
= agp_generic_alloc_page
,
1979 .agp_alloc_pages
= agp_generic_alloc_pages
,
1980 .agp_destroy_page
= agp_generic_destroy_page
,
1981 .agp_destroy_pages
= agp_generic_destroy_pages
,
1982 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1983 .chipset_flush
= intel_i915_chipset_flush
,
1986 static const struct agp_bridge_driver intel_i965_driver
= {
1987 .owner
= THIS_MODULE
,
1988 .aperture_sizes
= intel_i830_sizes
,
1989 .size_type
= FIXED_APER_SIZE
,
1990 .num_aperture_sizes
= 4,
1991 .needs_scratch_page
= true,
1992 .configure
= intel_i915_configure
,
1993 .fetch_size
= intel_i9xx_fetch_size
,
1994 .cleanup
= intel_i915_cleanup
,
1995 .tlb_flush
= intel_i810_tlbflush
,
1996 .mask_memory
= intel_i965_mask_memory
,
1997 .masks
= intel_i810_masks
,
1998 .agp_enable
= intel_i810_agp_enable
,
1999 .cache_flush
= global_cache_flush
,
2000 .create_gatt_table
= intel_i965_create_gatt_table
,
2001 .free_gatt_table
= intel_i830_free_gatt_table
,
2002 .insert_memory
= intel_i915_insert_entries
,
2003 .remove_memory
= intel_i915_remove_entries
,
2004 .alloc_by_type
= intel_i830_alloc_by_type
,
2005 .free_by_type
= intel_i810_free_by_type
,
2006 .agp_alloc_page
= agp_generic_alloc_page
,
2007 .agp_alloc_pages
= agp_generic_alloc_pages
,
2008 .agp_destroy_page
= agp_generic_destroy_page
,
2009 .agp_destroy_pages
= agp_generic_destroy_pages
,
2010 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
2011 .chipset_flush
= intel_i915_chipset_flush
,
2014 static const struct agp_bridge_driver intel_7505_driver
= {
2015 .owner
= THIS_MODULE
,
2016 .aperture_sizes
= intel_8xx_sizes
,
2017 .size_type
= U8_APER_SIZE
,
2018 .num_aperture_sizes
= 7,
2019 .configure
= intel_7505_configure
,
2020 .fetch_size
= intel_8xx_fetch_size
,
2021 .cleanup
= intel_8xx_cleanup
,
2022 .tlb_flush
= intel_8xx_tlbflush
,
2023 .mask_memory
= agp_generic_mask_memory
,
2024 .masks
= intel_generic_masks
,
2025 .agp_enable
= agp_generic_enable
,
2026 .cache_flush
= global_cache_flush
,
2027 .create_gatt_table
= agp_generic_create_gatt_table
,
2028 .free_gatt_table
= agp_generic_free_gatt_table
,
2029 .insert_memory
= agp_generic_insert_memory
,
2030 .remove_memory
= agp_generic_remove_memory
,
2031 .alloc_by_type
= agp_generic_alloc_by_type
,
2032 .free_by_type
= agp_generic_free_by_type
,
2033 .agp_alloc_page
= agp_generic_alloc_page
,
2034 .agp_alloc_pages
= agp_generic_alloc_pages
,
2035 .agp_destroy_page
= agp_generic_destroy_page
,
2036 .agp_destroy_pages
= agp_generic_destroy_pages
,
2037 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
2040 static const struct agp_bridge_driver intel_g33_driver
= {
2041 .owner
= THIS_MODULE
,
2042 .aperture_sizes
= intel_i830_sizes
,
2043 .size_type
= FIXED_APER_SIZE
,
2044 .num_aperture_sizes
= 4,
2045 .needs_scratch_page
= true,
2046 .configure
= intel_i915_configure
,
2047 .fetch_size
= intel_i9xx_fetch_size
,
2048 .cleanup
= intel_i915_cleanup
,
2049 .tlb_flush
= intel_i810_tlbflush
,
2050 .mask_memory
= intel_i965_mask_memory
,
2051 .masks
= intel_i810_masks
,
2052 .agp_enable
= intel_i810_agp_enable
,
2053 .cache_flush
= global_cache_flush
,
2054 .create_gatt_table
= intel_i915_create_gatt_table
,
2055 .free_gatt_table
= intel_i830_free_gatt_table
,
2056 .insert_memory
= intel_i915_insert_entries
,
2057 .remove_memory
= intel_i915_remove_entries
,
2058 .alloc_by_type
= intel_i830_alloc_by_type
,
2059 .free_by_type
= intel_i810_free_by_type
,
2060 .agp_alloc_page
= agp_generic_alloc_page
,
2061 .agp_alloc_pages
= agp_generic_alloc_pages
,
2062 .agp_destroy_page
= agp_generic_destroy_page
,
2063 .agp_destroy_pages
= agp_generic_destroy_pages
,
2064 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
2065 .chipset_flush
= intel_i915_chipset_flush
,
2068 static int find_gmch(u16 device
)
2070 struct pci_dev
*gmch_device
;
2072 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
, device
, NULL
);
2073 if (gmch_device
&& PCI_FUNC(gmch_device
->devfn
) != 0) {
2074 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
,
2075 device
, gmch_device
);
2081 intel_private
.pcidev
= gmch_device
;
2085 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2086 * driver and gmch_driver must be non-null, and find_gmch will determine
2087 * which one should be used if a gmch_chip_id is present.
2089 static const struct intel_driver_description
{
2090 unsigned int chip_id
;
2091 unsigned int gmch_chip_id
;
2092 unsigned int multi_gmch_chip
; /* if we have more gfx chip type on this HB. */
2094 const struct agp_bridge_driver
*driver
;
2095 const struct agp_bridge_driver
*gmch_driver
;
2096 } intel_agp_chipsets
[] = {
2097 { PCI_DEVICE_ID_INTEL_82443LX_0
, 0, 0, "440LX", &intel_generic_driver
, NULL
},
2098 { PCI_DEVICE_ID_INTEL_82443BX_0
, 0, 0, "440BX", &intel_generic_driver
, NULL
},
2099 { PCI_DEVICE_ID_INTEL_82443GX_0
, 0, 0, "440GX", &intel_generic_driver
, NULL
},
2100 { PCI_DEVICE_ID_INTEL_82810_MC1
, PCI_DEVICE_ID_INTEL_82810_IG1
, 0, "i810",
2101 NULL
, &intel_810_driver
},
2102 { PCI_DEVICE_ID_INTEL_82810_MC3
, PCI_DEVICE_ID_INTEL_82810_IG3
, 0, "i810",
2103 NULL
, &intel_810_driver
},
2104 { PCI_DEVICE_ID_INTEL_82810E_MC
, PCI_DEVICE_ID_INTEL_82810E_IG
, 0, "i810",
2105 NULL
, &intel_810_driver
},
2106 { PCI_DEVICE_ID_INTEL_82815_MC
, PCI_DEVICE_ID_INTEL_82815_CGC
, 0, "i815",
2107 &intel_815_driver
, &intel_810_driver
},
2108 { PCI_DEVICE_ID_INTEL_82820_HB
, 0, 0, "i820", &intel_820_driver
, NULL
},
2109 { PCI_DEVICE_ID_INTEL_82820_UP_HB
, 0, 0, "i820", &intel_820_driver
, NULL
},
2110 { PCI_DEVICE_ID_INTEL_82830_HB
, PCI_DEVICE_ID_INTEL_82830_CGC
, 0, "830M",
2111 &intel_830mp_driver
, &intel_830_driver
},
2112 { PCI_DEVICE_ID_INTEL_82840_HB
, 0, 0, "i840", &intel_840_driver
, NULL
},
2113 { PCI_DEVICE_ID_INTEL_82845_HB
, 0, 0, "845G", &intel_845_driver
, NULL
},
2114 { PCI_DEVICE_ID_INTEL_82845G_HB
, PCI_DEVICE_ID_INTEL_82845G_IG
, 0, "830M",
2115 &intel_845_driver
, &intel_830_driver
},
2116 { PCI_DEVICE_ID_INTEL_82850_HB
, 0, 0, "i850", &intel_850_driver
, NULL
},
2117 { PCI_DEVICE_ID_INTEL_82855PM_HB
, 0, 0, "855PM", &intel_845_driver
, NULL
},
2118 { PCI_DEVICE_ID_INTEL_82855GM_HB
, PCI_DEVICE_ID_INTEL_82855GM_IG
, 0, "855GM",
2119 &intel_845_driver
, &intel_830_driver
},
2120 { PCI_DEVICE_ID_INTEL_82860_HB
, 0, 0, "i860", &intel_860_driver
, NULL
},
2121 { PCI_DEVICE_ID_INTEL_82865_HB
, PCI_DEVICE_ID_INTEL_82865_IG
, 0, "865",
2122 &intel_845_driver
, &intel_830_driver
},
2123 { PCI_DEVICE_ID_INTEL_82875_HB
, 0, 0, "i875", &intel_845_driver
, NULL
},
2124 { PCI_DEVICE_ID_INTEL_E7221_HB
, PCI_DEVICE_ID_INTEL_E7221_IG
, 0, "E7221 (i915)",
2125 NULL
, &intel_915_driver
},
2126 { PCI_DEVICE_ID_INTEL_82915G_HB
, PCI_DEVICE_ID_INTEL_82915G_IG
, 0, "915G",
2127 NULL
, &intel_915_driver
},
2128 { PCI_DEVICE_ID_INTEL_82915GM_HB
, PCI_DEVICE_ID_INTEL_82915GM_IG
, 0, "915GM",
2129 NULL
, &intel_915_driver
},
2130 { PCI_DEVICE_ID_INTEL_82945G_HB
, PCI_DEVICE_ID_INTEL_82945G_IG
, 0, "945G",
2131 NULL
, &intel_915_driver
},
2132 { PCI_DEVICE_ID_INTEL_82945GM_HB
, PCI_DEVICE_ID_INTEL_82945GM_IG
, 0, "945GM",
2133 NULL
, &intel_915_driver
},
2134 { PCI_DEVICE_ID_INTEL_82945GME_HB
, PCI_DEVICE_ID_INTEL_82945GME_IG
, 0, "945GME",
2135 NULL
, &intel_915_driver
},
2136 { PCI_DEVICE_ID_INTEL_82946GZ_HB
, PCI_DEVICE_ID_INTEL_82946GZ_IG
, 0, "946GZ",
2137 NULL
, &intel_i965_driver
},
2138 { PCI_DEVICE_ID_INTEL_82G35_HB
, PCI_DEVICE_ID_INTEL_82G35_IG
, 0, "G35",
2139 NULL
, &intel_i965_driver
},
2140 { PCI_DEVICE_ID_INTEL_82965Q_HB
, PCI_DEVICE_ID_INTEL_82965Q_IG
, 0, "965Q",
2141 NULL
, &intel_i965_driver
},
2142 { PCI_DEVICE_ID_INTEL_82965G_HB
, PCI_DEVICE_ID_INTEL_82965G_IG
, 0, "965G",
2143 NULL
, &intel_i965_driver
},
2144 { PCI_DEVICE_ID_INTEL_82965GM_HB
, PCI_DEVICE_ID_INTEL_82965GM_IG
, 0, "965GM",
2145 NULL
, &intel_i965_driver
},
2146 { PCI_DEVICE_ID_INTEL_82965GME_HB
, PCI_DEVICE_ID_INTEL_82965GME_IG
, 0, "965GME/GLE",
2147 NULL
, &intel_i965_driver
},
2148 { PCI_DEVICE_ID_INTEL_7505_0
, 0, 0, "E7505", &intel_7505_driver
, NULL
},
2149 { PCI_DEVICE_ID_INTEL_7205_0
, 0, 0, "E7205", &intel_7505_driver
, NULL
},
2150 { PCI_DEVICE_ID_INTEL_G33_HB
, PCI_DEVICE_ID_INTEL_G33_IG
, 0, "G33",
2151 NULL
, &intel_g33_driver
},
2152 { PCI_DEVICE_ID_INTEL_Q35_HB
, PCI_DEVICE_ID_INTEL_Q35_IG
, 0, "Q35",
2153 NULL
, &intel_g33_driver
},
2154 { PCI_DEVICE_ID_INTEL_Q33_HB
, PCI_DEVICE_ID_INTEL_Q33_IG
, 0, "Q33",
2155 NULL
, &intel_g33_driver
},
2156 { PCI_DEVICE_ID_INTEL_GM45_HB
, PCI_DEVICE_ID_INTEL_GM45_IG
, 0,
2157 "Mobile Intel? GM45 Express", NULL
, &intel_i965_driver
},
2158 { PCI_DEVICE_ID_INTEL_IGD_E_HB
, PCI_DEVICE_ID_INTEL_IGD_E_IG
, 0,
2159 "Intel Integrated Graphics Device", NULL
, &intel_i965_driver
},
2160 { PCI_DEVICE_ID_INTEL_Q45_HB
, PCI_DEVICE_ID_INTEL_Q45_IG
, 0,
2161 "Q45/Q43", NULL
, &intel_i965_driver
},
2162 { PCI_DEVICE_ID_INTEL_G45_HB
, PCI_DEVICE_ID_INTEL_G45_IG
, 0,
2163 "G45/G43", NULL
, &intel_i965_driver
},
2164 { 0, 0, 0, NULL
, NULL
, NULL
}
2167 static int __devinit
agp_intel_probe(struct pci_dev
*pdev
,
2168 const struct pci_device_id
*ent
)
2170 struct agp_bridge_data
*bridge
;
2175 cap_ptr
= pci_find_capability(pdev
, PCI_CAP_ID_AGP
);
2177 bridge
= agp_alloc_bridge();
2181 for (i
= 0; intel_agp_chipsets
[i
].name
!= NULL
; i
++) {
2182 /* In case that multiple models of gfx chip may
2183 stand on same host bridge type, this can be
2184 sure we detect the right IGD. */
2185 if (pdev
->device
== intel_agp_chipsets
[i
].chip_id
) {
2186 if ((intel_agp_chipsets
[i
].gmch_chip_id
!= 0) &&
2187 find_gmch(intel_agp_chipsets
[i
].gmch_chip_id
)) {
2189 intel_agp_chipsets
[i
].gmch_driver
;
2191 } else if (intel_agp_chipsets
[i
].multi_gmch_chip
) {
2194 bridge
->driver
= intel_agp_chipsets
[i
].driver
;
2200 if (intel_agp_chipsets
[i
].name
== NULL
) {
2202 dev_warn(&pdev
->dev
, "unsupported Intel chipset [%04x/%04x]\n",
2203 pdev
->vendor
, pdev
->device
);
2204 agp_put_bridge(bridge
);
2208 if (bridge
->driver
== NULL
) {
2209 /* bridge has no AGP and no IGD detected */
2211 dev_warn(&pdev
->dev
, "can't find bridge device (chip_id: %04x)\n",
2212 intel_agp_chipsets
[i
].gmch_chip_id
);
2213 agp_put_bridge(bridge
);
2218 bridge
->capndx
= cap_ptr
;
2219 bridge
->dev_private_data
= &intel_private
;
2221 dev_info(&pdev
->dev
, "Intel %s Chipset\n", intel_agp_chipsets
[i
].name
);
2224 * The following fixes the case where the BIOS has "forgotten" to
2225 * provide an address range for the GART.
2226 * 20030610 - hamish@zot.org
2228 r
= &pdev
->resource
[0];
2229 if (!r
->start
&& r
->end
) {
2230 if (pci_assign_resource(pdev
, 0)) {
2231 dev_err(&pdev
->dev
, "can't assign resource 0\n");
2232 agp_put_bridge(bridge
);
2238 * If the device has not been properly setup, the following will catch
2239 * the problem and should stop the system from crashing.
2240 * 20030610 - hamish@zot.org
2242 if (pci_enable_device(pdev
)) {
2243 dev_err(&pdev
->dev
, "can't enable PCI device\n");
2244 agp_put_bridge(bridge
);
2248 /* Fill in the mode register */
2250 pci_read_config_dword(pdev
,
2251 bridge
->capndx
+PCI_AGP_STATUS
,
2255 pci_set_drvdata(pdev
, bridge
);
2256 return agp_add_bridge(bridge
);
2259 static void __devexit
agp_intel_remove(struct pci_dev
*pdev
)
2261 struct agp_bridge_data
*bridge
= pci_get_drvdata(pdev
);
2263 agp_remove_bridge(bridge
);
2265 if (intel_private
.pcidev
)
2266 pci_dev_put(intel_private
.pcidev
);
2268 agp_put_bridge(bridge
);
2272 static int agp_intel_resume(struct pci_dev
*pdev
)
2274 struct agp_bridge_data
*bridge
= pci_get_drvdata(pdev
);
2277 pci_restore_state(pdev
);
2279 /* We should restore our graphics device's config space,
2280 * as host bridge (00:00) resumes before graphics device (02:00),
2281 * then our access to its pci space can work right.
2283 if (intel_private
.pcidev
)
2284 pci_restore_state(intel_private
.pcidev
);
2286 if (bridge
->driver
== &intel_generic_driver
)
2288 else if (bridge
->driver
== &intel_850_driver
)
2289 intel_850_configure();
2290 else if (bridge
->driver
== &intel_845_driver
)
2291 intel_845_configure();
2292 else if (bridge
->driver
== &intel_830mp_driver
)
2293 intel_830mp_configure();
2294 else if (bridge
->driver
== &intel_915_driver
)
2295 intel_i915_configure();
2296 else if (bridge
->driver
== &intel_830_driver
)
2297 intel_i830_configure();
2298 else if (bridge
->driver
== &intel_810_driver
)
2299 intel_i810_configure();
2300 else if (bridge
->driver
== &intel_i965_driver
)
2301 intel_i915_configure();
2303 ret_val
= agp_rebind_memory();
2311 static struct pci_device_id agp_intel_pci_table
[] = {
2314 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2316 .vendor = PCI_VENDOR_ID_INTEL, \
2318 .subvendor = PCI_ANY_ID, \
2319 .subdevice = PCI_ANY_ID, \
2321 ID(PCI_DEVICE_ID_INTEL_82443LX_0
),
2322 ID(PCI_DEVICE_ID_INTEL_82443BX_0
),
2323 ID(PCI_DEVICE_ID_INTEL_82443GX_0
),
2324 ID(PCI_DEVICE_ID_INTEL_82810_MC1
),
2325 ID(PCI_DEVICE_ID_INTEL_82810_MC3
),
2326 ID(PCI_DEVICE_ID_INTEL_82810E_MC
),
2327 ID(PCI_DEVICE_ID_INTEL_82815_MC
),
2328 ID(PCI_DEVICE_ID_INTEL_82820_HB
),
2329 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB
),
2330 ID(PCI_DEVICE_ID_INTEL_82830_HB
),
2331 ID(PCI_DEVICE_ID_INTEL_82840_HB
),
2332 ID(PCI_DEVICE_ID_INTEL_82845_HB
),
2333 ID(PCI_DEVICE_ID_INTEL_82845G_HB
),
2334 ID(PCI_DEVICE_ID_INTEL_82850_HB
),
2335 ID(PCI_DEVICE_ID_INTEL_82855PM_HB
),
2336 ID(PCI_DEVICE_ID_INTEL_82855GM_HB
),
2337 ID(PCI_DEVICE_ID_INTEL_82860_HB
),
2338 ID(PCI_DEVICE_ID_INTEL_82865_HB
),
2339 ID(PCI_DEVICE_ID_INTEL_82875_HB
),
2340 ID(PCI_DEVICE_ID_INTEL_7505_0
),
2341 ID(PCI_DEVICE_ID_INTEL_7205_0
),
2342 ID(PCI_DEVICE_ID_INTEL_E7221_HB
),
2343 ID(PCI_DEVICE_ID_INTEL_82915G_HB
),
2344 ID(PCI_DEVICE_ID_INTEL_82915GM_HB
),
2345 ID(PCI_DEVICE_ID_INTEL_82945G_HB
),
2346 ID(PCI_DEVICE_ID_INTEL_82945GM_HB
),
2347 ID(PCI_DEVICE_ID_INTEL_82945GME_HB
),
2348 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB
),
2349 ID(PCI_DEVICE_ID_INTEL_82G35_HB
),
2350 ID(PCI_DEVICE_ID_INTEL_82965Q_HB
),
2351 ID(PCI_DEVICE_ID_INTEL_82965G_HB
),
2352 ID(PCI_DEVICE_ID_INTEL_82965GM_HB
),
2353 ID(PCI_DEVICE_ID_INTEL_82965GME_HB
),
2354 ID(PCI_DEVICE_ID_INTEL_G33_HB
),
2355 ID(PCI_DEVICE_ID_INTEL_Q35_HB
),
2356 ID(PCI_DEVICE_ID_INTEL_Q33_HB
),
2357 ID(PCI_DEVICE_ID_INTEL_GM45_HB
),
2358 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB
),
2359 ID(PCI_DEVICE_ID_INTEL_Q45_HB
),
2360 ID(PCI_DEVICE_ID_INTEL_G45_HB
),
2364 MODULE_DEVICE_TABLE(pci
, agp_intel_pci_table
);
2366 static struct pci_driver agp_intel_pci_driver
= {
2367 .name
= "agpgart-intel",
2368 .id_table
= agp_intel_pci_table
,
2369 .probe
= agp_intel_probe
,
2370 .remove
= __devexit_p(agp_intel_remove
),
2372 .resume
= agp_intel_resume
,
2376 static int __init
agp_intel_init(void)
2380 return pci_register_driver(&agp_intel_pci_driver
);
2383 static void __exit
agp_intel_cleanup(void)
2385 pci_unregister_driver(&agp_intel_pci_driver
);
2388 module_init(agp_intel_init
);
2389 module_exit(agp_intel_cleanup
);
2391 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2392 MODULE_LICENSE("GPL and additional rights");