2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 # define BREAKPOINT() asm(" int $3");
32 # define BREAKPOINT() { }
35 #define MAX_DEVICES 12
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
60 #include <asm/system.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
70 #ifdef CONFIG_HDLC_MODULE
74 #define GET_USER(error,value,addr) error = get_user(value,addr)
75 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
76 #define PUT_USER(error,value,addr) error = put_user(value,addr)
77 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
79 #include <asm/uaccess.h>
81 #include "linux/synclink.h"
83 static MGSL_PARAMS default_params
= {
84 MGSL_MODE_HDLC
, /* unsigned long mode */
85 0, /* unsigned char loopback; */
86 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
87 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
88 0, /* unsigned long clock_speed; */
89 0xff, /* unsigned char addr_filter; */
90 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
91 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
92 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
93 9600, /* unsigned long data_rate; */
94 8, /* unsigned char data_bits; */
95 1, /* unsigned char stop_bits; */
96 ASYNC_PARITY_NONE
/* unsigned char parity; */
99 /* size in bytes of DMA data buffers */
100 #define SCABUFSIZE 1024
101 #define SCA_MEM_SIZE 0x40000
102 #define SCA_BASE_SIZE 512
103 #define SCA_REG_SIZE 16
104 #define SCA_MAX_PORTS 4
105 #define SCAMAXDESC 128
107 #define BUFFERLISTSIZE 4096
109 /* SCA-I style DMA buffer descriptor */
110 typedef struct _SCADESC
112 u16 next
; /* lower l6 bits of next descriptor addr */
113 u16 buf_ptr
; /* lower 16 bits of buffer addr */
114 u8 buf_base
; /* upper 8 bits of buffer addr */
116 u16 length
; /* length of buffer */
117 u8 status
; /* status of buffer */
119 } SCADESC
, *PSCADESC
;
121 typedef struct _SCADESC_EX
123 /* device driver bookkeeping section */
124 char *virt_addr
; /* virtual address of data buffer */
125 u16 phys_entry
; /* lower 16-bits of physical address of this descriptor */
126 } SCADESC_EX
, *PSCADESC_EX
;
128 /* The queue of BH actions to be performed */
131 #define BH_TRANSMIT 2
134 #define IO_PIN_SHUTDOWN_LIMIT 100
136 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
138 struct _input_signal_events
{
150 * Device instance data structure
152 typedef struct _synclinkmp_info
{
153 void *if_ptr
; /* General purpose pointer (used by SPPP) */
156 int count
; /* count of opens */
158 unsigned short close_delay
;
159 unsigned short closing_wait
; /* time to wait before closing */
161 struct mgsl_icount icount
;
163 struct tty_struct
*tty
;
165 int x_char
; /* xon/xoff character */
166 int blocked_open
; /* # of blocked opens */
167 u16 read_status_mask1
; /* break detection (SR1 indications) */
168 u16 read_status_mask2
; /* parity/framing/overun (SR2 indications) */
169 unsigned char ignore_status_mask1
; /* break detection (SR1 indications) */
170 unsigned char ignore_status_mask2
; /* parity/framing/overun (SR2 indications) */
171 unsigned char *tx_buf
;
176 wait_queue_head_t open_wait
;
177 wait_queue_head_t close_wait
;
179 wait_queue_head_t status_event_wait_q
;
180 wait_queue_head_t event_wait_q
;
181 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
182 struct _synclinkmp_info
*next_device
; /* device list link */
183 struct timer_list status_timer
; /* input signal status check timer */
185 spinlock_t lock
; /* spinlock for synchronizing with ISR */
186 struct work_struct task
; /* task structure for scheduling bh */
188 u32 max_frame_size
; /* as set by device config */
192 int bh_running
; /* Protection from multiple */
196 int dcd_chkcount
; /* check counts to prevent */
197 int cts_chkcount
; /* too many IRQs if a signal */
198 int dsr_chkcount
; /* is floating */
201 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
202 unsigned long buffer_list_phys
;
204 unsigned int rx_buf_count
; /* count of total allocated Rx buffers */
205 SCADESC
*rx_buf_list
; /* list of receive buffer entries */
206 SCADESC_EX rx_buf_list_ex
[SCAMAXDESC
]; /* list of receive buffer entries */
207 unsigned int current_rx_buf
;
209 unsigned int tx_buf_count
; /* count of total allocated Tx buffers */
210 SCADESC
*tx_buf_list
; /* list of transmit buffer entries */
211 SCADESC_EX tx_buf_list_ex
[SCAMAXDESC
]; /* list of transmit buffer entries */
212 unsigned int last_tx_buf
;
214 unsigned char *tmp_rx_buf
;
215 unsigned int tmp_rx_buf_count
;
224 unsigned char ie0_value
;
225 unsigned char ie1_value
;
226 unsigned char ie2_value
;
227 unsigned char ctrlreg_value
;
228 unsigned char old_signals
;
230 char device_name
[25]; /* device instance name */
236 struct _synclinkmp_info
*port_array
[SCA_MAX_PORTS
];
238 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
240 unsigned int irq_level
; /* interrupt level */
241 unsigned long irq_flags
;
242 int irq_requested
; /* nonzero if IRQ requested */
244 MGSL_PARAMS params
; /* communications parameters */
246 unsigned char serial_signals
; /* current serial signal states */
248 int irq_occurred
; /* for diagnostics use */
249 unsigned int init_error
; /* Initialization startup error */
252 unsigned char* memory_base
; /* shared memory address (PCI only) */
253 u32 phys_memory_base
;
254 int shared_mem_requested
;
256 unsigned char* sca_base
; /* HD64570 SCA Memory address */
259 int sca_base_requested
;
261 unsigned char* lcr_base
; /* local config registers (PCI only) */
264 int lcr_mem_requested
;
266 unsigned char* statctrl_base
; /* status/control register memory */
267 u32 phys_statctrl_base
;
269 int sca_statctrl_requested
;
272 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
273 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
274 BOOLEAN drop_rts_on_tx_done
;
276 struct _input_signal_events input_signal_events
;
278 /* SPPP/Cisco HDLC device parts */
284 struct net_device
*netdev
;
289 #define MGSL_MAGIC 0x5401
292 * define serial signal status change macros
294 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
295 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
296 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
297 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
299 /* Common Register macros */
318 /* MSCI Register macros */
348 /* Timer Register Macros */
358 /* DMA Controller Register macros */
389 /* combine with timer or DMA register address */
397 /* SCA Command Codes */
400 #define TXENABLE 0x02
401 #define TXDISABLE 0x03
402 #define TXCRCINIT 0x04
403 #define TXCRCEXCL 0x05
407 #define TXBUFCLR 0x09
409 #define RXENABLE 0x12
410 #define RXDISABLE 0x13
411 #define RXCRCINIT 0x14
412 #define RXREJECT 0x15
413 #define SEARCHMP 0x16
414 #define RXCRCEXCL 0x17
415 #define RXCRCCALC 0x18
419 /* DMA command codes */
421 #define FEICLEAR 0x02
455 * Global linked list of SyncLink devices
457 static SLMP_INFO
*synclinkmp_device_list
= NULL
;
458 static int synclinkmp_adapter_count
= -1;
459 static int synclinkmp_device_count
= 0;
462 * Set this param to non-zero to load eax with the
463 * .text section address and breakpoint on module load.
464 * This is useful for use with gdb and add-symbol-file command.
466 static int break_on_load
=0;
469 * Driver major number, defaults to zero to get auto
470 * assigned major number. May be forced as module parameter.
472 static int ttymajor
=0;
475 * Array of user specified options for ISA adapters.
477 static int debug_level
= 0;
478 static int maxframe
[MAX_DEVICES
] = {0,};
479 static int dosyncppp
[MAX_DEVICES
] = {0,};
481 module_param(break_on_load
, bool, 0);
482 module_param(ttymajor
, int, 0);
483 module_param(debug_level
, int, 0);
484 module_param_array(maxframe
, int, NULL
, 0);
485 module_param_array(dosyncppp
, int, NULL
, 0);
487 static char *driver_name
= "SyncLink MultiPort driver";
488 static char *driver_version
= "$Revision: 4.38 $";
490 static int synclinkmp_init_one(struct pci_dev
*dev
,const struct pci_device_id
*ent
);
491 static void synclinkmp_remove_one(struct pci_dev
*dev
);
493 static struct pci_device_id synclinkmp_pci_tbl
[] = {
494 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_SCA
, PCI_ANY_ID
, PCI_ANY_ID
, },
495 { 0, }, /* terminate list */
497 MODULE_DEVICE_TABLE(pci
, synclinkmp_pci_tbl
);
499 MODULE_LICENSE("GPL");
501 static struct pci_driver synclinkmp_pci_driver
= {
502 .name
= "synclinkmp",
503 .id_table
= synclinkmp_pci_tbl
,
504 .probe
= synclinkmp_init_one
,
505 .remove
= __devexit_p(synclinkmp_remove_one
),
509 static struct tty_driver
*serial_driver
;
511 /* number of characters left in xmit buffer before we ask for more */
512 #define WAKEUP_CHARS 256
517 static int open(struct tty_struct
*tty
, struct file
* filp
);
518 static void close(struct tty_struct
*tty
, struct file
* filp
);
519 static void hangup(struct tty_struct
*tty
);
520 static void set_termios(struct tty_struct
*tty
, struct termios
*old_termios
);
522 static int write(struct tty_struct
*tty
, const unsigned char *buf
, int count
);
523 static void put_char(struct tty_struct
*tty
, unsigned char ch
);
524 static void send_xchar(struct tty_struct
*tty
, char ch
);
525 static void wait_until_sent(struct tty_struct
*tty
, int timeout
);
526 static int write_room(struct tty_struct
*tty
);
527 static void flush_chars(struct tty_struct
*tty
);
528 static void flush_buffer(struct tty_struct
*tty
);
529 static void tx_hold(struct tty_struct
*tty
);
530 static void tx_release(struct tty_struct
*tty
);
532 static int ioctl(struct tty_struct
*tty
, struct file
*file
, unsigned int cmd
, unsigned long arg
);
533 static int read_proc(char *page
, char **start
, off_t off
, int count
,int *eof
, void *data
);
534 static int chars_in_buffer(struct tty_struct
*tty
);
535 static void throttle(struct tty_struct
* tty
);
536 static void unthrottle(struct tty_struct
* tty
);
537 static void set_break(struct tty_struct
*tty
, int break_state
);
540 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
541 static void hdlcdev_tx_done(SLMP_INFO
*info
);
542 static void hdlcdev_rx(SLMP_INFO
*info
, char *buf
, int size
);
543 static int hdlcdev_init(SLMP_INFO
*info
);
544 static void hdlcdev_exit(SLMP_INFO
*info
);
549 static int get_stats(SLMP_INFO
*info
, struct mgsl_icount __user
*user_icount
);
550 static int get_params(SLMP_INFO
*info
, MGSL_PARAMS __user
*params
);
551 static int set_params(SLMP_INFO
*info
, MGSL_PARAMS __user
*params
);
552 static int get_txidle(SLMP_INFO
*info
, int __user
*idle_mode
);
553 static int set_txidle(SLMP_INFO
*info
, int idle_mode
);
554 static int tx_enable(SLMP_INFO
*info
, int enable
);
555 static int tx_abort(SLMP_INFO
*info
);
556 static int rx_enable(SLMP_INFO
*info
, int enable
);
557 static int modem_input_wait(SLMP_INFO
*info
,int arg
);
558 static int wait_mgsl_event(SLMP_INFO
*info
, int __user
*mask_ptr
);
559 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
560 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
561 unsigned int set
, unsigned int clear
);
562 static void set_break(struct tty_struct
*tty
, int break_state
);
564 static void add_device(SLMP_INFO
*info
);
565 static void device_init(int adapter_num
, struct pci_dev
*pdev
);
566 static int claim_resources(SLMP_INFO
*info
);
567 static void release_resources(SLMP_INFO
*info
);
569 static int startup(SLMP_INFO
*info
);
570 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,SLMP_INFO
*info
);
571 static void shutdown(SLMP_INFO
*info
);
572 static void program_hw(SLMP_INFO
*info
);
573 static void change_params(SLMP_INFO
*info
);
575 static int init_adapter(SLMP_INFO
*info
);
576 static int register_test(SLMP_INFO
*info
);
577 static int irq_test(SLMP_INFO
*info
);
578 static int loopback_test(SLMP_INFO
*info
);
579 static int adapter_test(SLMP_INFO
*info
);
580 static int memory_test(SLMP_INFO
*info
);
582 static void reset_adapter(SLMP_INFO
*info
);
583 static void reset_port(SLMP_INFO
*info
);
584 static void async_mode(SLMP_INFO
*info
);
585 static void hdlc_mode(SLMP_INFO
*info
);
587 static void rx_stop(SLMP_INFO
*info
);
588 static void rx_start(SLMP_INFO
*info
);
589 static void rx_reset_buffers(SLMP_INFO
*info
);
590 static void rx_free_frame_buffers(SLMP_INFO
*info
, unsigned int first
, unsigned int last
);
591 static int rx_get_frame(SLMP_INFO
*info
);
593 static void tx_start(SLMP_INFO
*info
);
594 static void tx_stop(SLMP_INFO
*info
);
595 static void tx_load_fifo(SLMP_INFO
*info
);
596 static void tx_set_idle(SLMP_INFO
*info
);
597 static void tx_load_dma_buffer(SLMP_INFO
*info
, const char *buf
, unsigned int count
);
599 static void get_signals(SLMP_INFO
*info
);
600 static void set_signals(SLMP_INFO
*info
);
601 static void enable_loopback(SLMP_INFO
*info
, int enable
);
602 static void set_rate(SLMP_INFO
*info
, u32 data_rate
);
604 static int bh_action(SLMP_INFO
*info
);
605 static void bh_handler(void* Context
);
606 static void bh_receive(SLMP_INFO
*info
);
607 static void bh_transmit(SLMP_INFO
*info
);
608 static void bh_status(SLMP_INFO
*info
);
609 static void isr_timer(SLMP_INFO
*info
);
610 static void isr_rxint(SLMP_INFO
*info
);
611 static void isr_rxrdy(SLMP_INFO
*info
);
612 static void isr_txint(SLMP_INFO
*info
);
613 static void isr_txrdy(SLMP_INFO
*info
);
614 static void isr_rxdmaok(SLMP_INFO
*info
);
615 static void isr_rxdmaerror(SLMP_INFO
*info
);
616 static void isr_txdmaok(SLMP_INFO
*info
);
617 static void isr_txdmaerror(SLMP_INFO
*info
);
618 static void isr_io_pin(SLMP_INFO
*info
, u16 status
);
620 static int alloc_dma_bufs(SLMP_INFO
*info
);
621 static void free_dma_bufs(SLMP_INFO
*info
);
622 static int alloc_buf_list(SLMP_INFO
*info
);
623 static int alloc_frame_bufs(SLMP_INFO
*info
, SCADESC
*list
, SCADESC_EX
*list_ex
,int count
);
624 static int alloc_tmp_rx_buf(SLMP_INFO
*info
);
625 static void free_tmp_rx_buf(SLMP_INFO
*info
);
627 static void load_pci_memory(SLMP_INFO
*info
, char* dest
, const char* src
, unsigned short count
);
628 static void trace_block(SLMP_INFO
*info
, const char* data
, int count
, int xmit
);
629 static void tx_timeout(unsigned long context
);
630 static void status_timeout(unsigned long context
);
632 static unsigned char read_reg(SLMP_INFO
*info
, unsigned char addr
);
633 static void write_reg(SLMP_INFO
*info
, unsigned char addr
, unsigned char val
);
634 static u16
read_reg16(SLMP_INFO
*info
, unsigned char addr
);
635 static void write_reg16(SLMP_INFO
*info
, unsigned char addr
, u16 val
);
636 static unsigned char read_status_reg(SLMP_INFO
* info
);
637 static void write_control_reg(SLMP_INFO
* info
);
640 static unsigned char rx_active_fifo_level
= 16; // rx request FIFO activation level in bytes
641 static unsigned char tx_active_fifo_level
= 16; // tx request FIFO activation level in bytes
642 static unsigned char tx_negate_fifo_level
= 32; // tx request FIFO negation level in bytes
644 static u32 misc_ctrl_value
= 0x007e4040;
645 static u32 lcr1_brdr_value
= 0x00800028;
647 static u32 read_ahead_count
= 8;
649 /* DPCR, DMA Priority Control
651 * 07..05 Not used, must be 0
652 * 04 BRC, bus release condition: 0=all transfers complete
653 * 1=release after 1 xfer on all channels
654 * 03 CCC, channel change condition: 0=every cycle
655 * 1=after each channel completes all xfers
656 * 02..00 PR<2..0>, priority 100=round robin
660 static unsigned char dma_priority
= 0x04;
662 // Number of bytes that can be written to shared RAM
663 // in a single write operation
664 static u32 sca_pci_load_interval
= 64;
667 * 1st function defined in .text section. Calling this function in
668 * init_module() followed by a breakpoint allows a remote debugger
669 * (gdb) to get the .text address for the add-symbol-file command.
670 * This allows remote debugging of dynamically loadable modules.
672 static void* synclinkmp_get_text_ptr(void);
673 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr
;}
675 static inline int sanity_check(SLMP_INFO
*info
,
676 char *name
, const char *routine
)
679 static const char *badmagic
=
680 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
681 static const char *badinfo
=
682 "Warning: null synclinkmp_struct for (%s) in %s\n";
685 printk(badinfo
, name
, routine
);
688 if (info
->magic
!= MGSL_MAGIC
) {
689 printk(badmagic
, name
, routine
);
700 * line discipline callback wrappers
702 * The wrappers maintain line discipline references
703 * while calling into the line discipline.
705 * ldisc_receive_buf - pass receive data to line discipline
708 static void ldisc_receive_buf(struct tty_struct
*tty
,
709 const __u8
*data
, char *flags
, int count
)
711 struct tty_ldisc
*ld
;
714 ld
= tty_ldisc_ref(tty
);
717 ld
->receive_buf(tty
, data
, flags
, count
);
724 /* Called when a port is opened. Init and enable port.
726 static int open(struct tty_struct
*tty
, struct file
*filp
)
733 if ((line
< 0) || (line
>= synclinkmp_device_count
)) {
734 printk("%s(%d): open with invalid line #%d.\n",
735 __FILE__
,__LINE__
,line
);
739 info
= synclinkmp_device_list
;
740 while(info
&& info
->line
!= line
)
741 info
= info
->next_device
;
742 if (sanity_check(info
, tty
->name
, "open"))
744 if ( info
->init_error
) {
745 printk("%s(%d):%s device is not allocated, init error=%d\n",
746 __FILE__
,__LINE__
,info
->device_name
,info
->init_error
);
750 tty
->driver_data
= info
;
753 if (debug_level
>= DEBUG_LEVEL_INFO
)
754 printk("%s(%d):%s open(), old ref count = %d\n",
755 __FILE__
,__LINE__
,tty
->driver
->name
, info
->count
);
757 /* If port is closing, signal caller to try again */
758 if (tty_hung_up_p(filp
) || info
->flags
& ASYNC_CLOSING
){
759 if (info
->flags
& ASYNC_CLOSING
)
760 interruptible_sleep_on(&info
->close_wait
);
761 retval
= ((info
->flags
& ASYNC_HUP_NOTIFY
) ?
762 -EAGAIN
: -ERESTARTSYS
);
766 info
->tty
->low_latency
= (info
->flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
768 spin_lock_irqsave(&info
->netlock
, flags
);
769 if (info
->netcount
) {
771 spin_unlock_irqrestore(&info
->netlock
, flags
);
775 spin_unlock_irqrestore(&info
->netlock
, flags
);
777 if (info
->count
== 1) {
778 /* 1st open on this device, init hardware */
779 retval
= startup(info
);
784 retval
= block_til_ready(tty
, filp
, info
);
786 if (debug_level
>= DEBUG_LEVEL_INFO
)
787 printk("%s(%d):%s block_til_ready() returned %d\n",
788 __FILE__
,__LINE__
, info
->device_name
, retval
);
792 if (debug_level
>= DEBUG_LEVEL_INFO
)
793 printk("%s(%d):%s open() success\n",
794 __FILE__
,__LINE__
, info
->device_name
);
800 info
->tty
= NULL
; /* tty layer will release tty struct */
808 /* Called when port is closed. Wait for remaining data to be
809 * sent. Disable port and free resources.
811 static void close(struct tty_struct
*tty
, struct file
*filp
)
813 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
815 if (sanity_check(info
, tty
->name
, "close"))
818 if (debug_level
>= DEBUG_LEVEL_INFO
)
819 printk("%s(%d):%s close() entry, count=%d\n",
820 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
825 if (tty_hung_up_p(filp
))
828 if ((tty
->count
== 1) && (info
->count
!= 1)) {
830 * tty->count is 1 and the tty structure will be freed.
831 * info->count should be one in this case.
832 * if it's not, correct it so that the port is shutdown.
834 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
835 "info->count is %d\n",
836 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
842 /* if at least one open remaining, leave hardware active */
846 info
->flags
|= ASYNC_CLOSING
;
848 /* set tty->closing to notify line discipline to
849 * only process XON/XOFF characters. Only the N_TTY
850 * discipline appears to use this (ppp does not).
854 /* wait for transmit data to clear all layers */
856 if (info
->closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
857 if (debug_level
>= DEBUG_LEVEL_INFO
)
858 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
859 __FILE__
,__LINE__
, info
->device_name
);
860 tty_wait_until_sent(tty
, info
->closing_wait
);
863 if (info
->flags
& ASYNC_INITIALIZED
)
864 wait_until_sent(tty
, info
->timeout
);
866 if (tty
->driver
->flush_buffer
)
867 tty
->driver
->flush_buffer(tty
);
869 tty_ldisc_flush(tty
);
876 if (info
->blocked_open
) {
877 if (info
->close_delay
) {
878 msleep_interruptible(jiffies_to_msecs(info
->close_delay
));
880 wake_up_interruptible(&info
->open_wait
);
883 info
->flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CLOSING
);
885 wake_up_interruptible(&info
->close_wait
);
888 if (debug_level
>= DEBUG_LEVEL_INFO
)
889 printk("%s(%d):%s close() exit, count=%d\n", __FILE__
,__LINE__
,
890 tty
->driver
->name
, info
->count
);
893 /* Called by tty_hangup() when a hangup is signaled.
894 * This is the same as closing all open descriptors for the port.
896 static void hangup(struct tty_struct
*tty
)
898 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
900 if (debug_level
>= DEBUG_LEVEL_INFO
)
901 printk("%s(%d):%s hangup()\n",
902 __FILE__
,__LINE__
, info
->device_name
);
904 if (sanity_check(info
, tty
->name
, "hangup"))
911 info
->flags
&= ~ASYNC_NORMAL_ACTIVE
;
914 wake_up_interruptible(&info
->open_wait
);
917 /* Set new termios settings
919 static void set_termios(struct tty_struct
*tty
, struct termios
*old_termios
)
921 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
924 if (debug_level
>= DEBUG_LEVEL_INFO
)
925 printk("%s(%d):%s set_termios()\n", __FILE__
,__LINE__
,
928 /* just return if nothing has changed */
929 if ((tty
->termios
->c_cflag
== old_termios
->c_cflag
)
930 && (RELEVANT_IFLAG(tty
->termios
->c_iflag
)
931 == RELEVANT_IFLAG(old_termios
->c_iflag
)))
936 /* Handle transition to B0 status */
937 if (old_termios
->c_cflag
& CBAUD
&&
938 !(tty
->termios
->c_cflag
& CBAUD
)) {
939 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
940 spin_lock_irqsave(&info
->lock
,flags
);
942 spin_unlock_irqrestore(&info
->lock
,flags
);
945 /* Handle transition away from B0 status */
946 if (!(old_termios
->c_cflag
& CBAUD
) &&
947 tty
->termios
->c_cflag
& CBAUD
) {
948 info
->serial_signals
|= SerialSignal_DTR
;
949 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
950 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
951 info
->serial_signals
|= SerialSignal_RTS
;
953 spin_lock_irqsave(&info
->lock
,flags
);
955 spin_unlock_irqrestore(&info
->lock
,flags
);
958 /* Handle turning off CRTSCTS */
959 if (old_termios
->c_cflag
& CRTSCTS
&&
960 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
966 /* Send a block of data
970 * tty pointer to tty information structure
971 * buf pointer to buffer containing send data
972 * count size of send data in bytes
974 * Return Value: number of characters written
976 static int write(struct tty_struct
*tty
,
977 const unsigned char *buf
, int count
)
980 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
983 if (debug_level
>= DEBUG_LEVEL_INFO
)
984 printk("%s(%d):%s write() count=%d\n",
985 __FILE__
,__LINE__
,info
->device_name
,count
);
987 if (sanity_check(info
, tty
->name
, "write"))
993 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
994 if (count
> info
->max_frame_size
) {
1000 if (info
->tx_count
) {
1001 /* send accumulated data from send_char() calls */
1002 /* as frame and wait before accepting more data. */
1003 tx_load_dma_buffer(info
, info
->tx_buf
, info
->tx_count
);
1006 ret
= info
->tx_count
= count
;
1007 tx_load_dma_buffer(info
, buf
, count
);
1012 c
= min_t(int, count
,
1013 min(info
->max_frame_size
- info
->tx_count
- 1,
1014 info
->max_frame_size
- info
->tx_put
));
1018 memcpy(info
->tx_buf
+ info
->tx_put
, buf
, c
);
1020 spin_lock_irqsave(&info
->lock
,flags
);
1022 if (info
->tx_put
>= info
->max_frame_size
)
1023 info
->tx_put
-= info
->max_frame_size
;
1024 info
->tx_count
+= c
;
1025 spin_unlock_irqrestore(&info
->lock
,flags
);
1032 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1034 ret
= info
->tx_count
= 0;
1037 tx_load_dma_buffer(info
, info
->tx_buf
, info
->tx_count
);
1040 if (info
->tx_count
&& !tty
->stopped
&& !tty
->hw_stopped
) {
1041 spin_lock_irqsave(&info
->lock
,flags
);
1042 if (!info
->tx_active
)
1044 spin_unlock_irqrestore(&info
->lock
,flags
);
1048 if (debug_level
>= DEBUG_LEVEL_INFO
)
1049 printk( "%s(%d):%s write() returning=%d\n",
1050 __FILE__
,__LINE__
,info
->device_name
,ret
);
1054 /* Add a character to the transmit buffer.
1056 static void put_char(struct tty_struct
*tty
, unsigned char ch
)
1058 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1059 unsigned long flags
;
1061 if ( debug_level
>= DEBUG_LEVEL_INFO
) {
1062 printk( "%s(%d):%s put_char(%d)\n",
1063 __FILE__
,__LINE__
,info
->device_name
,ch
);
1066 if (sanity_check(info
, tty
->name
, "put_char"))
1072 spin_lock_irqsave(&info
->lock
,flags
);
1074 if ( (info
->params
.mode
!= MGSL_MODE_HDLC
) ||
1075 !info
->tx_active
) {
1077 if (info
->tx_count
< info
->max_frame_size
- 1) {
1078 info
->tx_buf
[info
->tx_put
++] = ch
;
1079 if (info
->tx_put
>= info
->max_frame_size
)
1080 info
->tx_put
-= info
->max_frame_size
;
1085 spin_unlock_irqrestore(&info
->lock
,flags
);
1088 /* Send a high-priority XON/XOFF character
1090 static void send_xchar(struct tty_struct
*tty
, char ch
)
1092 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1093 unsigned long flags
;
1095 if (debug_level
>= DEBUG_LEVEL_INFO
)
1096 printk("%s(%d):%s send_xchar(%d)\n",
1097 __FILE__
,__LINE__
, info
->device_name
, ch
);
1099 if (sanity_check(info
, tty
->name
, "send_xchar"))
1104 /* Make sure transmit interrupts are on */
1105 spin_lock_irqsave(&info
->lock
,flags
);
1106 if (!info
->tx_enabled
)
1108 spin_unlock_irqrestore(&info
->lock
,flags
);
1112 /* Wait until the transmitter is empty.
1114 static void wait_until_sent(struct tty_struct
*tty
, int timeout
)
1116 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
1117 unsigned long orig_jiffies
, char_time
;
1122 if (debug_level
>= DEBUG_LEVEL_INFO
)
1123 printk("%s(%d):%s wait_until_sent() entry\n",
1124 __FILE__
,__LINE__
, info
->device_name
);
1126 if (sanity_check(info
, tty
->name
, "wait_until_sent"))
1129 if (!(info
->flags
& ASYNC_INITIALIZED
))
1132 orig_jiffies
= jiffies
;
1134 /* Set check interval to 1/5 of estimated time to
1135 * send a character, and make it at least 1. The check
1136 * interval should also be less than the timeout.
1137 * Note: use tight timings here to satisfy the NIST-PCTS.
1140 if ( info
->params
.data_rate
) {
1141 char_time
= info
->timeout
/(32 * 5);
1148 char_time
= min_t(unsigned long, char_time
, timeout
);
1150 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
1151 while (info
->tx_active
) {
1152 msleep_interruptible(jiffies_to_msecs(char_time
));
1153 if (signal_pending(current
))
1155 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
1159 //TODO: determine if there is something similar to USC16C32
1160 // TXSTATUS_ALL_SENT status
1161 while ( info
->tx_active
&& info
->tx_enabled
) {
1162 msleep_interruptible(jiffies_to_msecs(char_time
));
1163 if (signal_pending(current
))
1165 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
1171 if (debug_level
>= DEBUG_LEVEL_INFO
)
1172 printk("%s(%d):%s wait_until_sent() exit\n",
1173 __FILE__
,__LINE__
, info
->device_name
);
1176 /* Return the count of free bytes in transmit buffer
1178 static int write_room(struct tty_struct
*tty
)
1180 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1183 if (sanity_check(info
, tty
->name
, "write_room"))
1186 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1187 ret
= (info
->tx_active
) ? 0 : HDLC_MAX_FRAME_SIZE
;
1189 ret
= info
->max_frame_size
- info
->tx_count
- 1;
1194 if (debug_level
>= DEBUG_LEVEL_INFO
)
1195 printk("%s(%d):%s write_room()=%d\n",
1196 __FILE__
, __LINE__
, info
->device_name
, ret
);
1201 /* enable transmitter and send remaining buffered characters
1203 static void flush_chars(struct tty_struct
*tty
)
1205 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1206 unsigned long flags
;
1208 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1209 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1210 __FILE__
,__LINE__
,info
->device_name
,info
->tx_count
);
1212 if (sanity_check(info
, tty
->name
, "flush_chars"))
1215 if (info
->tx_count
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
1219 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1220 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1221 __FILE__
,__LINE__
,info
->device_name
);
1223 spin_lock_irqsave(&info
->lock
,flags
);
1225 if (!info
->tx_active
) {
1226 if ( (info
->params
.mode
== MGSL_MODE_HDLC
) &&
1228 /* operating in synchronous (frame oriented) mode */
1229 /* copy data from circular tx_buf to */
1230 /* transmit DMA buffer. */
1231 tx_load_dma_buffer(info
,
1232 info
->tx_buf
,info
->tx_count
);
1237 spin_unlock_irqrestore(&info
->lock
,flags
);
1240 /* Discard all data in the send buffer
1242 static void flush_buffer(struct tty_struct
*tty
)
1244 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1245 unsigned long flags
;
1247 if (debug_level
>= DEBUG_LEVEL_INFO
)
1248 printk("%s(%d):%s flush_buffer() entry\n",
1249 __FILE__
,__LINE__
, info
->device_name
);
1251 if (sanity_check(info
, tty
->name
, "flush_buffer"))
1254 spin_lock_irqsave(&info
->lock
,flags
);
1255 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
1256 del_timer(&info
->tx_timer
);
1257 spin_unlock_irqrestore(&info
->lock
,flags
);
1259 wake_up_interruptible(&tty
->write_wait
);
1263 /* throttle (stop) transmitter
1265 static void tx_hold(struct tty_struct
*tty
)
1267 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1268 unsigned long flags
;
1270 if (sanity_check(info
, tty
->name
, "tx_hold"))
1273 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1274 printk("%s(%d):%s tx_hold()\n",
1275 __FILE__
,__LINE__
,info
->device_name
);
1277 spin_lock_irqsave(&info
->lock
,flags
);
1278 if (info
->tx_enabled
)
1280 spin_unlock_irqrestore(&info
->lock
,flags
);
1283 /* release (start) transmitter
1285 static void tx_release(struct tty_struct
*tty
)
1287 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1288 unsigned long flags
;
1290 if (sanity_check(info
, tty
->name
, "tx_release"))
1293 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1294 printk("%s(%d):%s tx_release()\n",
1295 __FILE__
,__LINE__
,info
->device_name
);
1297 spin_lock_irqsave(&info
->lock
,flags
);
1298 if (!info
->tx_enabled
)
1300 spin_unlock_irqrestore(&info
->lock
,flags
);
1303 /* Service an IOCTL request
1307 * tty pointer to tty instance data
1308 * file pointer to associated file object for device
1309 * cmd IOCTL command code
1310 * arg command argument/context
1312 * Return Value: 0 if success, otherwise error code
1314 static int ioctl(struct tty_struct
*tty
, struct file
*file
,
1315 unsigned int cmd
, unsigned long arg
)
1317 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1319 struct mgsl_icount cnow
; /* kernel counter temps */
1320 struct serial_icounter_struct __user
*p_cuser
; /* user space */
1321 unsigned long flags
;
1322 void __user
*argp
= (void __user
*)arg
;
1324 if (debug_level
>= DEBUG_LEVEL_INFO
)
1325 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__
,__LINE__
,
1326 info
->device_name
, cmd
);
1328 if (sanity_check(info
, tty
->name
, "ioctl"))
1331 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
1332 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
1333 if (tty
->flags
& (1 << TTY_IO_ERROR
))
1338 case MGSL_IOCGPARAMS
:
1339 return get_params(info
, argp
);
1340 case MGSL_IOCSPARAMS
:
1341 return set_params(info
, argp
);
1342 case MGSL_IOCGTXIDLE
:
1343 return get_txidle(info
, argp
);
1344 case MGSL_IOCSTXIDLE
:
1345 return set_txidle(info
, (int)arg
);
1346 case MGSL_IOCTXENABLE
:
1347 return tx_enable(info
, (int)arg
);
1348 case MGSL_IOCRXENABLE
:
1349 return rx_enable(info
, (int)arg
);
1350 case MGSL_IOCTXABORT
:
1351 return tx_abort(info
);
1352 case MGSL_IOCGSTATS
:
1353 return get_stats(info
, argp
);
1354 case MGSL_IOCWAITEVENT
:
1355 return wait_mgsl_event(info
, argp
);
1356 case MGSL_IOCLOOPTXDONE
:
1357 return 0; // TODO: Not supported, need to document
1358 /* Wait for modem input (DCD,RI,DSR,CTS) change
1359 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1362 return modem_input_wait(info
,(int)arg
);
1365 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1366 * Return: write counters to the user passed counter struct
1367 * NB: both 1->0 and 0->1 transitions are counted except for
1368 * RI where only 0->1 is counted.
1371 spin_lock_irqsave(&info
->lock
,flags
);
1372 cnow
= info
->icount
;
1373 spin_unlock_irqrestore(&info
->lock
,flags
);
1375 PUT_USER(error
,cnow
.cts
, &p_cuser
->cts
);
1376 if (error
) return error
;
1377 PUT_USER(error
,cnow
.dsr
, &p_cuser
->dsr
);
1378 if (error
) return error
;
1379 PUT_USER(error
,cnow
.rng
, &p_cuser
->rng
);
1380 if (error
) return error
;
1381 PUT_USER(error
,cnow
.dcd
, &p_cuser
->dcd
);
1382 if (error
) return error
;
1383 PUT_USER(error
,cnow
.rx
, &p_cuser
->rx
);
1384 if (error
) return error
;
1385 PUT_USER(error
,cnow
.tx
, &p_cuser
->tx
);
1386 if (error
) return error
;
1387 PUT_USER(error
,cnow
.frame
, &p_cuser
->frame
);
1388 if (error
) return error
;
1389 PUT_USER(error
,cnow
.overrun
, &p_cuser
->overrun
);
1390 if (error
) return error
;
1391 PUT_USER(error
,cnow
.parity
, &p_cuser
->parity
);
1392 if (error
) return error
;
1393 PUT_USER(error
,cnow
.brk
, &p_cuser
->brk
);
1394 if (error
) return error
;
1395 PUT_USER(error
,cnow
.buf_overrun
, &p_cuser
->buf_overrun
);
1396 if (error
) return error
;
1399 return -ENOIOCTLCMD
;
1405 * /proc fs routines....
1408 static inline int line_info(char *buf
, SLMP_INFO
*info
)
1412 unsigned long flags
;
1414 ret
= sprintf(buf
, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1415 "\tIRQ=%d MaxFrameSize=%u\n",
1417 info
->phys_sca_base
,
1418 info
->phys_memory_base
,
1419 info
->phys_statctrl_base
,
1420 info
->phys_lcr_base
,
1422 info
->max_frame_size
);
1424 /* output current serial signal states */
1425 spin_lock_irqsave(&info
->lock
,flags
);
1427 spin_unlock_irqrestore(&info
->lock
,flags
);
1431 if (info
->serial_signals
& SerialSignal_RTS
)
1432 strcat(stat_buf
, "|RTS");
1433 if (info
->serial_signals
& SerialSignal_CTS
)
1434 strcat(stat_buf
, "|CTS");
1435 if (info
->serial_signals
& SerialSignal_DTR
)
1436 strcat(stat_buf
, "|DTR");
1437 if (info
->serial_signals
& SerialSignal_DSR
)
1438 strcat(stat_buf
, "|DSR");
1439 if (info
->serial_signals
& SerialSignal_DCD
)
1440 strcat(stat_buf
, "|CD");
1441 if (info
->serial_signals
& SerialSignal_RI
)
1442 strcat(stat_buf
, "|RI");
1444 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1445 ret
+= sprintf(buf
+ret
, "\tHDLC txok:%d rxok:%d",
1446 info
->icount
.txok
, info
->icount
.rxok
);
1447 if (info
->icount
.txunder
)
1448 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
1449 if (info
->icount
.txabort
)
1450 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
1451 if (info
->icount
.rxshort
)
1452 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
1453 if (info
->icount
.rxlong
)
1454 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
1455 if (info
->icount
.rxover
)
1456 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
1457 if (info
->icount
.rxcrc
)
1458 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxcrc
);
1460 ret
+= sprintf(buf
+ret
, "\tASYNC tx:%d rx:%d",
1461 info
->icount
.tx
, info
->icount
.rx
);
1462 if (info
->icount
.frame
)
1463 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
1464 if (info
->icount
.parity
)
1465 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
1466 if (info
->icount
.brk
)
1467 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
1468 if (info
->icount
.overrun
)
1469 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
1472 /* Append serial signal status to end */
1473 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
1475 ret
+= sprintf(buf
+ret
, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1476 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
1482 /* Called to print information about devices
1484 int read_proc(char *page
, char **start
, off_t off
, int count
,
1485 int *eof
, void *data
)
1491 len
+= sprintf(page
, "synclinkmp driver:%s\n", driver_version
);
1493 info
= synclinkmp_device_list
;
1495 l
= line_info(page
+ len
, info
);
1497 if (len
+begin
> off
+count
)
1499 if (len
+begin
< off
) {
1503 info
= info
->next_device
;
1508 if (off
>= len
+begin
)
1510 *start
= page
+ (off
-begin
);
1511 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
1514 /* Return the count of bytes in transmit buffer
1516 static int chars_in_buffer(struct tty_struct
*tty
)
1518 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1520 if (sanity_check(info
, tty
->name
, "chars_in_buffer"))
1523 if (debug_level
>= DEBUG_LEVEL_INFO
)
1524 printk("%s(%d):%s chars_in_buffer()=%d\n",
1525 __FILE__
, __LINE__
, info
->device_name
, info
->tx_count
);
1527 return info
->tx_count
;
1530 /* Signal remote device to throttle send data (our receive data)
1532 static void throttle(struct tty_struct
* tty
)
1534 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1535 unsigned long flags
;
1537 if (debug_level
>= DEBUG_LEVEL_INFO
)
1538 printk("%s(%d):%s throttle() entry\n",
1539 __FILE__
,__LINE__
, info
->device_name
);
1541 if (sanity_check(info
, tty
->name
, "throttle"))
1545 send_xchar(tty
, STOP_CHAR(tty
));
1547 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1548 spin_lock_irqsave(&info
->lock
,flags
);
1549 info
->serial_signals
&= ~SerialSignal_RTS
;
1551 spin_unlock_irqrestore(&info
->lock
,flags
);
1555 /* Signal remote device to stop throttling send data (our receive data)
1557 static void unthrottle(struct tty_struct
* tty
)
1559 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1560 unsigned long flags
;
1562 if (debug_level
>= DEBUG_LEVEL_INFO
)
1563 printk("%s(%d):%s unthrottle() entry\n",
1564 __FILE__
,__LINE__
, info
->device_name
);
1566 if (sanity_check(info
, tty
->name
, "unthrottle"))
1573 send_xchar(tty
, START_CHAR(tty
));
1576 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1577 spin_lock_irqsave(&info
->lock
,flags
);
1578 info
->serial_signals
|= SerialSignal_RTS
;
1580 spin_unlock_irqrestore(&info
->lock
,flags
);
1584 /* set or clear transmit break condition
1585 * break_state -1=set break condition, 0=clear
1587 static void set_break(struct tty_struct
*tty
, int break_state
)
1589 unsigned char RegValue
;
1590 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
1591 unsigned long flags
;
1593 if (debug_level
>= DEBUG_LEVEL_INFO
)
1594 printk("%s(%d):%s set_break(%d)\n",
1595 __FILE__
,__LINE__
, info
->device_name
, break_state
);
1597 if (sanity_check(info
, tty
->name
, "set_break"))
1600 spin_lock_irqsave(&info
->lock
,flags
);
1601 RegValue
= read_reg(info
, CTL
);
1602 if (break_state
== -1)
1606 write_reg(info
, CTL
, RegValue
);
1607 spin_unlock_irqrestore(&info
->lock
,flags
);
1613 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1614 * set encoding and frame check sequence (FCS) options
1616 * dev pointer to network device structure
1617 * encoding serial encoding setting
1618 * parity FCS setting
1620 * returns 0 if success, otherwise error code
1622 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
1623 unsigned short parity
)
1625 SLMP_INFO
*info
= dev_to_port(dev
);
1626 unsigned char new_encoding
;
1627 unsigned short new_crctype
;
1629 /* return error if TTY interface open */
1635 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
1636 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
1637 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
1638 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
1639 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
1640 default: return -EINVAL
;
1645 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
1646 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
1647 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
1648 default: return -EINVAL
;
1651 info
->params
.encoding
= new_encoding
;
1652 info
->params
.crc_type
= new_crctype
;
1654 /* if network interface up, reprogram hardware */
1662 * called by generic HDLC layer to send frame
1664 * skb socket buffer containing HDLC frame
1665 * dev pointer to network device structure
1667 * returns 0 if success, otherwise error code
1669 static int hdlcdev_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1671 SLMP_INFO
*info
= dev_to_port(dev
);
1672 struct net_device_stats
*stats
= hdlc_stats(dev
);
1673 unsigned long flags
;
1675 if (debug_level
>= DEBUG_LEVEL_INFO
)
1676 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
1678 /* stop sending until this frame completes */
1679 netif_stop_queue(dev
);
1681 /* copy data to device buffers */
1682 info
->tx_count
= skb
->len
;
1683 tx_load_dma_buffer(info
, skb
->data
, skb
->len
);
1685 /* update network statistics */
1686 stats
->tx_packets
++;
1687 stats
->tx_bytes
+= skb
->len
;
1689 /* done with socket buffer, so free it */
1692 /* save start time for transmit timeout detection */
1693 dev
->trans_start
= jiffies
;
1695 /* start hardware transmitter if necessary */
1696 spin_lock_irqsave(&info
->lock
,flags
);
1697 if (!info
->tx_active
)
1699 spin_unlock_irqrestore(&info
->lock
,flags
);
1705 * called by network layer when interface enabled
1706 * claim resources and initialize hardware
1708 * dev pointer to network device structure
1710 * returns 0 if success, otherwise error code
1712 static int hdlcdev_open(struct net_device
*dev
)
1714 SLMP_INFO
*info
= dev_to_port(dev
);
1716 unsigned long flags
;
1718 if (debug_level
>= DEBUG_LEVEL_INFO
)
1719 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
1721 /* generic HDLC layer open processing */
1722 if ((rc
= hdlc_open(dev
)))
1725 /* arbitrate between network and tty opens */
1726 spin_lock_irqsave(&info
->netlock
, flags
);
1727 if (info
->count
!= 0 || info
->netcount
!= 0) {
1728 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
1729 spin_unlock_irqrestore(&info
->netlock
, flags
);
1733 spin_unlock_irqrestore(&info
->netlock
, flags
);
1735 /* claim resources and init adapter */
1736 if ((rc
= startup(info
)) != 0) {
1737 spin_lock_irqsave(&info
->netlock
, flags
);
1739 spin_unlock_irqrestore(&info
->netlock
, flags
);
1743 /* assert DTR and RTS, apply hardware settings */
1744 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1747 /* enable network layer transmit */
1748 dev
->trans_start
= jiffies
;
1749 netif_start_queue(dev
);
1751 /* inform generic HDLC layer of current DCD status */
1752 spin_lock_irqsave(&info
->lock
, flags
);
1754 spin_unlock_irqrestore(&info
->lock
, flags
);
1755 hdlc_set_carrier(info
->serial_signals
& SerialSignal_DCD
, dev
);
1761 * called by network layer when interface is disabled
1762 * shutdown hardware and release resources
1764 * dev pointer to network device structure
1766 * returns 0 if success, otherwise error code
1768 static int hdlcdev_close(struct net_device
*dev
)
1770 SLMP_INFO
*info
= dev_to_port(dev
);
1771 unsigned long flags
;
1773 if (debug_level
>= DEBUG_LEVEL_INFO
)
1774 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
1776 netif_stop_queue(dev
);
1778 /* shutdown adapter and release resources */
1783 spin_lock_irqsave(&info
->netlock
, flags
);
1785 spin_unlock_irqrestore(&info
->netlock
, flags
);
1791 * called by network layer to process IOCTL call to network device
1793 * dev pointer to network device structure
1794 * ifr pointer to network interface request structure
1795 * cmd IOCTL command code
1797 * returns 0 if success, otherwise error code
1799 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1801 const size_t size
= sizeof(sync_serial_settings
);
1802 sync_serial_settings new_line
;
1803 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
1804 SLMP_INFO
*info
= dev_to_port(dev
);
1807 if (debug_level
>= DEBUG_LEVEL_INFO
)
1808 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
1810 /* return error if TTY interface open */
1814 if (cmd
!= SIOCWANDEV
)
1815 return hdlc_ioctl(dev
, ifr
, cmd
);
1817 switch(ifr
->ifr_settings
.type
) {
1818 case IF_GET_IFACE
: /* return current sync_serial_settings */
1820 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
1821 if (ifr
->ifr_settings
.size
< size
) {
1822 ifr
->ifr_settings
.size
= size
; /* data size wanted */
1826 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1827 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1828 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1829 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1832 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
1833 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
1834 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
1835 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
1836 default: new_line
.clock_type
= CLOCK_DEFAULT
;
1839 new_line
.clock_rate
= info
->params
.clock_speed
;
1840 new_line
.loopback
= info
->params
.loopback
? 1:0;
1842 if (copy_to_user(line
, &new_line
, size
))
1846 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
1848 if(!capable(CAP_NET_ADMIN
))
1850 if (copy_from_user(&new_line
, line
, size
))
1853 switch (new_line
.clock_type
)
1855 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
1856 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
1857 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
1858 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
1859 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
1860 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1861 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1862 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1863 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
1864 default: return -EINVAL
;
1867 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
1870 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1871 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1872 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1873 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1874 info
->params
.flags
|= flags
;
1876 info
->params
.loopback
= new_line
.loopback
;
1878 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
1879 info
->params
.clock_speed
= new_line
.clock_rate
;
1881 info
->params
.clock_speed
= 0;
1883 /* if network interface up, reprogram hardware */
1889 return hdlc_ioctl(dev
, ifr
, cmd
);
1894 * called by network layer when transmit timeout is detected
1896 * dev pointer to network device structure
1898 static void hdlcdev_tx_timeout(struct net_device
*dev
)
1900 SLMP_INFO
*info
= dev_to_port(dev
);
1901 struct net_device_stats
*stats
= hdlc_stats(dev
);
1902 unsigned long flags
;
1904 if (debug_level
>= DEBUG_LEVEL_INFO
)
1905 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
1908 stats
->tx_aborted_errors
++;
1910 spin_lock_irqsave(&info
->lock
,flags
);
1912 spin_unlock_irqrestore(&info
->lock
,flags
);
1914 netif_wake_queue(dev
);
1918 * called by device driver when transmit completes
1919 * reenable network layer transmit if stopped
1921 * info pointer to device instance information
1923 static void hdlcdev_tx_done(SLMP_INFO
*info
)
1925 if (netif_queue_stopped(info
->netdev
))
1926 netif_wake_queue(info
->netdev
);
1930 * called by device driver when frame received
1931 * pass frame to network layer
1933 * info pointer to device instance information
1934 * buf pointer to buffer contianing frame data
1935 * size count of data bytes in buf
1937 static void hdlcdev_rx(SLMP_INFO
*info
, char *buf
, int size
)
1939 struct sk_buff
*skb
= dev_alloc_skb(size
);
1940 struct net_device
*dev
= info
->netdev
;
1941 struct net_device_stats
*stats
= hdlc_stats(dev
);
1943 if (debug_level
>= DEBUG_LEVEL_INFO
)
1944 printk("hdlcdev_rx(%s)\n",dev
->name
);
1947 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n", dev
->name
);
1948 stats
->rx_dropped
++;
1952 memcpy(skb_put(skb
, size
),buf
,size
);
1954 skb
->protocol
= hdlc_type_trans(skb
, info
->netdev
);
1956 stats
->rx_packets
++;
1957 stats
->rx_bytes
+= size
;
1961 info
->netdev
->last_rx
= jiffies
;
1965 * called by device driver when adding device instance
1966 * do generic HDLC initialization
1968 * info pointer to device instance information
1970 * returns 0 if success, otherwise error code
1972 static int hdlcdev_init(SLMP_INFO
*info
)
1975 struct net_device
*dev
;
1978 /* allocate and initialize network and HDLC layer objects */
1980 if (!(dev
= alloc_hdlcdev(info
))) {
1981 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
1985 /* for network layer reporting purposes only */
1986 dev
->mem_start
= info
->phys_sca_base
;
1987 dev
->mem_end
= info
->phys_sca_base
+ SCA_BASE_SIZE
- 1;
1988 dev
->irq
= info
->irq_level
;
1990 /* network layer callbacks and settings */
1991 dev
->do_ioctl
= hdlcdev_ioctl
;
1992 dev
->open
= hdlcdev_open
;
1993 dev
->stop
= hdlcdev_close
;
1994 dev
->tx_timeout
= hdlcdev_tx_timeout
;
1995 dev
->watchdog_timeo
= 10*HZ
;
1996 dev
->tx_queue_len
= 50;
1998 /* generic HDLC layer callbacks and settings */
1999 hdlc
= dev_to_hdlc(dev
);
2000 hdlc
->attach
= hdlcdev_attach
;
2001 hdlc
->xmit
= hdlcdev_xmit
;
2003 /* register objects with HDLC layer */
2004 if ((rc
= register_hdlc_device(dev
))) {
2005 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
2015 * called by device driver when removing device instance
2016 * do generic HDLC cleanup
2018 * info pointer to device instance information
2020 static void hdlcdev_exit(SLMP_INFO
*info
)
2022 unregister_hdlc_device(info
->netdev
);
2023 free_netdev(info
->netdev
);
2024 info
->netdev
= NULL
;
2027 #endif /* CONFIG_HDLC */
2030 /* Return next bottom half action to perform.
2031 * Return Value: BH action code or 0 if nothing to do.
2033 int bh_action(SLMP_INFO
*info
)
2035 unsigned long flags
;
2038 spin_lock_irqsave(&info
->lock
,flags
);
2040 if (info
->pending_bh
& BH_RECEIVE
) {
2041 info
->pending_bh
&= ~BH_RECEIVE
;
2043 } else if (info
->pending_bh
& BH_TRANSMIT
) {
2044 info
->pending_bh
&= ~BH_TRANSMIT
;
2046 } else if (info
->pending_bh
& BH_STATUS
) {
2047 info
->pending_bh
&= ~BH_STATUS
;
2052 /* Mark BH routine as complete */
2053 info
->bh_running
= 0;
2054 info
->bh_requested
= 0;
2057 spin_unlock_irqrestore(&info
->lock
,flags
);
2062 /* Perform bottom half processing of work items queued by ISR.
2064 void bh_handler(void* Context
)
2066 SLMP_INFO
*info
= (SLMP_INFO
*)Context
;
2072 if ( debug_level
>= DEBUG_LEVEL_BH
)
2073 printk( "%s(%d):%s bh_handler() entry\n",
2074 __FILE__
,__LINE__
,info
->device_name
);
2076 info
->bh_running
= 1;
2078 while((action
= bh_action(info
)) != 0) {
2080 /* Process work item */
2081 if ( debug_level
>= DEBUG_LEVEL_BH
)
2082 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2083 __FILE__
,__LINE__
,info
->device_name
, action
);
2097 /* unknown work item ID */
2098 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2099 __FILE__
,__LINE__
,info
->device_name
,action
);
2104 if ( debug_level
>= DEBUG_LEVEL_BH
)
2105 printk( "%s(%d):%s bh_handler() exit\n",
2106 __FILE__
,__LINE__
,info
->device_name
);
2109 void bh_receive(SLMP_INFO
*info
)
2111 if ( debug_level
>= DEBUG_LEVEL_BH
)
2112 printk( "%s(%d):%s bh_receive()\n",
2113 __FILE__
,__LINE__
,info
->device_name
);
2115 while( rx_get_frame(info
) );
2118 void bh_transmit(SLMP_INFO
*info
)
2120 struct tty_struct
*tty
= info
->tty
;
2122 if ( debug_level
>= DEBUG_LEVEL_BH
)
2123 printk( "%s(%d):%s bh_transmit() entry\n",
2124 __FILE__
,__LINE__
,info
->device_name
);
2128 wake_up_interruptible(&tty
->write_wait
);
2132 void bh_status(SLMP_INFO
*info
)
2134 if ( debug_level
>= DEBUG_LEVEL_BH
)
2135 printk( "%s(%d):%s bh_status() entry\n",
2136 __FILE__
,__LINE__
,info
->device_name
);
2138 info
->ri_chkcount
= 0;
2139 info
->dsr_chkcount
= 0;
2140 info
->dcd_chkcount
= 0;
2141 info
->cts_chkcount
= 0;
2144 void isr_timer(SLMP_INFO
* info
)
2146 unsigned char timer
= (info
->port_num
& 1) ? TIMER2
: TIMER0
;
2148 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2149 write_reg(info
, IER2
, 0);
2151 /* TMCS, Timer Control/Status Register
2153 * 07 CMF, Compare match flag (read only) 1=match
2154 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2155 * 05 Reserved, must be 0
2156 * 04 TME, Timer Enable
2157 * 03..00 Reserved, must be 0
2161 write_reg(info
, (unsigned char)(timer
+ TMCS
), 0);
2163 info
->irq_occurred
= TRUE
;
2165 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2166 printk("%s(%d):%s isr_timer()\n",
2167 __FILE__
,__LINE__
,info
->device_name
);
2170 void isr_rxint(SLMP_INFO
* info
)
2172 struct tty_struct
*tty
= info
->tty
;
2173 struct mgsl_icount
*icount
= &info
->icount
;
2174 unsigned char status
= read_reg(info
, SR1
) & info
->ie1_value
& (FLGD
+ IDLD
+ CDCD
+ BRKD
);
2175 unsigned char status2
= read_reg(info
, SR2
) & info
->ie2_value
& OVRN
;
2177 /* clear status bits */
2179 write_reg(info
, SR1
, status
);
2182 write_reg(info
, SR2
, status2
);
2184 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2185 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2186 __FILE__
,__LINE__
,info
->device_name
,status
,status2
);
2188 if (info
->params
.mode
== MGSL_MODE_ASYNC
) {
2189 if (status
& BRKD
) {
2192 /* process break detection if tty control
2193 * is not set to ignore it
2196 if (!(status
& info
->ignore_status_mask1
)) {
2197 if (info
->read_status_mask1
& BRKD
) {
2198 tty_insert_flip_char(tty
, 0, TTY_BREAK
);
2199 if (info
->flags
& ASYNC_SAK
)
2207 if (status
& (FLGD
|IDLD
)) {
2209 info
->icount
.exithunt
++;
2210 else if (status
& IDLD
)
2211 info
->icount
.rxidle
++;
2212 wake_up_interruptible(&info
->event_wait_q
);
2216 if (status
& CDCD
) {
2217 /* simulate a common modem status change interrupt
2220 get_signals( info
);
2222 MISCSTATUS_DCD_LATCHED
|(info
->serial_signals
&SerialSignal_DCD
));
2227 * handle async rx data interrupts
2229 void isr_rxrdy(SLMP_INFO
* info
)
2232 unsigned char DataByte
;
2233 struct tty_struct
*tty
= info
->tty
;
2234 struct mgsl_icount
*icount
= &info
->icount
;
2236 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2237 printk("%s(%d):%s isr_rxrdy\n",
2238 __FILE__
,__LINE__
,info
->device_name
);
2240 while((status
= read_reg(info
,CST0
)) & BIT0
)
2244 DataByte
= read_reg(info
,TRB
);
2248 if ( status
& (PE
+ FRME
+ OVRN
) ) {
2249 printk("%s(%d):%s rxerr=%04X\n",
2250 __FILE__
,__LINE__
,info
->device_name
,status
);
2252 /* update error statistics */
2255 else if (status
& FRME
)
2257 else if (status
& OVRN
)
2260 /* discard char if tty control flags say so */
2261 if (status
& info
->ignore_status_mask2
)
2264 status
&= info
->read_status_mask2
;
2269 else if (status
& FRME
)
2271 if (status
& OVRN
) {
2272 /* Overrun is special, since it's
2273 * reported immediately, and doesn't
2274 * affect the current character
2279 } /* end of if (error) */
2282 tty_insert_flip_char(tty
, DataByte
, flag
);
2284 tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
2288 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
2289 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2290 __FILE__
,__LINE__
,info
->device_name
,
2291 icount
->rx
,icount
->brk
,icount
->parity
,
2292 icount
->frame
,icount
->overrun
);
2296 tty_flip_buffer_push(tty
);
2299 static void isr_txeom(SLMP_INFO
* info
, unsigned char status
)
2301 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2302 printk("%s(%d):%s isr_txeom status=%02x\n",
2303 __FILE__
,__LINE__
,info
->device_name
,status
);
2305 write_reg(info
, TXDMA
+ DIR, 0x00); /* disable Tx DMA IRQs */
2306 write_reg(info
, TXDMA
+ DSR
, 0xc0); /* clear IRQs and disable DMA */
2307 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
2309 if (status
& UDRN
) {
2310 write_reg(info
, CMD
, TXRESET
);
2311 write_reg(info
, CMD
, TXENABLE
);
2313 write_reg(info
, CMD
, TXBUFCLR
);
2315 /* disable and clear tx interrupts */
2316 info
->ie0_value
&= ~TXRDYE
;
2317 info
->ie1_value
&= ~(IDLE
+ UDRN
);
2318 write_reg16(info
, IE0
, (unsigned short)((info
->ie1_value
<< 8) + info
->ie0_value
));
2319 write_reg(info
, SR1
, (unsigned char)(UDRN
+ IDLE
));
2321 if ( info
->tx_active
) {
2322 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2324 info
->icount
.txunder
++;
2325 else if (status
& IDLE
)
2326 info
->icount
.txok
++;
2329 info
->tx_active
= 0;
2330 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
2332 del_timer(&info
->tx_timer
);
2334 if (info
->params
.mode
!= MGSL_MODE_ASYNC
&& info
->drop_rts_on_tx_done
) {
2335 info
->serial_signals
&= ~SerialSignal_RTS
;
2336 info
->drop_rts_on_tx_done
= 0;
2342 hdlcdev_tx_done(info
);
2346 if (info
->tty
&& (info
->tty
->stopped
|| info
->tty
->hw_stopped
)) {
2350 info
->pending_bh
|= BH_TRANSMIT
;
2357 * handle tx status interrupts
2359 void isr_txint(SLMP_INFO
* info
)
2361 unsigned char status
= read_reg(info
, SR1
) & info
->ie1_value
& (UDRN
+ IDLE
+ CCTS
);
2363 /* clear status bits */
2364 write_reg(info
, SR1
, status
);
2366 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2367 printk("%s(%d):%s isr_txint status=%02x\n",
2368 __FILE__
,__LINE__
,info
->device_name
,status
);
2370 if (status
& (UDRN
+ IDLE
))
2371 isr_txeom(info
, status
);
2373 if (status
& CCTS
) {
2374 /* simulate a common modem status change interrupt
2377 get_signals( info
);
2379 MISCSTATUS_CTS_LATCHED
|(info
->serial_signals
&SerialSignal_CTS
));
2385 * handle async tx data interrupts
2387 void isr_txrdy(SLMP_INFO
* info
)
2389 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2390 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2391 __FILE__
,__LINE__
,info
->device_name
,info
->tx_count
);
2393 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2394 /* disable TXRDY IRQ, enable IDLE IRQ */
2395 info
->ie0_value
&= ~TXRDYE
;
2396 info
->ie1_value
|= IDLE
;
2397 write_reg16(info
, IE0
, (unsigned short)((info
->ie1_value
<< 8) + info
->ie0_value
));
2401 if (info
->tty
&& (info
->tty
->stopped
|| info
->tty
->hw_stopped
)) {
2406 if ( info
->tx_count
)
2407 tx_load_fifo( info
);
2409 info
->tx_active
= 0;
2410 info
->ie0_value
&= ~TXRDYE
;
2411 write_reg(info
, IE0
, info
->ie0_value
);
2414 if (info
->tx_count
< WAKEUP_CHARS
)
2415 info
->pending_bh
|= BH_TRANSMIT
;
2418 void isr_rxdmaok(SLMP_INFO
* info
)
2420 /* BIT7 = EOT (end of transfer)
2421 * BIT6 = EOM (end of message/frame)
2423 unsigned char status
= read_reg(info
,RXDMA
+ DSR
) & 0xc0;
2425 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2426 write_reg(info
, RXDMA
+ DSR
, (unsigned char)(status
| 1));
2428 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2429 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2430 __FILE__
,__LINE__
,info
->device_name
,status
);
2432 info
->pending_bh
|= BH_RECEIVE
;
2435 void isr_rxdmaerror(SLMP_INFO
* info
)
2437 /* BIT5 = BOF (buffer overflow)
2438 * BIT4 = COF (counter overflow)
2440 unsigned char status
= read_reg(info
,RXDMA
+ DSR
) & 0x30;
2442 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2443 write_reg(info
, RXDMA
+ DSR
, (unsigned char)(status
| 1));
2445 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2446 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2447 __FILE__
,__LINE__
,info
->device_name
,status
);
2449 info
->rx_overflow
= TRUE
;
2450 info
->pending_bh
|= BH_RECEIVE
;
2453 void isr_txdmaok(SLMP_INFO
* info
)
2455 unsigned char status_reg1
= read_reg(info
, SR1
);
2457 write_reg(info
, TXDMA
+ DIR, 0x00); /* disable Tx DMA IRQs */
2458 write_reg(info
, TXDMA
+ DSR
, 0xc0); /* clear IRQs and disable DMA */
2459 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
2461 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2462 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2463 __FILE__
,__LINE__
,info
->device_name
,status_reg1
);
2465 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2466 write_reg16(info
, TRC0
, 0);
2467 info
->ie0_value
|= TXRDYE
;
2468 write_reg(info
, IE0
, info
->ie0_value
);
2471 void isr_txdmaerror(SLMP_INFO
* info
)
2473 /* BIT5 = BOF (buffer overflow)
2474 * BIT4 = COF (counter overflow)
2476 unsigned char status
= read_reg(info
,TXDMA
+ DSR
) & 0x30;
2478 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2479 write_reg(info
, TXDMA
+ DSR
, (unsigned char)(status
| 1));
2481 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2482 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2483 __FILE__
,__LINE__
,info
->device_name
,status
);
2486 /* handle input serial signal changes
2488 void isr_io_pin( SLMP_INFO
*info
, u16 status
)
2490 struct mgsl_icount
*icount
;
2492 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2493 printk("%s(%d):isr_io_pin status=%04X\n",
2494 __FILE__
,__LINE__
,status
);
2496 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
2497 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
2498 icount
= &info
->icount
;
2499 /* update input line counters */
2500 if (status
& MISCSTATUS_RI_LATCHED
) {
2502 if ( status
& SerialSignal_RI
)
2503 info
->input_signal_events
.ri_up
++;
2505 info
->input_signal_events
.ri_down
++;
2507 if (status
& MISCSTATUS_DSR_LATCHED
) {
2509 if ( status
& SerialSignal_DSR
)
2510 info
->input_signal_events
.dsr_up
++;
2512 info
->input_signal_events
.dsr_down
++;
2514 if (status
& MISCSTATUS_DCD_LATCHED
) {
2515 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
) {
2516 info
->ie1_value
&= ~CDCD
;
2517 write_reg(info
, IE1
, info
->ie1_value
);
2520 if (status
& SerialSignal_DCD
) {
2521 info
->input_signal_events
.dcd_up
++;
2523 info
->input_signal_events
.dcd_down
++;
2526 hdlc_set_carrier(status
& SerialSignal_DCD
, info
->netdev
);
2529 if (status
& MISCSTATUS_CTS_LATCHED
)
2531 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
) {
2532 info
->ie1_value
&= ~CCTS
;
2533 write_reg(info
, IE1
, info
->ie1_value
);
2536 if ( status
& SerialSignal_CTS
)
2537 info
->input_signal_events
.cts_up
++;
2539 info
->input_signal_events
.cts_down
++;
2541 wake_up_interruptible(&info
->status_event_wait_q
);
2542 wake_up_interruptible(&info
->event_wait_q
);
2544 if ( (info
->flags
& ASYNC_CHECK_CD
) &&
2545 (status
& MISCSTATUS_DCD_LATCHED
) ) {
2546 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2547 printk("%s CD now %s...", info
->device_name
,
2548 (status
& SerialSignal_DCD
) ? "on" : "off");
2549 if (status
& SerialSignal_DCD
)
2550 wake_up_interruptible(&info
->open_wait
);
2552 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2553 printk("doing serial hangup...");
2555 tty_hangup(info
->tty
);
2559 if ( (info
->flags
& ASYNC_CTS_FLOW
) &&
2560 (status
& MISCSTATUS_CTS_LATCHED
) ) {
2562 if (info
->tty
->hw_stopped
) {
2563 if (status
& SerialSignal_CTS
) {
2564 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2565 printk("CTS tx start...");
2566 info
->tty
->hw_stopped
= 0;
2568 info
->pending_bh
|= BH_TRANSMIT
;
2572 if (!(status
& SerialSignal_CTS
)) {
2573 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2574 printk("CTS tx stop...");
2575 info
->tty
->hw_stopped
= 1;
2583 info
->pending_bh
|= BH_STATUS
;
2586 /* Interrupt service routine entry point.
2589 * irq interrupt number that caused interrupt
2590 * dev_id device ID supplied during interrupt registration
2591 * regs interrupted processor context
2593 static irqreturn_t
synclinkmp_interrupt(int irq
, void *dev_id
,
2594 struct pt_regs
*regs
)
2597 unsigned char status
, status0
, status1
=0;
2598 unsigned char dmastatus
, dmastatus0
, dmastatus1
=0;
2599 unsigned char timerstatus0
, timerstatus1
=0;
2600 unsigned char shift
;
2604 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2605 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2606 __FILE__
,__LINE__
,irq
);
2608 info
= (SLMP_INFO
*)dev_id
;
2612 spin_lock(&info
->lock
);
2616 /* get status for SCA0 (ports 0-1) */
2617 tmp
= read_reg16(info
, ISR0
); /* get ISR0 and ISR1 in one read */
2618 status0
= (unsigned char)tmp
;
2619 dmastatus0
= (unsigned char)(tmp
>>8);
2620 timerstatus0
= read_reg(info
, ISR2
);
2622 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2623 printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2624 __FILE__
,__LINE__
,info
->device_name
,
2625 status0
,dmastatus0
,timerstatus0
);
2627 if (info
->port_count
== 4) {
2628 /* get status for SCA1 (ports 2-3) */
2629 tmp
= read_reg16(info
->port_array
[2], ISR0
);
2630 status1
= (unsigned char)tmp
;
2631 dmastatus1
= (unsigned char)(tmp
>>8);
2632 timerstatus1
= read_reg(info
->port_array
[2], ISR2
);
2634 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2635 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2636 __FILE__
,__LINE__
,info
->device_name
,
2637 status1
,dmastatus1
,timerstatus1
);
2640 if (!status0
&& !dmastatus0
&& !timerstatus0
&&
2641 !status1
&& !dmastatus1
&& !timerstatus1
)
2644 for(i
=0; i
< info
->port_count
; i
++) {
2645 if (info
->port_array
[i
] == NULL
)
2649 dmastatus
= dmastatus0
;
2652 dmastatus
= dmastatus1
;
2655 shift
= i
& 1 ? 4 :0;
2657 if (status
& BIT0
<< shift
)
2658 isr_rxrdy(info
->port_array
[i
]);
2659 if (status
& BIT1
<< shift
)
2660 isr_txrdy(info
->port_array
[i
]);
2661 if (status
& BIT2
<< shift
)
2662 isr_rxint(info
->port_array
[i
]);
2663 if (status
& BIT3
<< shift
)
2664 isr_txint(info
->port_array
[i
]);
2666 if (dmastatus
& BIT0
<< shift
)
2667 isr_rxdmaerror(info
->port_array
[i
]);
2668 if (dmastatus
& BIT1
<< shift
)
2669 isr_rxdmaok(info
->port_array
[i
]);
2670 if (dmastatus
& BIT2
<< shift
)
2671 isr_txdmaerror(info
->port_array
[i
]);
2672 if (dmastatus
& BIT3
<< shift
)
2673 isr_txdmaok(info
->port_array
[i
]);
2676 if (timerstatus0
& (BIT5
| BIT4
))
2677 isr_timer(info
->port_array
[0]);
2678 if (timerstatus0
& (BIT7
| BIT6
))
2679 isr_timer(info
->port_array
[1]);
2680 if (timerstatus1
& (BIT5
| BIT4
))
2681 isr_timer(info
->port_array
[2]);
2682 if (timerstatus1
& (BIT7
| BIT6
))
2683 isr_timer(info
->port_array
[3]);
2686 for(i
=0; i
< info
->port_count
; i
++) {
2687 SLMP_INFO
* port
= info
->port_array
[i
];
2689 /* Request bottom half processing if there's something
2690 * for it to do and the bh is not already running.
2692 * Note: startup adapter diags require interrupts.
2693 * do not request bottom half processing if the
2694 * device is not open in a normal mode.
2696 if ( port
&& (port
->count
|| port
->netcount
) &&
2697 port
->pending_bh
&& !port
->bh_running
&&
2698 !port
->bh_requested
) {
2699 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2700 printk("%s(%d):%s queueing bh task.\n",
2701 __FILE__
,__LINE__
,port
->device_name
);
2702 schedule_work(&port
->task
);
2703 port
->bh_requested
= 1;
2707 spin_unlock(&info
->lock
);
2709 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2710 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2711 __FILE__
,__LINE__
,irq
);
2715 /* Initialize and start device.
2717 static int startup(SLMP_INFO
* info
)
2719 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2720 printk("%s(%d):%s tx_releaseup()\n",__FILE__
,__LINE__
,info
->device_name
);
2722 if (info
->flags
& ASYNC_INITIALIZED
)
2725 if (!info
->tx_buf
) {
2726 info
->tx_buf
= (unsigned char *)kmalloc(info
->max_frame_size
, GFP_KERNEL
);
2727 if (!info
->tx_buf
) {
2728 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
2729 __FILE__
,__LINE__
,info
->device_name
);
2734 info
->pending_bh
= 0;
2736 memset(&info
->icount
, 0, sizeof(info
->icount
));
2738 /* program hardware for current parameters */
2741 change_params(info
);
2743 info
->status_timer
.expires
= jiffies
+ msecs_to_jiffies(10);
2744 add_timer(&info
->status_timer
);
2747 clear_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2749 info
->flags
|= ASYNC_INITIALIZED
;
2754 /* Called by close() and hangup() to shutdown hardware
2756 static void shutdown(SLMP_INFO
* info
)
2758 unsigned long flags
;
2760 if (!(info
->flags
& ASYNC_INITIALIZED
))
2763 if (debug_level
>= DEBUG_LEVEL_INFO
)
2764 printk("%s(%d):%s synclinkmp_shutdown()\n",
2765 __FILE__
,__LINE__
, info
->device_name
);
2767 /* clear status wait queue because status changes */
2768 /* can't happen after shutting down the hardware */
2769 wake_up_interruptible(&info
->status_event_wait_q
);
2770 wake_up_interruptible(&info
->event_wait_q
);
2772 del_timer(&info
->tx_timer
);
2773 del_timer(&info
->status_timer
);
2775 kfree(info
->tx_buf
);
2776 info
->tx_buf
= NULL
;
2778 spin_lock_irqsave(&info
->lock
,flags
);
2782 if (!info
->tty
|| info
->tty
->termios
->c_cflag
& HUPCL
) {
2783 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
2787 spin_unlock_irqrestore(&info
->lock
,flags
);
2790 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2792 info
->flags
&= ~ASYNC_INITIALIZED
;
2795 static void program_hw(SLMP_INFO
*info
)
2797 unsigned long flags
;
2799 spin_lock_irqsave(&info
->lock
,flags
);
2804 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
2806 if (info
->params
.mode
== MGSL_MODE_HDLC
|| info
->netcount
)
2813 info
->dcd_chkcount
= 0;
2814 info
->cts_chkcount
= 0;
2815 info
->ri_chkcount
= 0;
2816 info
->dsr_chkcount
= 0;
2818 info
->ie1_value
|= (CDCD
|CCTS
);
2819 write_reg(info
, IE1
, info
->ie1_value
);
2823 if (info
->netcount
|| (info
->tty
&& info
->tty
->termios
->c_cflag
& CREAD
) )
2826 spin_unlock_irqrestore(&info
->lock
,flags
);
2829 /* Reconfigure adapter based on new parameters
2831 static void change_params(SLMP_INFO
*info
)
2836 if (!info
->tty
|| !info
->tty
->termios
)
2839 if (debug_level
>= DEBUG_LEVEL_INFO
)
2840 printk("%s(%d):%s change_params()\n",
2841 __FILE__
,__LINE__
, info
->device_name
);
2843 cflag
= info
->tty
->termios
->c_cflag
;
2845 /* if B0 rate (hangup) specified then negate DTR and RTS */
2846 /* otherwise assert DTR and RTS */
2848 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
2850 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
2852 /* byte size and parity */
2854 switch (cflag
& CSIZE
) {
2855 case CS5
: info
->params
.data_bits
= 5; break;
2856 case CS6
: info
->params
.data_bits
= 6; break;
2857 case CS7
: info
->params
.data_bits
= 7; break;
2858 case CS8
: info
->params
.data_bits
= 8; break;
2859 /* Never happens, but GCC is too dumb to figure it out */
2860 default: info
->params
.data_bits
= 7; break;
2864 info
->params
.stop_bits
= 2;
2866 info
->params
.stop_bits
= 1;
2868 info
->params
.parity
= ASYNC_PARITY_NONE
;
2869 if (cflag
& PARENB
) {
2871 info
->params
.parity
= ASYNC_PARITY_ODD
;
2873 info
->params
.parity
= ASYNC_PARITY_EVEN
;
2876 info
->params
.parity
= ASYNC_PARITY_SPACE
;
2880 /* calculate number of jiffies to transmit a full
2881 * FIFO (32 bytes) at specified data rate
2883 bits_per_char
= info
->params
.data_bits
+
2884 info
->params
.stop_bits
+ 1;
2886 /* if port data rate is set to 460800 or less then
2887 * allow tty settings to override, otherwise keep the
2888 * current data rate.
2890 if (info
->params
.data_rate
<= 460800) {
2891 info
->params
.data_rate
= tty_get_baud_rate(info
->tty
);
2894 if ( info
->params
.data_rate
) {
2895 info
->timeout
= (32*HZ
*bits_per_char
) /
2896 info
->params
.data_rate
;
2898 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
2900 if (cflag
& CRTSCTS
)
2901 info
->flags
|= ASYNC_CTS_FLOW
;
2903 info
->flags
&= ~ASYNC_CTS_FLOW
;
2906 info
->flags
&= ~ASYNC_CHECK_CD
;
2908 info
->flags
|= ASYNC_CHECK_CD
;
2910 /* process tty input control flags */
2912 info
->read_status_mask2
= OVRN
;
2913 if (I_INPCK(info
->tty
))
2914 info
->read_status_mask2
|= PE
| FRME
;
2915 if (I_BRKINT(info
->tty
) || I_PARMRK(info
->tty
))
2916 info
->read_status_mask1
|= BRKD
;
2917 if (I_IGNPAR(info
->tty
))
2918 info
->ignore_status_mask2
|= PE
| FRME
;
2919 if (I_IGNBRK(info
->tty
)) {
2920 info
->ignore_status_mask1
|= BRKD
;
2921 /* If ignoring parity and break indicators, ignore
2922 * overruns too. (For real raw support).
2924 if (I_IGNPAR(info
->tty
))
2925 info
->ignore_status_mask2
|= OVRN
;
2931 static int get_stats(SLMP_INFO
* info
, struct mgsl_icount __user
*user_icount
)
2935 if (debug_level
>= DEBUG_LEVEL_INFO
)
2936 printk("%s(%d):%s get_params()\n",
2937 __FILE__
,__LINE__
, info
->device_name
);
2940 memset(&info
->icount
, 0, sizeof(info
->icount
));
2942 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2950 static int get_params(SLMP_INFO
* info
, MGSL_PARAMS __user
*user_params
)
2953 if (debug_level
>= DEBUG_LEVEL_INFO
)
2954 printk("%s(%d):%s get_params()\n",
2955 __FILE__
,__LINE__
, info
->device_name
);
2957 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2959 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2960 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2961 __FILE__
,__LINE__
,info
->device_name
);
2968 static int set_params(SLMP_INFO
* info
, MGSL_PARAMS __user
*new_params
)
2970 unsigned long flags
;
2971 MGSL_PARAMS tmp_params
;
2974 if (debug_level
>= DEBUG_LEVEL_INFO
)
2975 printk("%s(%d):%s set_params\n",
2976 __FILE__
,__LINE__
,info
->device_name
);
2977 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2979 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2980 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2981 __FILE__
,__LINE__
,info
->device_name
);
2985 spin_lock_irqsave(&info
->lock
,flags
);
2986 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2987 spin_unlock_irqrestore(&info
->lock
,flags
);
2989 change_params(info
);
2994 static int get_txidle(SLMP_INFO
* info
, int __user
*idle_mode
)
2998 if (debug_level
>= DEBUG_LEVEL_INFO
)
2999 printk("%s(%d):%s get_txidle()=%d\n",
3000 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
3002 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
3004 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3005 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3006 __FILE__
,__LINE__
,info
->device_name
);
3013 static int set_txidle(SLMP_INFO
* info
, int idle_mode
)
3015 unsigned long flags
;
3017 if (debug_level
>= DEBUG_LEVEL_INFO
)
3018 printk("%s(%d):%s set_txidle(%d)\n",
3019 __FILE__
,__LINE__
,info
->device_name
, idle_mode
);
3021 spin_lock_irqsave(&info
->lock
,flags
);
3022 info
->idle_mode
= idle_mode
;
3023 tx_set_idle( info
);
3024 spin_unlock_irqrestore(&info
->lock
,flags
);
3028 static int tx_enable(SLMP_INFO
* info
, int enable
)
3030 unsigned long flags
;
3032 if (debug_level
>= DEBUG_LEVEL_INFO
)
3033 printk("%s(%d):%s tx_enable(%d)\n",
3034 __FILE__
,__LINE__
,info
->device_name
, enable
);
3036 spin_lock_irqsave(&info
->lock
,flags
);
3038 if ( !info
->tx_enabled
) {
3042 if ( info
->tx_enabled
)
3045 spin_unlock_irqrestore(&info
->lock
,flags
);
3049 /* abort send HDLC frame
3051 static int tx_abort(SLMP_INFO
* info
)
3053 unsigned long flags
;
3055 if (debug_level
>= DEBUG_LEVEL_INFO
)
3056 printk("%s(%d):%s tx_abort()\n",
3057 __FILE__
,__LINE__
,info
->device_name
);
3059 spin_lock_irqsave(&info
->lock
,flags
);
3060 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
3061 info
->ie1_value
&= ~UDRN
;
3062 info
->ie1_value
|= IDLE
;
3063 write_reg(info
, IE1
, info
->ie1_value
); /* disable tx status interrupts */
3064 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
)); /* clear pending */
3066 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
3067 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
3069 write_reg(info
, CMD
, TXABORT
);
3071 spin_unlock_irqrestore(&info
->lock
,flags
);
3075 static int rx_enable(SLMP_INFO
* info
, int enable
)
3077 unsigned long flags
;
3079 if (debug_level
>= DEBUG_LEVEL_INFO
)
3080 printk("%s(%d):%s rx_enable(%d)\n",
3081 __FILE__
,__LINE__
,info
->device_name
,enable
);
3083 spin_lock_irqsave(&info
->lock
,flags
);
3085 if ( !info
->rx_enabled
)
3088 if ( info
->rx_enabled
)
3091 spin_unlock_irqrestore(&info
->lock
,flags
);
3095 /* wait for specified event to occur
3097 static int wait_mgsl_event(SLMP_INFO
* info
, int __user
*mask_ptr
)
3099 unsigned long flags
;
3102 struct mgsl_icount cprev
, cnow
;
3105 struct _input_signal_events oldsigs
, newsigs
;
3106 DECLARE_WAITQUEUE(wait
, current
);
3108 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
3113 if (debug_level
>= DEBUG_LEVEL_INFO
)
3114 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3115 __FILE__
,__LINE__
,info
->device_name
,mask
);
3117 spin_lock_irqsave(&info
->lock
,flags
);
3119 /* return immediately if state matches requested events */
3121 s
= info
->serial_signals
;
3124 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
3125 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
3126 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
3127 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
3129 spin_unlock_irqrestore(&info
->lock
,flags
);
3133 /* save current irq counts */
3134 cprev
= info
->icount
;
3135 oldsigs
= info
->input_signal_events
;
3137 /* enable hunt and idle irqs if needed */
3138 if (mask
& (MgslEvent_ExitHuntMode
+MgslEvent_IdleReceived
)) {
3139 unsigned char oldval
= info
->ie1_value
;
3140 unsigned char newval
= oldval
+
3141 (mask
& MgslEvent_ExitHuntMode
? FLGD
:0) +
3142 (mask
& MgslEvent_IdleReceived
? IDLD
:0);
3143 if ( oldval
!= newval
) {
3144 info
->ie1_value
= newval
;
3145 write_reg(info
, IE1
, info
->ie1_value
);
3149 set_current_state(TASK_INTERRUPTIBLE
);
3150 add_wait_queue(&info
->event_wait_q
, &wait
);
3152 spin_unlock_irqrestore(&info
->lock
,flags
);
3156 if (signal_pending(current
)) {
3161 /* get current irq counts */
3162 spin_lock_irqsave(&info
->lock
,flags
);
3163 cnow
= info
->icount
;
3164 newsigs
= info
->input_signal_events
;
3165 set_current_state(TASK_INTERRUPTIBLE
);
3166 spin_unlock_irqrestore(&info
->lock
,flags
);
3168 /* if no change, wait aborted for some reason */
3169 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
3170 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
3171 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
3172 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
3173 newsigs
.cts_up
== oldsigs
.cts_up
&&
3174 newsigs
.cts_down
== oldsigs
.cts_down
&&
3175 newsigs
.ri_up
== oldsigs
.ri_up
&&
3176 newsigs
.ri_down
== oldsigs
.ri_down
&&
3177 cnow
.exithunt
== cprev
.exithunt
&&
3178 cnow
.rxidle
== cprev
.rxidle
) {
3184 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
3185 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
3186 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
3187 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
3188 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
3189 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
3190 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
3191 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
3192 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
3193 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
3201 remove_wait_queue(&info
->event_wait_q
, &wait
);
3202 set_current_state(TASK_RUNNING
);
3205 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
3206 spin_lock_irqsave(&info
->lock
,flags
);
3207 if (!waitqueue_active(&info
->event_wait_q
)) {
3208 /* disable enable exit hunt mode/idle rcvd IRQs */
3209 info
->ie1_value
&= ~(FLGD
|IDLD
);
3210 write_reg(info
, IE1
, info
->ie1_value
);
3212 spin_unlock_irqrestore(&info
->lock
,flags
);
3216 PUT_USER(rc
, events
, mask_ptr
);
3221 static int modem_input_wait(SLMP_INFO
*info
,int arg
)
3223 unsigned long flags
;
3225 struct mgsl_icount cprev
, cnow
;
3226 DECLARE_WAITQUEUE(wait
, current
);
3228 /* save current irq counts */
3229 spin_lock_irqsave(&info
->lock
,flags
);
3230 cprev
= info
->icount
;
3231 add_wait_queue(&info
->status_event_wait_q
, &wait
);
3232 set_current_state(TASK_INTERRUPTIBLE
);
3233 spin_unlock_irqrestore(&info
->lock
,flags
);
3237 if (signal_pending(current
)) {
3242 /* get new irq counts */
3243 spin_lock_irqsave(&info
->lock
,flags
);
3244 cnow
= info
->icount
;
3245 set_current_state(TASK_INTERRUPTIBLE
);
3246 spin_unlock_irqrestore(&info
->lock
,flags
);
3248 /* if no change, wait aborted for some reason */
3249 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
3250 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
3255 /* check for change in caller specified modem input */
3256 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
3257 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
3258 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
3259 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
3266 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
3267 set_current_state(TASK_RUNNING
);
3271 /* return the state of the serial control and status signals
3273 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
3275 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
3276 unsigned int result
;
3277 unsigned long flags
;
3279 spin_lock_irqsave(&info
->lock
,flags
);
3281 spin_unlock_irqrestore(&info
->lock
,flags
);
3283 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
3284 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
3285 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
3286 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
3287 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
3288 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
3290 if (debug_level
>= DEBUG_LEVEL_INFO
)
3291 printk("%s(%d):%s tiocmget() value=%08X\n",
3292 __FILE__
,__LINE__
, info
->device_name
, result
);
3296 /* set modem control signals (DTR/RTS)
3298 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
3299 unsigned int set
, unsigned int clear
)
3301 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
3302 unsigned long flags
;
3304 if (debug_level
>= DEBUG_LEVEL_INFO
)
3305 printk("%s(%d):%s tiocmset(%x,%x)\n",
3306 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
3308 if (set
& TIOCM_RTS
)
3309 info
->serial_signals
|= SerialSignal_RTS
;
3310 if (set
& TIOCM_DTR
)
3311 info
->serial_signals
|= SerialSignal_DTR
;
3312 if (clear
& TIOCM_RTS
)
3313 info
->serial_signals
&= ~SerialSignal_RTS
;
3314 if (clear
& TIOCM_DTR
)
3315 info
->serial_signals
&= ~SerialSignal_DTR
;
3317 spin_lock_irqsave(&info
->lock
,flags
);
3319 spin_unlock_irqrestore(&info
->lock
,flags
);
3326 /* Block the current process until the specified port is ready to open.
3328 static int block_til_ready(struct tty_struct
*tty
, struct file
*filp
,
3331 DECLARE_WAITQUEUE(wait
, current
);
3333 int do_clocal
= 0, extra_count
= 0;
3334 unsigned long flags
;
3336 if (debug_level
>= DEBUG_LEVEL_INFO
)
3337 printk("%s(%d):%s block_til_ready()\n",
3338 __FILE__
,__LINE__
, tty
->driver
->name
);
3340 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3341 /* nonblock mode is set or port is not enabled */
3342 /* just verify that callout device is not active */
3343 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3347 if (tty
->termios
->c_cflag
& CLOCAL
)
3350 /* Wait for carrier detect and the line to become
3351 * free (i.e., not in use by the callout). While we are in
3352 * this loop, info->count is dropped by one, so that
3353 * close() knows when to free things. We restore it upon
3354 * exit, either normal or abnormal.
3358 add_wait_queue(&info
->open_wait
, &wait
);
3360 if (debug_level
>= DEBUG_LEVEL_INFO
)
3361 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3362 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3364 spin_lock_irqsave(&info
->lock
, flags
);
3365 if (!tty_hung_up_p(filp
)) {
3369 spin_unlock_irqrestore(&info
->lock
, flags
);
3370 info
->blocked_open
++;
3373 if ((tty
->termios
->c_cflag
& CBAUD
)) {
3374 spin_lock_irqsave(&info
->lock
,flags
);
3375 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3377 spin_unlock_irqrestore(&info
->lock
,flags
);
3380 set_current_state(TASK_INTERRUPTIBLE
);
3382 if (tty_hung_up_p(filp
) || !(info
->flags
& ASYNC_INITIALIZED
)){
3383 retval
= (info
->flags
& ASYNC_HUP_NOTIFY
) ?
3384 -EAGAIN
: -ERESTARTSYS
;
3388 spin_lock_irqsave(&info
->lock
,flags
);
3390 spin_unlock_irqrestore(&info
->lock
,flags
);
3392 if (!(info
->flags
& ASYNC_CLOSING
) &&
3393 (do_clocal
|| (info
->serial_signals
& SerialSignal_DCD
)) ) {
3397 if (signal_pending(current
)) {
3398 retval
= -ERESTARTSYS
;
3402 if (debug_level
>= DEBUG_LEVEL_INFO
)
3403 printk("%s(%d):%s block_til_ready() count=%d\n",
3404 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3409 set_current_state(TASK_RUNNING
);
3410 remove_wait_queue(&info
->open_wait
, &wait
);
3414 info
->blocked_open
--;
3416 if (debug_level
>= DEBUG_LEVEL_INFO
)
3417 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3418 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3421 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3426 int alloc_dma_bufs(SLMP_INFO
*info
)
3428 unsigned short BuffersPerFrame
;
3429 unsigned short BufferCount
;
3431 // Force allocation to start at 64K boundary for each port.
3432 // This is necessary because *all* buffer descriptors for a port
3433 // *must* be in the same 64K block. All descriptors on a port
3434 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3435 // into the CBP register.
3436 info
->port_array
[0]->last_mem_alloc
= (SCA_MEM_SIZE
/4) * info
->port_num
;
3438 /* Calculate the number of DMA buffers necessary to hold the */
3439 /* largest allowable frame size. Note: If the max frame size is */
3440 /* not an even multiple of the DMA buffer size then we need to */
3441 /* round the buffer count per frame up one. */
3443 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/SCABUFSIZE
);
3444 if ( info
->max_frame_size
% SCABUFSIZE
)
3447 /* calculate total number of data buffers (SCABUFSIZE) possible
3448 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3449 * for the descriptor list (BUFFERLISTSIZE).
3451 BufferCount
= (SCA_MEM_SIZE
/4 - BUFFERLISTSIZE
)/SCABUFSIZE
;
3453 /* limit number of buffers to maximum amount of descriptors */
3454 if (BufferCount
> BUFFERLISTSIZE
/sizeof(SCADESC
))
3455 BufferCount
= BUFFERLISTSIZE
/sizeof(SCADESC
);
3457 /* use enough buffers to transmit one max size frame */
3458 info
->tx_buf_count
= BuffersPerFrame
+ 1;
3460 /* never use more than half the available buffers for transmit */
3461 if (info
->tx_buf_count
> (BufferCount
/2))
3462 info
->tx_buf_count
= BufferCount
/2;
3464 if (info
->tx_buf_count
> SCAMAXDESC
)
3465 info
->tx_buf_count
= SCAMAXDESC
;
3467 /* use remaining buffers for receive */
3468 info
->rx_buf_count
= BufferCount
- info
->tx_buf_count
;
3470 if (info
->rx_buf_count
> SCAMAXDESC
)
3471 info
->rx_buf_count
= SCAMAXDESC
;
3473 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3474 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3475 __FILE__
,__LINE__
, info
->device_name
,
3476 info
->tx_buf_count
,info
->rx_buf_count
);
3478 if ( alloc_buf_list( info
) < 0 ||
3479 alloc_frame_bufs(info
,
3481 info
->rx_buf_list_ex
,
3482 info
->rx_buf_count
) < 0 ||
3483 alloc_frame_bufs(info
,
3485 info
->tx_buf_list_ex
,
3486 info
->tx_buf_count
) < 0 ||
3487 alloc_tmp_rx_buf(info
) < 0 ) {
3488 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3489 __FILE__
,__LINE__
, info
->device_name
);
3493 rx_reset_buffers( info
);
3498 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3500 int alloc_buf_list(SLMP_INFO
*info
)
3504 /* build list in adapter shared memory */
3505 info
->buffer_list
= info
->memory_base
+ info
->port_array
[0]->last_mem_alloc
;
3506 info
->buffer_list_phys
= info
->port_array
[0]->last_mem_alloc
;
3507 info
->port_array
[0]->last_mem_alloc
+= BUFFERLISTSIZE
;
3509 memset(info
->buffer_list
, 0, BUFFERLISTSIZE
);
3511 /* Save virtual address pointers to the receive and */
3512 /* transmit buffer lists. (Receive 1st). These pointers will */
3513 /* be used by the processor to access the lists. */
3514 info
->rx_buf_list
= (SCADESC
*)info
->buffer_list
;
3516 info
->tx_buf_list
= (SCADESC
*)info
->buffer_list
;
3517 info
->tx_buf_list
+= info
->rx_buf_count
;
3519 /* Build links for circular buffer entry lists (tx and rx)
3521 * Note: links are physical addresses read by the SCA device
3522 * to determine the next buffer entry to use.
3525 for ( i
= 0; i
< info
->rx_buf_count
; i
++ ) {
3526 /* calculate and store physical address of this buffer entry */
3527 info
->rx_buf_list_ex
[i
].phys_entry
=
3528 info
->buffer_list_phys
+ (i
* sizeof(SCABUFSIZE
));
3530 /* calculate and store physical address of */
3531 /* next entry in cirular list of entries */
3532 info
->rx_buf_list
[i
].next
= info
->buffer_list_phys
;
3533 if ( i
< info
->rx_buf_count
- 1 )
3534 info
->rx_buf_list
[i
].next
+= (i
+ 1) * sizeof(SCADESC
);
3536 info
->rx_buf_list
[i
].length
= SCABUFSIZE
;
3539 for ( i
= 0; i
< info
->tx_buf_count
; i
++ ) {
3540 /* calculate and store physical address of this buffer entry */
3541 info
->tx_buf_list_ex
[i
].phys_entry
= info
->buffer_list_phys
+
3542 ((info
->rx_buf_count
+ i
) * sizeof(SCADESC
));
3544 /* calculate and store physical address of */
3545 /* next entry in cirular list of entries */
3547 info
->tx_buf_list
[i
].next
= info
->buffer_list_phys
+
3548 info
->rx_buf_count
* sizeof(SCADESC
);
3550 if ( i
< info
->tx_buf_count
- 1 )
3551 info
->tx_buf_list
[i
].next
+= (i
+ 1) * sizeof(SCADESC
);
3557 /* Allocate the frame DMA buffers used by the specified buffer list.
3559 int alloc_frame_bufs(SLMP_INFO
*info
, SCADESC
*buf_list
,SCADESC_EX
*buf_list_ex
,int count
)
3562 unsigned long phys_addr
;
3564 for ( i
= 0; i
< count
; i
++ ) {
3565 buf_list_ex
[i
].virt_addr
= info
->memory_base
+ info
->port_array
[0]->last_mem_alloc
;
3566 phys_addr
= info
->port_array
[0]->last_mem_alloc
;
3567 info
->port_array
[0]->last_mem_alloc
+= SCABUFSIZE
;
3569 buf_list
[i
].buf_ptr
= (unsigned short)phys_addr
;
3570 buf_list
[i
].buf_base
= (unsigned char)(phys_addr
>> 16);
3576 void free_dma_bufs(SLMP_INFO
*info
)
3578 info
->buffer_list
= NULL
;
3579 info
->rx_buf_list
= NULL
;
3580 info
->tx_buf_list
= NULL
;
3583 /* allocate buffer large enough to hold max_frame_size.
3584 * This buffer is used to pass an assembled frame to the line discipline.
3586 int alloc_tmp_rx_buf(SLMP_INFO
*info
)
3588 info
->tmp_rx_buf
= kmalloc(info
->max_frame_size
, GFP_KERNEL
);
3589 if (info
->tmp_rx_buf
== NULL
)
3594 void free_tmp_rx_buf(SLMP_INFO
*info
)
3596 kfree(info
->tmp_rx_buf
);
3597 info
->tmp_rx_buf
= NULL
;
3600 int claim_resources(SLMP_INFO
*info
)
3602 if (request_mem_region(info
->phys_memory_base
,SCA_MEM_SIZE
,"synclinkmp") == NULL
) {
3603 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3604 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3605 info
->init_error
= DiagStatus_AddressConflict
;
3609 info
->shared_mem_requested
= 1;
3611 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclinkmp") == NULL
) {
3612 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3613 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
3614 info
->init_error
= DiagStatus_AddressConflict
;
3618 info
->lcr_mem_requested
= 1;
3620 if (request_mem_region(info
->phys_sca_base
+ info
->sca_offset
,SCA_BASE_SIZE
,"synclinkmp") == NULL
) {
3621 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3622 __FILE__
,__LINE__
,info
->device_name
, info
->phys_sca_base
);
3623 info
->init_error
= DiagStatus_AddressConflict
;
3627 info
->sca_base_requested
= 1;
3629 if (request_mem_region(info
->phys_statctrl_base
+ info
->statctrl_offset
,SCA_REG_SIZE
,"synclinkmp") == NULL
) {
3630 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3631 __FILE__
,__LINE__
,info
->device_name
, info
->phys_statctrl_base
);
3632 info
->init_error
= DiagStatus_AddressConflict
;
3636 info
->sca_statctrl_requested
= 1;
3638 info
->memory_base
= ioremap(info
->phys_memory_base
,SCA_MEM_SIZE
);
3639 if (!info
->memory_base
) {
3640 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3641 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3642 info
->init_error
= DiagStatus_CantAssignPciResources
;
3646 info
->lcr_base
= ioremap(info
->phys_lcr_base
,PAGE_SIZE
);
3647 if (!info
->lcr_base
) {
3648 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3649 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
3650 info
->init_error
= DiagStatus_CantAssignPciResources
;
3653 info
->lcr_base
+= info
->lcr_offset
;
3655 info
->sca_base
= ioremap(info
->phys_sca_base
,PAGE_SIZE
);
3656 if (!info
->sca_base
) {
3657 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3658 __FILE__
,__LINE__
,info
->device_name
, info
->phys_sca_base
);
3659 info
->init_error
= DiagStatus_CantAssignPciResources
;
3662 info
->sca_base
+= info
->sca_offset
;
3664 info
->statctrl_base
= ioremap(info
->phys_statctrl_base
,PAGE_SIZE
);
3665 if (!info
->statctrl_base
) {
3666 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3667 __FILE__
,__LINE__
,info
->device_name
, info
->phys_statctrl_base
);
3668 info
->init_error
= DiagStatus_CantAssignPciResources
;
3671 info
->statctrl_base
+= info
->statctrl_offset
;
3673 if ( !memory_test(info
) ) {
3674 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3675 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3676 info
->init_error
= DiagStatus_MemoryError
;
3683 release_resources( info
);
3687 void release_resources(SLMP_INFO
*info
)
3689 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3690 printk( "%s(%d):%s release_resources() entry\n",
3691 __FILE__
,__LINE__
,info
->device_name
);
3693 if ( info
->irq_requested
) {
3694 free_irq(info
->irq_level
, info
);
3695 info
->irq_requested
= 0;
3698 if ( info
->shared_mem_requested
) {
3699 release_mem_region(info
->phys_memory_base
,SCA_MEM_SIZE
);
3700 info
->shared_mem_requested
= 0;
3702 if ( info
->lcr_mem_requested
) {
3703 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
3704 info
->lcr_mem_requested
= 0;
3706 if ( info
->sca_base_requested
) {
3707 release_mem_region(info
->phys_sca_base
+ info
->sca_offset
,SCA_BASE_SIZE
);
3708 info
->sca_base_requested
= 0;
3710 if ( info
->sca_statctrl_requested
) {
3711 release_mem_region(info
->phys_statctrl_base
+ info
->statctrl_offset
,SCA_REG_SIZE
);
3712 info
->sca_statctrl_requested
= 0;
3715 if (info
->memory_base
){
3716 iounmap(info
->memory_base
);
3717 info
->memory_base
= NULL
;
3720 if (info
->sca_base
) {
3721 iounmap(info
->sca_base
- info
->sca_offset
);
3722 info
->sca_base
=NULL
;
3725 if (info
->statctrl_base
) {
3726 iounmap(info
->statctrl_base
- info
->statctrl_offset
);
3727 info
->statctrl_base
=NULL
;
3730 if (info
->lcr_base
){
3731 iounmap(info
->lcr_base
- info
->lcr_offset
);
3732 info
->lcr_base
= NULL
;
3735 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3736 printk( "%s(%d):%s release_resources() exit\n",
3737 __FILE__
,__LINE__
,info
->device_name
);
3740 /* Add the specified device instance data structure to the
3741 * global linked list of devices and increment the device count.
3743 void add_device(SLMP_INFO
*info
)
3745 info
->next_device
= NULL
;
3746 info
->line
= synclinkmp_device_count
;
3747 sprintf(info
->device_name
,"ttySLM%dp%d",info
->adapter_num
,info
->port_num
);
3749 if (info
->line
< MAX_DEVICES
) {
3750 if (maxframe
[info
->line
])
3751 info
->max_frame_size
= maxframe
[info
->line
];
3752 info
->dosyncppp
= dosyncppp
[info
->line
];
3755 synclinkmp_device_count
++;
3757 if ( !synclinkmp_device_list
)
3758 synclinkmp_device_list
= info
;
3760 SLMP_INFO
*current_dev
= synclinkmp_device_list
;
3761 while( current_dev
->next_device
)
3762 current_dev
= current_dev
->next_device
;
3763 current_dev
->next_device
= info
;
3766 if ( info
->max_frame_size
< 4096 )
3767 info
->max_frame_size
= 4096;
3768 else if ( info
->max_frame_size
> 65535 )
3769 info
->max_frame_size
= 65535;
3771 printk( "SyncLink MultiPort %s: "
3772 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3774 info
->phys_sca_base
,
3775 info
->phys_memory_base
,
3776 info
->phys_statctrl_base
,
3777 info
->phys_lcr_base
,
3779 info
->max_frame_size
);
3786 /* Allocate and initialize a device instance structure
3788 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3790 static SLMP_INFO
*alloc_dev(int adapter_num
, int port_num
, struct pci_dev
*pdev
)
3794 info
= (SLMP_INFO
*)kmalloc(sizeof(SLMP_INFO
),
3798 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3799 __FILE__
,__LINE__
, adapter_num
, port_num
);
3801 memset(info
, 0, sizeof(SLMP_INFO
));
3802 info
->magic
= MGSL_MAGIC
;
3803 INIT_WORK(&info
->task
, bh_handler
, info
);
3804 info
->max_frame_size
= 4096;
3805 info
->close_delay
= 5*HZ
/10;
3806 info
->closing_wait
= 30*HZ
;
3807 init_waitqueue_head(&info
->open_wait
);
3808 init_waitqueue_head(&info
->close_wait
);
3809 init_waitqueue_head(&info
->status_event_wait_q
);
3810 init_waitqueue_head(&info
->event_wait_q
);
3811 spin_lock_init(&info
->netlock
);
3812 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
3813 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
3814 info
->adapter_num
= adapter_num
;
3815 info
->port_num
= port_num
;
3817 /* Copy configuration info to device instance data */
3818 info
->irq_level
= pdev
->irq
;
3819 info
->phys_lcr_base
= pci_resource_start(pdev
,0);
3820 info
->phys_sca_base
= pci_resource_start(pdev
,2);
3821 info
->phys_memory_base
= pci_resource_start(pdev
,3);
3822 info
->phys_statctrl_base
= pci_resource_start(pdev
,4);
3824 /* Because veremap only works on page boundaries we must map
3825 * a larger area than is actually implemented for the LCR
3826 * memory range. We map a full page starting at the page boundary.
3828 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
3829 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
3831 info
->sca_offset
= info
->phys_sca_base
& (PAGE_SIZE
-1);
3832 info
->phys_sca_base
&= ~(PAGE_SIZE
-1);
3834 info
->statctrl_offset
= info
->phys_statctrl_base
& (PAGE_SIZE
-1);
3835 info
->phys_statctrl_base
&= ~(PAGE_SIZE
-1);
3837 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
3838 info
->irq_flags
= IRQF_SHARED
;
3840 init_timer(&info
->tx_timer
);
3841 info
->tx_timer
.data
= (unsigned long)info
;
3842 info
->tx_timer
.function
= tx_timeout
;
3844 init_timer(&info
->status_timer
);
3845 info
->status_timer
.data
= (unsigned long)info
;
3846 info
->status_timer
.function
= status_timeout
;
3848 /* Store the PCI9050 misc control register value because a flaw
3849 * in the PCI9050 prevents LCR registers from being read if
3850 * BIOS assigns an LCR base address with bit 7 set.
3852 * Only the misc control register is accessed for which only
3853 * write access is needed, so set an initial value and change
3854 * bits to the device instance data as we write the value
3855 * to the actual misc control register.
3857 info
->misc_ctrl_value
= 0x087e4546;
3859 /* initial port state is unknown - if startup errors
3860 * occur, init_error will be set to indicate the
3861 * problem. Once the port is fully initialized,
3862 * this value will be set to 0 to indicate the
3863 * port is available.
3865 info
->init_error
= -1;
3871 void device_init(int adapter_num
, struct pci_dev
*pdev
)
3873 SLMP_INFO
*port_array
[SCA_MAX_PORTS
];
3876 /* allocate device instances for up to SCA_MAX_PORTS devices */
3877 for ( port
= 0; port
< SCA_MAX_PORTS
; ++port
) {
3878 port_array
[port
] = alloc_dev(adapter_num
,port
,pdev
);
3879 if( port_array
[port
] == NULL
) {
3880 for ( --port
; port
>= 0; --port
)
3881 kfree(port_array
[port
]);
3886 /* give copy of port_array to all ports and add to device list */
3887 for ( port
= 0; port
< SCA_MAX_PORTS
; ++port
) {
3888 memcpy(port_array
[port
]->port_array
,port_array
,sizeof(port_array
));
3889 add_device( port_array
[port
] );
3890 spin_lock_init(&port_array
[port
]->lock
);
3893 /* Allocate and claim adapter resources */
3894 if ( !claim_resources(port_array
[0]) ) {
3896 alloc_dma_bufs(port_array
[0]);
3898 /* copy resource information from first port to others */
3899 for ( port
= 1; port
< SCA_MAX_PORTS
; ++port
) {
3900 port_array
[port
]->lock
= port_array
[0]->lock
;
3901 port_array
[port
]->irq_level
= port_array
[0]->irq_level
;
3902 port_array
[port
]->memory_base
= port_array
[0]->memory_base
;
3903 port_array
[port
]->sca_base
= port_array
[0]->sca_base
;
3904 port_array
[port
]->statctrl_base
= port_array
[0]->statctrl_base
;
3905 port_array
[port
]->lcr_base
= port_array
[0]->lcr_base
;
3906 alloc_dma_bufs(port_array
[port
]);
3909 if ( request_irq(port_array
[0]->irq_level
,
3910 synclinkmp_interrupt
,
3911 port_array
[0]->irq_flags
,
3912 port_array
[0]->device_name
,
3913 port_array
[0]) < 0 ) {
3914 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3916 port_array
[0]->device_name
,
3917 port_array
[0]->irq_level
);
3920 port_array
[0]->irq_requested
= 1;
3921 adapter_test(port_array
[0]);
3926 static struct tty_operations ops
= {
3930 .put_char
= put_char
,
3931 .flush_chars
= flush_chars
,
3932 .write_room
= write_room
,
3933 .chars_in_buffer
= chars_in_buffer
,
3934 .flush_buffer
= flush_buffer
,
3936 .throttle
= throttle
,
3937 .unthrottle
= unthrottle
,
3938 .send_xchar
= send_xchar
,
3939 .break_ctl
= set_break
,
3940 .wait_until_sent
= wait_until_sent
,
3941 .read_proc
= read_proc
,
3942 .set_termios
= set_termios
,
3944 .start
= tx_release
,
3946 .tiocmget
= tiocmget
,
3947 .tiocmset
= tiocmset
,
3950 static void synclinkmp_cleanup(void)
3956 printk("Unloading %s %s\n", driver_name
, driver_version
);
3958 if (serial_driver
) {
3959 if ((rc
= tty_unregister_driver(serial_driver
)))
3960 printk("%s(%d) failed to unregister tty driver err=%d\n",
3961 __FILE__
,__LINE__
,rc
);
3962 put_tty_driver(serial_driver
);
3966 info
= synclinkmp_device_list
;
3969 info
= info
->next_device
;
3972 /* release devices */
3973 info
= synclinkmp_device_list
;
3978 free_dma_bufs(info
);
3979 free_tmp_rx_buf(info
);
3980 if ( info
->port_num
== 0 ) {
3982 write_reg(info
, LPR
, 1); /* set low power mode */
3983 release_resources(info
);
3986 info
= info
->next_device
;
3990 pci_unregister_driver(&synclinkmp_pci_driver
);
3993 /* Driver initialization entry point.
3996 static int __init
synclinkmp_init(void)
4000 if (break_on_load
) {
4001 synclinkmp_get_text_ptr();
4005 printk("%s %s\n", driver_name
, driver_version
);
4007 if ((rc
= pci_register_driver(&synclinkmp_pci_driver
)) < 0) {
4008 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4012 serial_driver
= alloc_tty_driver(128);
4013 if (!serial_driver
) {
4018 /* Initialize the tty_driver structure */
4020 serial_driver
->owner
= THIS_MODULE
;
4021 serial_driver
->driver_name
= "synclinkmp";
4022 serial_driver
->name
= "ttySLM";
4023 serial_driver
->major
= ttymajor
;
4024 serial_driver
->minor_start
= 64;
4025 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4026 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4027 serial_driver
->init_termios
= tty_std_termios
;
4028 serial_driver
->init_termios
.c_cflag
=
4029 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4030 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4031 tty_set_operations(serial_driver
, &ops
);
4032 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4033 printk("%s(%d):Couldn't register serial driver\n",
4035 put_tty_driver(serial_driver
);
4036 serial_driver
= NULL
;
4040 printk("%s %s, tty major#%d\n",
4041 driver_name
, driver_version
,
4042 serial_driver
->major
);
4047 synclinkmp_cleanup();
4051 static void __exit
synclinkmp_exit(void)
4053 synclinkmp_cleanup();
4056 module_init(synclinkmp_init
);
4057 module_exit(synclinkmp_exit
);
4059 /* Set the port for internal loopback mode.
4060 * The TxCLK and RxCLK signals are generated from the BRG and
4061 * the TxD is looped back to the RxD internally.
4063 void enable_loopback(SLMP_INFO
*info
, int enable
)
4066 /* MD2 (Mode Register 2)
4067 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4069 write_reg(info
, MD2
, (unsigned char)(read_reg(info
, MD2
) | (BIT1
+ BIT0
)));
4071 /* degate external TxC clock source */
4072 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4073 write_control_reg(info
);
4075 /* RXS/TXS (Rx/Tx clock source)
4076 * 07 Reserved, must be 0
4077 * 06..04 Clock Source, 100=BRG
4078 * 03..00 Clock Divisor, 0000=1
4080 write_reg(info
, RXS
, 0x40);
4081 write_reg(info
, TXS
, 0x40);
4084 /* MD2 (Mode Register 2)
4085 * 01..00 CNCT<1..0> Channel connection, 0=normal
4087 write_reg(info
, MD2
, (unsigned char)(read_reg(info
, MD2
) & ~(BIT1
+ BIT0
)));
4089 /* RXS/TXS (Rx/Tx clock source)
4090 * 07 Reserved, must be 0
4091 * 06..04 Clock Source, 000=RxC/TxC Pin
4092 * 03..00 Clock Divisor, 0000=1
4094 write_reg(info
, RXS
, 0x00);
4095 write_reg(info
, TXS
, 0x00);
4098 /* set LinkSpeed if available, otherwise default to 2Mbps */
4099 if (info
->params
.clock_speed
)
4100 set_rate(info
, info
->params
.clock_speed
);
4102 set_rate(info
, 3686400);
4105 /* Set the baud rate register to the desired speed
4107 * data_rate data rate of clock in bits per second
4108 * A data rate of 0 disables the AUX clock.
4110 void set_rate( SLMP_INFO
*info
, u32 data_rate
)
4113 unsigned char BRValue
;
4116 /* fBRG = fCLK/(TMC * 2^BR)
4118 if (data_rate
!= 0) {
4119 Divisor
= 14745600/data_rate
;
4126 if (TMCValue
!= 1 && TMCValue
!= 2) {
4127 /* BRValue of 0 provides 50/50 duty cycle *only* when
4128 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4135 /* while TMCValue is too big for TMC register, divide
4136 * by 2 and increment BR exponent.
4138 for(; TMCValue
> 256 && BRValue
< 10; BRValue
++)
4141 write_reg(info
, TXS
,
4142 (unsigned char)((read_reg(info
, TXS
) & 0xf0) | BRValue
));
4143 write_reg(info
, RXS
,
4144 (unsigned char)((read_reg(info
, RXS
) & 0xf0) | BRValue
));
4145 write_reg(info
, TMC
, (unsigned char)TMCValue
);
4148 write_reg(info
, TXS
,0);
4149 write_reg(info
, RXS
,0);
4150 write_reg(info
, TMC
, 0);
4156 void rx_stop(SLMP_INFO
*info
)
4158 if (debug_level
>= DEBUG_LEVEL_ISR
)
4159 printk("%s(%d):%s rx_stop()\n",
4160 __FILE__
,__LINE__
, info
->device_name
);
4162 write_reg(info
, CMD
, RXRESET
);
4164 info
->ie0_value
&= ~RXRDYE
;
4165 write_reg(info
, IE0
, info
->ie0_value
); /* disable Rx data interrupts */
4167 write_reg(info
, RXDMA
+ DSR
, 0); /* disable Rx DMA */
4168 write_reg(info
, RXDMA
+ DCMD
, SWABORT
); /* reset/init Rx DMA */
4169 write_reg(info
, RXDMA
+ DIR, 0); /* disable Rx DMA interrupts */
4171 info
->rx_enabled
= 0;
4172 info
->rx_overflow
= 0;
4175 /* enable the receiver
4177 void rx_start(SLMP_INFO
*info
)
4181 if (debug_level
>= DEBUG_LEVEL_ISR
)
4182 printk("%s(%d):%s rx_start()\n",
4183 __FILE__
,__LINE__
, info
->device_name
);
4185 write_reg(info
, CMD
, RXRESET
);
4187 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
4188 /* HDLC, disabe IRQ on rxdata */
4189 info
->ie0_value
&= ~RXRDYE
;
4190 write_reg(info
, IE0
, info
->ie0_value
);
4192 /* Reset all Rx DMA buffers and program rx dma */
4193 write_reg(info
, RXDMA
+ DSR
, 0); /* disable Rx DMA */
4194 write_reg(info
, RXDMA
+ DCMD
, SWABORT
); /* reset/init Rx DMA */
4196 for (i
= 0; i
< info
->rx_buf_count
; i
++) {
4197 info
->rx_buf_list
[i
].status
= 0xff;
4199 // throttle to 4 shared memory writes at a time to prevent
4200 // hogging local bus (keep latency time for DMA requests low).
4202 read_status_reg(info
);
4204 info
->current_rx_buf
= 0;
4206 /* set current/1st descriptor address */
4207 write_reg16(info
, RXDMA
+ CDA
,
4208 info
->rx_buf_list_ex
[0].phys_entry
);
4210 /* set new last rx descriptor address */
4211 write_reg16(info
, RXDMA
+ EDA
,
4212 info
->rx_buf_list_ex
[info
->rx_buf_count
- 1].phys_entry
);
4214 /* set buffer length (shared by all rx dma data buffers) */
4215 write_reg16(info
, RXDMA
+ BFL
, SCABUFSIZE
);
4217 write_reg(info
, RXDMA
+ DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4218 write_reg(info
, RXDMA
+ DSR
, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4220 /* async, enable IRQ on rxdata */
4221 info
->ie0_value
|= RXRDYE
;
4222 write_reg(info
, IE0
, info
->ie0_value
);
4225 write_reg(info
, CMD
, RXENABLE
);
4227 info
->rx_overflow
= FALSE
;
4228 info
->rx_enabled
= 1;
4231 /* Enable the transmitter and send a transmit frame if
4232 * one is loaded in the DMA buffers.
4234 void tx_start(SLMP_INFO
*info
)
4236 if (debug_level
>= DEBUG_LEVEL_ISR
)
4237 printk("%s(%d):%s tx_start() tx_count=%d\n",
4238 __FILE__
,__LINE__
, info
->device_name
,info
->tx_count
);
4240 if (!info
->tx_enabled
) {
4241 write_reg(info
, CMD
, TXRESET
);
4242 write_reg(info
, CMD
, TXENABLE
);
4243 info
->tx_enabled
= TRUE
;
4246 if ( info
->tx_count
) {
4248 /* If auto RTS enabled and RTS is inactive, then assert */
4249 /* RTS and set a flag indicating that the driver should */
4250 /* negate RTS when the transmission completes. */
4252 info
->drop_rts_on_tx_done
= 0;
4254 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
4256 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
4257 get_signals( info
);
4258 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
4259 info
->serial_signals
|= SerialSignal_RTS
;
4260 set_signals( info
);
4261 info
->drop_rts_on_tx_done
= 1;
4265 write_reg16(info
, TRC0
,
4266 (unsigned short)(((tx_negate_fifo_level
-1)<<8) + tx_active_fifo_level
));
4268 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
4269 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
4271 /* set TX CDA (current descriptor address) */
4272 write_reg16(info
, TXDMA
+ CDA
,
4273 info
->tx_buf_list_ex
[0].phys_entry
);
4275 /* set TX EDA (last descriptor address) */
4276 write_reg16(info
, TXDMA
+ EDA
,
4277 info
->tx_buf_list_ex
[info
->last_tx_buf
].phys_entry
);
4279 /* enable underrun IRQ */
4280 info
->ie1_value
&= ~IDLE
;
4281 info
->ie1_value
|= UDRN
;
4282 write_reg(info
, IE1
, info
->ie1_value
);
4283 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
));
4285 write_reg(info
, TXDMA
+ DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4286 write_reg(info
, TXDMA
+ DSR
, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4288 info
->tx_timer
.expires
= jiffies
+ msecs_to_jiffies(5000);
4289 add_timer(&info
->tx_timer
);
4293 /* async, enable IRQ on txdata */
4294 info
->ie0_value
|= TXRDYE
;
4295 write_reg(info
, IE0
, info
->ie0_value
);
4298 info
->tx_active
= 1;
4302 /* stop the transmitter and DMA
4304 void tx_stop( SLMP_INFO
*info
)
4306 if (debug_level
>= DEBUG_LEVEL_ISR
)
4307 printk("%s(%d):%s tx_stop()\n",
4308 __FILE__
,__LINE__
, info
->device_name
);
4310 del_timer(&info
->tx_timer
);
4312 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
4313 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
4315 write_reg(info
, CMD
, TXRESET
);
4317 info
->ie1_value
&= ~(UDRN
+ IDLE
);
4318 write_reg(info
, IE1
, info
->ie1_value
); /* disable tx status interrupts */
4319 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
)); /* clear pending */
4321 info
->ie0_value
&= ~TXRDYE
;
4322 write_reg(info
, IE0
, info
->ie0_value
); /* disable tx data interrupts */
4324 info
->tx_enabled
= 0;
4325 info
->tx_active
= 0;
4328 /* Fill the transmit FIFO until the FIFO is full or
4329 * there is no more data to load.
4331 void tx_load_fifo(SLMP_INFO
*info
)
4335 /* do nothing is now tx data available and no XON/XOFF pending */
4337 if ( !info
->tx_count
&& !info
->x_char
)
4340 /* load the Transmit FIFO until FIFOs full or all data sent */
4342 while( info
->tx_count
&& (read_reg(info
,SR0
) & BIT1
) ) {
4344 /* there is more space in the transmit FIFO and */
4345 /* there is more data in transmit buffer */
4347 if ( (info
->tx_count
> 1) && !info
->x_char
) {
4349 TwoBytes
[0] = info
->tx_buf
[info
->tx_get
++];
4350 if (info
->tx_get
>= info
->max_frame_size
)
4351 info
->tx_get
-= info
->max_frame_size
;
4352 TwoBytes
[1] = info
->tx_buf
[info
->tx_get
++];
4353 if (info
->tx_get
>= info
->max_frame_size
)
4354 info
->tx_get
-= info
->max_frame_size
;
4356 write_reg16(info
, TRB
, *((u16
*)TwoBytes
));
4358 info
->tx_count
-= 2;
4359 info
->icount
.tx
+= 2;
4361 /* only 1 byte left to transmit or 1 FIFO slot left */
4364 /* transmit pending high priority char */
4365 write_reg(info
, TRB
, info
->x_char
);
4368 write_reg(info
, TRB
, info
->tx_buf
[info
->tx_get
++]);
4369 if (info
->tx_get
>= info
->max_frame_size
)
4370 info
->tx_get
-= info
->max_frame_size
;
4378 /* Reset a port to a known state
4380 void reset_port(SLMP_INFO
*info
)
4382 if (info
->sca_base
) {
4387 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
4390 /* disable all port interrupts */
4391 info
->ie0_value
= 0;
4392 info
->ie1_value
= 0;
4393 info
->ie2_value
= 0;
4394 write_reg(info
, IE0
, info
->ie0_value
);
4395 write_reg(info
, IE1
, info
->ie1_value
);
4396 write_reg(info
, IE2
, info
->ie2_value
);
4398 write_reg(info
, CMD
, CHRESET
);
4402 /* Reset all the ports to a known state.
4404 void reset_adapter(SLMP_INFO
*info
)
4408 for ( i
=0; i
< SCA_MAX_PORTS
; ++i
) {
4409 if (info
->port_array
[i
])
4410 reset_port(info
->port_array
[i
]);
4414 /* Program port for asynchronous communications.
4416 void async_mode(SLMP_INFO
*info
)
4419 unsigned char RegValue
;
4424 /* MD0, Mode Register 0
4426 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4427 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4428 * 03 Reserved, must be 0
4429 * 02 CRCCC, CRC Calculation, 0=disabled
4430 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4435 if (info
->params
.stop_bits
!= 1)
4437 write_reg(info
, MD0
, RegValue
);
4439 /* MD1, Mode Register 1
4441 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4442 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4443 * 03..02 RXCHR<1..0>, rx char size
4444 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4449 switch (info
->params
.data_bits
) {
4450 case 7: RegValue
|= BIT4
+ BIT2
; break;
4451 case 6: RegValue
|= BIT5
+ BIT3
; break;
4452 case 5: RegValue
|= BIT5
+ BIT4
+ BIT3
+ BIT2
; break;
4454 if (info
->params
.parity
!= ASYNC_PARITY_NONE
) {
4456 if (info
->params
.parity
== ASYNC_PARITY_ODD
)
4459 write_reg(info
, MD1
, RegValue
);
4461 /* MD2, Mode Register 2
4463 * 07..02 Reserved, must be 0
4464 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4469 if (info
->params
.loopback
)
4470 RegValue
|= (BIT1
+ BIT0
);
4471 write_reg(info
, MD2
, RegValue
);
4473 /* RXS, Receive clock source
4475 * 07 Reserved, must be 0
4476 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4477 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4480 write_reg(info
, RXS
, RegValue
);
4482 /* TXS, Transmit clock source
4484 * 07 Reserved, must be 0
4485 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4486 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4489 write_reg(info
, TXS
, RegValue
);
4493 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4495 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4496 write_control_reg(info
);
4500 /* RRC Receive Ready Control 0
4502 * 07..05 Reserved, must be 0
4503 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4505 write_reg(info
, RRC
, 0x00);
4507 /* TRC0 Transmit Ready Control 0
4509 * 07..05 Reserved, must be 0
4510 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4512 write_reg(info
, TRC0
, 0x10);
4514 /* TRC1 Transmit Ready Control 1
4516 * 07..05 Reserved, must be 0
4517 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4519 write_reg(info
, TRC1
, 0x1e);
4521 /* CTL, MSCI control register
4523 * 07..06 Reserved, set to 0
4524 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4525 * 04 IDLC, idle control, 0=mark 1=idle register
4526 * 03 BRK, break, 0=off 1 =on (async)
4527 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4528 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4529 * 00 RTS, RTS output control, 0=active 1=inactive
4534 if (!(info
->serial_signals
& SerialSignal_RTS
))
4536 write_reg(info
, CTL
, RegValue
);
4538 /* enable status interrupts */
4539 info
->ie0_value
|= TXINTE
+ RXINTE
;
4540 write_reg(info
, IE0
, info
->ie0_value
);
4542 /* enable break detect interrupt */
4543 info
->ie1_value
= BRKD
;
4544 write_reg(info
, IE1
, info
->ie1_value
);
4546 /* enable rx overrun interrupt */
4547 info
->ie2_value
= OVRN
;
4548 write_reg(info
, IE2
, info
->ie2_value
);
4550 set_rate( info
, info
->params
.data_rate
* 16 );
4553 /* Program the SCA for HDLC communications.
4555 void hdlc_mode(SLMP_INFO
*info
)
4557 unsigned char RegValue
;
4560 // Can't use DPLL because SCA outputs recovered clock on RxC when
4561 // DPLL mode selected. This causes output contention with RxC receiver.
4562 // Use of DPLL would require external hardware to disable RxC receiver
4563 // when DPLL mode selected.
4564 info
->params
.flags
&= ~(HDLC_FLAG_TXC_DPLL
+ HDLC_FLAG_RXC_DPLL
);
4566 /* disable DMA interrupts */
4567 write_reg(info
, TXDMA
+ DIR, 0);
4568 write_reg(info
, RXDMA
+ DIR, 0);
4570 /* MD0, Mode Register 0
4572 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4573 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4574 * 03 Reserved, must be 0
4575 * 02 CRCCC, CRC Calculation, 1=enabled
4576 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4577 * 00 CRC0, CRC initial value, 1 = all 1s
4582 if (info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
4584 if (info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
4586 if (info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
4587 RegValue
|= BIT2
+ BIT1
;
4588 write_reg(info
, MD0
, RegValue
);
4590 /* MD1, Mode Register 1
4592 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4593 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4594 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4595 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4600 write_reg(info
, MD1
, RegValue
);
4602 /* MD2, Mode Register 2
4604 * 07 NRZFM, 0=NRZ, 1=FM
4605 * 06..05 CODE<1..0> Encoding, 00=NRZ
4606 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4607 * 02 Reserved, must be 0
4608 * 01..00 CNCT<1..0> Channel connection, 0=normal
4613 switch(info
->params
.encoding
) {
4614 case HDLC_ENCODING_NRZI
: RegValue
|= BIT5
; break;
4615 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT7
+ BIT5
; break; /* aka FM1 */
4616 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT7
+ BIT6
; break; /* aka FM0 */
4617 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT7
; break; /* aka Manchester */
4619 case HDLC_ENCODING_NRZB
: /* not supported */
4620 case HDLC_ENCODING_NRZI_MARK
: /* not supported */
4621 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: /* not supported */
4624 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
4627 } else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
4633 write_reg(info
, MD2
, RegValue
);
4636 /* RXS, Receive clock source
4638 * 07 Reserved, must be 0
4639 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4640 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4643 if (info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4645 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4646 RegValue
|= BIT6
+ BIT5
;
4647 write_reg(info
, RXS
, RegValue
);
4649 /* TXS, Transmit clock source
4651 * 07 Reserved, must be 0
4652 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4653 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4656 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4658 if (info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4659 RegValue
|= BIT6
+ BIT5
;
4660 write_reg(info
, TXS
, RegValue
);
4662 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4663 set_rate(info
, info
->params
.clock_speed
* DpllDivisor
);
4665 set_rate(info
, info
->params
.clock_speed
);
4667 /* GPDATA (General Purpose I/O Data Register)
4669 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4671 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4672 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4674 info
->port_array
[0]->ctrlreg_value
&= ~(BIT0
<< (info
->port_num
* 2));
4675 write_control_reg(info
);
4677 /* RRC Receive Ready Control 0
4679 * 07..05 Reserved, must be 0
4680 * 04..00 RRC<4..0> Rx FIFO trigger active
4682 write_reg(info
, RRC
, rx_active_fifo_level
);
4684 /* TRC0 Transmit Ready Control 0
4686 * 07..05 Reserved, must be 0
4687 * 04..00 TRC<4..0> Tx FIFO trigger active
4689 write_reg(info
, TRC0
, tx_active_fifo_level
);
4691 /* TRC1 Transmit Ready Control 1
4693 * 07..05 Reserved, must be 0
4694 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4696 write_reg(info
, TRC1
, (unsigned char)(tx_negate_fifo_level
- 1));
4698 /* DMR, DMA Mode Register
4700 * 07..05 Reserved, must be 0
4701 * 04 TMOD, Transfer Mode: 1=chained-block
4702 * 03 Reserved, must be 0
4703 * 02 NF, Number of Frames: 1=multi-frame
4704 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4705 * 00 Reserved, must be 0
4709 write_reg(info
, TXDMA
+ DMR
, 0x14);
4710 write_reg(info
, RXDMA
+ DMR
, 0x14);
4712 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4713 write_reg(info
, RXDMA
+ CPB
,
4714 (unsigned char)(info
->buffer_list_phys
>> 16));
4716 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4717 write_reg(info
, TXDMA
+ CPB
,
4718 (unsigned char)(info
->buffer_list_phys
>> 16));
4720 /* enable status interrupts. other code enables/disables
4721 * the individual sources for these two interrupt classes.
4723 info
->ie0_value
|= TXINTE
+ RXINTE
;
4724 write_reg(info
, IE0
, info
->ie0_value
);
4726 /* CTL, MSCI control register
4728 * 07..06 Reserved, set to 0
4729 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4730 * 04 IDLC, idle control, 0=mark 1=idle register
4731 * 03 BRK, break, 0=off 1 =on (async)
4732 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4733 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4734 * 00 RTS, RTS output control, 0=active 1=inactive
4739 if (!(info
->serial_signals
& SerialSignal_RTS
))
4741 write_reg(info
, CTL
, RegValue
);
4743 /* preamble not supported ! */
4749 set_rate(info
, info
->params
.clock_speed
);
4751 if (info
->params
.loopback
)
4752 enable_loopback(info
,1);
4755 /* Set the transmit HDLC idle mode
4757 void tx_set_idle(SLMP_INFO
*info
)
4759 unsigned char RegValue
= 0xff;
4761 /* Map API idle mode to SCA register bits */
4762 switch(info
->idle_mode
) {
4763 case HDLC_TXIDLE_FLAGS
: RegValue
= 0x7e; break;
4764 case HDLC_TXIDLE_ALT_ZEROS_ONES
: RegValue
= 0xaa; break;
4765 case HDLC_TXIDLE_ZEROS
: RegValue
= 0x00; break;
4766 case HDLC_TXIDLE_ONES
: RegValue
= 0xff; break;
4767 case HDLC_TXIDLE_ALT_MARK_SPACE
: RegValue
= 0xaa; break;
4768 case HDLC_TXIDLE_SPACE
: RegValue
= 0x00; break;
4769 case HDLC_TXIDLE_MARK
: RegValue
= 0xff; break;
4772 write_reg(info
, IDL
, RegValue
);
4775 /* Query the adapter for the state of the V24 status (input) signals.
4777 void get_signals(SLMP_INFO
*info
)
4779 u16 status
= read_reg(info
, SR3
);
4780 u16 gpstatus
= read_status_reg(info
);
4783 /* clear all serial signals except DTR and RTS */
4784 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
4786 /* set serial signal bits to reflect MISR */
4788 if (!(status
& BIT3
))
4789 info
->serial_signals
|= SerialSignal_CTS
;
4791 if ( !(status
& BIT2
))
4792 info
->serial_signals
|= SerialSignal_DCD
;
4794 testbit
= BIT1
<< (info
->port_num
* 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4795 if (!(gpstatus
& testbit
))
4796 info
->serial_signals
|= SerialSignal_RI
;
4798 testbit
= BIT0
<< (info
->port_num
* 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4799 if (!(gpstatus
& testbit
))
4800 info
->serial_signals
|= SerialSignal_DSR
;
4803 /* Set the state of DTR and RTS based on contents of
4804 * serial_signals member of device context.
4806 void set_signals(SLMP_INFO
*info
)
4808 unsigned char RegValue
;
4811 RegValue
= read_reg(info
, CTL
);
4812 if (info
->serial_signals
& SerialSignal_RTS
)
4816 write_reg(info
, CTL
, RegValue
);
4818 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4819 EnableBit
= BIT1
<< (info
->port_num
*2);
4820 if (info
->serial_signals
& SerialSignal_DTR
)
4821 info
->port_array
[0]->ctrlreg_value
&= ~EnableBit
;
4823 info
->port_array
[0]->ctrlreg_value
|= EnableBit
;
4824 write_control_reg(info
);
4827 /*******************/
4828 /* DMA Buffer Code */
4829 /*******************/
4831 /* Set the count for all receive buffers to SCABUFSIZE
4832 * and set the current buffer to the first buffer. This effectively
4833 * makes all buffers free and discards any data in buffers.
4835 void rx_reset_buffers(SLMP_INFO
*info
)
4837 rx_free_frame_buffers(info
, 0, info
->rx_buf_count
- 1);
4840 /* Free the buffers used by a received frame
4842 * info pointer to device instance data
4843 * first index of 1st receive buffer of frame
4844 * last index of last receive buffer of frame
4846 void rx_free_frame_buffers(SLMP_INFO
*info
, unsigned int first
, unsigned int last
)
4851 /* reset current buffer for reuse */
4852 info
->rx_buf_list
[first
].status
= 0xff;
4854 if (first
== last
) {
4856 /* set new last rx descriptor address */
4857 write_reg16(info
, RXDMA
+ EDA
, info
->rx_buf_list_ex
[first
].phys_entry
);
4861 if (first
== info
->rx_buf_count
)
4865 /* set current buffer to next buffer after last buffer of frame */
4866 info
->current_rx_buf
= first
;
4869 /* Return a received frame from the receive DMA buffers.
4870 * Only frames received without errors are returned.
4872 * Return Value: 1 if frame returned, otherwise 0
4874 int rx_get_frame(SLMP_INFO
*info
)
4876 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
4877 unsigned short status
;
4878 unsigned int framesize
= 0;
4880 unsigned long flags
;
4881 struct tty_struct
*tty
= info
->tty
;
4882 unsigned char addr_field
= 0xff;
4884 SCADESC_EX
*desc_ex
;
4887 /* assume no frame returned, set zero length */
4892 * current_rx_buf points to the 1st buffer of the next available
4893 * receive frame. To find the last buffer of the frame look for
4894 * a non-zero status field in the buffer entries. (The status
4895 * field is set by the 16C32 after completing a receive frame.
4897 StartIndex
= EndIndex
= info
->current_rx_buf
;
4900 desc
= &info
->rx_buf_list
[EndIndex
];
4901 desc_ex
= &info
->rx_buf_list_ex
[EndIndex
];
4903 if (desc
->status
== 0xff)
4904 goto Cleanup
; /* current desc still in use, no frames available */
4906 if (framesize
== 0 && info
->params
.addr_filter
!= 0xff)
4907 addr_field
= desc_ex
->virt_addr
[0];
4909 framesize
+= desc
->length
;
4911 /* Status != 0 means last buffer of frame */
4916 if (EndIndex
== info
->rx_buf_count
)
4919 if (EndIndex
== info
->current_rx_buf
) {
4920 /* all buffers have been 'used' but none mark */
4921 /* the end of a frame. Reset buffers and receiver. */
4922 if ( info
->rx_enabled
){
4923 spin_lock_irqsave(&info
->lock
,flags
);
4925 spin_unlock_irqrestore(&info
->lock
,flags
);
4932 /* check status of receive frame */
4934 /* frame status is byte stored after frame data
4936 * 7 EOM (end of msg), 1 = last buffer of frame
4937 * 6 Short Frame, 1 = short frame
4938 * 5 Abort, 1 = frame aborted
4939 * 4 Residue, 1 = last byte is partial
4940 * 3 Overrun, 1 = overrun occurred during frame reception
4941 * 2 CRC, 1 = CRC error detected
4944 status
= desc
->status
;
4946 /* ignore CRC bit if not using CRC (bit is undefined) */
4947 /* Note:CRC is not save to data buffer */
4948 if (info
->params
.crc_type
== HDLC_CRC_NONE
)
4951 if (framesize
== 0 ||
4952 (addr_field
!= 0xff && addr_field
!= info
->params
.addr_filter
)) {
4953 /* discard 0 byte frames, this seems to occur sometime
4954 * when remote is idling flags.
4956 rx_free_frame_buffers(info
, StartIndex
, EndIndex
);
4963 if (status
& (BIT6
+BIT5
+BIT3
+BIT2
)) {
4964 /* received frame has errors,
4965 * update counts and mark frame size as 0
4968 info
->icount
.rxshort
++;
4969 else if (status
& BIT5
)
4970 info
->icount
.rxabort
++;
4971 else if (status
& BIT3
)
4972 info
->icount
.rxover
++;
4974 info
->icount
.rxcrc
++;
4979 struct net_device_stats
*stats
= hdlc_stats(info
->netdev
);
4981 stats
->rx_frame_errors
++;
4986 if ( debug_level
>= DEBUG_LEVEL_BH
)
4987 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4988 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
4990 if ( debug_level
>= DEBUG_LEVEL_DATA
)
4991 trace_block(info
,info
->rx_buf_list_ex
[StartIndex
].virt_addr
,
4992 min_t(int, framesize
,SCABUFSIZE
),0);
4995 if (framesize
> info
->max_frame_size
)
4996 info
->icount
.rxlong
++;
4998 /* copy dma buffer(s) to contiguous intermediate buffer */
4999 int copy_count
= framesize
;
5000 int index
= StartIndex
;
5001 unsigned char *ptmp
= info
->tmp_rx_buf
;
5002 info
->tmp_rx_buf_count
= framesize
;
5004 info
->icount
.rxok
++;
5007 int partial_count
= min(copy_count
,SCABUFSIZE
);
5009 info
->rx_buf_list_ex
[index
].virt_addr
,
5011 ptmp
+= partial_count
;
5012 copy_count
-= partial_count
;
5014 if ( ++index
== info
->rx_buf_count
)
5020 hdlcdev_rx(info
,info
->tmp_rx_buf
,framesize
);
5023 ldisc_receive_buf(tty
,info
->tmp_rx_buf
,
5024 info
->flag_buf
, framesize
);
5027 /* Free the buffers used by this frame. */
5028 rx_free_frame_buffers( info
, StartIndex
, EndIndex
);
5033 if ( info
->rx_enabled
&& info
->rx_overflow
) {
5034 /* Receiver is enabled, but needs to restarted due to
5035 * rx buffer overflow. If buffers are empty, restart receiver.
5037 if (info
->rx_buf_list
[EndIndex
].status
== 0xff) {
5038 spin_lock_irqsave(&info
->lock
,flags
);
5040 spin_unlock_irqrestore(&info
->lock
,flags
);
5047 /* load the transmit DMA buffer with data
5049 void tx_load_dma_buffer(SLMP_INFO
*info
, const char *buf
, unsigned int count
)
5051 unsigned short copy_count
;
5054 SCADESC_EX
*desc_ex
;
5056 if ( debug_level
>= DEBUG_LEVEL_DATA
)
5057 trace_block(info
,buf
, min_t(int, count
,SCABUFSIZE
), 1);
5059 /* Copy source buffer to one or more DMA buffers, starting with
5060 * the first transmit dma buffer.
5064 copy_count
= min_t(unsigned short,count
,SCABUFSIZE
);
5066 desc
= &info
->tx_buf_list
[i
];
5067 desc_ex
= &info
->tx_buf_list_ex
[i
];
5069 load_pci_memory(info
, desc_ex
->virt_addr
,buf
,copy_count
);
5071 desc
->length
= copy_count
;
5075 count
-= copy_count
;
5081 if (i
>= info
->tx_buf_count
)
5085 info
->tx_buf_list
[i
].status
= 0x81; /* set EOM and EOT status */
5086 info
->last_tx_buf
= ++i
;
5089 int register_test(SLMP_INFO
*info
)
5091 static unsigned char testval
[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5092 static unsigned int count
= ARRAY_SIZE(testval
);
5095 unsigned long flags
;
5097 spin_lock_irqsave(&info
->lock
,flags
);
5100 /* assume failure */
5101 info
->init_error
= DiagStatus_AddressFailure
;
5103 /* Write bit patterns to various registers but do it out of */
5104 /* sync, then read back and verify values. */
5106 for (i
= 0 ; i
< count
; i
++) {
5107 write_reg(info
, TMC
, testval
[i
]);
5108 write_reg(info
, IDL
, testval
[(i
+1)%count
]);
5109 write_reg(info
, SA0
, testval
[(i
+2)%count
]);
5110 write_reg(info
, SA1
, testval
[(i
+3)%count
]);
5112 if ( (read_reg(info
, TMC
) != testval
[i
]) ||
5113 (read_reg(info
, IDL
) != testval
[(i
+1)%count
]) ||
5114 (read_reg(info
, SA0
) != testval
[(i
+2)%count
]) ||
5115 (read_reg(info
, SA1
) != testval
[(i
+3)%count
]) )
5123 spin_unlock_irqrestore(&info
->lock
,flags
);
5128 int irq_test(SLMP_INFO
*info
)
5130 unsigned long timeout
;
5131 unsigned long flags
;
5133 unsigned char timer
= (info
->port_num
& 1) ? TIMER2
: TIMER0
;
5135 spin_lock_irqsave(&info
->lock
,flags
);
5138 /* assume failure */
5139 info
->init_error
= DiagStatus_IrqFailure
;
5140 info
->irq_occurred
= FALSE
;
5142 /* setup timer0 on SCA0 to interrupt */
5144 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5145 write_reg(info
, IER2
, (unsigned char)((info
->port_num
& 1) ? BIT6
: BIT4
));
5147 write_reg(info
, (unsigned char)(timer
+ TEPR
), 0); /* timer expand prescale */
5148 write_reg16(info
, (unsigned char)(timer
+ TCONR
), 1); /* timer constant */
5151 /* TMCS, Timer Control/Status Register
5153 * 07 CMF, Compare match flag (read only) 1=match
5154 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5155 * 05 Reserved, must be 0
5156 * 04 TME, Timer Enable
5157 * 03..00 Reserved, must be 0
5161 write_reg(info
, (unsigned char)(timer
+ TMCS
), 0x50);
5163 spin_unlock_irqrestore(&info
->lock
,flags
);
5166 while( timeout
-- && !info
->irq_occurred
) {
5167 msleep_interruptible(10);
5170 spin_lock_irqsave(&info
->lock
,flags
);
5172 spin_unlock_irqrestore(&info
->lock
,flags
);
5174 return info
->irq_occurred
;
5177 /* initialize individual SCA device (2 ports)
5179 static int sca_init(SLMP_INFO
*info
)
5181 /* set wait controller to single mem partition (low), no wait states */
5182 write_reg(info
, PABR0
, 0); /* wait controller addr boundary 0 */
5183 write_reg(info
, PABR1
, 0); /* wait controller addr boundary 1 */
5184 write_reg(info
, WCRL
, 0); /* wait controller low range */
5185 write_reg(info
, WCRM
, 0); /* wait controller mid range */
5186 write_reg(info
, WCRH
, 0); /* wait controller high range */
5188 /* DPCR, DMA Priority Control
5190 * 07..05 Not used, must be 0
5191 * 04 BRC, bus release condition: 0=all transfers complete
5192 * 03 CCC, channel change condition: 0=every cycle
5193 * 02..00 PR<2..0>, priority 100=round robin
5197 write_reg(info
, DPCR
, dma_priority
);
5199 /* DMA Master Enable, BIT7: 1=enable all channels */
5200 write_reg(info
, DMER
, 0x80);
5202 /* enable all interrupt classes */
5203 write_reg(info
, IER0
, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5204 write_reg(info
, IER1
, 0xff); /* DMIB,DMIA (channels 0-3) */
5205 write_reg(info
, IER2
, 0xf0); /* TIRQ (timers 0-3) */
5207 /* ITCR, interrupt control register
5208 * 07 IPC, interrupt priority, 0=MSCI->DMA
5209 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5210 * 04 VOS, Vector Output, 0=unmodified vector
5211 * 03..00 Reserved, must be 0
5213 write_reg(info
, ITCR
, 0);
5218 /* initialize adapter hardware
5220 int init_adapter(SLMP_INFO
*info
)
5224 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5225 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5228 info
->misc_ctrl_value
|= BIT30
;
5229 *MiscCtrl
= info
->misc_ctrl_value
;
5232 * Force at least 170ns delay before clearing
5233 * reset bit. Each read from LCR takes at least
5234 * 30ns so 10 times for 300ns to be safe.
5237 readval
= *MiscCtrl
;
5239 info
->misc_ctrl_value
&= ~BIT30
;
5240 *MiscCtrl
= info
->misc_ctrl_value
;
5242 /* init control reg (all DTRs off, all clksel=input) */
5243 info
->ctrlreg_value
= 0xaa;
5244 write_control_reg(info
);
5247 volatile u32
*LCR1BRDR
= (u32
*)(info
->lcr_base
+ 0x2c);
5248 lcr1_brdr_value
&= ~(BIT5
+ BIT4
+ BIT3
);
5250 switch(read_ahead_count
)
5253 lcr1_brdr_value
|= BIT5
+ BIT4
+ BIT3
;
5256 lcr1_brdr_value
|= BIT5
+ BIT4
;
5259 lcr1_brdr_value
|= BIT5
+ BIT3
;
5262 lcr1_brdr_value
|= BIT5
;
5266 *LCR1BRDR
= lcr1_brdr_value
;
5267 *MiscCtrl
= misc_ctrl_value
;
5270 sca_init(info
->port_array
[0]);
5271 sca_init(info
->port_array
[2]);
5276 /* Loopback an HDLC frame to test the hardware
5277 * interrupt and DMA functions.
5279 int loopback_test(SLMP_INFO
*info
)
5281 #define TESTFRAMESIZE 20
5283 unsigned long timeout
;
5284 u16 count
= TESTFRAMESIZE
;
5285 unsigned char buf
[TESTFRAMESIZE
];
5287 unsigned long flags
;
5289 struct tty_struct
*oldtty
= info
->tty
;
5290 u32 speed
= info
->params
.clock_speed
;
5292 info
->params
.clock_speed
= 3686400;
5295 /* assume failure */
5296 info
->init_error
= DiagStatus_DmaFailure
;
5298 /* build and send transmit frame */
5299 for (count
= 0; count
< TESTFRAMESIZE
;++count
)
5300 buf
[count
] = (unsigned char)count
;
5302 memset(info
->tmp_rx_buf
,0,TESTFRAMESIZE
);
5304 /* program hardware for HDLC and enabled receiver */
5305 spin_lock_irqsave(&info
->lock
,flags
);
5307 enable_loopback(info
,1);
5309 info
->tx_count
= count
;
5310 tx_load_dma_buffer(info
,buf
,count
);
5312 spin_unlock_irqrestore(&info
->lock
,flags
);
5314 /* wait for receive complete */
5315 /* Set a timeout for waiting for interrupt. */
5316 for ( timeout
= 100; timeout
; --timeout
) {
5317 msleep_interruptible(10);
5319 if (rx_get_frame(info
)) {
5325 /* verify received frame length and contents */
5327 ( info
->tmp_rx_buf_count
!= count
||
5328 memcmp(buf
, info
->tmp_rx_buf
,count
))) {
5332 spin_lock_irqsave(&info
->lock
,flags
);
5333 reset_adapter(info
);
5334 spin_unlock_irqrestore(&info
->lock
,flags
);
5336 info
->params
.clock_speed
= speed
;
5342 /* Perform diagnostics on hardware
5344 int adapter_test( SLMP_INFO
*info
)
5346 unsigned long flags
;
5347 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5348 printk( "%s(%d):Testing device %s\n",
5349 __FILE__
,__LINE__
,info
->device_name
);
5351 spin_lock_irqsave(&info
->lock
,flags
);
5353 spin_unlock_irqrestore(&info
->lock
,flags
);
5355 info
->port_array
[0]->port_count
= 0;
5357 if ( register_test(info
->port_array
[0]) &&
5358 register_test(info
->port_array
[1])) {
5360 info
->port_array
[0]->port_count
= 2;
5362 if ( register_test(info
->port_array
[2]) &&
5363 register_test(info
->port_array
[3]) )
5364 info
->port_array
[0]->port_count
+= 2;
5367 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5368 __FILE__
,__LINE__
,info
->device_name
, (unsigned long)(info
->phys_sca_base
));
5372 if ( !irq_test(info
->port_array
[0]) ||
5373 !irq_test(info
->port_array
[1]) ||
5374 (info
->port_count
== 4 && !irq_test(info
->port_array
[2])) ||
5375 (info
->port_count
== 4 && !irq_test(info
->port_array
[3]))) {
5376 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5377 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
5381 if (!loopback_test(info
->port_array
[0]) ||
5382 !loopback_test(info
->port_array
[1]) ||
5383 (info
->port_count
== 4 && !loopback_test(info
->port_array
[2])) ||
5384 (info
->port_count
== 4 && !loopback_test(info
->port_array
[3]))) {
5385 printk( "%s(%d):DMA test failure for device %s\n",
5386 __FILE__
,__LINE__
,info
->device_name
);
5390 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5391 printk( "%s(%d):device %s passed diagnostics\n",
5392 __FILE__
,__LINE__
,info
->device_name
);
5394 info
->port_array
[0]->init_error
= 0;
5395 info
->port_array
[1]->init_error
= 0;
5396 if ( info
->port_count
> 2 ) {
5397 info
->port_array
[2]->init_error
= 0;
5398 info
->port_array
[3]->init_error
= 0;
5404 /* Test the shared memory on a PCI adapter.
5406 int memory_test(SLMP_INFO
*info
)
5408 static unsigned long testval
[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5409 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5410 unsigned long count
= ARRAY_SIZE(testval
);
5412 unsigned long limit
= SCA_MEM_SIZE
/sizeof(unsigned long);
5413 unsigned long * addr
= (unsigned long *)info
->memory_base
;
5415 /* Test data lines with test pattern at one location. */
5417 for ( i
= 0 ; i
< count
; i
++ ) {
5419 if ( *addr
!= testval
[i
] )
5423 /* Test address lines with incrementing pattern over */
5424 /* entire address range. */
5426 for ( i
= 0 ; i
< limit
; i
++ ) {
5431 addr
= (unsigned long *)info
->memory_base
;
5433 for ( i
= 0 ; i
< limit
; i
++ ) {
5434 if ( *addr
!= i
* 4 )
5439 memset( info
->memory_base
, 0, SCA_MEM_SIZE
);
5443 /* Load data into PCI adapter shared memory.
5445 * The PCI9050 releases control of the local bus
5446 * after completing the current read or write operation.
5448 * While the PCI9050 write FIFO not empty, the
5449 * PCI9050 treats all of the writes as a single transaction
5450 * and does not release the bus. This causes DMA latency problems
5451 * at high speeds when copying large data blocks to the shared memory.
5453 * This function breaks a write into multiple transations by
5454 * interleaving a read which flushes the write FIFO and 'completes'
5455 * the write transation. This allows any pending DMA request to gain control
5456 * of the local bus in a timely fasion.
5458 void load_pci_memory(SLMP_INFO
*info
, char* dest
, const char* src
, unsigned short count
)
5460 /* A load interval of 16 allows for 4 32-bit writes at */
5461 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5463 unsigned short interval
= count
/ sca_pci_load_interval
;
5466 for ( i
= 0 ; i
< interval
; i
++ )
5468 memcpy(dest
, src
, sca_pci_load_interval
);
5469 read_status_reg(info
);
5470 dest
+= sca_pci_load_interval
;
5471 src
+= sca_pci_load_interval
;
5474 memcpy(dest
, src
, count
% sca_pci_load_interval
);
5477 void trace_block(SLMP_INFO
*info
,const char* data
, int count
, int xmit
)
5482 printk("%s tx data:\n",info
->device_name
);
5484 printk("%s rx data:\n",info
->device_name
);
5492 for(i
=0;i
<linecount
;i
++)
5493 printk("%02X ",(unsigned char)data
[i
]);
5496 for(i
=0;i
<linecount
;i
++) {
5497 if (data
[i
]>=040 && data
[i
]<=0176)
5498 printk("%c",data
[i
]);
5507 } /* end of trace_block() */
5509 /* called when HDLC frame times out
5510 * update stats and do tx completion processing
5512 void tx_timeout(unsigned long context
)
5514 SLMP_INFO
*info
= (SLMP_INFO
*)context
;
5515 unsigned long flags
;
5517 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5518 printk( "%s(%d):%s tx_timeout()\n",
5519 __FILE__
,__LINE__
,info
->device_name
);
5520 if(info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
5521 info
->icount
.txtimeout
++;
5523 spin_lock_irqsave(&info
->lock
,flags
);
5524 info
->tx_active
= 0;
5525 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
5527 spin_unlock_irqrestore(&info
->lock
,flags
);
5531 hdlcdev_tx_done(info
);
5537 /* called to periodically check the DSR/RI modem signal input status
5539 void status_timeout(unsigned long context
)
5542 SLMP_INFO
*info
= (SLMP_INFO
*)context
;
5543 unsigned long flags
;
5544 unsigned char delta
;
5547 spin_lock_irqsave(&info
->lock
,flags
);
5549 spin_unlock_irqrestore(&info
->lock
,flags
);
5551 /* check for DSR/RI state change */
5553 delta
= info
->old_signals
^ info
->serial_signals
;
5554 info
->old_signals
= info
->serial_signals
;
5556 if (delta
& SerialSignal_DSR
)
5557 status
|= MISCSTATUS_DSR_LATCHED
|(info
->serial_signals
&SerialSignal_DSR
);
5559 if (delta
& SerialSignal_RI
)
5560 status
|= MISCSTATUS_RI_LATCHED
|(info
->serial_signals
&SerialSignal_RI
);
5562 if (delta
& SerialSignal_DCD
)
5563 status
|= MISCSTATUS_DCD_LATCHED
|(info
->serial_signals
&SerialSignal_DCD
);
5565 if (delta
& SerialSignal_CTS
)
5566 status
|= MISCSTATUS_CTS_LATCHED
|(info
->serial_signals
&SerialSignal_CTS
);
5569 isr_io_pin(info
,status
);
5571 info
->status_timer
.data
= (unsigned long)info
;
5572 info
->status_timer
.function
= status_timeout
;
5573 info
->status_timer
.expires
= jiffies
+ msecs_to_jiffies(10);
5574 add_timer(&info
->status_timer
);
5578 /* Register Access Routines -
5579 * All registers are memory mapped
5581 #define CALC_REGADDR() \
5582 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5583 if (info->port_num > 1) \
5584 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5585 if ( info->port_num & 1) { \
5587 RegAddr += 0x40; /* DMA access */ \
5588 else if (Addr > 0x1f && Addr < 0x60) \
5589 RegAddr += 0x20; /* MSCI access */ \
5593 unsigned char read_reg(SLMP_INFO
* info
, unsigned char Addr
)
5598 void write_reg(SLMP_INFO
* info
, unsigned char Addr
, unsigned char Value
)
5604 u16
read_reg16(SLMP_INFO
* info
, unsigned char Addr
)
5607 return *((u16
*)RegAddr
);
5610 void write_reg16(SLMP_INFO
* info
, unsigned char Addr
, u16 Value
)
5613 *((u16
*)RegAddr
) = Value
;
5616 unsigned char read_status_reg(SLMP_INFO
* info
)
5618 unsigned char *RegAddr
= (unsigned char *)info
->statctrl_base
;
5622 void write_control_reg(SLMP_INFO
* info
)
5624 unsigned char *RegAddr
= (unsigned char *)info
->statctrl_base
;
5625 *RegAddr
= info
->port_array
[0]->ctrlreg_value
;
5629 static int __devinit
synclinkmp_init_one (struct pci_dev
*dev
,
5630 const struct pci_device_id
*ent
)
5632 if (pci_enable_device(dev
)) {
5633 printk("error enabling pci device %p\n", dev
);
5636 device_init( ++synclinkmp_adapter_count
, dev
);
5640 static void __devexit
synclinkmp_remove_one (struct pci_dev
*dev
)