]>
git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/clk/hisilicon/clk.c
2 * Hisilicon clock driver
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
26 #include <linux/kernel.h>
27 #include <linux/clk-provider.h>
28 #include <linux/clkdev.h>
29 #include <linux/delay.h>
32 #include <linux/of_address.h>
33 #include <linux/of_device.h>
34 #include <linux/slab.h>
35 #include <linux/clk.h>
39 static DEFINE_SPINLOCK(hisi_clk_lock
);
41 struct hisi_clock_data __init
*hisi_clk_init(struct device_node
*np
,
44 struct hisi_clock_data
*clk_data
;
45 struct clk
**clk_table
;
49 base
= of_iomap(np
, 0);
51 pr_err("failed to map Hisilicon clock registers\n");
55 pr_err("failed to find Hisilicon clock node in DTS\n");
59 clk_data
= kzalloc(sizeof(*clk_data
), GFP_KERNEL
);
61 pr_err("%s: could not allocate clock data\n", __func__
);
64 clk_data
->base
= base
;
66 clk_table
= kzalloc(sizeof(struct clk
*) * nr_clks
, GFP_KERNEL
);
68 pr_err("%s: could not allocate clock lookup table\n", __func__
);
71 clk_data
->clk_data
.clks
= clk_table
;
72 clk_data
->clk_data
.clk_num
= nr_clks
;
73 of_clk_add_provider(np
, of_clk_src_onecell_get
, &clk_data
->clk_data
);
81 void __init
hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock
*clks
,
82 int nums
, struct hisi_clock_data
*data
)
87 for (i
= 0; i
< nums
; i
++) {
88 clk
= clk_register_fixed_rate(NULL
, clks
[i
].name
,
93 pr_err("%s: failed to register clock %s\n",
94 __func__
, clks
[i
].name
);
97 data
->clk_data
.clks
[clks
[i
].id
] = clk
;
101 void __init
hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock
*clks
,
103 struct hisi_clock_data
*data
)
108 for (i
= 0; i
< nums
; i
++) {
109 clk
= clk_register_fixed_factor(NULL
, clks
[i
].name
,
111 clks
[i
].flags
, clks
[i
].mult
,
114 pr_err("%s: failed to register clock %s\n",
115 __func__
, clks
[i
].name
);
118 data
->clk_data
.clks
[clks
[i
].id
] = clk
;
122 void __init
hisi_clk_register_mux(struct hisi_mux_clock
*clks
,
123 int nums
, struct hisi_clock_data
*data
)
126 void __iomem
*base
= data
->base
;
129 for (i
= 0; i
< nums
; i
++) {
130 u32 mask
= BIT(clks
[i
].width
) - 1;
132 clk
= clk_register_mux_table(NULL
, clks
[i
].name
,
133 clks
[i
].parent_names
,
134 clks
[i
].num_parents
, clks
[i
].flags
,
135 base
+ clks
[i
].offset
, clks
[i
].shift
,
136 mask
, clks
[i
].mux_flags
,
137 clks
[i
].table
, &hisi_clk_lock
);
139 pr_err("%s: failed to register clock %s\n",
140 __func__
, clks
[i
].name
);
145 clk_register_clkdev(clk
, clks
[i
].alias
, NULL
);
147 data
->clk_data
.clks
[clks
[i
].id
] = clk
;
151 void __init
hisi_clk_register_divider(struct hisi_divider_clock
*clks
,
152 int nums
, struct hisi_clock_data
*data
)
155 void __iomem
*base
= data
->base
;
158 for (i
= 0; i
< nums
; i
++) {
159 clk
= clk_register_divider_table(NULL
, clks
[i
].name
,
162 base
+ clks
[i
].offset
,
163 clks
[i
].shift
, clks
[i
].width
,
168 pr_err("%s: failed to register clock %s\n",
169 __func__
, clks
[i
].name
);
174 clk_register_clkdev(clk
, clks
[i
].alias
, NULL
);
176 data
->clk_data
.clks
[clks
[i
].id
] = clk
;
180 void __init
hisi_clk_register_gate(struct hisi_gate_clock
*clks
,
181 int nums
, struct hisi_clock_data
*data
)
184 void __iomem
*base
= data
->base
;
187 for (i
= 0; i
< nums
; i
++) {
188 clk
= clk_register_gate(NULL
, clks
[i
].name
,
191 base
+ clks
[i
].offset
,
196 pr_err("%s: failed to register clock %s\n",
197 __func__
, clks
[i
].name
);
202 clk_register_clkdev(clk
, clks
[i
].alias
, NULL
);
204 data
->clk_data
.clks
[clks
[i
].id
] = clk
;
208 void __init
hisi_clk_register_gate_sep(struct hisi_gate_clock
*clks
,
209 int nums
, struct hisi_clock_data
*data
)
212 void __iomem
*base
= data
->base
;
215 for (i
= 0; i
< nums
; i
++) {
216 clk
= hisi_register_clkgate_sep(NULL
, clks
[i
].name
,
219 base
+ clks
[i
].offset
,
224 pr_err("%s: failed to register clock %s\n",
225 __func__
, clks
[i
].name
);
230 clk_register_clkdev(clk
, clks
[i
].alias
, NULL
);
232 data
->clk_data
.clks
[clks
[i
].id
] = clk
;
236 void __init
hi6220_clk_register_divider(struct hi6220_divider_clock
*clks
,
237 int nums
, struct hisi_clock_data
*data
)
240 void __iomem
*base
= data
->base
;
243 for (i
= 0; i
< nums
; i
++) {
244 clk
= hi6220_register_clkdiv(NULL
, clks
[i
].name
,
247 base
+ clks
[i
].offset
,
253 pr_err("%s: failed to register clock %s\n",
254 __func__
, clks
[i
].name
);
259 clk_register_clkdev(clk
, clks
[i
].alias
, NULL
);
261 data
->clk_data
.clks
[clks
[i
].id
] = clk
;