2 * PLL clock driver for Keystone devices
4 * Copyright (C) 2013 Texas Instruments Inc.
5 * Murali Karicheri <m-karicheri2@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/err.h>
17 #include <linux/slab.h>
18 #include <linux/of_address.h>
20 #include <linux/module.h>
22 #define PLLM_LOW_MASK 0x3f
23 #define PLLM_HIGH_MASK 0x7ffc0
24 #define MAIN_PLLM_HIGH_MASK 0x7f000
25 #define PLLM_HIGH_SHIFT 6
26 #define PLLD_MASK 0x3f
29 * struct clk_pll_data - pll data structure
30 * @has_pllctrl: If set to non zero, lower 6 bits of multiplier is in pllm
31 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
32 * @phy_pllm: Physical address of PLLM in pll controller. Used when
33 * has_pllctrl is non zero.
34 * @phy_pll_ctl0: Physical address of PLL ctrl0. This could be that of
35 * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
36 * or PA PLL available on keystone2. These PLLs are controlled by
37 * this register. Main PLL is controlled by a PLL controller.
38 * @pllm: PLL register map address
39 * @pll_ctl0: PLL controller map address
40 * @pllm_lower_mask: multiplier lower mask
41 * @pllm_upper_mask: multiplier upper mask
42 * @pllm_upper_shift: multiplier upper shift
43 * @plld_mask: divider mask
44 * @postdiv: Post divider
51 void __iomem
*pll_ctl0
;
60 * struct clk_pll - Main pll clock
61 * @hw: clk_hw for the pll
62 * @pll_data: PLL driver specific data
66 struct clk_pll_data
*pll_data
;
69 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
71 static unsigned long clk_pllclk_recalc(struct clk_hw
*hw
,
72 unsigned long parent_rate
)
74 struct clk_pll
*pll
= to_clk_pll(hw
);
75 struct clk_pll_data
*pll_data
= pll
->pll_data
;
76 unsigned long rate
= parent_rate
;
77 u32 mult
= 0, prediv
, postdiv
, val
;
80 * get bits 0-5 of multiplier from pllctrl PLLM register
81 * if has_pllctrl is non zero
83 if (pll_data
->has_pllctrl
) {
84 val
= readl(pll_data
->pllm
);
85 mult
= (val
& pll_data
->pllm_lower_mask
);
88 /* bit6-12 of PLLM is in Main PLL control register */
89 val
= readl(pll_data
->pll_ctl0
);
90 mult
|= ((val
& pll_data
->pllm_upper_mask
)
91 >> pll_data
->pllm_upper_shift
);
92 prediv
= (val
& pll_data
->plld_mask
);
93 postdiv
= pll_data
->postdiv
;
96 rate
= (rate
* (mult
+ 1));
102 static const struct clk_ops clk_pll_ops
= {
103 .recalc_rate
= clk_pllclk_recalc
,
106 static struct clk
*clk_register_pll(struct device
*dev
,
108 const char *parent_name
,
109 struct clk_pll_data
*pll_data
)
111 struct clk_init_data init
;
115 pll
= kzalloc(sizeof(*pll
), GFP_KERNEL
);
117 return ERR_PTR(-ENOMEM
);
120 init
.ops
= &clk_pll_ops
;
122 init
.parent_names
= (parent_name
? &parent_name
: NULL
);
123 init
.num_parents
= (parent_name
? 1 : 0);
125 pll
->pll_data
= pll_data
;
126 pll
->hw
.init
= &init
;
128 clk
= clk_register(NULL
, &pll
->hw
);
139 * _of_clk_init - PLL initialisation via DT
140 * @node: device tree node for this clock
141 * @pllctrl: If true, lower 6 bits of multiplier is in pllm register of
142 * pll controller, else it is in the control regsiter0(bit 11-6)
144 static void __init
_of_pll_clk_init(struct device_node
*node
, bool pllctrl
)
146 struct clk_pll_data
*pll_data
;
147 const char *parent_name
;
151 pll_data
= kzalloc(sizeof(*pll_data
), GFP_KERNEL
);
153 pr_err("%s: Out of memory\n", __func__
);
157 parent_name
= of_clk_get_parent_name(node
, 0);
158 if (of_property_read_u32(node
, "fixed-postdiv", &pll_data
->postdiv
))
161 i
= of_property_match_string(node
, "reg-names", "control");
162 pll_data
->pll_ctl0
= of_iomap(node
, i
);
163 if (!pll_data
->pll_ctl0
) {
164 pr_err("%s: ioremap failed\n", __func__
);
168 pll_data
->pllm_lower_mask
= PLLM_LOW_MASK
;
169 pll_data
->pllm_upper_shift
= PLLM_HIGH_SHIFT
;
170 pll_data
->plld_mask
= PLLD_MASK
;
171 pll_data
->has_pllctrl
= pllctrl
;
172 if (!pll_data
->has_pllctrl
) {
173 pll_data
->pllm_upper_mask
= PLLM_HIGH_MASK
;
175 pll_data
->pllm_upper_mask
= MAIN_PLLM_HIGH_MASK
;
176 i
= of_property_match_string(node
, "reg-names", "multiplier");
177 pll_data
->pllm
= of_iomap(node
, i
);
178 if (!pll_data
->pllm
) {
179 iounmap(pll_data
->pll_ctl0
);
184 clk
= clk_register_pll(NULL
, node
->name
, parent_name
, pll_data
);
186 of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
191 pr_err("%s: error initializing pll %s\n", __func__
, node
->name
);
196 * of_keystone_pll_clk_init - PLL initialisation DT wrapper
197 * @node: device tree node for this clock
199 static void __init
of_keystone_pll_clk_init(struct device_node
*node
)
201 _of_pll_clk_init(node
, false);
203 CLK_OF_DECLARE(keystone_pll_clock
, "ti,keystone,pll-clock",
204 of_keystone_pll_clk_init
);
207 * of_keystone_pll_main_clk_init - Main PLL initialisation DT wrapper
208 * @node: device tree node for this clock
210 static void __init
of_keystone_main_pll_clk_init(struct device_node
*node
)
212 _of_pll_clk_init(node
, true);
214 CLK_OF_DECLARE(keystone_main_pll_clock
, "ti,keystone,main-pll-clock",
215 of_keystone_main_pll_clk_init
);
218 * of_pll_div_clk_init - PLL divider setup function
219 * @node: device tree node for this clock
221 static void __init
of_pll_div_clk_init(struct device_node
*node
)
223 const char *parent_name
;
227 const char *clk_name
= node
->name
;
229 of_property_read_string(node
, "clock-output-names", &clk_name
);
230 reg
= of_iomap(node
, 0);
232 pr_err("%s: ioremap failed\n", __func__
);
236 parent_name
= of_clk_get_parent_name(node
, 0);
238 pr_err("%s: missing parent clock\n", __func__
);
242 if (of_property_read_u32(node
, "bit-shift", &shift
)) {
243 pr_err("%s: missing 'shift' property\n", __func__
);
247 if (of_property_read_u32(node
, "bit-mask", &mask
)) {
248 pr_err("%s: missing 'bit-mask' property\n", __func__
);
252 clk
= clk_register_divider(NULL
, clk_name
, parent_name
, 0, reg
, shift
,
255 of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
257 pr_err("%s: error registering divider %s\n", __func__
, clk_name
);
259 CLK_OF_DECLARE(pll_divider_clock
, "ti,keystone,pll-divider-clock", of_pll_div_clk_init
);
262 * of_pll_mux_clk_init - PLL mux setup function
263 * @node: device tree node for this clock
265 static void __init
of_pll_mux_clk_init(struct device_node
*node
)
270 const char *parents
[2];
271 const char *clk_name
= node
->name
;
273 of_property_read_string(node
, "clock-output-names", &clk_name
);
274 reg
= of_iomap(node
, 0);
276 pr_err("%s: ioremap failed\n", __func__
);
280 parents
[0] = of_clk_get_parent_name(node
, 0);
281 parents
[1] = of_clk_get_parent_name(node
, 1);
282 if (!parents
[0] || !parents
[1]) {
283 pr_err("%s: missing parent clocks\n", __func__
);
287 if (of_property_read_u32(node
, "bit-shift", &shift
)) {
288 pr_err("%s: missing 'shift' property\n", __func__
);
292 if (of_property_read_u32(node
, "bit-mask", &mask
)) {
293 pr_err("%s: missing 'bit-mask' property\n", __func__
);
297 clk
= clk_register_mux(NULL
, clk_name
, (const char **)&parents
,
298 ARRAY_SIZE(parents
) , 0, reg
, shift
, mask
,
301 of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
303 pr_err("%s: error registering mux %s\n", __func__
, clk_name
);
305 CLK_OF_DECLARE(pll_mux_clock
, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init
);