drivers/clk/mvebu/cp110-system-controller.c

   1 /*
   2  * Marvell Armada CP110 System Controller
   3  *
   4  * Copyright (C) 2016 Marvell
   5  *
   6  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 /*
  14  * CP110 has 5 core clocks:
  15  *
  16  *  - APLL              (1 Ghz)
  17  *    - PPv2 core       (1/3 APLL)
  18  *    - EIP             (1/2 APLL)
  19  *      - Core          (1/2 EIP)
  20  *
  21  *  - NAND clock, which is either:
  22  *    - Equal to the core clock
  23  *    - 2/5 APLL
  24  *
  25  * CP110 has 32 gatable clocks, for the various peripherals in the
  26  * IP. They have fairly complicated parent/child relationships.
  27  */
  28
  29 #define pr_fmt(fmt) "cp110-system-controller: " fmt
  30
  31 #include <linux/clk-provider.h>
  32 #include <linux/mfd/syscon.h>
  33 #include <linux/init.h>
  34 #include <linux/of.h>
  35 #include <linux/of_address.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/regmap.h>
  38 #include <linux/slab.h>
  39
  40 #define CP110_PM_CLOCK_GATING_REG       0x220
  41 #define CP110_NAND_FLASH_CLK_CTRL_REG   0x700
  42 #define    NF_CLOCK_SEL_400_MASK        BIT(0)
  43
  44 enum {
  45         CP110_CLK_TYPE_CORE,
  46         CP110_CLK_TYPE_GATABLE,
  47 };
  48
  49 #define CP110_MAX_CORE_CLOCKS           5
  50 #define CP110_MAX_GATABLE_CLOCKS        32
  51
  52 #define CP110_CLK_NUM \
  53         (CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS)
  54
  55 #define CP110_CORE_APLL                 0
  56 #define CP110_CORE_PPV2                 1
  57 #define CP110_CORE_EIP                  2
  58 #define CP110_CORE_CORE                 3
  59 #define CP110_CORE_NAND                 4
  60
  61 /* A number of gatable clocks need special handling */
  62 #define CP110_GATE_AUDIO                0
  63 #define CP110_GATE_COMM_UNIT            1
  64 #define CP110_GATE_NAND                 2
  65 #define CP110_GATE_PPV2                 3
  66 #define CP110_GATE_SDIO                 4
  67 #define CP110_GATE_MG                   5
  68 #define CP110_GATE_MG_CORE              6
  69 #define CP110_GATE_XOR1                 7
  70 #define CP110_GATE_XOR0                 8
  71 #define CP110_GATE_GOP_DP               9
  72 #define CP110_GATE_PCIE_X1_0            11
  73 #define CP110_GATE_PCIE_X1_1            12
  74 #define CP110_GATE_PCIE_X4              13
  75 #define CP110_GATE_PCIE_XOR             14
  76 #define CP110_GATE_SATA                 15
  77 #define CP110_GATE_SATA_USB             16
  78 #define CP110_GATE_MAIN                 17
  79 #define CP110_GATE_SDMMC_GOP            18
  80 #define CP110_GATE_SLOW_IO              21
  81 #define CP110_GATE_USB3H0               22
  82 #define CP110_GATE_USB3H1               23
  83 #define CP110_GATE_USB3DEV              24
  84 #define CP110_GATE_EIP150               25
  85 #define CP110_GATE_EIP197               26
  86
  87 struct cp110_gate_clk {
  88         struct clk_hw hw;
  89         struct regmap *regmap;
  90         u8 bit_idx;
  91 };
  92
  93 #define to_cp110_gate_clk(hw) container_of(hw, struct cp110_gate_clk, hw)
  94
  95 static int cp110_gate_enable(struct clk_hw *hw)
  96 {
  97         struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
  98
  99         regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
 100                            BIT(gate->bit_idx), BIT(gate->bit_idx));
 101
 102         return 0;
 103 }
 104
 105 static void cp110_gate_disable(struct clk_hw *hw)
 106 {
 107         struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
 108
 109         regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
 110                            BIT(gate->bit_idx), 0);
 111 }
 112
 113 static int cp110_gate_is_enabled(struct clk_hw *hw)
 114 {
 115         struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
 116         u32 val;
 117
 118         regmap_read(gate->regmap, CP110_PM_CLOCK_GATING_REG, &val);
 119
 120         return val & BIT(gate->bit_idx);
 121 }
 122
 123 static const struct clk_ops cp110_gate_ops = {
 124         .enable = cp110_gate_enable,
 125         .disable = cp110_gate_disable,
 126         .is_enabled = cp110_gate_is_enabled,
 127 };
 128
 129 static struct clk_hw *cp110_register_gate(const char *name,
 130                                           const char *parent_name,
 131                                           struct regmap *regmap, u8 bit_idx)
 132 {
 133         struct cp110_gate_clk *gate;
 134         struct clk_hw *hw;
 135         struct clk_init_data init;
 136         int ret;
 137
 138         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 139         if (!gate)
 140                 return ERR_PTR(-ENOMEM);
 141
 142         memset(&init, 0, sizeof(init));
 143
 144         init.name = name;
 145         init.ops = &cp110_gate_ops;
 146         init.parent_names = &parent_name;
 147         init.num_parents = 1;
 148
 149         gate->regmap = regmap;
 150         gate->bit_idx = bit_idx;
 151         gate->hw.init = &init;
 152
 153         hw = &gate->hw;
 154         ret = clk_hw_register(NULL, hw);
 155         if (ret) {
 156                 kfree(gate);
 157                 hw = ERR_PTR(ret);
 158         }
 159
 160         return hw;
 161 }
 162
 163 static void cp110_unregister_gate(struct clk_hw *hw)
 164 {
 165         clk_hw_unregister(hw);
 166         kfree(to_cp110_gate_clk(hw));
 167 }
 168
 169 static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec,
 170                                        void *data)
 171 {
 172         struct clk_hw_onecell_data *clk_data = data;
 173         unsigned int type = clkspec->args[0];
 174         unsigned int idx = clkspec->args[1];
 175
 176         if (type == CP110_CLK_TYPE_CORE) {
 177                 if (idx > CP110_MAX_CORE_CLOCKS)
 178                         return ERR_PTR(-EINVAL);
 179                 return clk_data->hws[idx];
 180         } else if (type == CP110_CLK_TYPE_GATABLE) {
 181                 if (idx > CP110_MAX_GATABLE_CLOCKS)
 182                         return ERR_PTR(-EINVAL);
 183                 return clk_data->hws[CP110_MAX_CORE_CLOCKS + idx];
 184         }
 185
 186         return ERR_PTR(-EINVAL);
 187 }
 188
 189 static int cp110_syscon_clk_probe(struct platform_device *pdev)
 190 {
 191         struct regmap *regmap;
 192         struct device_node *np = pdev->dev.of_node;
 193         const char *ppv2_name, *apll_name, *core_name, *eip_name, *nand_name;
 194         struct clk_hw_onecell_data *cp110_clk_data;
 195         struct clk_hw *hw, **cp110_clks;
 196         u32 nand_clk_ctrl;
 197         int i, ret;
 198
 199         regmap = syscon_node_to_regmap(np);
 200         if (IS_ERR(regmap))
 201                 return PTR_ERR(regmap);
 202
 203         ret = regmap_read(regmap, CP110_NAND_FLASH_CLK_CTRL_REG,
 204                           &nand_clk_ctrl);
 205         if (ret)
 206                 return ret;
 207
 208         cp110_clk_data = devm_kzalloc(&pdev->dev, sizeof(*cp110_clk_data) +
 209                                       sizeof(struct clk_hw *) * CP110_CLK_NUM,
 210                                       GFP_KERNEL);
 211         if (!cp110_clk_data)
 212                 return -ENOMEM;
 213
 214         cp110_clks = cp110_clk_data->hws;
 215         cp110_clk_data->num = CP110_CLK_NUM;
 216
 217         /* Register the APLL which is the root of the hw tree */
 218         of_property_read_string_index(np, "core-clock-output-names",
 219                                       CP110_CORE_APLL, &apll_name);
 220         hw = clk_hw_register_fixed_rate(NULL, apll_name, NULL, 0,
 221                                         1000 * 1000 * 1000);
 222         if (IS_ERR(hw)) {
 223                 ret = PTR_ERR(hw);
 224                 goto fail0;
 225         }
 226
 227         cp110_clks[CP110_CORE_APLL] = hw;
 228
 229         /* PPv2 is APLL/3 */
 230         of_property_read_string_index(np, "core-clock-output-names",
 231                                       CP110_CORE_PPV2, &ppv2_name);
 232         hw = clk_hw_register_fixed_factor(NULL, ppv2_name, apll_name, 0, 1, 3);
 233         if (IS_ERR(hw)) {
 234                 ret = PTR_ERR(hw);
 235                 goto fail1;
 236         }
 237
 238         cp110_clks[CP110_CORE_PPV2] = hw;
 239
 240         /* EIP clock is APLL/2 */
 241         of_property_read_string_index(np, "core-clock-output-names",
 242                                       CP110_CORE_EIP, &eip_name);
 243         hw = clk_hw_register_fixed_factor(NULL, eip_name, apll_name, 0, 1, 2);
 244         if (IS_ERR(hw)) {
 245                 ret = PTR_ERR(hw);
 246                 goto fail2;
 247         }
 248
 249         cp110_clks[CP110_CORE_EIP] = hw;
 250
 251         /* Core clock is EIP/2 */
 252         of_property_read_string_index(np, "core-clock-output-names",
 253                                       CP110_CORE_CORE, &core_name);
 254         hw = clk_hw_register_fixed_factor(NULL, core_name, eip_name, 0, 1, 2);
 255         if (IS_ERR(hw)) {
 256                 ret = PTR_ERR(hw);
 257                 goto fail3;
 258         }
 259
 260         cp110_clks[CP110_CORE_CORE] = hw;
 261
 262         /* NAND can be either APLL/2.5 or core clock */
 263         of_property_read_string_index(np, "core-clock-output-names",
 264                                       CP110_CORE_NAND, &nand_name);
 265         if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
 266                 hw = clk_hw_register_fixed_factor(NULL, nand_name,
 267                                                    apll_name, 0, 2, 5);
 268         else
 269                 hw = clk_hw_register_fixed_factor(NULL, nand_name,
 270                                                    core_name, 0, 1, 1);
 271         if (IS_ERR(hw)) {
 272                 ret = PTR_ERR(hw);
 273                 goto fail4;
 274         }
 275
 276         cp110_clks[CP110_CORE_NAND] = hw;
 277
 278         for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
 279                 const char *parent, *name;
 280                 int ret;
 281
 282                 ret = of_property_read_string_index(np,
 283                                                     "gate-clock-output-names",
 284                                                     i, &name);
 285                 /* Reached the end of the list? */
 286                 if (ret < 0)
 287                         break;
 288
 289                 if (!strcmp(name, "none"))
 290                         continue;
 291
 292                 switch (i) {
 293                 case CP110_GATE_AUDIO:
 294                 case CP110_GATE_COMM_UNIT:
 295                 case CP110_GATE_EIP150:
 296                 case CP110_GATE_EIP197:
 297                 case CP110_GATE_SLOW_IO:
 298                         of_property_read_string_index(np,
 299                                                       "gate-clock-output-names",
 300                                                       CP110_GATE_MAIN, &parent);
 301                         break;
 302                 case CP110_GATE_MG:
 303                         of_property_read_string_index(np,
 304                                                       "gate-clock-output-names",
 305                                                       CP110_GATE_MG_CORE, &parent);
 306                         break;
 307                 case CP110_GATE_NAND:
 308                         parent = nand_name;
 309                         break;
 310                 case CP110_GATE_PPV2:
 311                         parent = ppv2_name;
 312                         break;
 313                 case CP110_GATE_SDIO:
 314                 case CP110_GATE_GOP_DP:
 315                         of_property_read_string_index(np,
 316                                                       "gate-clock-output-names",
 317                                                       CP110_GATE_SDMMC_GOP, &parent);
 318                         break;
 319                 case CP110_GATE_XOR1:
 320                 case CP110_GATE_XOR0:
 321                 case CP110_GATE_PCIE_X1_0:
 322                 case CP110_GATE_PCIE_X1_1:
 323                 case CP110_GATE_PCIE_X4:
 324                         of_property_read_string_index(np,
 325                                                       "gate-clock-output-names",
 326                                                       CP110_GATE_PCIE_XOR, &parent);
 327                         break;
 328                 case CP110_GATE_SATA:
 329                 case CP110_GATE_USB3H0:
 330                 case CP110_GATE_USB3H1:
 331                 case CP110_GATE_USB3DEV:
 332                         of_property_read_string_index(np,
 333                                                       "gate-clock-output-names",
 334                                                       CP110_GATE_SATA_USB, &parent);
 335                         break;
 336                 default:
 337                         parent = core_name;
 338                         break;
 339                 }
 340
 341                 hw = cp110_register_gate(name, parent, regmap, i);
 342                 if (IS_ERR(hw)) {
 343                         ret = PTR_ERR(hw);
 344                         goto fail_gate;
 345                 }
 346
 347                 cp110_clks[CP110_MAX_CORE_CLOCKS + i] = hw;
 348         }
 349
 350         ret = of_clk_add_hw_provider(np, cp110_of_clk_get, cp110_clk_data);
 351         if (ret)
 352                 goto fail_clk_add;
 353
 354         platform_set_drvdata(pdev, cp110_clks);
 355
 356         return 0;
 357
 358 fail_clk_add:
 359 fail_gate:
 360         for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
 361                 hw = cp110_clks[CP110_MAX_CORE_CLOCKS + i];
 362
 363                 if (hw)
 364                         cp110_unregister_gate(hw);
 365         }
 366
 367         clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
 368 fail4:
 369         clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
 370 fail3:
 371         clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_EIP]);
 372 fail2:
 373         clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]);
 374 fail1:
 375         clk_hw_unregister_fixed_rate(cp110_clks[CP110_CORE_APLL]);
 376 fail0:
 377         return ret;
 378 }
 379
 380 static const struct of_device_id cp110_syscon_of_match[] = {
 381         { .compatible = "marvell,cp110-system-controller0", },
 382         { }
 383 };
 384
 385 static struct platform_driver cp110_syscon_driver = {
 386         .probe = cp110_syscon_clk_probe,
 387         .driver         = {
 388                 .name   = "marvell-cp110-system-controller0",
 389                 .of_match_table = cp110_syscon_of_match,
 390                 .suppress_bind_attrs = true,
 391         },
 392 };
 393 builtin_platform_driver(cp110_syscon_driver);