2 * Renesas Clock Pulse Generator / Module Standby and Software Reset
4 * Copyright (C) 2015 Glider bvba
6 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
8 * Copyright (C) 2013 Ideas On Board SPRL
9 * Copyright (C) 2015 Renesas Electronics Corp.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/clk/renesas.h>
19 #include <linux/delay.h>
20 #include <linux/device.h>
21 #include <linux/init.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/module.h>
24 #include <linux/of_address.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_clock.h>
28 #include <linux/pm_domain.h>
29 #include <linux/reset-controller.h>
30 #include <linux/slab.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "renesas-cpg-mssr.h"
38 #define WARN_DEBUG(x) WARN_ON(x)
40 #define WARN_DEBUG(x) do { } while (0)
45 * Module Standby and Software Reset register offets.
47 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
48 * R-Car Gen2, R-Car Gen3, and RZ/G1.
49 * These are NOT valid for R-Car Gen1 and RZ/A1!
53 * Module Stop Status Register offsets
56 static const u16 mstpsr
[] = {
57 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
58 0x9A0, 0x9A4, 0x9A8, 0x9AC,
61 #define MSTPSR(i) mstpsr[i]
65 * System Module Stop Control Register offsets
68 static const u16 smstpcr
[] = {
69 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
70 0x990, 0x994, 0x998, 0x99C,
73 #define SMSTPCR(i) smstpcr[i]
77 * Software Reset Register offsets
80 static const u16 srcr
[] = {
81 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
82 0x920, 0x924, 0x928, 0x92C,
85 #define SRCR(i) srcr[i]
88 /* Realtime Module Stop Control Register offsets */
89 #define RMSTPCR(i) (smstpcr[i] - 0x20)
91 /* Modem Module Stop Control Register offsets (r8a73a4) */
92 #define MMSTPCR(i) (smstpcr[i] + 0x20)
94 /* Software Reset Clearing Register offsets */
95 #define SRSTCLR(i) (0x940 + (i) * 4)
99 * Clock Pulse Generator / Module Standby and Software Reset Private Data
101 * @rcdev: Optional reset controller entity
102 * @dev: CPG/MSSR device
103 * @base: CPG/MSSR register block base address
104 * @rmw_lock: protects RMW register accesses
105 * @clks: Array containing all Core and Module Clocks
106 * @num_core_clks: Number of Core Clocks in clks[]
107 * @num_mod_clks: Number of Module Clocks in clks[]
108 * @last_dt_core_clk: ID of the last Core Clock exported to DT
110 struct cpg_mssr_priv
{
111 #ifdef CONFIG_RESET_CONTROLLER
112 struct reset_controller_dev rcdev
;
119 unsigned int num_core_clks
;
120 unsigned int num_mod_clks
;
121 unsigned int last_dt_core_clk
;
126 * struct mstp_clock - MSTP gating clock
127 * @hw: handle between common and hardware-specific interfaces
128 * @index: MSTP clock number
129 * @priv: CPG/MSSR private data
134 struct cpg_mssr_priv
*priv
;
137 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
139 static int cpg_mstp_clock_endisable(struct clk_hw
*hw
, bool enable
)
141 struct mstp_clock
*clock
= to_mstp_clock(hw
);
142 struct cpg_mssr_priv
*priv
= clock
->priv
;
143 unsigned int reg
= clock
->index
/ 32;
144 unsigned int bit
= clock
->index
% 32;
145 struct device
*dev
= priv
->dev
;
146 u32 bitmask
= BIT(bit
);
151 dev_dbg(dev
, "MSTP %u%02u/%pC %s\n", reg
, bit
, hw
->clk
,
152 enable
? "ON" : "OFF");
153 spin_lock_irqsave(&priv
->rmw_lock
, flags
);
155 value
= readl(priv
->base
+ SMSTPCR(reg
));
160 writel(value
, priv
->base
+ SMSTPCR(reg
));
162 spin_unlock_irqrestore(&priv
->rmw_lock
, flags
);
167 for (i
= 1000; i
> 0; --i
) {
168 if (!(readl(priv
->base
+ MSTPSR(reg
)) & bitmask
))
174 dev_err(dev
, "Failed to enable SMSTP %p[%d]\n",
175 priv
->base
+ SMSTPCR(reg
), bit
);
182 static int cpg_mstp_clock_enable(struct clk_hw
*hw
)
184 return cpg_mstp_clock_endisable(hw
, true);
187 static void cpg_mstp_clock_disable(struct clk_hw
*hw
)
189 cpg_mstp_clock_endisable(hw
, false);
192 static int cpg_mstp_clock_is_enabled(struct clk_hw
*hw
)
194 struct mstp_clock
*clock
= to_mstp_clock(hw
);
195 struct cpg_mssr_priv
*priv
= clock
->priv
;
198 value
= readl(priv
->base
+ MSTPSR(clock
->index
/ 32));
200 return !(value
& BIT(clock
->index
% 32));
203 static const struct clk_ops cpg_mstp_clock_ops
= {
204 .enable
= cpg_mstp_clock_enable
,
205 .disable
= cpg_mstp_clock_disable
,
206 .is_enabled
= cpg_mstp_clock_is_enabled
,
210 struct clk
*cpg_mssr_clk_src_twocell_get(struct of_phandle_args
*clkspec
,
213 unsigned int clkidx
= clkspec
->args
[1];
214 struct cpg_mssr_priv
*priv
= data
;
215 struct device
*dev
= priv
->dev
;
220 switch (clkspec
->args
[0]) {
223 if (clkidx
> priv
->last_dt_core_clk
) {
224 dev_err(dev
, "Invalid %s clock index %u\n", type
,
226 return ERR_PTR(-EINVAL
);
228 clk
= priv
->clks
[clkidx
];
233 idx
= MOD_CLK_PACK(clkidx
);
234 if (clkidx
% 100 > 31 || idx
>= priv
->num_mod_clks
) {
235 dev_err(dev
, "Invalid %s clock index %u\n", type
,
237 return ERR_PTR(-EINVAL
);
239 clk
= priv
->clks
[priv
->num_core_clks
+ idx
];
243 dev_err(dev
, "Invalid CPG clock type %u\n", clkspec
->args
[0]);
244 return ERR_PTR(-EINVAL
);
248 dev_err(dev
, "Cannot get %s clock %u: %ld", type
, clkidx
,
251 dev_dbg(dev
, "clock (%u, %u) is %pC at %pCr Hz\n",
252 clkspec
->args
[0], clkspec
->args
[1], clk
, clk
);
256 static void __init
cpg_mssr_register_core_clk(const struct cpg_core_clk
*core
,
257 const struct cpg_mssr_info
*info
,
258 struct cpg_mssr_priv
*priv
)
260 struct clk
*clk
= ERR_PTR(-ENOTSUPP
), *parent
;
261 struct device
*dev
= priv
->dev
;
262 unsigned int id
= core
->id
, div
= core
->div
;
263 const char *parent_name
;
265 WARN_DEBUG(id
>= priv
->num_core_clks
);
266 WARN_DEBUG(PTR_ERR(priv
->clks
[id
]) != -ENOENT
);
269 /* Skip NULLified clock */
273 switch (core
->type
) {
275 clk
= of_clk_get_by_name(priv
->dev
->of_node
, core
->name
);
279 case CLK_TYPE_DIV6P1
:
280 case CLK_TYPE_DIV6_RO
:
281 WARN_DEBUG(core
->parent
>= priv
->num_core_clks
);
282 parent
= priv
->clks
[core
->parent
];
283 if (IS_ERR(parent
)) {
288 parent_name
= __clk_get_name(parent
);
290 if (core
->type
== CLK_TYPE_DIV6_RO
)
291 /* Multiply with the DIV6 register value */
292 div
*= (readl(priv
->base
+ core
->offset
) & 0x3f) + 1;
294 if (core
->type
== CLK_TYPE_DIV6P1
) {
295 clk
= cpg_div6_register(core
->name
, 1, &parent_name
,
296 priv
->base
+ core
->offset
);
298 clk
= clk_register_fixed_factor(NULL
, core
->name
,
305 if (info
->cpg_clk_register
)
306 clk
= info
->cpg_clk_register(dev
, core
, info
,
307 priv
->clks
, priv
->base
);
309 dev_err(dev
, "%s has unsupported core clock type %u\n",
310 core
->name
, core
->type
);
314 if (IS_ERR_OR_NULL(clk
))
317 dev_dbg(dev
, "Core clock %pC at %pCr Hz\n", clk
, clk
);
318 priv
->clks
[id
] = clk
;
322 dev_err(dev
, "Failed to register %s clock %s: %ld\n", "core",
323 core
->name
, PTR_ERR(clk
));
326 static void __init
cpg_mssr_register_mod_clk(const struct mssr_mod_clk
*mod
,
327 const struct cpg_mssr_info
*info
,
328 struct cpg_mssr_priv
*priv
)
330 struct mstp_clock
*clock
= NULL
;
331 struct device
*dev
= priv
->dev
;
332 unsigned int id
= mod
->id
;
333 struct clk_init_data init
;
334 struct clk
*parent
, *clk
;
335 const char *parent_name
;
338 WARN_DEBUG(id
< priv
->num_core_clks
);
339 WARN_DEBUG(id
>= priv
->num_core_clks
+ priv
->num_mod_clks
);
340 WARN_DEBUG(mod
->parent
>= priv
->num_core_clks
+ priv
->num_mod_clks
);
341 WARN_DEBUG(PTR_ERR(priv
->clks
[id
]) != -ENOENT
);
344 /* Skip NULLified clock */
348 parent
= priv
->clks
[mod
->parent
];
349 if (IS_ERR(parent
)) {
354 clock
= kzalloc(sizeof(*clock
), GFP_KERNEL
);
356 clk
= ERR_PTR(-ENOMEM
);
360 init
.name
= mod
->name
;
361 init
.ops
= &cpg_mstp_clock_ops
;
362 init
.flags
= CLK_IS_BASIC
| CLK_SET_RATE_PARENT
;
363 for (i
= 0; i
< info
->num_crit_mod_clks
; i
++)
364 if (id
== info
->crit_mod_clks
[i
]) {
365 dev_dbg(dev
, "MSTP %s setting CLK_IS_CRITICAL\n",
367 init
.flags
|= CLK_IS_CRITICAL
;
371 parent_name
= __clk_get_name(parent
);
372 init
.parent_names
= &parent_name
;
373 init
.num_parents
= 1;
375 clock
->index
= id
- priv
->num_core_clks
;
377 clock
->hw
.init
= &init
;
379 clk
= clk_register(NULL
, &clock
->hw
);
383 dev_dbg(dev
, "Module clock %pC at %pCr Hz\n", clk
, clk
);
384 priv
->clks
[id
] = clk
;
388 dev_err(dev
, "Failed to register %s clock %s: %ld\n", "module",
389 mod
->name
, PTR_ERR(clk
));
393 struct cpg_mssr_clk_domain
{
394 struct generic_pm_domain genpd
;
395 struct device_node
*np
;
396 unsigned int num_core_pm_clks
;
397 unsigned int core_pm_clks
[0];
400 static struct cpg_mssr_clk_domain
*cpg_mssr_clk_domain
;
402 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args
*clkspec
,
403 struct cpg_mssr_clk_domain
*pd
)
407 if (clkspec
->np
!= pd
->np
|| clkspec
->args_count
!= 2)
410 switch (clkspec
->args
[0]) {
412 for (i
= 0; i
< pd
->num_core_pm_clks
; i
++)
413 if (clkspec
->args
[1] == pd
->core_pm_clks
[i
])
425 int cpg_mssr_attach_dev(struct generic_pm_domain
*unused
, struct device
*dev
)
427 struct cpg_mssr_clk_domain
*pd
= cpg_mssr_clk_domain
;
428 struct device_node
*np
= dev
->of_node
;
429 struct of_phandle_args clkspec
;
435 dev_dbg(dev
, "CPG/MSSR clock domain not yet available\n");
436 return -EPROBE_DEFER
;
439 while (!of_parse_phandle_with_args(np
, "clocks", "#clock-cells", i
,
441 if (cpg_mssr_is_pm_clk(&clkspec
, pd
))
444 of_node_put(clkspec
.np
);
451 clk
= of_clk_get_from_provider(&clkspec
);
452 of_node_put(clkspec
.np
);
457 error
= pm_clk_create(dev
);
459 dev_err(dev
, "pm_clk_create failed %d\n", error
);
463 error
= pm_clk_add_clk(dev
, clk
);
465 dev_err(dev
, "pm_clk_add_clk %pC failed %d\n", clk
, error
);
478 void cpg_mssr_detach_dev(struct generic_pm_domain
*unused
, struct device
*dev
)
480 if (!pm_clk_no_clocks(dev
))
484 static int __init
cpg_mssr_add_clk_domain(struct device
*dev
,
485 const unsigned int *core_pm_clks
,
486 unsigned int num_core_pm_clks
)
488 struct device_node
*np
= dev
->of_node
;
489 struct generic_pm_domain
*genpd
;
490 struct cpg_mssr_clk_domain
*pd
;
491 size_t pm_size
= num_core_pm_clks
* sizeof(core_pm_clks
[0]);
493 pd
= devm_kzalloc(dev
, sizeof(*pd
) + pm_size
, GFP_KERNEL
);
498 pd
->num_core_pm_clks
= num_core_pm_clks
;
499 memcpy(pd
->core_pm_clks
, core_pm_clks
, pm_size
);
502 genpd
->name
= np
->name
;
503 genpd
->flags
= GENPD_FLAG_PM_CLK
;
504 genpd
->attach_dev
= cpg_mssr_attach_dev
;
505 genpd
->detach_dev
= cpg_mssr_detach_dev
;
506 pm_genpd_init(genpd
, &pm_domain_always_on_gov
, false);
507 cpg_mssr_clk_domain
= pd
;
509 of_genpd_add_provider_simple(np
, genpd
);
513 #ifdef CONFIG_RESET_CONTROLLER
515 #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev)
517 static int cpg_mssr_reset(struct reset_controller_dev
*rcdev
,
520 struct cpg_mssr_priv
*priv
= rcdev_to_priv(rcdev
);
521 unsigned int reg
= id
/ 32;
522 unsigned int bit
= id
% 32;
523 u32 bitmask
= BIT(bit
);
527 dev_dbg(priv
->dev
, "reset %u%02u\n", reg
, bit
);
530 spin_lock_irqsave(&priv
->rmw_lock
, flags
);
531 value
= readl(priv
->base
+ SRCR(reg
));
533 writel(value
, priv
->base
+ SRCR(reg
));
534 spin_unlock_irqrestore(&priv
->rmw_lock
, flags
);
536 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
539 /* Release module from reset state */
540 writel(bitmask
, priv
->base
+ SRSTCLR(reg
));
545 static int cpg_mssr_assert(struct reset_controller_dev
*rcdev
, unsigned long id
)
547 struct cpg_mssr_priv
*priv
= rcdev_to_priv(rcdev
);
548 unsigned int reg
= id
/ 32;
549 unsigned int bit
= id
% 32;
550 u32 bitmask
= BIT(bit
);
554 dev_dbg(priv
->dev
, "assert %u%02u\n", reg
, bit
);
556 spin_lock_irqsave(&priv
->rmw_lock
, flags
);
557 value
= readl(priv
->base
+ SRCR(reg
));
559 writel(value
, priv
->base
+ SRCR(reg
));
560 spin_unlock_irqrestore(&priv
->rmw_lock
, flags
);
564 static int cpg_mssr_deassert(struct reset_controller_dev
*rcdev
,
567 struct cpg_mssr_priv
*priv
= rcdev_to_priv(rcdev
);
568 unsigned int reg
= id
/ 32;
569 unsigned int bit
= id
% 32;
570 u32 bitmask
= BIT(bit
);
572 dev_dbg(priv
->dev
, "deassert %u%02u\n", reg
, bit
);
574 writel(bitmask
, priv
->base
+ SRSTCLR(reg
));
578 static int cpg_mssr_status(struct reset_controller_dev
*rcdev
,
581 struct cpg_mssr_priv
*priv
= rcdev_to_priv(rcdev
);
582 unsigned int reg
= id
/ 32;
583 unsigned int bit
= id
% 32;
584 u32 bitmask
= BIT(bit
);
586 return !!(readl(priv
->base
+ SRCR(reg
)) & bitmask
);
589 static const struct reset_control_ops cpg_mssr_reset_ops
= {
590 .reset
= cpg_mssr_reset
,
591 .assert = cpg_mssr_assert
,
592 .deassert
= cpg_mssr_deassert
,
593 .status
= cpg_mssr_status
,
596 static int cpg_mssr_reset_xlate(struct reset_controller_dev
*rcdev
,
597 const struct of_phandle_args
*reset_spec
)
599 struct cpg_mssr_priv
*priv
= rcdev_to_priv(rcdev
);
600 unsigned int unpacked
= reset_spec
->args
[0];
601 unsigned int idx
= MOD_CLK_PACK(unpacked
);
603 if (unpacked
% 100 > 31 || idx
>= rcdev
->nr_resets
) {
604 dev_err(priv
->dev
, "Invalid reset index %u\n", unpacked
);
611 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv
*priv
)
613 priv
->rcdev
.ops
= &cpg_mssr_reset_ops
;
614 priv
->rcdev
.of_node
= priv
->dev
->of_node
;
615 priv
->rcdev
.of_reset_n_cells
= 1;
616 priv
->rcdev
.of_xlate
= cpg_mssr_reset_xlate
;
617 priv
->rcdev
.nr_resets
= priv
->num_mod_clks
;
618 return devm_reset_controller_register(priv
->dev
, &priv
->rcdev
);
621 #else /* !CONFIG_RESET_CONTROLLER */
622 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv
*priv
)
626 #endif /* !CONFIG_RESET_CONTROLLER */
629 static const struct of_device_id cpg_mssr_match
[] = {
630 #ifdef CONFIG_CLK_R8A7743
632 .compatible
= "renesas,r8a7743-cpg-mssr",
633 .data
= &r8a7743_cpg_mssr_info
,
636 #ifdef CONFIG_CLK_R8A7745
638 .compatible
= "renesas,r8a7745-cpg-mssr",
639 .data
= &r8a7745_cpg_mssr_info
,
642 #ifdef CONFIG_CLK_R8A7790
644 .compatible
= "renesas,r8a7790-cpg-mssr",
645 .data
= &r8a7790_cpg_mssr_info
,
648 #ifdef CONFIG_CLK_R8A7791
650 .compatible
= "renesas,r8a7791-cpg-mssr",
651 .data
= &r8a7791_cpg_mssr_info
,
653 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
655 .compatible
= "renesas,r8a7793-cpg-mssr",
656 .data
= &r8a7791_cpg_mssr_info
,
659 #ifdef CONFIG_CLK_R8A7792
661 .compatible
= "renesas,r8a7792-cpg-mssr",
662 .data
= &r8a7792_cpg_mssr_info
,
665 #ifdef CONFIG_CLK_R8A7794
667 .compatible
= "renesas,r8a7794-cpg-mssr",
668 .data
= &r8a7794_cpg_mssr_info
,
671 #ifdef CONFIG_CLK_R8A7795
673 .compatible
= "renesas,r8a7795-cpg-mssr",
674 .data
= &r8a7795_cpg_mssr_info
,
677 #ifdef CONFIG_CLK_R8A7796
679 .compatible
= "renesas,r8a7796-cpg-mssr",
680 .data
= &r8a7796_cpg_mssr_info
,
686 static void cpg_mssr_del_clk_provider(void *data
)
688 of_clk_del_provider(data
);
691 static int __init
cpg_mssr_probe(struct platform_device
*pdev
)
693 struct device
*dev
= &pdev
->dev
;
694 struct device_node
*np
= dev
->of_node
;
695 const struct cpg_mssr_info
*info
;
696 struct cpg_mssr_priv
*priv
;
697 unsigned int nclks
, i
;
698 struct resource
*res
;
702 info
= of_device_get_match_data(dev
);
704 error
= info
->init(dev
);
709 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
714 spin_lock_init(&priv
->rmw_lock
);
716 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
717 priv
->base
= devm_ioremap_resource(dev
, res
);
718 if (IS_ERR(priv
->base
))
719 return PTR_ERR(priv
->base
);
721 nclks
= info
->num_total_core_clks
+ info
->num_hw_mod_clks
;
722 clks
= devm_kmalloc_array(dev
, nclks
, sizeof(*clks
), GFP_KERNEL
);
727 priv
->num_core_clks
= info
->num_total_core_clks
;
728 priv
->num_mod_clks
= info
->num_hw_mod_clks
;
729 priv
->last_dt_core_clk
= info
->last_dt_core_clk
;
731 for (i
= 0; i
< nclks
; i
++)
732 clks
[i
] = ERR_PTR(-ENOENT
);
734 for (i
= 0; i
< info
->num_core_clks
; i
++)
735 cpg_mssr_register_core_clk(&info
->core_clks
[i
], info
, priv
);
737 for (i
= 0; i
< info
->num_mod_clks
; i
++)
738 cpg_mssr_register_mod_clk(&info
->mod_clks
[i
], info
, priv
);
740 error
= of_clk_add_provider(np
, cpg_mssr_clk_src_twocell_get
, priv
);
744 error
= devm_add_action_or_reset(dev
,
745 cpg_mssr_del_clk_provider
,
750 error
= cpg_mssr_add_clk_domain(dev
, info
->core_pm_clks
,
751 info
->num_core_pm_clks
);
755 error
= cpg_mssr_reset_controller_register(priv
);
762 static struct platform_driver cpg_mssr_driver
= {
764 .name
= "renesas-cpg-mssr",
765 .of_match_table
= cpg_mssr_match
,
769 static int __init
cpg_mssr_init(void)
771 return platform_driver_probe(&cpg_mssr_driver
, cpg_mssr_probe
);
774 subsys_initcall(cpg_mssr_init
);
776 void __init
cpg_core_nullify_range(struct cpg_core_clk
*core_clks
,
777 unsigned int num_core_clks
,
778 unsigned int first_clk
,
779 unsigned int last_clk
)
783 for (i
= 0; i
< num_core_clks
; i
++)
784 if (core_clks
[i
].id
>= first_clk
&&
785 core_clks
[i
].id
<= last_clk
)
786 core_clks
[i
].name
= NULL
;
789 void __init
mssr_mod_nullify(struct mssr_mod_clk
*mod_clks
,
790 unsigned int num_mod_clks
,
791 const unsigned int *clks
, unsigned int n
)
795 for (i
= 0, j
= 0; i
< num_mod_clks
&& j
< n
; i
++)
796 if (mod_clks
[i
].id
== clks
[j
]) {
797 mod_clks
[i
].name
= NULL
;
802 void __init
mssr_mod_reparent(struct mssr_mod_clk
*mod_clks
,
803 unsigned int num_mod_clks
,
804 const struct mssr_mod_reparent
*clks
,
809 for (i
= 0, j
= 0; i
< num_mod_clks
&& j
< n
; i
++)
810 if (mod_clks
[i
].id
== clks
[j
].clk
) {
811 mod_clks
[i
].parent
= clks
[j
].parent
;
816 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
817 MODULE_LICENSE("GPL v2");