drivers/cxl/pci.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /* Copyright(c) 2020 Intel Corporation. All rights reserved. */
   3 #ifndef __CXL_PCI_H__
   4 #define __CXL_PCI_H__
   5
   6 #define CXL_MEMORY_PROGIF       0x10
   7
   8 /*
   9  * See section 8.1 Configuration Space Registers in the CXL 2.0
  10  * Specification
  11  */
  12 #define PCI_DVSEC_HEADER1_LENGTH_MASK   GENMASK(31, 20)
  13 #define PCI_DVSEC_VENDOR_ID_CXL         0x1E98
  14 #define PCI_DVSEC_ID_CXL                0x0
  15
  16 #define PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID        0x8
  17 #define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET   0xC
  18
  19 /* BAR Indicator Register (BIR) */
  20 #define CXL_REGLOC_BIR_MASK GENMASK(2, 0)
  21
  22 /* Register Block Identifier (RBI) */
  23 #define CXL_REGLOC_RBI_MASK GENMASK(15, 8)
  24 #define CXL_REGLOC_RBI_EMPTY 0
  25 #define CXL_REGLOC_RBI_COMPONENT 1
  26 #define CXL_REGLOC_RBI_VIRT 2
  27 #define CXL_REGLOC_RBI_MEMDEV 3
  28
  29 #define CXL_REGLOC_ADDR_MASK GENMASK(31, 16)
  30
  31 #endif /* __CXL_PCI_H__ */