1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
8 #include <asm/cacheflush.h>
9 #include <linux/ctype.h>
10 #include <linux/delay.h>
11 #include <linux/edac.h>
12 #include <linux/firmware/intel/stratix10-smc.h>
13 #include <linux/genalloc.h>
14 #include <linux/interrupt.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/notifier.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/types.h>
25 #include <linux/uaccess.h>
27 #include "altera_edac.h"
28 #include "edac_module.h"
30 #define EDAC_MOD_STR "altera_edac"
31 #define EDAC_DEVICE "Altera"
33 #ifdef CONFIG_EDAC_ALTERA_SDRAM
34 static const struct altr_sdram_prv_data c5_data
= {
35 .ecc_ctrl_offset
= CV_CTLCFG_OFST
,
36 .ecc_ctl_en_mask
= CV_CTLCFG_ECC_AUTO_EN
,
37 .ecc_stat_offset
= CV_DRAMSTS_OFST
,
38 .ecc_stat_ce_mask
= CV_DRAMSTS_SBEERR
,
39 .ecc_stat_ue_mask
= CV_DRAMSTS_DBEERR
,
40 .ecc_saddr_offset
= CV_ERRADDR_OFST
,
41 .ecc_daddr_offset
= CV_ERRADDR_OFST
,
42 .ecc_cecnt_offset
= CV_SBECOUNT_OFST
,
43 .ecc_uecnt_offset
= CV_DBECOUNT_OFST
,
44 .ecc_irq_en_offset
= CV_DRAMINTR_OFST
,
45 .ecc_irq_en_mask
= CV_DRAMINTR_INTREN
,
46 .ecc_irq_clr_offset
= CV_DRAMINTR_OFST
,
47 .ecc_irq_clr_mask
= (CV_DRAMINTR_INTRCLR
| CV_DRAMINTR_INTREN
),
48 .ecc_cnt_rst_offset
= CV_DRAMINTR_OFST
,
49 .ecc_cnt_rst_mask
= CV_DRAMINTR_INTRCLR
,
50 .ce_ue_trgr_offset
= CV_CTLCFG_OFST
,
51 .ce_set_mask
= CV_CTLCFG_GEN_SB_ERR
,
52 .ue_set_mask
= CV_CTLCFG_GEN_DB_ERR
,
55 static const struct altr_sdram_prv_data a10_data
= {
56 .ecc_ctrl_offset
= A10_ECCCTRL1_OFST
,
57 .ecc_ctl_en_mask
= A10_ECCCTRL1_ECC_EN
,
58 .ecc_stat_offset
= A10_INTSTAT_OFST
,
59 .ecc_stat_ce_mask
= A10_INTSTAT_SBEERR
,
60 .ecc_stat_ue_mask
= A10_INTSTAT_DBEERR
,
61 .ecc_saddr_offset
= A10_SERRADDR_OFST
,
62 .ecc_daddr_offset
= A10_DERRADDR_OFST
,
63 .ecc_irq_en_offset
= A10_ERRINTEN_OFST
,
64 .ecc_irq_en_mask
= A10_ECC_IRQ_EN_MASK
,
65 .ecc_irq_clr_offset
= A10_INTSTAT_OFST
,
66 .ecc_irq_clr_mask
= (A10_INTSTAT_SBEERR
| A10_INTSTAT_DBEERR
),
67 .ecc_cnt_rst_offset
= A10_ECCCTRL1_OFST
,
68 .ecc_cnt_rst_mask
= A10_ECC_CNT_RESET_MASK
,
69 .ce_ue_trgr_offset
= A10_DIAGINTTEST_OFST
,
70 .ce_set_mask
= A10_DIAGINT_TSERRA_MASK
,
71 .ue_set_mask
= A10_DIAGINT_TDERRA_MASK
,
74 /*********************** EDAC Memory Controller Functions ****************/
76 /* The SDRAM controller uses the EDAC Memory Controller framework. */
78 static irqreturn_t
altr_sdram_mc_err_handler(int irq
, void *dev_id
)
80 struct mem_ctl_info
*mci
= dev_id
;
81 struct altr_sdram_mc_data
*drvdata
= mci
->pvt_info
;
82 const struct altr_sdram_prv_data
*priv
= drvdata
->data
;
83 u32 status
, err_count
= 1, err_addr
;
85 regmap_read(drvdata
->mc_vbase
, priv
->ecc_stat_offset
, &status
);
87 if (status
& priv
->ecc_stat_ue_mask
) {
88 regmap_read(drvdata
->mc_vbase
, priv
->ecc_daddr_offset
,
90 if (priv
->ecc_uecnt_offset
)
91 regmap_read(drvdata
->mc_vbase
, priv
->ecc_uecnt_offset
,
93 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
96 if (status
& priv
->ecc_stat_ce_mask
) {
97 regmap_read(drvdata
->mc_vbase
, priv
->ecc_saddr_offset
,
99 if (priv
->ecc_uecnt_offset
)
100 regmap_read(drvdata
->mc_vbase
, priv
->ecc_cecnt_offset
,
102 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED
, mci
, err_count
,
103 err_addr
>> PAGE_SHIFT
,
104 err_addr
& ~PAGE_MASK
, 0,
105 0, 0, -1, mci
->ctl_name
, "");
106 /* Clear IRQ to resume */
107 regmap_write(drvdata
->mc_vbase
, priv
->ecc_irq_clr_offset
,
108 priv
->ecc_irq_clr_mask
);
115 static ssize_t
altr_sdr_mc_err_inject_write(struct file
*file
,
116 const char __user
*data
,
117 size_t count
, loff_t
*ppos
)
119 struct mem_ctl_info
*mci
= file
->private_data
;
120 struct altr_sdram_mc_data
*drvdata
= mci
->pvt_info
;
121 const struct altr_sdram_prv_data
*priv
= drvdata
->data
;
123 dma_addr_t dma_handle
;
126 ptemp
= dma_alloc_coherent(mci
->pdev
, 16, &dma_handle
, GFP_KERNEL
);
128 dma_free_coherent(mci
->pdev
, 16, ptemp
, dma_handle
);
129 edac_printk(KERN_ERR
, EDAC_MC
,
130 "Inject: Buffer Allocation error\n");
134 regmap_read(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
136 read_reg
&= ~(priv
->ce_set_mask
| priv
->ue_set_mask
);
138 /* Error are injected by writing a word while the SBE or DBE
139 * bit in the CTLCFG register is set. Reading the word will
140 * trigger the SBE or DBE error and the corresponding IRQ.
143 edac_printk(KERN_ALERT
, EDAC_MC
,
144 "Inject Double bit error\n");
146 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
147 (read_reg
| priv
->ue_set_mask
));
150 edac_printk(KERN_ALERT
, EDAC_MC
,
151 "Inject Single bit error\n");
153 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
154 (read_reg
| priv
->ce_set_mask
));
158 ptemp
[0] = 0x5A5A5A5A;
159 ptemp
[1] = 0xA5A5A5A5;
161 /* Clear the error injection bits */
162 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
, read_reg
);
163 /* Ensure it has been written out */
167 * To trigger the error, we need to read the data back
168 * (the data was written with errors above).
169 * The READ_ONCE macros and printk are used to prevent the
170 * the compiler optimizing these reads out.
172 reg
= READ_ONCE(ptemp
[0]);
173 read_reg
= READ_ONCE(ptemp
[1]);
177 edac_printk(KERN_ALERT
, EDAC_MC
, "Read Data [0x%X, 0x%X]\n",
180 dma_free_coherent(mci
->pdev
, 16, ptemp
, dma_handle
);
185 static const struct file_operations altr_sdr_mc_debug_inject_fops
= {
187 .write
= altr_sdr_mc_err_inject_write
,
188 .llseek
= generic_file_llseek
,
191 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info
*mci
)
193 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
199 edac_debugfs_create_file("altr_trigger", S_IWUSR
, mci
->debugfs
, mci
,
200 &altr_sdr_mc_debug_inject_fops
);
203 /* Get total memory size from Open Firmware DTB */
204 static unsigned long get_total_mem(void)
206 struct device_node
*np
= NULL
;
209 unsigned long total_mem
= 0;
211 for_each_node_by_type(np
, "memory") {
212 ret
= of_address_to_resource(np
, 0, &res
);
216 total_mem
+= resource_size(&res
);
218 edac_dbg(0, "total_mem 0x%lx\n", total_mem
);
222 static const struct of_device_id altr_sdram_ctrl_of_match
[] = {
223 { .compatible
= "altr,sdram-edac", .data
= &c5_data
},
224 { .compatible
= "altr,sdram-edac-a10", .data
= &a10_data
},
225 { .compatible
= "altr,sdram-edac-s10", .data
= &a10_data
},
228 MODULE_DEVICE_TABLE(of
, altr_sdram_ctrl_of_match
);
230 static int a10_init(struct regmap
*mc_vbase
)
232 if (regmap_update_bits(mc_vbase
, A10_INTMODE_OFST
,
233 A10_INTMODE_SB_INT
, A10_INTMODE_SB_INT
)) {
234 edac_printk(KERN_ERR
, EDAC_MC
,
235 "Error setting SB IRQ mode\n");
239 if (regmap_write(mc_vbase
, A10_SERRCNTREG_OFST
, 1)) {
240 edac_printk(KERN_ERR
, EDAC_MC
,
241 "Error setting trigger count\n");
248 static int a10_unmask_irq(struct platform_device
*pdev
, u32 mask
)
250 void __iomem
*sm_base
;
253 if (!request_mem_region(A10_SYMAN_INTMASK_CLR
, sizeof(u32
),
254 dev_name(&pdev
->dev
))) {
255 edac_printk(KERN_ERR
, EDAC_MC
,
256 "Unable to request mem region\n");
260 sm_base
= ioremap(A10_SYMAN_INTMASK_CLR
, sizeof(u32
));
262 edac_printk(KERN_ERR
, EDAC_MC
,
263 "Unable to ioremap device\n");
269 iowrite32(mask
, sm_base
);
274 release_mem_region(A10_SYMAN_INTMASK_CLR
, sizeof(u32
));
279 static int socfpga_is_a10(void);
280 static int altr_sdram_probe(struct platform_device
*pdev
)
282 const struct of_device_id
*id
;
283 struct edac_mc_layer layers
[2];
284 struct mem_ctl_info
*mci
;
285 struct altr_sdram_mc_data
*drvdata
;
286 const struct altr_sdram_prv_data
*priv
;
287 struct regmap
*mc_vbase
;
288 struct dimm_info
*dimm
;
290 int irq
, irq2
, res
= 0;
291 unsigned long mem_size
, irqflags
= 0;
293 id
= of_match_device(altr_sdram_ctrl_of_match
, &pdev
->dev
);
297 /* Grab the register range from the sdr controller in device tree */
298 mc_vbase
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
300 if (IS_ERR(mc_vbase
)) {
301 edac_printk(KERN_ERR
, EDAC_MC
,
302 "regmap for altr,sdr-syscon lookup failed.\n");
306 /* Check specific dependencies for the module */
307 priv
= of_match_node(altr_sdram_ctrl_of_match
,
308 pdev
->dev
.of_node
)->data
;
310 /* Validate the SDRAM controller has ECC enabled */
311 if (regmap_read(mc_vbase
, priv
->ecc_ctrl_offset
, &read_reg
) ||
312 ((read_reg
& priv
->ecc_ctl_en_mask
) != priv
->ecc_ctl_en_mask
)) {
313 edac_printk(KERN_ERR
, EDAC_MC
,
314 "No ECC/ECC disabled [0x%08X]\n", read_reg
);
318 /* Grab memory size from device tree. */
319 mem_size
= get_total_mem();
321 edac_printk(KERN_ERR
, EDAC_MC
, "Unable to calculate memory size\n");
325 /* Ensure the SDRAM Interrupt is disabled */
326 if (regmap_update_bits(mc_vbase
, priv
->ecc_irq_en_offset
,
327 priv
->ecc_irq_en_mask
, 0)) {
328 edac_printk(KERN_ERR
, EDAC_MC
,
329 "Error disabling SDRAM ECC IRQ\n");
333 /* Toggle to clear the SDRAM Error count */
334 if (regmap_update_bits(mc_vbase
, priv
->ecc_cnt_rst_offset
,
335 priv
->ecc_cnt_rst_mask
,
336 priv
->ecc_cnt_rst_mask
)) {
337 edac_printk(KERN_ERR
, EDAC_MC
,
338 "Error clearing SDRAM ECC count\n");
342 if (regmap_update_bits(mc_vbase
, priv
->ecc_cnt_rst_offset
,
343 priv
->ecc_cnt_rst_mask
, 0)) {
344 edac_printk(KERN_ERR
, EDAC_MC
,
345 "Error clearing SDRAM ECC count\n");
349 irq
= platform_get_irq(pdev
, 0);
351 edac_printk(KERN_ERR
, EDAC_MC
,
352 "No irq %d in DT\n", irq
);
356 /* Arria10 has a 2nd IRQ */
357 irq2
= platform_get_irq(pdev
, 1);
359 layers
[0].type
= EDAC_MC_LAYER_CHIP_SELECT
;
361 layers
[0].is_virt_csrow
= true;
362 layers
[1].type
= EDAC_MC_LAYER_CHANNEL
;
364 layers
[1].is_virt_csrow
= false;
365 mci
= edac_mc_alloc(0, ARRAY_SIZE(layers
), layers
,
366 sizeof(struct altr_sdram_mc_data
));
370 mci
->pdev
= &pdev
->dev
;
371 drvdata
= mci
->pvt_info
;
372 drvdata
->mc_vbase
= mc_vbase
;
373 drvdata
->data
= priv
;
374 platform_set_drvdata(pdev
, mci
);
376 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
)) {
377 edac_printk(KERN_ERR
, EDAC_MC
,
378 "Unable to get managed device resource\n");
383 mci
->mtype_cap
= MEM_FLAG_DDR3
;
384 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
;
385 mci
->edac_cap
= EDAC_FLAG_SECDED
;
386 mci
->mod_name
= EDAC_MOD_STR
;
387 mci
->ctl_name
= dev_name(&pdev
->dev
);
388 mci
->scrub_mode
= SCRUB_SW_SRC
;
389 mci
->dev_name
= dev_name(&pdev
->dev
);
392 dimm
->nr_pages
= ((mem_size
- 1) >> PAGE_SHIFT
) + 1;
394 dimm
->dtype
= DEV_X8
;
395 dimm
->mtype
= MEM_DDR3
;
396 dimm
->edac_mode
= EDAC_SECDED
;
398 res
= edac_mc_add_mc(mci
);
402 /* Only the Arria10 has separate IRQs */
403 if (socfpga_is_a10()) {
404 /* Arria10 specific initialization */
405 res
= a10_init(mc_vbase
);
409 res
= devm_request_irq(&pdev
->dev
, irq2
,
410 altr_sdram_mc_err_handler
,
411 IRQF_SHARED
, dev_name(&pdev
->dev
), mci
);
413 edac_mc_printk(mci
, KERN_ERR
,
414 "Unable to request irq %d\n", irq2
);
419 res
= a10_unmask_irq(pdev
, A10_DDR0_IRQ_MASK
);
423 irqflags
= IRQF_SHARED
;
426 res
= devm_request_irq(&pdev
->dev
, irq
, altr_sdram_mc_err_handler
,
427 irqflags
, dev_name(&pdev
->dev
), mci
);
429 edac_mc_printk(mci
, KERN_ERR
,
430 "Unable to request irq %d\n", irq
);
435 /* Infrastructure ready - enable the IRQ */
436 if (regmap_update_bits(drvdata
->mc_vbase
, priv
->ecc_irq_en_offset
,
437 priv
->ecc_irq_en_mask
, priv
->ecc_irq_en_mask
)) {
438 edac_mc_printk(mci
, KERN_ERR
,
439 "Error enabling SDRAM ECC IRQ\n");
444 altr_sdr_mc_create_debugfs_nodes(mci
);
446 devres_close_group(&pdev
->dev
, NULL
);
451 edac_mc_del_mc(&pdev
->dev
);
453 devres_release_group(&pdev
->dev
, NULL
);
456 edac_printk(KERN_ERR
, EDAC_MC
,
457 "EDAC Probe Failed; Error %d\n", res
);
462 static int altr_sdram_remove(struct platform_device
*pdev
)
464 struct mem_ctl_info
*mci
= platform_get_drvdata(pdev
);
466 edac_mc_del_mc(&pdev
->dev
);
468 platform_set_drvdata(pdev
, NULL
);
474 * If you want to suspend, need to disable EDAC by removing it
475 * from the device tree or defconfig.
478 static int altr_sdram_prepare(struct device
*dev
)
480 pr_err("Suspend not allowed when EDAC is enabled.\n");
485 static const struct dev_pm_ops altr_sdram_pm_ops
= {
486 .prepare
= altr_sdram_prepare
,
490 static struct platform_driver altr_sdram_edac_driver
= {
491 .probe
= altr_sdram_probe
,
492 .remove
= altr_sdram_remove
,
494 .name
= "altr_sdram_edac",
496 .pm
= &altr_sdram_pm_ops
,
498 .of_match_table
= altr_sdram_ctrl_of_match
,
502 module_platform_driver(altr_sdram_edac_driver
);
504 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
506 /**************** Stratix 10 EDAC Memory Controller Functions ************/
509 * s10_protected_reg_write
510 * Write to a protected SMC register.
511 * @context: Not used.
512 * @reg: Address of register
513 * @value: Value to write
514 * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
515 * INTEL_SIP_SMC_REG_ERROR on error
516 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
518 static int s10_protected_reg_write(void *context
, unsigned int reg
,
521 struct arm_smccc_res result
;
522 unsigned long offset
= (unsigned long)context
;
524 arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE
, offset
+ reg
, val
, 0, 0,
527 return (int)result
.a0
;
531 * s10_protected_reg_read
532 * Read the status of a protected SMC register
533 * @context: Not used.
534 * @reg: Address of register
535 * @value: Value read.
536 * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
537 * INTEL_SIP_SMC_REG_ERROR on error
538 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
540 static int s10_protected_reg_read(void *context
, unsigned int reg
,
543 struct arm_smccc_res result
;
544 unsigned long offset
= (unsigned long)context
;
546 arm_smccc_smc(INTEL_SIP_SMC_REG_READ
, offset
+ reg
, 0, 0, 0,
549 *val
= (unsigned int)result
.a1
;
551 return (int)result
.a0
;
554 static const struct regmap_config s10_sdram_regmap_cfg
= {
559 .max_register
= 0xffd12228,
560 .reg_read
= s10_protected_reg_read
,
561 .reg_write
= s10_protected_reg_write
,
562 .use_single_read
= true,
563 .use_single_write
= true,
566 /************** </Stratix10 EDAC Memory Controller Functions> ***********/
568 /************************* EDAC Parent Probe *************************/
570 static const struct of_device_id altr_edac_device_of_match
[];
572 static const struct of_device_id altr_edac_of_match
[] = {
573 { .compatible
= "altr,socfpga-ecc-manager" },
576 MODULE_DEVICE_TABLE(of
, altr_edac_of_match
);
578 static int altr_edac_probe(struct platform_device
*pdev
)
580 of_platform_populate(pdev
->dev
.of_node
, altr_edac_device_of_match
,
585 static struct platform_driver altr_edac_driver
= {
586 .probe
= altr_edac_probe
,
588 .name
= "socfpga_ecc_manager",
589 .of_match_table
= altr_edac_of_match
,
592 module_platform_driver(altr_edac_driver
);
594 /************************* EDAC Device Functions *************************/
597 * EDAC Device Functions (shared between various IPs).
598 * The discrete memories use the EDAC Device framework. The probe
599 * and error handling functions are very similar between memories
600 * so they are shared. The memory allocation and freeing for EDAC
601 * trigger testing are different for each memory.
604 static const struct edac_device_prv_data ocramecc_data
;
605 static const struct edac_device_prv_data l2ecc_data
;
606 static const struct edac_device_prv_data a10_ocramecc_data
;
607 static const struct edac_device_prv_data a10_l2ecc_data
;
609 static irqreturn_t
altr_edac_device_handler(int irq
, void *dev_id
)
611 irqreturn_t ret_value
= IRQ_NONE
;
612 struct edac_device_ctl_info
*dci
= dev_id
;
613 struct altr_edac_device_dev
*drvdata
= dci
->pvt_info
;
614 const struct edac_device_prv_data
*priv
= drvdata
->data
;
616 if (irq
== drvdata
->sb_irq
) {
617 if (priv
->ce_clear_mask
)
618 writel(priv
->ce_clear_mask
, drvdata
->base
);
619 edac_device_handle_ce(dci
, 0, 0, drvdata
->edac_dev_name
);
620 ret_value
= IRQ_HANDLED
;
621 } else if (irq
== drvdata
->db_irq
) {
622 if (priv
->ue_clear_mask
)
623 writel(priv
->ue_clear_mask
, drvdata
->base
);
624 edac_device_handle_ue(dci
, 0, 0, drvdata
->edac_dev_name
);
625 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
626 ret_value
= IRQ_HANDLED
;
634 static ssize_t
altr_edac_device_trig(struct file
*file
,
635 const char __user
*user_buf
,
636 size_t count
, loff_t
*ppos
)
639 u32
*ptemp
, i
, error_mask
;
643 struct edac_device_ctl_info
*edac_dci
= file
->private_data
;
644 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
645 const struct edac_device_prv_data
*priv
= drvdata
->data
;
646 void *generic_ptr
= edac_dci
->dev
;
648 if (!user_buf
|| get_user(trig_type
, user_buf
))
651 if (!priv
->alloc_mem
)
655 * Note that generic_ptr is initialized to the device * but in
656 * some alloc_functions, this is overridden and returns data.
658 ptemp
= priv
->alloc_mem(priv
->trig_alloc_sz
, &generic_ptr
);
660 edac_printk(KERN_ERR
, EDAC_DEVICE
,
661 "Inject: Buffer Allocation error\n");
665 if (trig_type
== ALTR_UE_TRIGGER_CHAR
)
666 error_mask
= priv
->ue_set_mask
;
668 error_mask
= priv
->ce_set_mask
;
670 edac_printk(KERN_ALERT
, EDAC_DEVICE
,
671 "Trigger Error Mask (0x%X)\n", error_mask
);
673 local_irq_save(flags
);
674 /* write ECC corrupted data out. */
675 for (i
= 0; i
< (priv
->trig_alloc_sz
/ sizeof(*ptemp
)); i
++) {
676 /* Read data so we're in the correct state */
678 if (READ_ONCE(ptemp
[i
]))
680 /* Toggle Error bit (it is latched), leave ECC enabled */
681 writel(error_mask
, (drvdata
->base
+ priv
->set_err_ofst
));
682 writel(priv
->ecc_enable_mask
, (drvdata
->base
+
683 priv
->set_err_ofst
));
686 /* Ensure it has been written out */
688 local_irq_restore(flags
);
691 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Mem Not Cleared\n");
693 /* Read out written data. ECC error caused here */
694 for (i
= 0; i
< ALTR_TRIGGER_READ_WRD_CNT
; i
++)
695 if (READ_ONCE(ptemp
[i
]) != i
)
696 edac_printk(KERN_ERR
, EDAC_DEVICE
,
697 "Read doesn't match written data\n");
700 priv
->free_mem(ptemp
, priv
->trig_alloc_sz
, generic_ptr
);
705 static const struct file_operations altr_edac_device_inject_fops
= {
707 .write
= altr_edac_device_trig
,
708 .llseek
= generic_file_llseek
,
711 static ssize_t
altr_edac_a10_device_trig(struct file
*file
,
712 const char __user
*user_buf
,
713 size_t count
, loff_t
*ppos
);
715 static const struct file_operations altr_edac_a10_device_inject_fops
= {
717 .write
= altr_edac_a10_device_trig
,
718 .llseek
= generic_file_llseek
,
721 static ssize_t
altr_edac_a10_device_trig2(struct file
*file
,
722 const char __user
*user_buf
,
723 size_t count
, loff_t
*ppos
);
725 static const struct file_operations altr_edac_a10_device_inject2_fops
= {
727 .write
= altr_edac_a10_device_trig2
,
728 .llseek
= generic_file_llseek
,
731 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info
*edac_dci
,
732 const struct edac_device_prv_data
*priv
)
734 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
736 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
739 drvdata
->debugfs_dir
= edac_debugfs_create_dir(drvdata
->edac_dev_name
);
740 if (!drvdata
->debugfs_dir
)
743 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR
,
744 drvdata
->debugfs_dir
, edac_dci
,
746 debugfs_remove_recursive(drvdata
->debugfs_dir
);
749 static const struct of_device_id altr_edac_device_of_match
[] = {
750 #ifdef CONFIG_EDAC_ALTERA_L2C
751 { .compatible
= "altr,socfpga-l2-ecc", .data
= &l2ecc_data
},
753 #ifdef CONFIG_EDAC_ALTERA_OCRAM
754 { .compatible
= "altr,socfpga-ocram-ecc", .data
= &ocramecc_data
},
758 MODULE_DEVICE_TABLE(of
, altr_edac_device_of_match
);
761 * altr_edac_device_probe()
762 * This is a generic EDAC device driver that will support
763 * various Altera memory devices such as the L2 cache ECC and
764 * OCRAM ECC as well as the memories for other peripherals.
765 * Module specific initialization is done by passing the
766 * function index in the device tree.
768 static int altr_edac_device_probe(struct platform_device
*pdev
)
770 struct edac_device_ctl_info
*dci
;
771 struct altr_edac_device_dev
*drvdata
;
774 struct device_node
*np
= pdev
->dev
.of_node
;
775 char *ecc_name
= (char *)np
->name
;
776 static int dev_instance
;
778 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
)) {
779 edac_printk(KERN_ERR
, EDAC_DEVICE
,
780 "Unable to open devm\n");
784 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
786 edac_printk(KERN_ERR
, EDAC_DEVICE
,
787 "Unable to get mem resource\n");
792 if (!devm_request_mem_region(&pdev
->dev
, r
->start
, resource_size(r
),
793 dev_name(&pdev
->dev
))) {
794 edac_printk(KERN_ERR
, EDAC_DEVICE
,
795 "%s:Error requesting mem region\n", ecc_name
);
800 dci
= edac_device_alloc_ctl_info(sizeof(*drvdata
), ecc_name
,
801 1, ecc_name
, 1, 0, NULL
, 0,
805 edac_printk(KERN_ERR
, EDAC_DEVICE
,
806 "%s: Unable to allocate EDAC device\n", ecc_name
);
811 drvdata
= dci
->pvt_info
;
812 dci
->dev
= &pdev
->dev
;
813 platform_set_drvdata(pdev
, dci
);
814 drvdata
->edac_dev_name
= ecc_name
;
816 drvdata
->base
= devm_ioremap(&pdev
->dev
, r
->start
, resource_size(r
));
817 if (!drvdata
->base
) {
822 /* Get driver specific data for this EDAC device */
823 drvdata
->data
= of_match_node(altr_edac_device_of_match
, np
)->data
;
825 /* Check specific dependencies for the module */
826 if (drvdata
->data
->setup
) {
827 res
= drvdata
->data
->setup(drvdata
);
832 drvdata
->sb_irq
= platform_get_irq(pdev
, 0);
833 res
= devm_request_irq(&pdev
->dev
, drvdata
->sb_irq
,
834 altr_edac_device_handler
,
835 0, dev_name(&pdev
->dev
), dci
);
839 drvdata
->db_irq
= platform_get_irq(pdev
, 1);
840 res
= devm_request_irq(&pdev
->dev
, drvdata
->db_irq
,
841 altr_edac_device_handler
,
842 0, dev_name(&pdev
->dev
), dci
);
846 dci
->mod_name
= "Altera ECC Manager";
847 dci
->dev_name
= drvdata
->edac_dev_name
;
849 res
= edac_device_add_device(dci
);
853 altr_create_edacdev_dbgfs(dci
, drvdata
->data
);
855 devres_close_group(&pdev
->dev
, NULL
);
860 edac_device_free_ctl_info(dci
);
862 devres_release_group(&pdev
->dev
, NULL
);
863 edac_printk(KERN_ERR
, EDAC_DEVICE
,
864 "%s:Error setting up EDAC device: %d\n", ecc_name
, res
);
869 static int altr_edac_device_remove(struct platform_device
*pdev
)
871 struct edac_device_ctl_info
*dci
= platform_get_drvdata(pdev
);
872 struct altr_edac_device_dev
*drvdata
= dci
->pvt_info
;
874 debugfs_remove_recursive(drvdata
->debugfs_dir
);
875 edac_device_del_device(&pdev
->dev
);
876 edac_device_free_ctl_info(dci
);
881 static struct platform_driver altr_edac_device_driver
= {
882 .probe
= altr_edac_device_probe
,
883 .remove
= altr_edac_device_remove
,
885 .name
= "altr_edac_device",
886 .of_match_table
= altr_edac_device_of_match
,
889 module_platform_driver(altr_edac_device_driver
);
891 /******************* Arria10 Device ECC Shared Functions *****************/
894 * Test for memory's ECC dependencies upon entry because platform specific
895 * startup should have initialized the memory and enabled the ECC.
896 * Can't turn on ECC here because accessing un-initialized memory will
897 * cause CE/UE errors possibly causing an ABORT.
899 static int __maybe_unused
900 altr_check_ecc_deps(struct altr_edac_device_dev
*device
)
902 void __iomem
*base
= device
->base
;
903 const struct edac_device_prv_data
*prv
= device
->data
;
905 if (readl(base
+ prv
->ecc_en_ofst
) & prv
->ecc_enable_mask
)
908 edac_printk(KERN_ERR
, EDAC_DEVICE
,
909 "%s: No ECC present or ECC disabled.\n",
910 device
->edac_dev_name
);
914 static irqreturn_t __maybe_unused
altr_edac_a10_ecc_irq(int irq
, void *dev_id
)
916 struct altr_edac_device_dev
*dci
= dev_id
;
917 void __iomem
*base
= dci
->base
;
919 if (irq
== dci
->sb_irq
) {
920 writel(ALTR_A10_ECC_SERRPENA
,
921 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
922 edac_device_handle_ce(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
925 } else if (irq
== dci
->db_irq
) {
926 writel(ALTR_A10_ECC_DERRPENA
,
927 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
928 edac_device_handle_ue(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
929 if (dci
->data
->panic
)
930 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
940 /******************* Arria10 Memory Buffer Functions *********************/
942 static inline int a10_get_irq_mask(struct device_node
*np
)
945 const u32
*handle
= of_get_property(np
, "interrupts", NULL
);
949 irq
= be32_to_cpup(handle
);
953 static inline void ecc_set_bits(u32 bit_mask
, void __iomem
*ioaddr
)
955 u32 value
= readl(ioaddr
);
958 writel(value
, ioaddr
);
961 static inline void ecc_clear_bits(u32 bit_mask
, void __iomem
*ioaddr
)
963 u32 value
= readl(ioaddr
);
966 writel(value
, ioaddr
);
969 static inline int ecc_test_bits(u32 bit_mask
, void __iomem
*ioaddr
)
971 u32 value
= readl(ioaddr
);
973 return (value
& bit_mask
) ? 1 : 0;
977 * This function uses the memory initialization block in the Arria10 ECC
978 * controller to initialize/clear the entire memory data and ECC data.
980 static int __maybe_unused
altr_init_memory_port(void __iomem
*ioaddr
, int port
)
982 int limit
= ALTR_A10_ECC_INIT_WATCHDOG_10US
;
983 u32 init_mask
, stat_mask
, clear_mask
;
987 init_mask
= ALTR_A10_ECC_INITB
;
988 stat_mask
= ALTR_A10_ECC_INITCOMPLETEB
;
989 clear_mask
= ALTR_A10_ECC_ERRPENB_MASK
;
991 init_mask
= ALTR_A10_ECC_INITA
;
992 stat_mask
= ALTR_A10_ECC_INITCOMPLETEA
;
993 clear_mask
= ALTR_A10_ECC_ERRPENA_MASK
;
996 ecc_set_bits(init_mask
, (ioaddr
+ ALTR_A10_ECC_CTRL_OFST
));
998 if (ecc_test_bits(stat_mask
,
999 (ioaddr
+ ALTR_A10_ECC_INITSTAT_OFST
)))
1006 /* Clear any pending ECC interrupts */
1007 writel(clear_mask
, (ioaddr
+ ALTR_A10_ECC_INTSTAT_OFST
));
1012 static int socfpga_is_a10(void)
1014 return of_machine_is_compatible("altr,socfpga-arria10");
1017 static int socfpga_is_s10(void)
1019 return of_machine_is_compatible("altr,socfpga-stratix10");
1022 static __init
int __maybe_unused
1023 altr_init_a10_ecc_block(struct device_node
*np
, u32 irq_mask
,
1024 u32 ecc_ctrl_en_mask
, bool dual_port
)
1027 void __iomem
*ecc_block_base
;
1028 struct regmap
*ecc_mgr_map
;
1030 struct device_node
*np_eccmgr
;
1032 ecc_name
= (char *)np
->name
;
1034 /* Get the ECC Manager - parent of the device EDACs */
1035 np_eccmgr
= of_get_parent(np
);
1037 if (socfpga_is_a10()) {
1038 ecc_mgr_map
= syscon_regmap_lookup_by_phandle(np_eccmgr
,
1039 "altr,sysmgr-syscon");
1041 struct device_node
*sysmgr_np
;
1042 struct resource res
;
1045 sysmgr_np
= of_parse_phandle(np_eccmgr
,
1046 "altr,sysmgr-syscon", 0);
1048 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1049 "Unable to find altr,sysmgr-syscon\n");
1053 if (of_address_to_resource(sysmgr_np
, 0, &res
)) {
1054 of_node_put(sysmgr_np
);
1058 /* Need physical address for SMCC call */
1061 ecc_mgr_map
= regmap_init(NULL
, NULL
, (void *)base
,
1062 &s10_sdram_regmap_cfg
);
1063 of_node_put(sysmgr_np
);
1065 of_node_put(np_eccmgr
);
1066 if (IS_ERR(ecc_mgr_map
)) {
1067 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1068 "Unable to get syscon altr,sysmgr-syscon\n");
1072 /* Map the ECC Block */
1073 ecc_block_base
= of_iomap(np
, 0);
1074 if (!ecc_block_base
) {
1075 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1076 "Unable to map %s ECC block\n", ecc_name
);
1081 regmap_write(ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_SET_OFST
, irq_mask
);
1082 writel(ALTR_A10_ECC_SERRINTEN
,
1083 (ecc_block_base
+ ALTR_A10_ECC_ERRINTENR_OFST
));
1084 ecc_clear_bits(ecc_ctrl_en_mask
,
1085 (ecc_block_base
+ ALTR_A10_ECC_CTRL_OFST
));
1086 /* Ensure all writes complete */
1088 /* Use HW initialization block to initialize memory for ECC */
1089 ret
= altr_init_memory_port(ecc_block_base
, 0);
1091 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1092 "ECC: cannot init %s PORTA memory\n", ecc_name
);
1097 ret
= altr_init_memory_port(ecc_block_base
, 1);
1099 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1100 "ECC: cannot init %s PORTB memory\n",
1106 /* Interrupt mode set to every SBERR */
1107 regmap_write(ecc_mgr_map
, ALTR_A10_ECC_INTMODE_OFST
,
1108 ALTR_A10_ECC_INTMODE
);
1110 ecc_set_bits(ecc_ctrl_en_mask
, (ecc_block_base
+
1111 ALTR_A10_ECC_CTRL_OFST
));
1112 writel(ALTR_A10_ECC_SERRINTEN
,
1113 (ecc_block_base
+ ALTR_A10_ECC_ERRINTENS_OFST
));
1114 regmap_write(ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_CLR_OFST
, irq_mask
);
1115 /* Ensure all writes complete */
1118 iounmap(ecc_block_base
);
1122 static int validate_parent_available(struct device_node
*np
);
1123 static const struct of_device_id altr_edac_a10_device_of_match
[];
1124 static int __init __maybe_unused
altr_init_a10_ecc_device_type(char *compat
)
1127 struct device_node
*child
, *np
;
1129 if (!socfpga_is_a10() && !socfpga_is_s10())
1132 np
= of_find_compatible_node(NULL
, NULL
,
1133 "altr,socfpga-a10-ecc-manager");
1135 edac_printk(KERN_ERR
, EDAC_DEVICE
, "ECC Manager not found\n");
1139 for_each_child_of_node(np
, child
) {
1140 const struct of_device_id
*pdev_id
;
1141 const struct edac_device_prv_data
*prv
;
1143 if (!of_device_is_available(child
))
1145 if (!of_device_is_compatible(child
, compat
))
1148 if (validate_parent_available(child
))
1151 irq
= a10_get_irq_mask(child
);
1155 /* Get matching node and check for valid result */
1156 pdev_id
= of_match_node(altr_edac_a10_device_of_match
, child
);
1157 if (IS_ERR_OR_NULL(pdev_id
))
1160 /* Validate private data pointer before dereferencing */
1161 prv
= pdev_id
->data
;
1165 altr_init_a10_ecc_block(child
, BIT(irq
),
1166 prv
->ecc_enable_mask
, 0);
1173 /*********************** OCRAM EDAC Device Functions *********************/
1175 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1177 static void *ocram_alloc_mem(size_t size
, void **other
)
1179 struct device_node
*np
;
1180 struct gen_pool
*gp
;
1183 np
= of_find_compatible_node(NULL
, NULL
, "altr,socfpga-ocram-ecc");
1187 gp
= of_gen_pool_get(np
, "iram", 0);
1192 sram_addr
= (void *)gen_pool_alloc(gp
, size
);
1196 memset(sram_addr
, 0, size
);
1197 /* Ensure data is written out */
1200 /* Remember this handle for freeing later */
1206 static void ocram_free_mem(void *p
, size_t size
, void *other
)
1208 gen_pool_free((struct gen_pool
*)other
, (unsigned long)p
, size
);
1211 static const struct edac_device_prv_data ocramecc_data
= {
1212 .setup
= altr_check_ecc_deps
,
1213 .ce_clear_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_SERR
),
1214 .ue_clear_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_DERR
),
1215 .alloc_mem
= ocram_alloc_mem
,
1216 .free_mem
= ocram_free_mem
,
1217 .ecc_enable_mask
= ALTR_OCR_ECC_EN
,
1218 .ecc_en_ofst
= ALTR_OCR_ECC_REG_OFFSET
,
1219 .ce_set_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_INJS
),
1220 .ue_set_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_INJD
),
1221 .set_err_ofst
= ALTR_OCR_ECC_REG_OFFSET
,
1222 .trig_alloc_sz
= ALTR_TRIG_OCRAM_BYTE_SIZE
,
1223 .inject_fops
= &altr_edac_device_inject_fops
,
1226 static int __maybe_unused
1227 altr_check_ocram_deps_init(struct altr_edac_device_dev
*device
)
1229 void __iomem
*base
= device
->base
;
1232 ret
= altr_check_ecc_deps(device
);
1236 /* Verify OCRAM has been initialized */
1237 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA
,
1238 (base
+ ALTR_A10_ECC_INITSTAT_OFST
)))
1241 /* Enable IRQ on Single Bit Error */
1242 writel(ALTR_A10_ECC_SERRINTEN
, (base
+ ALTR_A10_ECC_ERRINTENS_OFST
));
1243 /* Ensure all writes complete */
1249 static const struct edac_device_prv_data a10_ocramecc_data
= {
1250 .setup
= altr_check_ocram_deps_init
,
1251 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1252 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1253 .irq_status_mask
= A10_SYSMGR_ECC_INTSTAT_OCRAM
,
1254 .ecc_enable_mask
= ALTR_A10_OCRAM_ECC_EN_CTL
,
1255 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1256 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1257 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1258 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1259 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1260 .inject_fops
= &altr_edac_a10_device_inject2_fops
,
1262 * OCRAM panic on uncorrectable error because sleep/resume
1263 * functions and FPGA contents are stored in OCRAM. Prefer
1264 * a kernel panic over executing/loading corrupted data.
1269 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
1271 /********************* L2 Cache EDAC Device Functions ********************/
1273 #ifdef CONFIG_EDAC_ALTERA_L2C
1275 static void *l2_alloc_mem(size_t size
, void **other
)
1277 struct device
*dev
= *other
;
1278 void *ptemp
= devm_kzalloc(dev
, size
, GFP_KERNEL
);
1283 /* Make sure everything is written out */
1287 * Clean all cache levels up to LoC (includes L2)
1288 * This ensures the corrupted data is written into
1289 * L2 cache for readback test (which causes ECC error).
1296 static void l2_free_mem(void *p
, size_t size
, void *other
)
1298 struct device
*dev
= other
;
1305 * altr_l2_check_deps()
1306 * Test for L2 cache ECC dependencies upon entry because
1307 * platform specific startup should have initialized the L2
1308 * memory and enabled the ECC.
1309 * Bail if ECC is not enabled.
1310 * Note that L2 Cache Enable is forced at build time.
1312 static int altr_l2_check_deps(struct altr_edac_device_dev
*device
)
1314 void __iomem
*base
= device
->base
;
1315 const struct edac_device_prv_data
*prv
= device
->data
;
1317 if ((readl(base
) & prv
->ecc_enable_mask
) ==
1318 prv
->ecc_enable_mask
)
1321 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1322 "L2: No ECC present, or ECC disabled\n");
1326 static irqreturn_t
altr_edac_a10_l2_irq(int irq
, void *dev_id
)
1328 struct altr_edac_device_dev
*dci
= dev_id
;
1330 if (irq
== dci
->sb_irq
) {
1331 regmap_write(dci
->edac
->ecc_mgr_map
,
1332 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST
,
1333 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB
);
1334 edac_device_handle_ce(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
1337 } else if (irq
== dci
->db_irq
) {
1338 regmap_write(dci
->edac
->ecc_mgr_map
,
1339 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST
,
1340 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB
);
1341 edac_device_handle_ue(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
1342 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1352 static const struct edac_device_prv_data l2ecc_data
= {
1353 .setup
= altr_l2_check_deps
,
1356 .alloc_mem
= l2_alloc_mem
,
1357 .free_mem
= l2_free_mem
,
1358 .ecc_enable_mask
= ALTR_L2_ECC_EN
,
1359 .ce_set_mask
= (ALTR_L2_ECC_EN
| ALTR_L2_ECC_INJS
),
1360 .ue_set_mask
= (ALTR_L2_ECC_EN
| ALTR_L2_ECC_INJD
),
1361 .set_err_ofst
= ALTR_L2_ECC_REG_OFFSET
,
1362 .trig_alloc_sz
= ALTR_TRIG_L2C_BYTE_SIZE
,
1363 .inject_fops
= &altr_edac_device_inject_fops
,
1366 static const struct edac_device_prv_data a10_l2ecc_data
= {
1367 .setup
= altr_l2_check_deps
,
1368 .ce_clear_mask
= ALTR_A10_L2_ECC_SERR_CLR
,
1369 .ue_clear_mask
= ALTR_A10_L2_ECC_MERR_CLR
,
1370 .irq_status_mask
= A10_SYSMGR_ECC_INTSTAT_L2
,
1371 .alloc_mem
= l2_alloc_mem
,
1372 .free_mem
= l2_free_mem
,
1373 .ecc_enable_mask
= ALTR_A10_L2_ECC_EN_CTL
,
1374 .ce_set_mask
= ALTR_A10_L2_ECC_CE_INJ_MASK
,
1375 .ue_set_mask
= ALTR_A10_L2_ECC_UE_INJ_MASK
,
1376 .set_err_ofst
= ALTR_A10_L2_ECC_INJ_OFST
,
1377 .ecc_irq_handler
= altr_edac_a10_l2_irq
,
1378 .trig_alloc_sz
= ALTR_TRIG_L2C_BYTE_SIZE
,
1379 .inject_fops
= &altr_edac_device_inject_fops
,
1382 #endif /* CONFIG_EDAC_ALTERA_L2C */
1384 /********************* Ethernet Device Functions ********************/
1386 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1388 static int __init
socfpga_init_ethernet_ecc(struct altr_edac_device_dev
*dev
)
1392 ret
= altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1396 return altr_check_ecc_deps(dev
);
1399 static const struct edac_device_prv_data a10_enetecc_data
= {
1400 .setup
= socfpga_init_ethernet_ecc
,
1401 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1402 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1403 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1404 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1405 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1406 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1407 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1408 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1409 .inject_fops
= &altr_edac_a10_device_inject2_fops
,
1412 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1414 /********************** NAND Device Functions **********************/
1416 #ifdef CONFIG_EDAC_ALTERA_NAND
1418 static int __init
socfpga_init_nand_ecc(struct altr_edac_device_dev
*device
)
1422 ret
= altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1426 return altr_check_ecc_deps(device
);
1429 static const struct edac_device_prv_data a10_nandecc_data
= {
1430 .setup
= socfpga_init_nand_ecc
,
1431 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1432 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1433 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1434 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1435 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1436 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1437 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1438 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1439 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1442 #endif /* CONFIG_EDAC_ALTERA_NAND */
1444 /********************** DMA Device Functions **********************/
1446 #ifdef CONFIG_EDAC_ALTERA_DMA
1448 static int __init
socfpga_init_dma_ecc(struct altr_edac_device_dev
*device
)
1452 ret
= altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1456 return altr_check_ecc_deps(device
);
1459 static const struct edac_device_prv_data a10_dmaecc_data
= {
1460 .setup
= socfpga_init_dma_ecc
,
1461 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1462 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1463 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1464 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1465 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1466 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1467 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1468 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1469 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1472 #endif /* CONFIG_EDAC_ALTERA_DMA */
1474 /********************** USB Device Functions **********************/
1476 #ifdef CONFIG_EDAC_ALTERA_USB
1478 static int __init
socfpga_init_usb_ecc(struct altr_edac_device_dev
*device
)
1482 ret
= altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1486 return altr_check_ecc_deps(device
);
1489 static const struct edac_device_prv_data a10_usbecc_data
= {
1490 .setup
= socfpga_init_usb_ecc
,
1491 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1492 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1493 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1494 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1495 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1496 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1497 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1498 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1499 .inject_fops
= &altr_edac_a10_device_inject2_fops
,
1502 #endif /* CONFIG_EDAC_ALTERA_USB */
1504 /********************** QSPI Device Functions **********************/
1506 #ifdef CONFIG_EDAC_ALTERA_QSPI
1508 static int __init
socfpga_init_qspi_ecc(struct altr_edac_device_dev
*device
)
1512 ret
= altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1516 return altr_check_ecc_deps(device
);
1519 static const struct edac_device_prv_data a10_qspiecc_data
= {
1520 .setup
= socfpga_init_qspi_ecc
,
1521 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1522 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1523 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1524 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1525 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
1526 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
1527 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1528 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1529 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1532 #endif /* CONFIG_EDAC_ALTERA_QSPI */
1534 /********************* SDMMC Device Functions **********************/
1536 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1538 static const struct edac_device_prv_data a10_sdmmceccb_data
;
1539 static int altr_portb_setup(struct altr_edac_device_dev
*device
)
1541 struct edac_device_ctl_info
*dci
;
1542 struct altr_edac_device_dev
*altdev
;
1543 char *ecc_name
= "sdmmcb-ecc";
1545 struct device_node
*np
;
1546 const struct edac_device_prv_data
*prv
= &a10_sdmmceccb_data
;
1548 rc
= altr_check_ecc_deps(device
);
1552 np
= of_find_compatible_node(NULL
, NULL
, "altr,socfpga-sdmmc-ecc");
1554 edac_printk(KERN_WARNING
, EDAC_DEVICE
, "SDMMC node not found\n");
1558 /* Create the PortB EDAC device */
1559 edac_idx
= edac_device_alloc_index();
1560 dci
= edac_device_alloc_ctl_info(sizeof(*altdev
), ecc_name
, 1,
1561 ecc_name
, 1, 0, NULL
, 0, edac_idx
);
1563 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1564 "%s: Unable to allocate PortB EDAC device\n",
1569 /* Initialize the PortB EDAC device structure from PortA structure */
1570 altdev
= dci
->pvt_info
;
1573 if (!devres_open_group(&altdev
->ddev
, altr_portb_setup
, GFP_KERNEL
))
1576 /* Update PortB specific values */
1577 altdev
->edac_dev_name
= ecc_name
;
1578 altdev
->edac_idx
= edac_idx
;
1579 altdev
->edac_dev
= dci
;
1581 dci
->dev
= &altdev
->ddev
;
1582 dci
->ctl_name
= "Altera ECC Manager";
1583 dci
->mod_name
= ecc_name
;
1584 dci
->dev_name
= ecc_name
;
1586 /* Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly */
1587 #ifdef CONFIG_ARCH_STRATIX10
1588 altdev
->sb_irq
= irq_of_parse_and_map(np
, 1);
1590 altdev
->sb_irq
= irq_of_parse_and_map(np
, 2);
1592 if (!altdev
->sb_irq
) {
1593 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error PortB SBIRQ alloc\n");
1595 goto err_release_group_1
;
1597 rc
= devm_request_irq(&altdev
->ddev
, altdev
->sb_irq
,
1598 prv
->ecc_irq_handler
,
1599 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1602 edac_printk(KERN_ERR
, EDAC_DEVICE
, "PortB SBERR IRQ error\n");
1603 goto err_release_group_1
;
1606 #ifdef CONFIG_ARCH_STRATIX10
1607 /* Use IRQ to determine SError origin instead of assigning IRQ */
1608 rc
= of_property_read_u32_index(np
, "interrupts", 1, &altdev
->db_irq
);
1610 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1611 "Error PortB DBIRQ alloc\n");
1612 goto err_release_group_1
;
1615 altdev
->db_irq
= irq_of_parse_and_map(np
, 3);
1616 if (!altdev
->db_irq
) {
1617 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error PortB DBIRQ alloc\n");
1619 goto err_release_group_1
;
1621 rc
= devm_request_irq(&altdev
->ddev
, altdev
->db_irq
,
1622 prv
->ecc_irq_handler
,
1623 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1626 edac_printk(KERN_ERR
, EDAC_DEVICE
, "PortB DBERR IRQ error\n");
1627 goto err_release_group_1
;
1631 rc
= edac_device_add_device(dci
);
1633 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1634 "edac_device_add_device portB failed\n");
1636 goto err_release_group_1
;
1638 altr_create_edacdev_dbgfs(dci
, prv
);
1640 list_add(&altdev
->next
, &altdev
->edac
->a10_ecc_devices
);
1642 devres_remove_group(&altdev
->ddev
, altr_portb_setup
);
1646 err_release_group_1
:
1647 edac_device_free_ctl_info(dci
);
1648 devres_release_group(&altdev
->ddev
, altr_portb_setup
);
1649 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1650 "%s:Error setting up EDAC device: %d\n", ecc_name
, rc
);
1654 static int __init
socfpga_init_sdmmc_ecc(struct altr_edac_device_dev
*device
)
1657 struct device_node
*child
;
1659 child
= of_find_compatible_node(NULL
, NULL
, "altr,socfpga-sdmmc-ecc");
1663 if (!of_device_is_available(child
))
1666 if (validate_parent_available(child
))
1670 rc
= altr_init_a10_ecc_block(child
, ALTR_A10_SDMMC_IRQ_MASK
,
1671 a10_sdmmceccb_data
.ecc_enable_mask
, 1);
1676 return altr_portb_setup(device
);
1683 static irqreturn_t
altr_edac_a10_ecc_irq_portb(int irq
, void *dev_id
)
1685 struct altr_edac_device_dev
*ad
= dev_id
;
1686 void __iomem
*base
= ad
->base
;
1687 const struct edac_device_prv_data
*priv
= ad
->data
;
1689 if (irq
== ad
->sb_irq
) {
1690 writel(priv
->ce_clear_mask
,
1691 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
1692 edac_device_handle_ce(ad
->edac_dev
, 0, 0, ad
->edac_dev_name
);
1694 } else if (irq
== ad
->db_irq
) {
1695 writel(priv
->ue_clear_mask
,
1696 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
1697 edac_device_handle_ue(ad
->edac_dev
, 0, 0, ad
->edac_dev_name
);
1701 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq
);
1706 static const struct edac_device_prv_data a10_sdmmcecca_data
= {
1707 .setup
= socfpga_init_sdmmc_ecc
,
1708 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
1709 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
1710 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1711 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1712 .ce_set_mask
= ALTR_A10_ECC_SERRPENA
,
1713 .ue_set_mask
= ALTR_A10_ECC_DERRPENA
,
1714 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1715 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
1716 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1719 static const struct edac_device_prv_data a10_sdmmceccb_data
= {
1720 .setup
= socfpga_init_sdmmc_ecc
,
1721 .ce_clear_mask
= ALTR_A10_ECC_SERRPENB
,
1722 .ue_clear_mask
= ALTR_A10_ECC_DERRPENB
,
1723 .ecc_enable_mask
= ALTR_A10_COMMON_ECC_EN_CTL
,
1724 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
1725 .ce_set_mask
= ALTR_A10_ECC_TSERRB
,
1726 .ue_set_mask
= ALTR_A10_ECC_TDERRB
,
1727 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
1728 .ecc_irq_handler
= altr_edac_a10_ecc_irq_portb
,
1729 .inject_fops
= &altr_edac_a10_device_inject_fops
,
1732 #endif /* CONFIG_EDAC_ALTERA_SDMMC */
1734 /********************* Arria10 EDAC Device Functions *************************/
1735 static const struct of_device_id altr_edac_a10_device_of_match
[] = {
1736 #ifdef CONFIG_EDAC_ALTERA_L2C
1737 { .compatible
= "altr,socfpga-a10-l2-ecc", .data
= &a10_l2ecc_data
},
1739 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1740 { .compatible
= "altr,socfpga-a10-ocram-ecc",
1741 .data
= &a10_ocramecc_data
},
1743 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1744 { .compatible
= "altr,socfpga-eth-mac-ecc",
1745 .data
= &a10_enetecc_data
},
1747 #ifdef CONFIG_EDAC_ALTERA_NAND
1748 { .compatible
= "altr,socfpga-nand-ecc", .data
= &a10_nandecc_data
},
1750 #ifdef CONFIG_EDAC_ALTERA_DMA
1751 { .compatible
= "altr,socfpga-dma-ecc", .data
= &a10_dmaecc_data
},
1753 #ifdef CONFIG_EDAC_ALTERA_USB
1754 { .compatible
= "altr,socfpga-usb-ecc", .data
= &a10_usbecc_data
},
1756 #ifdef CONFIG_EDAC_ALTERA_QSPI
1757 { .compatible
= "altr,socfpga-qspi-ecc", .data
= &a10_qspiecc_data
},
1759 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1760 { .compatible
= "altr,socfpga-sdmmc-ecc", .data
= &a10_sdmmcecca_data
},
1764 MODULE_DEVICE_TABLE(of
, altr_edac_a10_device_of_match
);
1767 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1768 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1769 * manager manages the IRQs and the children.
1770 * Based on xgene_edac.c peripheral code.
1773 static ssize_t
altr_edac_a10_device_trig(struct file
*file
,
1774 const char __user
*user_buf
,
1775 size_t count
, loff_t
*ppos
)
1777 struct edac_device_ctl_info
*edac_dci
= file
->private_data
;
1778 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
1779 const struct edac_device_prv_data
*priv
= drvdata
->data
;
1780 void __iomem
*set_addr
= (drvdata
->base
+ priv
->set_err_ofst
);
1781 unsigned long flags
;
1784 if (!user_buf
|| get_user(trig_type
, user_buf
))
1787 local_irq_save(flags
);
1788 if (trig_type
== ALTR_UE_TRIGGER_CHAR
)
1789 writel(priv
->ue_set_mask
, set_addr
);
1791 writel(priv
->ce_set_mask
, set_addr
);
1793 /* Ensure the interrupt test bits are set */
1795 local_irq_restore(flags
);
1801 * The Stratix10 EDAC Error Injection Functions differ from Arria10
1802 * slightly. A few Arria10 peripherals can use this injection function.
1803 * Inject the error into the memory and then readback to trigger the IRQ.
1805 static ssize_t
altr_edac_a10_device_trig2(struct file
*file
,
1806 const char __user
*user_buf
,
1807 size_t count
, loff_t
*ppos
)
1809 struct edac_device_ctl_info
*edac_dci
= file
->private_data
;
1810 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
1811 const struct edac_device_prv_data
*priv
= drvdata
->data
;
1812 void __iomem
*set_addr
= (drvdata
->base
+ priv
->set_err_ofst
);
1813 unsigned long flags
;
1816 if (!user_buf
|| get_user(trig_type
, user_buf
))
1819 local_irq_save(flags
);
1820 if (trig_type
== ALTR_UE_TRIGGER_CHAR
) {
1821 writel(priv
->ue_set_mask
, set_addr
);
1823 /* Setup read/write of 4 bytes */
1824 writel(ECC_WORD_WRITE
, drvdata
->base
+ ECC_BLK_DBYTECTRL_OFST
);
1825 /* Setup Address to 0 */
1826 writel(0, drvdata
->base
+ ECC_BLK_ADDRESS_OFST
);
1827 /* Setup accctrl to read & ecc & data override */
1828 writel(ECC_READ_EDOVR
, drvdata
->base
+ ECC_BLK_ACCCTRL_OFST
);
1830 writel(ECC_XACT_KICK
, drvdata
->base
+ ECC_BLK_STARTACC_OFST
);
1831 /* Setup write for single bit change */
1832 writel(readl(drvdata
->base
+ ECC_BLK_RDATA0_OFST
) ^ 0x1,
1833 drvdata
->base
+ ECC_BLK_WDATA0_OFST
);
1834 writel(readl(drvdata
->base
+ ECC_BLK_RDATA1_OFST
),
1835 drvdata
->base
+ ECC_BLK_WDATA1_OFST
);
1836 writel(readl(drvdata
->base
+ ECC_BLK_RDATA2_OFST
),
1837 drvdata
->base
+ ECC_BLK_WDATA2_OFST
);
1838 writel(readl(drvdata
->base
+ ECC_BLK_RDATA3_OFST
),
1839 drvdata
->base
+ ECC_BLK_WDATA3_OFST
);
1841 /* Copy Read ECC to Write ECC */
1842 writel(readl(drvdata
->base
+ ECC_BLK_RECC0_OFST
),
1843 drvdata
->base
+ ECC_BLK_WECC0_OFST
);
1844 writel(readl(drvdata
->base
+ ECC_BLK_RECC1_OFST
),
1845 drvdata
->base
+ ECC_BLK_WECC1_OFST
);
1846 /* Setup accctrl to write & ecc override & data override */
1847 writel(ECC_WRITE_EDOVR
, drvdata
->base
+ ECC_BLK_ACCCTRL_OFST
);
1849 writel(ECC_XACT_KICK
, drvdata
->base
+ ECC_BLK_STARTACC_OFST
);
1850 /* Setup accctrl to read & ecc overwrite & data overwrite */
1851 writel(ECC_READ_EDOVR
, drvdata
->base
+ ECC_BLK_ACCCTRL_OFST
);
1853 writel(ECC_XACT_KICK
, drvdata
->base
+ ECC_BLK_STARTACC_OFST
);
1856 /* Ensure the interrupt test bits are set */
1858 local_irq_restore(flags
);
1863 static void altr_edac_a10_irq_handler(struct irq_desc
*desc
)
1865 int dberr
, bit
, sm_offset
, irq_status
;
1866 struct altr_arria10_edac
*edac
= irq_desc_get_handler_data(desc
);
1867 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1868 int irq
= irq_desc_get_irq(desc
);
1871 dberr
= (irq
== edac
->db_irq
) ? 1 : 0;
1872 sm_offset
= dberr
? A10_SYSMGR_ECC_INTSTAT_DERR_OFST
:
1873 A10_SYSMGR_ECC_INTSTAT_SERR_OFST
;
1875 chained_irq_enter(chip
, desc
);
1877 regmap_read(edac
->ecc_mgr_map
, sm_offset
, &irq_status
);
1880 for_each_set_bit(bit
, &bits
, 32) {
1881 irq
= irq_linear_revmap(edac
->domain
, dberr
* 32 + bit
);
1883 generic_handle_irq(irq
);
1886 chained_irq_exit(chip
, desc
);
1889 static int validate_parent_available(struct device_node
*np
)
1891 struct device_node
*parent
;
1894 /* Ensure parent device is enabled if parent node exists */
1895 parent
= of_parse_phandle(np
, "altr,ecc-parent", 0);
1896 if (parent
&& !of_device_is_available(parent
))
1899 of_node_put(parent
);
1903 static int altr_edac_a10_device_add(struct altr_arria10_edac
*edac
,
1904 struct device_node
*np
)
1906 struct edac_device_ctl_info
*dci
;
1907 struct altr_edac_device_dev
*altdev
;
1908 char *ecc_name
= (char *)np
->name
;
1909 struct resource res
;
1912 const struct edac_device_prv_data
*prv
;
1913 /* Get matching node and check for valid result */
1914 const struct of_device_id
*pdev_id
=
1915 of_match_node(altr_edac_a10_device_of_match
, np
);
1916 if (IS_ERR_OR_NULL(pdev_id
))
1919 /* Get driver specific data for this EDAC device */
1920 prv
= pdev_id
->data
;
1921 if (IS_ERR_OR_NULL(prv
))
1924 if (validate_parent_available(np
))
1927 if (!devres_open_group(edac
->dev
, altr_edac_a10_device_add
, GFP_KERNEL
))
1930 rc
= of_address_to_resource(np
, 0, &res
);
1932 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1933 "%s: no resource address\n", ecc_name
);
1934 goto err_release_group
;
1937 edac_idx
= edac_device_alloc_index();
1938 dci
= edac_device_alloc_ctl_info(sizeof(*altdev
), ecc_name
,
1939 1, ecc_name
, 1, 0, NULL
, 0,
1943 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1944 "%s: Unable to allocate EDAC device\n", ecc_name
);
1946 goto err_release_group
;
1949 altdev
= dci
->pvt_info
;
1950 dci
->dev
= edac
->dev
;
1951 altdev
->edac_dev_name
= ecc_name
;
1952 altdev
->edac_idx
= edac_idx
;
1953 altdev
->edac
= edac
;
1954 altdev
->edac_dev
= dci
;
1956 altdev
->ddev
= *edac
->dev
;
1957 dci
->dev
= &altdev
->ddev
;
1958 dci
->ctl_name
= "Altera ECC Manager";
1959 dci
->mod_name
= ecc_name
;
1960 dci
->dev_name
= ecc_name
;
1962 altdev
->base
= devm_ioremap_resource(edac
->dev
, &res
);
1963 if (IS_ERR(altdev
->base
)) {
1964 rc
= PTR_ERR(altdev
->base
);
1965 goto err_release_group1
;
1968 /* Check specific dependencies for the module */
1969 if (altdev
->data
->setup
) {
1970 rc
= altdev
->data
->setup(altdev
);
1972 goto err_release_group1
;
1975 altdev
->sb_irq
= irq_of_parse_and_map(np
, 0);
1976 if (!altdev
->sb_irq
) {
1977 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error allocating SBIRQ\n");
1979 goto err_release_group1
;
1981 rc
= devm_request_irq(edac
->dev
, altdev
->sb_irq
, prv
->ecc_irq_handler
,
1982 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1985 edac_printk(KERN_ERR
, EDAC_DEVICE
, "No SBERR IRQ resource\n");
1986 goto err_release_group1
;
1989 #ifdef CONFIG_ARCH_STRATIX10
1990 /* Use IRQ to determine SError origin instead of assigning IRQ */
1991 rc
= of_property_read_u32_index(np
, "interrupts", 0, &altdev
->db_irq
);
1993 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1994 "Unable to parse DB IRQ index\n");
1995 goto err_release_group1
;
1998 altdev
->db_irq
= irq_of_parse_and_map(np
, 1);
1999 if (!altdev
->db_irq
) {
2000 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error allocating DBIRQ\n");
2002 goto err_release_group1
;
2004 rc
= devm_request_irq(edac
->dev
, altdev
->db_irq
, prv
->ecc_irq_handler
,
2005 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
2008 edac_printk(KERN_ERR
, EDAC_DEVICE
, "No DBERR IRQ resource\n");
2009 goto err_release_group1
;
2013 rc
= edac_device_add_device(dci
);
2015 dev_err(edac
->dev
, "edac_device_add_device failed\n");
2017 goto err_release_group1
;
2020 altr_create_edacdev_dbgfs(dci
, prv
);
2022 list_add(&altdev
->next
, &edac
->a10_ecc_devices
);
2024 devres_remove_group(edac
->dev
, altr_edac_a10_device_add
);
2029 edac_device_free_ctl_info(dci
);
2031 devres_release_group(edac
->dev
, NULL
);
2032 edac_printk(KERN_ERR
, EDAC_DEVICE
,
2033 "%s:Error setting up EDAC device: %d\n", ecc_name
, rc
);
2038 static void a10_eccmgr_irq_mask(struct irq_data
*d
)
2040 struct altr_arria10_edac
*edac
= irq_data_get_irq_chip_data(d
);
2042 regmap_write(edac
->ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_SET_OFST
,
2046 static void a10_eccmgr_irq_unmask(struct irq_data
*d
)
2048 struct altr_arria10_edac
*edac
= irq_data_get_irq_chip_data(d
);
2050 regmap_write(edac
->ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_CLR_OFST
,
2054 static int a10_eccmgr_irqdomain_map(struct irq_domain
*d
, unsigned int irq
,
2055 irq_hw_number_t hwirq
)
2057 struct altr_arria10_edac
*edac
= d
->host_data
;
2059 irq_set_chip_and_handler(irq
, &edac
->irq_chip
, handle_simple_irq
);
2060 irq_set_chip_data(irq
, edac
);
2061 irq_set_noprobe(irq
);
2066 static const struct irq_domain_ops a10_eccmgr_ic_ops
= {
2067 .map
= a10_eccmgr_irqdomain_map
,
2068 .xlate
= irq_domain_xlate_twocell
,
2071 /************** Stratix 10 EDAC Double Bit Error Handler ************/
2072 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2074 #ifdef CONFIG_ARCH_STRATIX10
2075 /* panic routine issues reboot on non-zero panic_timeout */
2076 extern int panic_timeout
;
2079 * The double bit error is handled through SError which is fatal. This is
2080 * called as a panic notifier to printout ECC error info as part of the panic.
2082 static int s10_edac_dberr_handler(struct notifier_block
*this,
2083 unsigned long event
, void *ptr
)
2085 struct altr_arria10_edac
*edac
= to_a10edac(this, panic_notifier
);
2086 int err_addr
, dberror
;
2088 regmap_read(edac
->ecc_mgr_map
, S10_SYSMGR_ECC_INTSTAT_DERR_OFST
,
2090 regmap_write(edac
->ecc_mgr_map
, S10_SYSMGR_UE_VAL_OFST
, dberror
);
2091 if (dberror
& S10_DBE_IRQ_MASK
) {
2092 struct list_head
*position
;
2093 struct altr_edac_device_dev
*ed
;
2094 struct arm_smccc_res result
;
2096 /* Find the matching DBE in the list of devices */
2097 list_for_each(position
, &edac
->a10_ecc_devices
) {
2098 ed
= list_entry(position
, struct altr_edac_device_dev
,
2100 if (!(BIT(ed
->db_irq
) & dberror
))
2103 writel(ALTR_A10_ECC_DERRPENA
,
2104 ed
->base
+ ALTR_A10_ECC_INTSTAT_OFST
);
2105 err_addr
= readl(ed
->base
+ ALTR_S10_DERR_ADDRA_OFST
);
2106 regmap_write(edac
->ecc_mgr_map
,
2107 S10_SYSMGR_UE_ADDR_OFST
, err_addr
);
2108 edac_printk(KERN_ERR
, EDAC_DEVICE
,
2109 "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
2110 ed
->edac_dev_name
, err_addr
);
2113 /* Notify the System through SMC. Reboot delay = 1 second */
2115 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE
, dberror
, 0, 0, 0, 0,
2123 /****************** Arria 10 EDAC Probe Function *********************/
2124 static int altr_edac_a10_probe(struct platform_device
*pdev
)
2126 struct altr_arria10_edac
*edac
;
2127 struct device_node
*child
;
2129 edac
= devm_kzalloc(&pdev
->dev
, sizeof(*edac
), GFP_KERNEL
);
2133 edac
->dev
= &pdev
->dev
;
2134 platform_set_drvdata(pdev
, edac
);
2135 INIT_LIST_HEAD(&edac
->a10_ecc_devices
);
2137 if (socfpga_is_a10()) {
2139 syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
2140 "altr,sysmgr-syscon");
2142 struct device_node
*sysmgr_np
;
2143 struct resource res
;
2146 sysmgr_np
= of_parse_phandle(pdev
->dev
.of_node
,
2147 "altr,sysmgr-syscon", 0);
2149 edac_printk(KERN_ERR
, EDAC_DEVICE
,
2150 "Unable to find altr,sysmgr-syscon\n");
2154 if (of_address_to_resource(sysmgr_np
, 0, &res
))
2157 /* Need physical address for SMCC call */
2160 edac
->ecc_mgr_map
= devm_regmap_init(&pdev
->dev
, NULL
,
2162 &s10_sdram_regmap_cfg
);
2165 if (IS_ERR(edac
->ecc_mgr_map
)) {
2166 edac_printk(KERN_ERR
, EDAC_DEVICE
,
2167 "Unable to get syscon altr,sysmgr-syscon\n");
2168 return PTR_ERR(edac
->ecc_mgr_map
);
2171 edac
->irq_chip
.name
= pdev
->dev
.of_node
->name
;
2172 edac
->irq_chip
.irq_mask
= a10_eccmgr_irq_mask
;
2173 edac
->irq_chip
.irq_unmask
= a10_eccmgr_irq_unmask
;
2174 edac
->domain
= irq_domain_add_linear(pdev
->dev
.of_node
, 64,
2175 &a10_eccmgr_ic_ops
, edac
);
2176 if (!edac
->domain
) {
2177 dev_err(&pdev
->dev
, "Error adding IRQ domain\n");
2181 edac
->sb_irq
= platform_get_irq(pdev
, 0);
2182 if (edac
->sb_irq
< 0) {
2183 dev_err(&pdev
->dev
, "No SBERR IRQ resource\n");
2184 return edac
->sb_irq
;
2187 irq_set_chained_handler_and_data(edac
->sb_irq
,
2188 altr_edac_a10_irq_handler
,
2191 #ifdef CONFIG_ARCH_STRATIX10
2193 int dberror
, err_addr
;
2195 edac
->panic_notifier
.notifier_call
= s10_edac_dberr_handler
;
2196 atomic_notifier_chain_register(&panic_notifier_list
,
2197 &edac
->panic_notifier
);
2199 /* Printout a message if uncorrectable error previously. */
2200 regmap_read(edac
->ecc_mgr_map
, S10_SYSMGR_UE_VAL_OFST
,
2203 regmap_read(edac
->ecc_mgr_map
, S10_SYSMGR_UE_ADDR_OFST
,
2205 edac_printk(KERN_ERR
, EDAC_DEVICE
,
2206 "Previous Boot UE detected[0x%X] @ 0x%X\n",
2208 /* Reset the sticky registers */
2209 regmap_write(edac
->ecc_mgr_map
,
2210 S10_SYSMGR_UE_VAL_OFST
, 0);
2211 regmap_write(edac
->ecc_mgr_map
,
2212 S10_SYSMGR_UE_ADDR_OFST
, 0);
2216 edac
->db_irq
= platform_get_irq(pdev
, 1);
2217 if (edac
->db_irq
< 0) {
2218 dev_err(&pdev
->dev
, "No DBERR IRQ resource\n");
2219 return edac
->db_irq
;
2221 irq_set_chained_handler_and_data(edac
->db_irq
,
2222 altr_edac_a10_irq_handler
, edac
);
2225 for_each_child_of_node(pdev
->dev
.of_node
, child
) {
2226 if (!of_device_is_available(child
))
2229 if (of_device_is_compatible(child
, "altr,socfpga-a10-l2-ecc") ||
2230 of_device_is_compatible(child
, "altr,socfpga-a10-ocram-ecc") ||
2231 of_device_is_compatible(child
, "altr,socfpga-eth-mac-ecc") ||
2232 of_device_is_compatible(child
, "altr,socfpga-nand-ecc") ||
2233 of_device_is_compatible(child
, "altr,socfpga-dma-ecc") ||
2234 of_device_is_compatible(child
, "altr,socfpga-usb-ecc") ||
2235 of_device_is_compatible(child
, "altr,socfpga-qspi-ecc") ||
2236 of_device_is_compatible(child
, "altr,socfpga-sdmmc-ecc"))
2238 altr_edac_a10_device_add(edac
, child
);
2240 #ifdef CONFIG_EDAC_ALTERA_SDRAM
2241 else if ((of_device_is_compatible(child
, "altr,sdram-edac-a10")) ||
2242 (of_device_is_compatible(child
, "altr,sdram-edac-s10")))
2243 of_platform_populate(pdev
->dev
.of_node
,
2244 altr_sdram_ctrl_of_match
,
2252 static const struct of_device_id altr_edac_a10_of_match
[] = {
2253 { .compatible
= "altr,socfpga-a10-ecc-manager" },
2254 { .compatible
= "altr,socfpga-s10-ecc-manager" },
2257 MODULE_DEVICE_TABLE(of
, altr_edac_a10_of_match
);
2259 static struct platform_driver altr_edac_a10_driver
= {
2260 .probe
= altr_edac_a10_probe
,
2262 .name
= "socfpga_a10_ecc_manager",
2263 .of_match_table
= altr_edac_a10_of_match
,
2266 module_platform_driver(altr_edac_a10_driver
);
2268 MODULE_LICENSE("GPL v2");
2269 MODULE_AUTHOR("Thor Thayer");
2270 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");