2 * Cavium ThunderX memory controller kernel module
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright Cavium, Inc. (C) 2015-2017. All rights reserved.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/edac.h>
15 #include <linux/interrupt.h>
16 #include <linux/string.h>
17 #include <linux/stop_machine.h>
18 #include <linux/delay.h>
19 #include <linux/sizes.h>
20 #include <linux/atomic.h>
21 #include <linux/bitfield.h>
22 #include <linux/circ_buf.h>
26 #include "edac_module.h"
28 #define phys_to_pfn(phys) (PFN_DOWN(phys))
30 #define THUNDERX_NODE GENMASK(45, 44)
38 #define MAX_SYNDROME_REGS 4
40 struct error_syndrome
{
41 u64 reg
[MAX_SYNDROME_REGS
];
50 static void decode_register(char *str
, size_t size
,
51 const struct error_descr
*descr
,
56 while (descr
->type
&& descr
->mask
&& descr
->descr
) {
57 if (reg
& descr
->mask
) {
58 ret
= snprintf(str
, size
, "\n\t%s, %s",
59 descr
->type
== ERR_CORRECTED
?
60 "Corrected" : "Uncorrected",
69 static unsigned long get_bits(unsigned long data
, int pos
, int width
)
71 return (data
>> pos
) & ((1 << width
) - 1);
74 #define L2C_CTL 0x87E080800000
75 #define L2C_CTL_DISIDXALIAS BIT(0)
77 #define PCI_DEVICE_ID_THUNDER_LMC 0xa022
80 #define LMC_FADR_FDIMM(x) ((x >> 37) & 0x1)
81 #define LMC_FADR_FBUNK(x) ((x >> 36) & 0x1)
82 #define LMC_FADR_FBANK(x) ((x >> 32) & 0xf)
83 #define LMC_FADR_FROW(x) ((x >> 14) & 0xffff)
84 #define LMC_FADR_FCOL(x) ((x >> 0) & 0x1fff)
86 #define LMC_NXM_FADR 0x28
87 #define LMC_ECC_SYND 0x38
89 #define LMC_ECC_PARITY_TEST 0x108
91 #define LMC_INT_W1S 0x150
93 #define LMC_INT_ENA_W1C 0x158
94 #define LMC_INT_ENA_W1S 0x160
96 #define LMC_CONFIG 0x188
98 #define LMC_CONFIG_BG2 BIT(62)
99 #define LMC_CONFIG_RANK_ENA BIT(42)
100 #define LMC_CONFIG_PBANK_LSB(x) (((x) >> 5) & 0xF)
101 #define LMC_CONFIG_ROW_LSB(x) (((x) >> 2) & 0x7)
103 #define LMC_CONTROL 0x190
104 #define LMC_CONTROL_XOR_BANK BIT(16)
106 #define LMC_INT 0x1F0
108 #define LMC_INT_DDR_ERR BIT(11)
109 #define LMC_INT_DED_ERR (0xFUL << 5)
110 #define LMC_INT_SEC_ERR (0xFUL << 1)
111 #define LMC_INT_NXM_WR_MASK BIT(0)
113 #define LMC_DDR_PLL_CTL 0x258
114 #define LMC_DDR_PLL_CTL_DDR4 BIT(29)
116 #define LMC_FADR_SCRAMBLED 0x330
118 #define LMC_INT_UE (LMC_INT_DDR_ERR | LMC_INT_DED_ERR | \
121 #define LMC_INT_CE (LMC_INT_SEC_ERR)
123 static const struct error_descr lmc_errors
[] = {
125 .type
= ERR_CORRECTED
,
126 .mask
= LMC_INT_SEC_ERR
,
127 .descr
= "Single-bit ECC error",
130 .type
= ERR_UNCORRECTED
,
131 .mask
= LMC_INT_DDR_ERR
,
132 .descr
= "DDR chip error",
135 .type
= ERR_UNCORRECTED
,
136 .mask
= LMC_INT_DED_ERR
,
137 .descr
= "Double-bit ECC error",
140 .type
= ERR_UNCORRECTED
,
141 .mask
= LMC_INT_NXM_WR_MASK
,
142 .descr
= "Non-existent memory write",
147 #define LMC_INT_EN_DDR_ERROR_ALERT_ENA BIT(5)
148 #define LMC_INT_EN_DLCRAM_DED_ERR BIT(4)
149 #define LMC_INT_EN_DLCRAM_SEC_ERR BIT(3)
150 #define LMC_INT_INTR_DED_ENA BIT(2)
151 #define LMC_INT_INTR_SEC_ENA BIT(1)
152 #define LMC_INT_INTR_NXM_WR_ENA BIT(0)
154 #define LMC_INT_ENA_ALL GENMASK(5, 0)
156 #define LMC_DDR_PLL_CTL 0x258
157 #define LMC_DDR_PLL_CTL_DDR4 BIT(29)
159 #define LMC_CONTROL 0x190
160 #define LMC_CONTROL_RDIMM BIT(0)
162 #define LMC_SCRAM_FADR 0x330
164 #define LMC_CHAR_MASK0 0x228
165 #define LMC_CHAR_MASK2 0x238
167 #define RING_ENTRIES 8
169 struct debugfs_entry
{
172 const struct file_operations fops
;
183 struct thunderx_lmc
{
185 struct pci_dev
*pdev
;
186 struct msix_entry msix_ent
;
209 struct lmc_err_ctx err_ctx
[RING_ENTRIES
];
210 unsigned long ring_head
;
211 unsigned long ring_tail
;
214 #define ring_pos(pos, size) ((pos) & (size - 1))
216 #define DEBUGFS_STRUCT(_name, _mode, _write, _read) \
217 static struct debugfs_entry debugfs_##_name = { \
218 .name = __stringify(_name), \
219 .mode = VERIFY_OCTAL_PERMISSIONS(_mode), \
221 .open = simple_open, \
224 .llseek = generic_file_llseek, \
228 #define DEBUGFS_FIELD_ATTR(_type, _field) \
229 static ssize_t thunderx_##_type##_##_field##_read(struct file *file, \
231 size_t count, loff_t *ppos) \
233 struct thunderx_##_type *pdata = file->private_data; \
236 snprintf(buf, count, "0x%016llx", pdata->_field); \
237 return simple_read_from_buffer(data, count, ppos, \
241 static ssize_t thunderx_##_type##_##_field##_write(struct file *file, \
242 const char __user *data, \
243 size_t count, loff_t *ppos) \
245 struct thunderx_##_type *pdata = file->private_data; \
248 res = kstrtoull_from_user(data, count, 0, &pdata->_field); \
250 return res ? res : count; \
253 DEBUGFS_STRUCT(_field, 0600, \
254 thunderx_##_type##_##_field##_write, \
255 thunderx_##_type##_##_field##_read) \
257 #define DEBUGFS_REG_ATTR(_type, _name, _reg) \
258 static ssize_t thunderx_##_type##_##_name##_read(struct file *file, \
260 size_t count, loff_t *ppos) \
262 struct thunderx_##_type *pdata = file->private_data; \
265 sprintf(buf, "0x%016llx", readq(pdata->regs + _reg)); \
266 return simple_read_from_buffer(data, count, ppos, \
270 static ssize_t thunderx_##_type##_##_name##_write(struct file *file, \
271 const char __user *data, \
272 size_t count, loff_t *ppos) \
274 struct thunderx_##_type *pdata = file->private_data; \
278 res = kstrtoull_from_user(data, count, 0, &val); \
281 writeq(val, pdata->regs + _reg); \
288 DEBUGFS_STRUCT(_name, 0600, \
289 thunderx_##_type##_##_name##_write, \
290 thunderx_##_type##_##_name##_read)
292 #define LMC_DEBUGFS_ENT(_field) DEBUGFS_FIELD_ATTR(lmc, _field)
295 * To get an ECC error injected, the following steps are needed:
296 * - Setup the ECC injection by writing the appropriate parameters:
297 * echo <bit mask value> > /sys/kernel/debug/<device number>/ecc_mask0
298 * echo <bit mask value> > /sys/kernel/debug/<device number>/ecc_mask2
299 * echo 0x802 > /sys/kernel/debug/<device number>/ecc_parity_test
300 * - Do the actual injection:
301 * echo 1 > /sys/kernel/debug/<device number>/inject_ecc
303 static ssize_t
thunderx_lmc_inject_int_write(struct file
*file
,
304 const char __user
*data
,
305 size_t count
, loff_t
*ppos
)
307 struct thunderx_lmc
*lmc
= file
->private_data
;
311 res
= kstrtoull_from_user(data
, count
, 0, &val
);
314 /* Trigger the interrupt */
315 writeq(val
, lmc
->regs
+ LMC_INT_W1S
);
322 static ssize_t
thunderx_lmc_int_read(struct file
*file
,
324 size_t count
, loff_t
*ppos
)
326 struct thunderx_lmc
*lmc
= file
->private_data
;
328 u64 lmc_int
= readq(lmc
->regs
+ LMC_INT
);
330 snprintf(buf
, sizeof(buf
), "0x%016llx", lmc_int
);
331 return simple_read_from_buffer(data
, count
, ppos
, buf
, sizeof(buf
));
334 #define TEST_PATTERN 0xa5
336 static int inject_ecc_fn(void *arg
)
338 struct thunderx_lmc
*lmc
= arg
;
339 uintptr_t addr
, phys
;
340 unsigned int cline_size
= cache_line_size();
341 const unsigned int lines
= PAGE_SIZE
/ cline_size
;
342 unsigned int i
, cl_idx
;
344 addr
= (uintptr_t)page_address(lmc
->mem
);
345 phys
= (uintptr_t)page_to_phys(lmc
->mem
);
347 cl_idx
= (phys
& 0x7f) >> 4;
348 lmc
->parity_test
&= ~(7ULL << 8);
349 lmc
->parity_test
|= (cl_idx
<< 8);
351 writeq(lmc
->mask0
, lmc
->regs
+ LMC_CHAR_MASK0
);
352 writeq(lmc
->mask2
, lmc
->regs
+ LMC_CHAR_MASK2
);
353 writeq(lmc
->parity_test
, lmc
->regs
+ LMC_ECC_PARITY_TEST
);
355 readq(lmc
->regs
+ LMC_CHAR_MASK0
);
356 readq(lmc
->regs
+ LMC_CHAR_MASK2
);
357 readq(lmc
->regs
+ LMC_ECC_PARITY_TEST
);
359 for (i
= 0; i
< lines
; i
++) {
360 memset((void *)addr
, TEST_PATTERN
, cline_size
);
364 * Flush L1 cachelines to the PoC (L2).
365 * This will cause cacheline eviction to the L2.
367 asm volatile("dc civac, %0\n"
369 : : "r"(addr
+ i
* cline_size
));
372 for (i
= 0; i
< lines
; i
++) {
374 * Flush L2 cachelines to the DRAM.
375 * This will cause cacheline eviction to the DRAM
376 * and ECC corruption according to the masks set.
378 __asm__
volatile("sys #0,c11,C1,#2, %0\n"
379 : : "r"(phys
+ i
* cline_size
));
382 for (i
= 0; i
< lines
; i
++) {
384 * Invalidate L2 cachelines.
385 * The subsequent load will cause cacheline fetch
386 * from the DRAM and an error interrupt
388 __asm__
volatile("sys #0,c11,C1,#1, %0"
389 : : "r"(phys
+ i
* cline_size
));
392 for (i
= 0; i
< lines
; i
++) {
394 * Invalidate L1 cachelines.
395 * The subsequent load will cause cacheline fetch
396 * from the L2 and/or DRAM
398 asm volatile("dc ivac, %0\n"
400 : : "r"(addr
+ i
* cline_size
));
406 static ssize_t
thunderx_lmc_inject_ecc_write(struct file
*file
,
407 const char __user
*data
,
408 size_t count
, loff_t
*ppos
)
410 struct thunderx_lmc
*lmc
= file
->private_data
;
412 unsigned int cline_size
= cache_line_size();
416 unsigned int offs
, timeout
= 100000;
418 atomic_set(&lmc
->ecc_int
, 0);
420 lmc
->mem
= alloc_pages_node(lmc
->node
, GFP_KERNEL
, 0);
425 addr
= page_address(lmc
->mem
);
427 while (!atomic_read(&lmc
->ecc_int
) && timeout
--) {
428 stop_machine(inject_ecc_fn
, lmc
, NULL
);
430 for (offs
= 0; offs
< PAGE_SIZE
; offs
+= sizeof(tmp
)) {
432 * Do a load from the previously rigged location
433 * This should generate an error interrupt.
435 memcpy(tmp
, addr
+ offs
, cline_size
);
436 asm volatile("dsb ld\n");
440 __free_pages(lmc
->mem
, 0);
445 LMC_DEBUGFS_ENT(mask0
);
446 LMC_DEBUGFS_ENT(mask2
);
447 LMC_DEBUGFS_ENT(parity_test
);
449 DEBUGFS_STRUCT(inject_int
, 0200, thunderx_lmc_inject_int_write
, NULL
);
450 DEBUGFS_STRUCT(inject_ecc
, 0200, thunderx_lmc_inject_ecc_write
, NULL
);
451 DEBUGFS_STRUCT(int_w1c
, 0400, NULL
, thunderx_lmc_int_read
);
453 struct debugfs_entry
*lmc_dfs_ents
[] = {
456 &debugfs_parity_test
,
462 static int thunderx_create_debugfs_nodes(struct dentry
*parent
,
463 struct debugfs_entry
*attrs
[],
470 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
476 for (i
= 0; i
< num
; i
++) {
477 ent
= edac_debugfs_create_file(attrs
[i
]->name
, attrs
[i
]->mode
,
478 parent
, data
, &attrs
[i
]->fops
);
487 static phys_addr_t
thunderx_faddr_to_phys(u64 faddr
, struct thunderx_lmc
*lmc
)
489 phys_addr_t addr
= 0;
492 addr
|= lmc
->node
<< 40;
493 addr
|= LMC_FADR_FDIMM(faddr
) << lmc
->dimm_lsb
;
494 addr
|= LMC_FADR_FBUNK(faddr
) << lmc
->rank_lsb
;
495 addr
|= LMC_FADR_FROW(faddr
) << lmc
->row_lsb
;
496 addr
|= (LMC_FADR_FCOL(faddr
) >> 4) << lmc
->col_hi_lsb
;
498 bank
= LMC_FADR_FBANK(faddr
) << lmc
->bank_lsb
;
501 bank
^= get_bits(addr
, 12 + lmc
->xbits
, lmc
->bank_width
);
503 addr
|= bank
<< lmc
->bank_lsb
;
505 xbits
= PCI_FUNC(lmc
->pdev
->devfn
);
508 xbits
^= get_bits(addr
, 20, lmc
->xbits
) ^
509 get_bits(addr
, 12, lmc
->xbits
);
516 static unsigned int thunderx_get_num_lmcs(unsigned int node
)
518 unsigned int number
= 0;
519 struct pci_dev
*pdev
= NULL
;
522 pdev
= pci_get_device(PCI_VENDOR_ID_CAVIUM
,
523 PCI_DEVICE_ID_THUNDER_LMC
,
527 if (pdev
->dev
.numa_node
== node
)
538 #define LMC_MESSAGE_SIZE 120
539 #define LMC_OTHER_SIZE (50 * ARRAY_SIZE(lmc_errors))
541 static irqreturn_t
thunderx_lmc_err_isr(int irq
, void *dev_id
)
543 struct mem_ctl_info
*mci
= dev_id
;
544 struct thunderx_lmc
*lmc
= mci
->pvt_info
;
546 unsigned long head
= ring_pos(lmc
->ring_head
, ARRAY_SIZE(lmc
->err_ctx
));
547 struct lmc_err_ctx
*ctx
= &lmc
->err_ctx
[head
];
549 writeq(0, lmc
->regs
+ LMC_CHAR_MASK0
);
550 writeq(0, lmc
->regs
+ LMC_CHAR_MASK2
);
551 writeq(0x2, lmc
->regs
+ LMC_ECC_PARITY_TEST
);
553 ctx
->reg_int
= readq(lmc
->regs
+ LMC_INT
);
554 ctx
->reg_fadr
= readq(lmc
->regs
+ LMC_FADR
);
555 ctx
->reg_nxm_fadr
= readq(lmc
->regs
+ LMC_NXM_FADR
);
556 ctx
->reg_scram_fadr
= readq(lmc
->regs
+ LMC_SCRAM_FADR
);
557 ctx
->reg_ecc_synd
= readq(lmc
->regs
+ LMC_ECC_SYND
);
561 atomic_set(&lmc
->ecc_int
, 1);
563 /* Clear the interrupt */
564 writeq(ctx
->reg_int
, lmc
->regs
+ LMC_INT
);
566 return IRQ_WAKE_THREAD
;
569 static irqreturn_t
thunderx_lmc_threaded_isr(int irq
, void *dev_id
)
571 struct mem_ctl_info
*mci
= dev_id
;
572 struct thunderx_lmc
*lmc
= mci
->pvt_info
;
573 phys_addr_t phys_addr
;
576 struct lmc_err_ctx
*ctx
;
578 irqreturn_t ret
= IRQ_NONE
;
583 msg
= kmalloc(LMC_MESSAGE_SIZE
, GFP_KERNEL
);
584 other
= kmalloc(LMC_OTHER_SIZE
, GFP_KERNEL
);
589 while (CIRC_CNT(lmc
->ring_head
, lmc
->ring_tail
,
590 ARRAY_SIZE(lmc
->err_ctx
))) {
591 tail
= ring_pos(lmc
->ring_tail
, ARRAY_SIZE(lmc
->err_ctx
));
593 ctx
= &lmc
->err_ctx
[tail
];
595 dev_dbg(&lmc
->pdev
->dev
, "LMC_INT: %016llx\n",
597 dev_dbg(&lmc
->pdev
->dev
, "LMC_FADR: %016llx\n",
599 dev_dbg(&lmc
->pdev
->dev
, "LMC_NXM_FADR: %016llx\n",
601 dev_dbg(&lmc
->pdev
->dev
, "LMC_SCRAM_FADR: %016llx\n",
602 ctx
->reg_scram_fadr
);
603 dev_dbg(&lmc
->pdev
->dev
, "LMC_ECC_SYND: %016llx\n",
606 snprintf(msg
, LMC_MESSAGE_SIZE
,
607 "DIMM %lld rank %lld bank %lld row %lld col %lld",
608 LMC_FADR_FDIMM(ctx
->reg_scram_fadr
),
609 LMC_FADR_FBUNK(ctx
->reg_scram_fadr
),
610 LMC_FADR_FBANK(ctx
->reg_scram_fadr
),
611 LMC_FADR_FROW(ctx
->reg_scram_fadr
),
612 LMC_FADR_FCOL(ctx
->reg_scram_fadr
));
614 decode_register(other
, LMC_OTHER_SIZE
, lmc_errors
,
617 phys_addr
= thunderx_faddr_to_phys(ctx
->reg_fadr
, lmc
);
619 if (ctx
->reg_int
& LMC_INT_UE
)
620 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED
, mci
, 1,
621 phys_to_pfn(phys_addr
),
622 offset_in_page(phys_addr
),
623 0, -1, -1, -1, msg
, other
);
624 else if (ctx
->reg_int
& LMC_INT_CE
)
625 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED
, mci
, 1,
626 phys_to_pfn(phys_addr
),
627 offset_in_page(phys_addr
),
628 0, -1, -1, -1, msg
, other
);
643 static int thunderx_lmc_suspend(struct pci_dev
*pdev
, pm_message_t state
)
645 pci_save_state(pdev
);
646 pci_disable_device(pdev
);
648 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
653 static int thunderx_lmc_resume(struct pci_dev
*pdev
)
655 pci_set_power_state(pdev
, PCI_D0
);
656 pci_enable_wake(pdev
, PCI_D0
, 0);
657 pci_restore_state(pdev
);
663 static const struct pci_device_id thunderx_lmc_pci_tbl
[] = {
664 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_LMC
) },
668 static inline int pci_dev_to_mc_idx(struct pci_dev
*pdev
)
670 int node
= dev_to_node(&pdev
->dev
);
671 int ret
= PCI_FUNC(pdev
->devfn
);
673 ret
+= max(node
, 0) << 3;
678 static int thunderx_lmc_probe(struct pci_dev
*pdev
,
679 const struct pci_device_id
*id
)
681 struct thunderx_lmc
*lmc
;
682 struct edac_mc_layer layer
;
683 struct mem_ctl_info
*mci
;
684 u64 lmc_control
, lmc_ddr_pll_ctl
, lmc_config
;
689 layer
.type
= EDAC_MC_LAYER_SLOT
;
691 layer
.is_virt_csrow
= false;
693 ret
= pcim_enable_device(pdev
);
695 dev_err(&pdev
->dev
, "Cannot enable PCI device: %d\n", ret
);
699 ret
= pcim_iomap_regions(pdev
, BIT(0), "thunderx_lmc");
701 dev_err(&pdev
->dev
, "Cannot map PCI resources: %d\n", ret
);
705 mci
= edac_mc_alloc(pci_dev_to_mc_idx(pdev
), 1, &layer
,
706 sizeof(struct thunderx_lmc
));
710 mci
->pdev
= &pdev
->dev
;
713 pci_set_drvdata(pdev
, mci
);
715 lmc
->regs
= pcim_iomap_table(pdev
)[0];
717 lmc_control
= readq(lmc
->regs
+ LMC_CONTROL
);
718 lmc_ddr_pll_ctl
= readq(lmc
->regs
+ LMC_DDR_PLL_CTL
);
719 lmc_config
= readq(lmc
->regs
+ LMC_CONFIG
);
721 if (lmc_control
& LMC_CONTROL_RDIMM
) {
722 mci
->mtype_cap
= FIELD_GET(LMC_DDR_PLL_CTL_DDR4
,
724 MEM_RDDR4
: MEM_RDDR3
;
726 mci
->mtype_cap
= FIELD_GET(LMC_DDR_PLL_CTL_DDR4
,
731 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
;
732 mci
->edac_cap
= EDAC_FLAG_SECDED
;
734 mci
->mod_name
= "thunderx-lmc";
735 mci
->ctl_name
= "thunderx-lmc";
736 mci
->dev_name
= dev_name(&pdev
->dev
);
737 mci
->scrub_mode
= SCRUB_NONE
;
740 lmc
->msix_ent
.entry
= 0;
745 ret
= pci_enable_msix_exact(pdev
, &lmc
->msix_ent
, 1);
747 dev_err(&pdev
->dev
, "Cannot enable interrupt: %d\n", ret
);
751 ret
= devm_request_threaded_irq(&pdev
->dev
, lmc
->msix_ent
.vector
,
752 thunderx_lmc_err_isr
,
753 thunderx_lmc_threaded_isr
, 0,
754 "[EDAC] ThunderX LMC", mci
);
756 dev_err(&pdev
->dev
, "Cannot set ISR: %d\n", ret
);
760 lmc
->node
= FIELD_GET(THUNDERX_NODE
, pci_resource_start(pdev
, 0));
762 lmc
->xbits
= thunderx_get_num_lmcs(lmc
->node
) >> 1;
763 lmc
->bank_width
= (FIELD_GET(LMC_DDR_PLL_CTL_DDR4
, lmc_ddr_pll_ctl
) &&
764 FIELD_GET(LMC_CONFIG_BG2
, lmc_config
)) ? 4 : 3;
766 lmc
->pbank_lsb
= (lmc_config
>> 5) & 0xf;
767 lmc
->dimm_lsb
= 28 + lmc
->pbank_lsb
+ lmc
->xbits
;
768 lmc
->rank_lsb
= lmc
->dimm_lsb
;
769 lmc
->rank_lsb
-= FIELD_GET(LMC_CONFIG_RANK_ENA
, lmc_config
) ? 1 : 0;
770 lmc
->bank_lsb
= 7 + lmc
->xbits
;
771 lmc
->row_lsb
= 14 + LMC_CONFIG_ROW_LSB(lmc_config
) + lmc
->xbits
;
773 lmc
->col_hi_lsb
= lmc
->bank_lsb
+ lmc
->bank_width
;
775 lmc
->xor_bank
= lmc_control
& LMC_CONTROL_XOR_BANK
;
777 l2c_ioaddr
= ioremap(L2C_CTL
| FIELD_PREP(THUNDERX_NODE
, lmc
->node
),
781 dev_err(&pdev
->dev
, "Cannot map L2C_CTL\n");
785 lmc
->l2c_alias
= !(readq(l2c_ioaddr
) & L2C_CTL_DISIDXALIAS
);
789 ret
= edac_mc_add_mc(mci
);
791 dev_err(&pdev
->dev
, "Cannot add the MC: %d\n", ret
);
795 lmc_int
= readq(lmc
->regs
+ LMC_INT
);
796 writeq(lmc_int
, lmc
->regs
+ LMC_INT
);
798 writeq(LMC_INT_ENA_ALL
, lmc
->regs
+ LMC_INT_ENA_W1S
);
800 if (IS_ENABLED(CONFIG_EDAC_DEBUG
)) {
801 ret
= thunderx_create_debugfs_nodes(mci
->debugfs
,
804 ARRAY_SIZE(lmc_dfs_ents
));
806 if (ret
!= ARRAY_SIZE(lmc_dfs_ents
)) {
807 dev_warn(&pdev
->dev
, "Error creating debugfs entries: %d%s\n",
808 ret
, ret
>= 0 ? " created" : "");
815 pci_set_drvdata(pdev
, NULL
);
821 static void thunderx_lmc_remove(struct pci_dev
*pdev
)
823 struct mem_ctl_info
*mci
= pci_get_drvdata(pdev
);
824 struct thunderx_lmc
*lmc
= mci
->pvt_info
;
826 writeq(LMC_INT_ENA_ALL
, lmc
->regs
+ LMC_INT_ENA_W1C
);
828 edac_mc_del_mc(&pdev
->dev
);
832 MODULE_DEVICE_TABLE(pci
, thunderx_lmc_pci_tbl
);
834 static struct pci_driver thunderx_lmc_driver
= {
835 .name
= "thunderx_lmc_edac",
836 .probe
= thunderx_lmc_probe
,
837 .remove
= thunderx_lmc_remove
,
839 .suspend
= thunderx_lmc_suspend
,
840 .resume
= thunderx_lmc_resume
,
842 .id_table
= thunderx_lmc_pci_tbl
,
845 /*---------------------- OCX driver ---------------------------------*/
847 #define PCI_DEVICE_ID_THUNDER_OCX 0xa013
849 #define OCX_LINK_INTS 3
850 #define OCX_INTS (OCX_LINK_INTS + 1)
851 #define OCX_RX_LANES 24
852 #define OCX_RX_LANE_STATS 15
854 #define OCX_COM_INT 0x100
855 #define OCX_COM_INT_W1S 0x108
856 #define OCX_COM_INT_ENA_W1S 0x110
857 #define OCX_COM_INT_ENA_W1C 0x118
859 #define OCX_COM_IO_BADID BIT(54)
860 #define OCX_COM_MEM_BADID BIT(53)
861 #define OCX_COM_COPR_BADID BIT(52)
862 #define OCX_COM_WIN_REQ_BADID BIT(51)
863 #define OCX_COM_WIN_REQ_TOUT BIT(50)
864 #define OCX_COM_RX_LANE GENMASK(23, 0)
866 #define OCX_COM_INT_CE (OCX_COM_IO_BADID | \
867 OCX_COM_MEM_BADID | \
868 OCX_COM_COPR_BADID | \
869 OCX_COM_WIN_REQ_BADID | \
870 OCX_COM_WIN_REQ_TOUT)
872 static const struct error_descr ocx_com_errors
[] = {
874 .type
= ERR_CORRECTED
,
875 .mask
= OCX_COM_IO_BADID
,
876 .descr
= "Invalid IO transaction node ID",
879 .type
= ERR_CORRECTED
,
880 .mask
= OCX_COM_MEM_BADID
,
881 .descr
= "Invalid memory transaction node ID",
884 .type
= ERR_CORRECTED
,
885 .mask
= OCX_COM_COPR_BADID
,
886 .descr
= "Invalid coprocessor transaction node ID",
889 .type
= ERR_CORRECTED
,
890 .mask
= OCX_COM_WIN_REQ_BADID
,
891 .descr
= "Invalid SLI transaction node ID",
894 .type
= ERR_CORRECTED
,
895 .mask
= OCX_COM_WIN_REQ_TOUT
,
896 .descr
= "Window/core request timeout",
901 #define OCX_COM_LINKX_INT(x) (0x120 + (x) * 8)
902 #define OCX_COM_LINKX_INT_W1S(x) (0x140 + (x) * 8)
903 #define OCX_COM_LINKX_INT_ENA_W1S(x) (0x160 + (x) * 8)
904 #define OCX_COM_LINKX_INT_ENA_W1C(x) (0x180 + (x) * 8)
906 #define OCX_COM_LINK_BAD_WORD BIT(13)
907 #define OCX_COM_LINK_ALIGN_FAIL BIT(12)
908 #define OCX_COM_LINK_ALIGN_DONE BIT(11)
909 #define OCX_COM_LINK_UP BIT(10)
910 #define OCX_COM_LINK_STOP BIT(9)
911 #define OCX_COM_LINK_BLK_ERR BIT(8)
912 #define OCX_COM_LINK_REINIT BIT(7)
913 #define OCX_COM_LINK_LNK_DATA BIT(6)
914 #define OCX_COM_LINK_RXFIFO_DBE BIT(5)
915 #define OCX_COM_LINK_RXFIFO_SBE BIT(4)
916 #define OCX_COM_LINK_TXFIFO_DBE BIT(3)
917 #define OCX_COM_LINK_TXFIFO_SBE BIT(2)
918 #define OCX_COM_LINK_REPLAY_DBE BIT(1)
919 #define OCX_COM_LINK_REPLAY_SBE BIT(0)
921 static const struct error_descr ocx_com_link_errors
[] = {
923 .type
= ERR_CORRECTED
,
924 .mask
= OCX_COM_LINK_REPLAY_SBE
,
925 .descr
= "Replay buffer single-bit error",
928 .type
= ERR_CORRECTED
,
929 .mask
= OCX_COM_LINK_TXFIFO_SBE
,
930 .descr
= "TX FIFO single-bit error",
933 .type
= ERR_CORRECTED
,
934 .mask
= OCX_COM_LINK_RXFIFO_SBE
,
935 .descr
= "RX FIFO single-bit error",
938 .type
= ERR_CORRECTED
,
939 .mask
= OCX_COM_LINK_BLK_ERR
,
940 .descr
= "Block code error",
943 .type
= ERR_CORRECTED
,
944 .mask
= OCX_COM_LINK_ALIGN_FAIL
,
945 .descr
= "Link alignment failure",
948 .type
= ERR_CORRECTED
,
949 .mask
= OCX_COM_LINK_BAD_WORD
,
950 .descr
= "Bad code word",
953 .type
= ERR_UNCORRECTED
,
954 .mask
= OCX_COM_LINK_REPLAY_DBE
,
955 .descr
= "Replay buffer double-bit error",
958 .type
= ERR_UNCORRECTED
,
959 .mask
= OCX_COM_LINK_TXFIFO_DBE
,
960 .descr
= "TX FIFO double-bit error",
963 .type
= ERR_UNCORRECTED
,
964 .mask
= OCX_COM_LINK_RXFIFO_DBE
,
965 .descr
= "RX FIFO double-bit error",
968 .type
= ERR_UNCORRECTED
,
969 .mask
= OCX_COM_LINK_STOP
,
970 .descr
= "Link stopped",
975 #define OCX_COM_LINK_INT_UE (OCX_COM_LINK_REPLAY_DBE | \
976 OCX_COM_LINK_TXFIFO_DBE | \
977 OCX_COM_LINK_RXFIFO_DBE | \
980 #define OCX_COM_LINK_INT_CE (OCX_COM_LINK_REPLAY_SBE | \
981 OCX_COM_LINK_TXFIFO_SBE | \
982 OCX_COM_LINK_RXFIFO_SBE | \
983 OCX_COM_LINK_BLK_ERR | \
984 OCX_COM_LINK_ALIGN_FAIL | \
985 OCX_COM_LINK_BAD_WORD)
987 #define OCX_LNE_INT(x) (0x8018 + (x) * 0x100)
988 #define OCX_LNE_INT_EN(x) (0x8020 + (x) * 0x100)
989 #define OCX_LNE_BAD_CNT(x) (0x8028 + (x) * 0x100)
990 #define OCX_LNE_CFG(x) (0x8000 + (x) * 0x100)
991 #define OCX_LNE_STAT(x, y) (0x8040 + (x) * 0x100 + (y) * 8)
993 #define OCX_LNE_CFG_RX_BDRY_LOCK_DIS BIT(8)
994 #define OCX_LNE_CFG_RX_STAT_WRAP_DIS BIT(2)
995 #define OCX_LNE_CFG_RX_STAT_RDCLR BIT(1)
996 #define OCX_LNE_CFG_RX_STAT_ENA BIT(0)
999 #define OCX_LANE_BAD_64B67B BIT(8)
1000 #define OCX_LANE_DSKEW_FIFO_OVFL BIT(5)
1001 #define OCX_LANE_SCRM_SYNC_LOSS BIT(4)
1002 #define OCX_LANE_UKWN_CNTL_WORD BIT(3)
1003 #define OCX_LANE_CRC32_ERR BIT(2)
1004 #define OCX_LANE_BDRY_SYNC_LOSS BIT(1)
1005 #define OCX_LANE_SERDES_LOCK_LOSS BIT(0)
1007 #define OCX_COM_LANE_INT_UE (0)
1008 #define OCX_COM_LANE_INT_CE (OCX_LANE_SERDES_LOCK_LOSS | \
1009 OCX_LANE_BDRY_SYNC_LOSS | \
1010 OCX_LANE_CRC32_ERR | \
1011 OCX_LANE_UKWN_CNTL_WORD | \
1012 OCX_LANE_SCRM_SYNC_LOSS | \
1013 OCX_LANE_DSKEW_FIFO_OVFL | \
1014 OCX_LANE_BAD_64B67B)
1016 static const struct error_descr ocx_lane_errors
[] = {
1018 .type
= ERR_CORRECTED
,
1019 .mask
= OCX_LANE_SERDES_LOCK_LOSS
,
1020 .descr
= "RX SerDes lock lost",
1023 .type
= ERR_CORRECTED
,
1024 .mask
= OCX_LANE_BDRY_SYNC_LOSS
,
1025 .descr
= "RX word boundary lost",
1028 .type
= ERR_CORRECTED
,
1029 .mask
= OCX_LANE_CRC32_ERR
,
1030 .descr
= "CRC32 error",
1033 .type
= ERR_CORRECTED
,
1034 .mask
= OCX_LANE_UKWN_CNTL_WORD
,
1035 .descr
= "Unknown control word",
1038 .type
= ERR_CORRECTED
,
1039 .mask
= OCX_LANE_SCRM_SYNC_LOSS
,
1040 .descr
= "Scrambler synchronization lost",
1043 .type
= ERR_CORRECTED
,
1044 .mask
= OCX_LANE_DSKEW_FIFO_OVFL
,
1045 .descr
= "RX deskew FIFO overflow",
1048 .type
= ERR_CORRECTED
,
1049 .mask
= OCX_LANE_BAD_64B67B
,
1050 .descr
= "Bad 64B/67B codeword",
1055 #define OCX_LNE_INT_ENA_ALL (GENMASK(9, 8) | GENMASK(6, 0))
1056 #define OCX_COM_INT_ENA_ALL (GENMASK(54, 50) | GENMASK(23, 0))
1057 #define OCX_COM_LINKX_INT_ENA_ALL (GENMASK(13, 12) | \
1058 GENMASK(9, 7) | GENMASK(5, 0))
1060 #define OCX_TLKX_ECC_CTL(x) (0x10018 + (x) * 0x2000)
1061 #define OCX_RLKX_ECC_CTL(x) (0x18018 + (x) * 0x2000)
1063 struct ocx_com_err_ctx
{
1065 u64 reg_lane_int
[OCX_RX_LANES
];
1066 u64 reg_lane_stat11
[OCX_RX_LANES
];
1069 struct ocx_link_err_ctx
{
1070 u64 reg_com_link_int
;
1074 struct thunderx_ocx
{
1077 struct pci_dev
*pdev
;
1078 struct edac_device_ctl_info
*edac_dev
;
1080 struct dentry
*debugfs
;
1081 struct msix_entry msix_ent
[OCX_INTS
];
1083 struct ocx_com_err_ctx com_err_ctx
[RING_ENTRIES
];
1084 struct ocx_link_err_ctx link_err_ctx
[RING_ENTRIES
];
1086 unsigned long com_ring_head
;
1087 unsigned long com_ring_tail
;
1089 unsigned long link_ring_head
;
1090 unsigned long link_ring_tail
;
1093 #define OCX_MESSAGE_SIZE SZ_1K
1094 #define OCX_OTHER_SIZE (50 * ARRAY_SIZE(ocx_com_link_errors))
1096 /* This handler is threaded */
1097 static irqreturn_t
thunderx_ocx_com_isr(int irq
, void *irq_id
)
1099 struct msix_entry
*msix
= irq_id
;
1100 struct thunderx_ocx
*ocx
= container_of(msix
, struct thunderx_ocx
,
1101 msix_ent
[msix
->entry
]);
1104 unsigned long head
= ring_pos(ocx
->com_ring_head
,
1105 ARRAY_SIZE(ocx
->com_err_ctx
));
1106 struct ocx_com_err_ctx
*ctx
= &ocx
->com_err_ctx
[head
];
1108 ctx
->reg_com_int
= readq(ocx
->regs
+ OCX_COM_INT
);
1110 for (lane
= 0; lane
< OCX_RX_LANES
; lane
++) {
1111 ctx
->reg_lane_int
[lane
] =
1112 readq(ocx
->regs
+ OCX_LNE_INT(lane
));
1113 ctx
->reg_lane_stat11
[lane
] =
1114 readq(ocx
->regs
+ OCX_LNE_STAT(lane
, 11));
1116 writeq(ctx
->reg_lane_int
[lane
], ocx
->regs
+ OCX_LNE_INT(lane
));
1119 writeq(ctx
->reg_com_int
, ocx
->regs
+ OCX_COM_INT
);
1121 ocx
->com_ring_head
++;
1123 return IRQ_WAKE_THREAD
;
1126 static irqreturn_t
thunderx_ocx_com_threaded_isr(int irq
, void *irq_id
)
1128 struct msix_entry
*msix
= irq_id
;
1129 struct thunderx_ocx
*ocx
= container_of(msix
, struct thunderx_ocx
,
1130 msix_ent
[msix
->entry
]);
1132 irqreturn_t ret
= IRQ_NONE
;
1135 struct ocx_com_err_ctx
*ctx
;
1140 msg
= kmalloc(OCX_MESSAGE_SIZE
, GFP_KERNEL
);
1141 other
= kmalloc(OCX_OTHER_SIZE
, GFP_KERNEL
);
1146 while (CIRC_CNT(ocx
->com_ring_head
, ocx
->com_ring_tail
,
1147 ARRAY_SIZE(ocx
->com_err_ctx
))) {
1148 tail
= ring_pos(ocx
->com_ring_tail
,
1149 ARRAY_SIZE(ocx
->com_err_ctx
));
1150 ctx
= &ocx
->com_err_ctx
[tail
];
1152 snprintf(msg
, OCX_MESSAGE_SIZE
, "%s: OCX_COM_INT: %016llx",
1153 ocx
->edac_dev
->ctl_name
, ctx
->reg_com_int
);
1155 decode_register(other
, OCX_OTHER_SIZE
,
1156 ocx_com_errors
, ctx
->reg_com_int
);
1158 strncat(msg
, other
, OCX_MESSAGE_SIZE
);
1160 for (lane
= 0; lane
< OCX_RX_LANES
; lane
++)
1161 if (ctx
->reg_com_int
& BIT(lane
)) {
1162 snprintf(other
, OCX_OTHER_SIZE
,
1163 "\n\tOCX_LNE_INT[%02d]: %016llx OCX_LNE_STAT11[%02d]: %016llx",
1164 lane
, ctx
->reg_lane_int
[lane
],
1165 lane
, ctx
->reg_lane_stat11
[lane
]);
1167 strncat(msg
, other
, OCX_MESSAGE_SIZE
);
1169 decode_register(other
, OCX_OTHER_SIZE
,
1171 ctx
->reg_lane_int
[lane
]);
1172 strncat(msg
, other
, OCX_MESSAGE_SIZE
);
1175 if (ctx
->reg_com_int
& OCX_COM_INT_CE
)
1176 edac_device_handle_ce(ocx
->edac_dev
, 0, 0, msg
);
1178 ocx
->com_ring_tail
++;
1190 static irqreturn_t
thunderx_ocx_lnk_isr(int irq
, void *irq_id
)
1192 struct msix_entry
*msix
= irq_id
;
1193 struct thunderx_ocx
*ocx
= container_of(msix
, struct thunderx_ocx
,
1194 msix_ent
[msix
->entry
]);
1195 unsigned long head
= ring_pos(ocx
->link_ring_head
,
1196 ARRAY_SIZE(ocx
->link_err_ctx
));
1197 struct ocx_link_err_ctx
*ctx
= &ocx
->link_err_ctx
[head
];
1199 ctx
->link
= msix
->entry
;
1200 ctx
->reg_com_link_int
= readq(ocx
->regs
+ OCX_COM_LINKX_INT(ctx
->link
));
1202 writeq(ctx
->reg_com_link_int
, ocx
->regs
+ OCX_COM_LINKX_INT(ctx
->link
));
1204 ocx
->link_ring_head
++;
1206 return IRQ_WAKE_THREAD
;
1209 static irqreturn_t
thunderx_ocx_lnk_threaded_isr(int irq
, void *irq_id
)
1211 struct msix_entry
*msix
= irq_id
;
1212 struct thunderx_ocx
*ocx
= container_of(msix
, struct thunderx_ocx
,
1213 msix_ent
[msix
->entry
]);
1214 irqreturn_t ret
= IRQ_NONE
;
1216 struct ocx_link_err_ctx
*ctx
;
1221 msg
= kmalloc(OCX_MESSAGE_SIZE
, GFP_KERNEL
);
1222 other
= kmalloc(OCX_OTHER_SIZE
, GFP_KERNEL
);
1227 while (CIRC_CNT(ocx
->link_ring_head
, ocx
->link_ring_tail
,
1228 ARRAY_SIZE(ocx
->link_err_ctx
))) {
1229 tail
= ring_pos(ocx
->link_ring_head
,
1230 ARRAY_SIZE(ocx
->link_err_ctx
));
1232 ctx
= &ocx
->link_err_ctx
[tail
];
1234 snprintf(msg
, OCX_MESSAGE_SIZE
,
1235 "%s: OCX_COM_LINK_INT[%d]: %016llx",
1236 ocx
->edac_dev
->ctl_name
,
1237 ctx
->link
, ctx
->reg_com_link_int
);
1239 decode_register(other
, OCX_OTHER_SIZE
,
1240 ocx_com_link_errors
, ctx
->reg_com_link_int
);
1242 strncat(msg
, other
, OCX_MESSAGE_SIZE
);
1244 if (ctx
->reg_com_link_int
& OCX_COM_LINK_INT_UE
)
1245 edac_device_handle_ue(ocx
->edac_dev
, 0, 0, msg
);
1246 else if (ctx
->reg_com_link_int
& OCX_COM_LINK_INT_CE
)
1247 edac_device_handle_ce(ocx
->edac_dev
, 0, 0, msg
);
1249 ocx
->link_ring_tail
++;
1260 #define OCX_DEBUGFS_ATTR(_name, _reg) DEBUGFS_REG_ATTR(ocx, _name, _reg)
1262 OCX_DEBUGFS_ATTR(tlk0_ecc_ctl
, OCX_TLKX_ECC_CTL(0));
1263 OCX_DEBUGFS_ATTR(tlk1_ecc_ctl
, OCX_TLKX_ECC_CTL(1));
1264 OCX_DEBUGFS_ATTR(tlk2_ecc_ctl
, OCX_TLKX_ECC_CTL(2));
1266 OCX_DEBUGFS_ATTR(rlk0_ecc_ctl
, OCX_RLKX_ECC_CTL(0));
1267 OCX_DEBUGFS_ATTR(rlk1_ecc_ctl
, OCX_RLKX_ECC_CTL(1));
1268 OCX_DEBUGFS_ATTR(rlk2_ecc_ctl
, OCX_RLKX_ECC_CTL(2));
1270 OCX_DEBUGFS_ATTR(com_link0_int
, OCX_COM_LINKX_INT_W1S(0));
1271 OCX_DEBUGFS_ATTR(com_link1_int
, OCX_COM_LINKX_INT_W1S(1));
1272 OCX_DEBUGFS_ATTR(com_link2_int
, OCX_COM_LINKX_INT_W1S(2));
1274 OCX_DEBUGFS_ATTR(lne00_badcnt
, OCX_LNE_BAD_CNT(0));
1275 OCX_DEBUGFS_ATTR(lne01_badcnt
, OCX_LNE_BAD_CNT(1));
1276 OCX_DEBUGFS_ATTR(lne02_badcnt
, OCX_LNE_BAD_CNT(2));
1277 OCX_DEBUGFS_ATTR(lne03_badcnt
, OCX_LNE_BAD_CNT(3));
1278 OCX_DEBUGFS_ATTR(lne04_badcnt
, OCX_LNE_BAD_CNT(4));
1279 OCX_DEBUGFS_ATTR(lne05_badcnt
, OCX_LNE_BAD_CNT(5));
1280 OCX_DEBUGFS_ATTR(lne06_badcnt
, OCX_LNE_BAD_CNT(6));
1281 OCX_DEBUGFS_ATTR(lne07_badcnt
, OCX_LNE_BAD_CNT(7));
1283 OCX_DEBUGFS_ATTR(lne08_badcnt
, OCX_LNE_BAD_CNT(8));
1284 OCX_DEBUGFS_ATTR(lne09_badcnt
, OCX_LNE_BAD_CNT(9));
1285 OCX_DEBUGFS_ATTR(lne10_badcnt
, OCX_LNE_BAD_CNT(10));
1286 OCX_DEBUGFS_ATTR(lne11_badcnt
, OCX_LNE_BAD_CNT(11));
1287 OCX_DEBUGFS_ATTR(lne12_badcnt
, OCX_LNE_BAD_CNT(12));
1288 OCX_DEBUGFS_ATTR(lne13_badcnt
, OCX_LNE_BAD_CNT(13));
1289 OCX_DEBUGFS_ATTR(lne14_badcnt
, OCX_LNE_BAD_CNT(14));
1290 OCX_DEBUGFS_ATTR(lne15_badcnt
, OCX_LNE_BAD_CNT(15));
1292 OCX_DEBUGFS_ATTR(lne16_badcnt
, OCX_LNE_BAD_CNT(16));
1293 OCX_DEBUGFS_ATTR(lne17_badcnt
, OCX_LNE_BAD_CNT(17));
1294 OCX_DEBUGFS_ATTR(lne18_badcnt
, OCX_LNE_BAD_CNT(18));
1295 OCX_DEBUGFS_ATTR(lne19_badcnt
, OCX_LNE_BAD_CNT(19));
1296 OCX_DEBUGFS_ATTR(lne20_badcnt
, OCX_LNE_BAD_CNT(20));
1297 OCX_DEBUGFS_ATTR(lne21_badcnt
, OCX_LNE_BAD_CNT(21));
1298 OCX_DEBUGFS_ATTR(lne22_badcnt
, OCX_LNE_BAD_CNT(22));
1299 OCX_DEBUGFS_ATTR(lne23_badcnt
, OCX_LNE_BAD_CNT(23));
1301 OCX_DEBUGFS_ATTR(com_int
, OCX_COM_INT_W1S
);
1303 struct debugfs_entry
*ocx_dfs_ents
[] = {
1304 &debugfs_tlk0_ecc_ctl
,
1305 &debugfs_tlk1_ecc_ctl
,
1306 &debugfs_tlk2_ecc_ctl
,
1308 &debugfs_rlk0_ecc_ctl
,
1309 &debugfs_rlk1_ecc_ctl
,
1310 &debugfs_rlk2_ecc_ctl
,
1312 &debugfs_com_link0_int
,
1313 &debugfs_com_link1_int
,
1314 &debugfs_com_link2_int
,
1316 &debugfs_lne00_badcnt
,
1317 &debugfs_lne01_badcnt
,
1318 &debugfs_lne02_badcnt
,
1319 &debugfs_lne03_badcnt
,
1320 &debugfs_lne04_badcnt
,
1321 &debugfs_lne05_badcnt
,
1322 &debugfs_lne06_badcnt
,
1323 &debugfs_lne07_badcnt
,
1324 &debugfs_lne08_badcnt
,
1325 &debugfs_lne09_badcnt
,
1326 &debugfs_lne10_badcnt
,
1327 &debugfs_lne11_badcnt
,
1328 &debugfs_lne12_badcnt
,
1329 &debugfs_lne13_badcnt
,
1330 &debugfs_lne14_badcnt
,
1331 &debugfs_lne15_badcnt
,
1332 &debugfs_lne16_badcnt
,
1333 &debugfs_lne17_badcnt
,
1334 &debugfs_lne18_badcnt
,
1335 &debugfs_lne19_badcnt
,
1336 &debugfs_lne20_badcnt
,
1337 &debugfs_lne21_badcnt
,
1338 &debugfs_lne22_badcnt
,
1339 &debugfs_lne23_badcnt
,
1344 static const struct pci_device_id thunderx_ocx_pci_tbl
[] = {
1345 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_OCX
) },
1349 static void thunderx_ocx_clearstats(struct thunderx_ocx
*ocx
)
1351 int lane
, stat
, cfg
;
1353 for (lane
= 0; lane
< OCX_RX_LANES
; lane
++) {
1354 cfg
= readq(ocx
->regs
+ OCX_LNE_CFG(lane
));
1355 cfg
|= OCX_LNE_CFG_RX_STAT_RDCLR
;
1356 cfg
&= ~OCX_LNE_CFG_RX_STAT_ENA
;
1357 writeq(cfg
, ocx
->regs
+ OCX_LNE_CFG(lane
));
1359 for (stat
= 0; stat
< OCX_RX_LANE_STATS
; stat
++)
1360 readq(ocx
->regs
+ OCX_LNE_STAT(lane
, stat
));
1364 static int thunderx_ocx_probe(struct pci_dev
*pdev
,
1365 const struct pci_device_id
*id
)
1367 struct thunderx_ocx
*ocx
;
1368 struct edac_device_ctl_info
*edac_dev
;
1375 ret
= pcim_enable_device(pdev
);
1377 dev_err(&pdev
->dev
, "Cannot enable PCI device: %d\n", ret
);
1381 ret
= pcim_iomap_regions(pdev
, BIT(0), "thunderx_ocx");
1383 dev_err(&pdev
->dev
, "Cannot map PCI resources: %d\n", ret
);
1387 idx
= edac_device_alloc_index();
1388 snprintf(name
, sizeof(name
), "OCX%d", idx
);
1389 edac_dev
= edac_device_alloc_ctl_info(sizeof(struct thunderx_ocx
),
1393 dev_err(&pdev
->dev
, "Cannot allocate EDAC device: %d\n", ret
);
1396 ocx
= edac_dev
->pvt_info
;
1397 ocx
->edac_dev
= edac_dev
;
1398 ocx
->com_ring_head
= 0;
1399 ocx
->com_ring_tail
= 0;
1400 ocx
->link_ring_head
= 0;
1401 ocx
->link_ring_tail
= 0;
1403 ocx
->regs
= pcim_iomap_table(pdev
)[0];
1405 dev_err(&pdev
->dev
, "Cannot map PCI resources: %d\n", ret
);
1412 for (i
= 0; i
< OCX_INTS
; i
++) {
1413 ocx
->msix_ent
[i
].entry
= i
;
1414 ocx
->msix_ent
[i
].vector
= 0;
1417 ret
= pci_enable_msix_exact(pdev
, ocx
->msix_ent
, OCX_INTS
);
1419 dev_err(&pdev
->dev
, "Cannot enable interrupt: %d\n", ret
);
1423 for (i
= 0; i
< OCX_INTS
; i
++) {
1424 ret
= devm_request_threaded_irq(&pdev
->dev
,
1425 ocx
->msix_ent
[i
].vector
,
1427 thunderx_ocx_com_isr
:
1428 thunderx_ocx_lnk_isr
,
1430 thunderx_ocx_com_threaded_isr
:
1431 thunderx_ocx_lnk_threaded_isr
,
1432 0, "[EDAC] ThunderX OCX",
1438 edac_dev
->dev
= &pdev
->dev
;
1439 edac_dev
->dev_name
= dev_name(&pdev
->dev
);
1440 edac_dev
->mod_name
= "thunderx-ocx";
1441 edac_dev
->ctl_name
= "thunderx-ocx";
1443 ret
= edac_device_add_device(edac_dev
);
1445 dev_err(&pdev
->dev
, "Cannot add EDAC device: %d\n", ret
);
1449 if (IS_ENABLED(CONFIG_EDAC_DEBUG
)) {
1450 ocx
->debugfs
= edac_debugfs_create_dir(pdev
->dev
.kobj
.name
);
1452 ret
= thunderx_create_debugfs_nodes(ocx
->debugfs
,
1455 ARRAY_SIZE(ocx_dfs_ents
));
1456 if (ret
!= ARRAY_SIZE(ocx_dfs_ents
)) {
1457 dev_warn(&pdev
->dev
, "Error creating debugfs entries: %d%s\n",
1458 ret
, ret
>= 0 ? " created" : "");
1462 pci_set_drvdata(pdev
, edac_dev
);
1464 thunderx_ocx_clearstats(ocx
);
1466 for (i
= 0; i
< OCX_RX_LANES
; i
++) {
1467 writeq(OCX_LNE_INT_ENA_ALL
,
1468 ocx
->regs
+ OCX_LNE_INT_EN(i
));
1470 reg
= readq(ocx
->regs
+ OCX_LNE_INT(i
));
1471 writeq(reg
, ocx
->regs
+ OCX_LNE_INT(i
));
1475 for (i
= 0; i
< OCX_LINK_INTS
; i
++) {
1476 reg
= readq(ocx
->regs
+ OCX_COM_LINKX_INT(i
));
1477 writeq(reg
, ocx
->regs
+ OCX_COM_LINKX_INT(i
));
1479 writeq(OCX_COM_LINKX_INT_ENA_ALL
,
1480 ocx
->regs
+ OCX_COM_LINKX_INT_ENA_W1S(i
));
1483 reg
= readq(ocx
->regs
+ OCX_COM_INT
);
1484 writeq(reg
, ocx
->regs
+ OCX_COM_INT
);
1486 writeq(OCX_COM_INT_ENA_ALL
, ocx
->regs
+ OCX_COM_INT_ENA_W1S
);
1490 edac_device_free_ctl_info(edac_dev
);
1495 static void thunderx_ocx_remove(struct pci_dev
*pdev
)
1497 struct edac_device_ctl_info
*edac_dev
= pci_get_drvdata(pdev
);
1498 struct thunderx_ocx
*ocx
= edac_dev
->pvt_info
;
1501 writeq(OCX_COM_INT_ENA_ALL
, ocx
->regs
+ OCX_COM_INT_ENA_W1C
);
1503 for (i
= 0; i
< OCX_INTS
; i
++) {
1504 writeq(OCX_COM_LINKX_INT_ENA_ALL
,
1505 ocx
->regs
+ OCX_COM_LINKX_INT_ENA_W1C(i
));
1508 edac_debugfs_remove_recursive(ocx
->debugfs
);
1510 edac_device_del_device(&pdev
->dev
);
1511 edac_device_free_ctl_info(edac_dev
);
1514 MODULE_DEVICE_TABLE(pci
, thunderx_ocx_pci_tbl
);
1516 static struct pci_driver thunderx_ocx_driver
= {
1517 .name
= "thunderx_ocx_edac",
1518 .probe
= thunderx_ocx_probe
,
1519 .remove
= thunderx_ocx_remove
,
1520 .id_table
= thunderx_ocx_pci_tbl
,
1523 /*---------------------- L2C driver ---------------------------------*/
1525 #define PCI_DEVICE_ID_THUNDER_L2C_TAD 0xa02e
1526 #define PCI_DEVICE_ID_THUNDER_L2C_CBC 0xa02f
1527 #define PCI_DEVICE_ID_THUNDER_L2C_MCI 0xa030
1529 #define L2C_TAD_INT_W1C 0x40000
1530 #define L2C_TAD_INT_W1S 0x40008
1532 #define L2C_TAD_INT_ENA_W1C 0x40020
1533 #define L2C_TAD_INT_ENA_W1S 0x40028
1536 #define L2C_TAD_INT_L2DDBE BIT(1)
1537 #define L2C_TAD_INT_SBFSBE BIT(2)
1538 #define L2C_TAD_INT_SBFDBE BIT(3)
1539 #define L2C_TAD_INT_FBFSBE BIT(4)
1540 #define L2C_TAD_INT_FBFDBE BIT(5)
1541 #define L2C_TAD_INT_TAGDBE BIT(9)
1542 #define L2C_TAD_INT_RDDISLMC BIT(15)
1543 #define L2C_TAD_INT_WRDISLMC BIT(16)
1544 #define L2C_TAD_INT_LFBTO BIT(17)
1545 #define L2C_TAD_INT_GSYNCTO BIT(18)
1546 #define L2C_TAD_INT_RTGSBE BIT(32)
1547 #define L2C_TAD_INT_RTGDBE BIT(33)
1548 #define L2C_TAD_INT_RDDISOCI BIT(34)
1549 #define L2C_TAD_INT_WRDISOCI BIT(35)
1551 #define L2C_TAD_INT_ECC (L2C_TAD_INT_L2DDBE | \
1552 L2C_TAD_INT_SBFSBE | L2C_TAD_INT_SBFDBE | \
1553 L2C_TAD_INT_FBFSBE | L2C_TAD_INT_FBFDBE)
1555 #define L2C_TAD_INT_CE (L2C_TAD_INT_SBFSBE | \
1558 #define L2C_TAD_INT_UE (L2C_TAD_INT_L2DDBE | \
1559 L2C_TAD_INT_SBFDBE | \
1560 L2C_TAD_INT_FBFDBE | \
1561 L2C_TAD_INT_TAGDBE | \
1562 L2C_TAD_INT_RTGDBE | \
1563 L2C_TAD_INT_WRDISOCI | \
1564 L2C_TAD_INT_RDDISOCI | \
1565 L2C_TAD_INT_WRDISLMC | \
1566 L2C_TAD_INT_RDDISLMC | \
1567 L2C_TAD_INT_LFBTO | \
1568 L2C_TAD_INT_GSYNCTO)
1570 static const struct error_descr l2_tad_errors
[] = {
1572 .type
= ERR_CORRECTED
,
1573 .mask
= L2C_TAD_INT_SBFSBE
,
1574 .descr
= "SBF single-bit error",
1577 .type
= ERR_CORRECTED
,
1578 .mask
= L2C_TAD_INT_FBFSBE
,
1579 .descr
= "FBF single-bit error",
1582 .type
= ERR_UNCORRECTED
,
1583 .mask
= L2C_TAD_INT_L2DDBE
,
1584 .descr
= "L2D double-bit error",
1587 .type
= ERR_UNCORRECTED
,
1588 .mask
= L2C_TAD_INT_SBFDBE
,
1589 .descr
= "SBF double-bit error",
1592 .type
= ERR_UNCORRECTED
,
1593 .mask
= L2C_TAD_INT_FBFDBE
,
1594 .descr
= "FBF double-bit error",
1597 .type
= ERR_UNCORRECTED
,
1598 .mask
= L2C_TAD_INT_TAGDBE
,
1599 .descr
= "TAG double-bit error",
1602 .type
= ERR_UNCORRECTED
,
1603 .mask
= L2C_TAD_INT_RTGDBE
,
1604 .descr
= "RTG double-bit error",
1607 .type
= ERR_UNCORRECTED
,
1608 .mask
= L2C_TAD_INT_WRDISOCI
,
1609 .descr
= "Write to a disabled CCPI",
1612 .type
= ERR_UNCORRECTED
,
1613 .mask
= L2C_TAD_INT_RDDISOCI
,
1614 .descr
= "Read from a disabled CCPI",
1617 .type
= ERR_UNCORRECTED
,
1618 .mask
= L2C_TAD_INT_WRDISLMC
,
1619 .descr
= "Write to a disabled LMC",
1622 .type
= ERR_UNCORRECTED
,
1623 .mask
= L2C_TAD_INT_RDDISLMC
,
1624 .descr
= "Read from a disabled LMC",
1627 .type
= ERR_UNCORRECTED
,
1628 .mask
= L2C_TAD_INT_LFBTO
,
1629 .descr
= "LFB entry timeout",
1632 .type
= ERR_UNCORRECTED
,
1633 .mask
= L2C_TAD_INT_GSYNCTO
,
1634 .descr
= "Global sync CCPI timeout",
1639 #define L2C_TAD_INT_TAG (L2C_TAD_INT_TAGDBE)
1641 #define L2C_TAD_INT_RTG (L2C_TAD_INT_RTGDBE)
1643 #define L2C_TAD_INT_DISLMC (L2C_TAD_INT_WRDISLMC | L2C_TAD_INT_RDDISLMC)
1645 #define L2C_TAD_INT_DISOCI (L2C_TAD_INT_WRDISOCI | L2C_TAD_INT_RDDISOCI)
1647 #define L2C_TAD_INT_ENA_ALL (L2C_TAD_INT_ECC | L2C_TAD_INT_TAG | \
1649 L2C_TAD_INT_DISLMC | L2C_TAD_INT_DISOCI | \
1652 #define L2C_TAD_TIMETWO 0x50000
1653 #define L2C_TAD_TIMEOUT 0x50100
1654 #define L2C_TAD_ERR 0x60000
1655 #define L2C_TAD_TQD_ERR 0x60100
1656 #define L2C_TAD_TTG_ERR 0x60200
1659 #define L2C_CBC_INT_W1C 0x60000
1661 #define L2C_CBC_INT_RSDSBE BIT(0)
1662 #define L2C_CBC_INT_RSDDBE BIT(1)
1664 #define L2C_CBC_INT_RSD (L2C_CBC_INT_RSDSBE | L2C_CBC_INT_RSDDBE)
1666 #define L2C_CBC_INT_MIBSBE BIT(4)
1667 #define L2C_CBC_INT_MIBDBE BIT(5)
1669 #define L2C_CBC_INT_MIB (L2C_CBC_INT_MIBSBE | L2C_CBC_INT_MIBDBE)
1671 #define L2C_CBC_INT_IORDDISOCI BIT(6)
1672 #define L2C_CBC_INT_IOWRDISOCI BIT(7)
1674 #define L2C_CBC_INT_IODISOCI (L2C_CBC_INT_IORDDISOCI | \
1675 L2C_CBC_INT_IOWRDISOCI)
1677 #define L2C_CBC_INT_CE (L2C_CBC_INT_RSDSBE | L2C_CBC_INT_MIBSBE)
1678 #define L2C_CBC_INT_UE (L2C_CBC_INT_RSDDBE | L2C_CBC_INT_MIBDBE)
1681 static const struct error_descr l2_cbc_errors
[] = {
1683 .type
= ERR_CORRECTED
,
1684 .mask
= L2C_CBC_INT_RSDSBE
,
1685 .descr
= "RSD single-bit error",
1688 .type
= ERR_CORRECTED
,
1689 .mask
= L2C_CBC_INT_MIBSBE
,
1690 .descr
= "MIB single-bit error",
1693 .type
= ERR_UNCORRECTED
,
1694 .mask
= L2C_CBC_INT_RSDDBE
,
1695 .descr
= "RSD double-bit error",
1698 .type
= ERR_UNCORRECTED
,
1699 .mask
= L2C_CBC_INT_MIBDBE
,
1700 .descr
= "MIB double-bit error",
1703 .type
= ERR_UNCORRECTED
,
1704 .mask
= L2C_CBC_INT_IORDDISOCI
,
1705 .descr
= "Read from a disabled CCPI",
1708 .type
= ERR_UNCORRECTED
,
1709 .mask
= L2C_CBC_INT_IOWRDISOCI
,
1710 .descr
= "Write to a disabled CCPI",
1715 #define L2C_CBC_INT_W1S 0x60008
1716 #define L2C_CBC_INT_ENA_W1C 0x60020
1718 #define L2C_CBC_INT_ENA_ALL (L2C_CBC_INT_RSD | L2C_CBC_INT_MIB | \
1719 L2C_CBC_INT_IODISOCI)
1721 #define L2C_CBC_INT_ENA_W1S 0x60028
1723 #define L2C_CBC_IODISOCIERR 0x80008
1724 #define L2C_CBC_IOCERR 0x80010
1725 #define L2C_CBC_RSDERR 0x80018
1726 #define L2C_CBC_MIBERR 0x80020
1729 #define L2C_MCI_INT_W1C 0x0
1731 #define L2C_MCI_INT_VBFSBE BIT(0)
1732 #define L2C_MCI_INT_VBFDBE BIT(1)
1734 static const struct error_descr l2_mci_errors
[] = {
1736 .type
= ERR_CORRECTED
,
1737 .mask
= L2C_MCI_INT_VBFSBE
,
1738 .descr
= "VBF single-bit error",
1741 .type
= ERR_UNCORRECTED
,
1742 .mask
= L2C_MCI_INT_VBFDBE
,
1743 .descr
= "VBF double-bit error",
1748 #define L2C_MCI_INT_W1S 0x8
1749 #define L2C_MCI_INT_ENA_W1C 0x20
1751 #define L2C_MCI_INT_ENA_ALL (L2C_MCI_INT_VBFSBE | L2C_MCI_INT_VBFDBE)
1753 #define L2C_MCI_INT_ENA_W1S 0x28
1755 #define L2C_MCI_ERR 0x10000
1757 #define L2C_MESSAGE_SIZE SZ_1K
1758 #define L2C_OTHER_SIZE (50 * ARRAY_SIZE(l2_tad_errors))
1760 struct l2c_err_ctx
{
1766 struct thunderx_l2c
{
1768 struct pci_dev
*pdev
;
1769 struct edac_device_ctl_info
*edac_dev
;
1771 struct dentry
*debugfs
;
1775 struct msix_entry msix_ent
;
1777 struct l2c_err_ctx err_ctx
[RING_ENTRIES
];
1778 unsigned long ring_head
;
1779 unsigned long ring_tail
;
1782 static irqreturn_t
thunderx_l2c_tad_isr(int irq
, void *irq_id
)
1784 struct msix_entry
*msix
= irq_id
;
1785 struct thunderx_l2c
*tad
= container_of(msix
, struct thunderx_l2c
,
1788 unsigned long head
= ring_pos(tad
->ring_head
, ARRAY_SIZE(tad
->err_ctx
));
1789 struct l2c_err_ctx
*ctx
= &tad
->err_ctx
[head
];
1791 ctx
->reg_int
= readq(tad
->regs
+ L2C_TAD_INT_W1C
);
1793 if (ctx
->reg_int
& L2C_TAD_INT_ECC
) {
1794 ctx
->reg_ext_name
= "TQD_ERR";
1795 ctx
->reg_ext
= readq(tad
->regs
+ L2C_TAD_TQD_ERR
);
1796 } else if (ctx
->reg_int
& L2C_TAD_INT_TAG
) {
1797 ctx
->reg_ext_name
= "TTG_ERR";
1798 ctx
->reg_ext
= readq(tad
->regs
+ L2C_TAD_TTG_ERR
);
1799 } else if (ctx
->reg_int
& L2C_TAD_INT_LFBTO
) {
1800 ctx
->reg_ext_name
= "TIMEOUT";
1801 ctx
->reg_ext
= readq(tad
->regs
+ L2C_TAD_TIMEOUT
);
1802 } else if (ctx
->reg_int
& L2C_TAD_INT_DISOCI
) {
1803 ctx
->reg_ext_name
= "ERR";
1804 ctx
->reg_ext
= readq(tad
->regs
+ L2C_TAD_ERR
);
1807 writeq(ctx
->reg_int
, tad
->regs
+ L2C_TAD_INT_W1C
);
1811 return IRQ_WAKE_THREAD
;
1814 static irqreturn_t
thunderx_l2c_cbc_isr(int irq
, void *irq_id
)
1816 struct msix_entry
*msix
= irq_id
;
1817 struct thunderx_l2c
*cbc
= container_of(msix
, struct thunderx_l2c
,
1820 unsigned long head
= ring_pos(cbc
->ring_head
, ARRAY_SIZE(cbc
->err_ctx
));
1821 struct l2c_err_ctx
*ctx
= &cbc
->err_ctx
[head
];
1823 ctx
->reg_int
= readq(cbc
->regs
+ L2C_CBC_INT_W1C
);
1825 if (ctx
->reg_int
& L2C_CBC_INT_RSD
) {
1826 ctx
->reg_ext_name
= "RSDERR";
1827 ctx
->reg_ext
= readq(cbc
->regs
+ L2C_CBC_RSDERR
);
1828 } else if (ctx
->reg_int
& L2C_CBC_INT_MIB
) {
1829 ctx
->reg_ext_name
= "MIBERR";
1830 ctx
->reg_ext
= readq(cbc
->regs
+ L2C_CBC_MIBERR
);
1831 } else if (ctx
->reg_int
& L2C_CBC_INT_IODISOCI
) {
1832 ctx
->reg_ext_name
= "IODISOCIERR";
1833 ctx
->reg_ext
= readq(cbc
->regs
+ L2C_CBC_IODISOCIERR
);
1836 writeq(ctx
->reg_int
, cbc
->regs
+ L2C_CBC_INT_W1C
);
1840 return IRQ_WAKE_THREAD
;
1843 static irqreturn_t
thunderx_l2c_mci_isr(int irq
, void *irq_id
)
1845 struct msix_entry
*msix
= irq_id
;
1846 struct thunderx_l2c
*mci
= container_of(msix
, struct thunderx_l2c
,
1849 unsigned long head
= ring_pos(mci
->ring_head
, ARRAY_SIZE(mci
->err_ctx
));
1850 struct l2c_err_ctx
*ctx
= &mci
->err_ctx
[head
];
1852 ctx
->reg_int
= readq(mci
->regs
+ L2C_MCI_INT_W1C
);
1853 ctx
->reg_ext
= readq(mci
->regs
+ L2C_MCI_ERR
);
1855 writeq(ctx
->reg_int
, mci
->regs
+ L2C_MCI_INT_W1C
);
1857 ctx
->reg_ext_name
= "ERR";
1861 return IRQ_WAKE_THREAD
;
1864 static irqreturn_t
thunderx_l2c_threaded_isr(int irq
, void *irq_id
)
1866 struct msix_entry
*msix
= irq_id
;
1867 struct thunderx_l2c
*l2c
= container_of(msix
, struct thunderx_l2c
,
1870 unsigned long tail
= ring_pos(l2c
->ring_tail
, ARRAY_SIZE(l2c
->err_ctx
));
1871 struct l2c_err_ctx
*ctx
= &l2c
->err_ctx
[tail
];
1872 irqreturn_t ret
= IRQ_NONE
;
1874 u64 mask_ue
, mask_ce
;
1875 const struct error_descr
*l2_errors
;
1881 msg
= kmalloc(OCX_MESSAGE_SIZE
, GFP_KERNEL
);
1882 other
= kmalloc(OCX_OTHER_SIZE
, GFP_KERNEL
);
1887 switch (l2c
->pdev
->device
) {
1888 case PCI_DEVICE_ID_THUNDER_L2C_TAD
:
1889 reg_int_name
= "L2C_TAD_INT";
1890 mask_ue
= L2C_TAD_INT_UE
;
1891 mask_ce
= L2C_TAD_INT_CE
;
1892 l2_errors
= l2_tad_errors
;
1894 case PCI_DEVICE_ID_THUNDER_L2C_CBC
:
1895 reg_int_name
= "L2C_CBC_INT";
1896 mask_ue
= L2C_CBC_INT_UE
;
1897 mask_ce
= L2C_CBC_INT_CE
;
1898 l2_errors
= l2_cbc_errors
;
1900 case PCI_DEVICE_ID_THUNDER_L2C_MCI
:
1901 reg_int_name
= "L2C_MCI_INT";
1902 mask_ue
= L2C_MCI_INT_VBFDBE
;
1903 mask_ce
= L2C_MCI_INT_VBFSBE
;
1904 l2_errors
= l2_mci_errors
;
1907 dev_err(&l2c
->pdev
->dev
, "Unsupported device: %04x\n",
1912 while (CIRC_CNT(l2c
->ring_head
, l2c
->ring_tail
,
1913 ARRAY_SIZE(l2c
->err_ctx
))) {
1914 snprintf(msg
, L2C_MESSAGE_SIZE
,
1915 "%s: %s: %016llx, %s: %016llx",
1916 l2c
->edac_dev
->ctl_name
, reg_int_name
, ctx
->reg_int
,
1917 ctx
->reg_ext_name
, ctx
->reg_ext
);
1919 decode_register(other
, L2C_OTHER_SIZE
, l2_errors
, ctx
->reg_int
);
1921 strncat(msg
, other
, L2C_MESSAGE_SIZE
);
1923 if (ctx
->reg_int
& mask_ue
)
1924 edac_device_handle_ue(l2c
->edac_dev
, 0, 0, msg
);
1925 else if (ctx
->reg_int
& mask_ce
)
1926 edac_device_handle_ce(l2c
->edac_dev
, 0, 0, msg
);
1940 #define L2C_DEBUGFS_ATTR(_name, _reg) DEBUGFS_REG_ATTR(l2c, _name, _reg)
1942 L2C_DEBUGFS_ATTR(tad_int
, L2C_TAD_INT_W1S
);
1944 struct debugfs_entry
*l2c_tad_dfs_ents
[] = {
1948 L2C_DEBUGFS_ATTR(cbc_int
, L2C_CBC_INT_W1S
);
1950 struct debugfs_entry
*l2c_cbc_dfs_ents
[] = {
1954 L2C_DEBUGFS_ATTR(mci_int
, L2C_MCI_INT_W1S
);
1956 struct debugfs_entry
*l2c_mci_dfs_ents
[] = {
1960 static const struct pci_device_id thunderx_l2c_pci_tbl
[] = {
1961 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_L2C_TAD
), },
1962 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_L2C_CBC
), },
1963 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_L2C_MCI
), },
1967 static int thunderx_l2c_probe(struct pci_dev
*pdev
,
1968 const struct pci_device_id
*id
)
1970 struct thunderx_l2c
*l2c
;
1971 struct edac_device_ctl_info
*edac_dev
;
1972 struct debugfs_entry
**l2c_devattr
;
1974 irqreturn_t (*thunderx_l2c_isr
)(int, void *) = NULL
;
1977 u64 reg_en_offs
, reg_en_mask
;
1981 ret
= pcim_enable_device(pdev
);
1983 dev_err(&pdev
->dev
, "Cannot enable PCI device: %d\n", ret
);
1987 ret
= pcim_iomap_regions(pdev
, BIT(0), "thunderx_l2c");
1989 dev_err(&pdev
->dev
, "Cannot map PCI resources: %d\n", ret
);
1993 switch (pdev
->device
) {
1994 case PCI_DEVICE_ID_THUNDER_L2C_TAD
:
1995 thunderx_l2c_isr
= thunderx_l2c_tad_isr
;
1996 l2c_devattr
= l2c_tad_dfs_ents
;
1997 dfs_entries
= ARRAY_SIZE(l2c_tad_dfs_ents
);
1999 reg_en_offs
= L2C_TAD_INT_ENA_W1S
;
2000 reg_en_mask
= L2C_TAD_INT_ENA_ALL
;
2002 case PCI_DEVICE_ID_THUNDER_L2C_CBC
:
2003 thunderx_l2c_isr
= thunderx_l2c_cbc_isr
;
2004 l2c_devattr
= l2c_cbc_dfs_ents
;
2005 dfs_entries
= ARRAY_SIZE(l2c_cbc_dfs_ents
);
2007 reg_en_offs
= L2C_CBC_INT_ENA_W1S
;
2008 reg_en_mask
= L2C_CBC_INT_ENA_ALL
;
2010 case PCI_DEVICE_ID_THUNDER_L2C_MCI
:
2011 thunderx_l2c_isr
= thunderx_l2c_mci_isr
;
2012 l2c_devattr
= l2c_mci_dfs_ents
;
2013 dfs_entries
= ARRAY_SIZE(l2c_mci_dfs_ents
);
2015 reg_en_offs
= L2C_MCI_INT_ENA_W1S
;
2016 reg_en_mask
= L2C_MCI_INT_ENA_ALL
;
2019 //Should never ever get here
2020 dev_err(&pdev
->dev
, "Unsupported PCI device: %04x\n",
2025 idx
= edac_device_alloc_index();
2026 snprintf(name
, sizeof(name
), fmt
, idx
);
2028 edac_dev
= edac_device_alloc_ctl_info(sizeof(struct thunderx_l2c
),
2029 name
, 1, "L2C", 1, 0,
2032 dev_err(&pdev
->dev
, "Cannot allocate EDAC device\n");
2036 l2c
= edac_dev
->pvt_info
;
2037 l2c
->edac_dev
= edac_dev
;
2039 l2c
->regs
= pcim_iomap_table(pdev
)[0];
2041 dev_err(&pdev
->dev
, "Cannot map PCI resources\n");
2051 l2c
->msix_ent
.entry
= 0;
2052 l2c
->msix_ent
.vector
= 0;
2054 ret
= pci_enable_msix_exact(pdev
, &l2c
->msix_ent
, 1);
2056 dev_err(&pdev
->dev
, "Cannot enable interrupt: %d\n", ret
);
2060 ret
= devm_request_threaded_irq(&pdev
->dev
, l2c
->msix_ent
.vector
,
2062 thunderx_l2c_threaded_isr
,
2063 0, "[EDAC] ThunderX L2C",
2068 edac_dev
->dev
= &pdev
->dev
;
2069 edac_dev
->dev_name
= dev_name(&pdev
->dev
);
2070 edac_dev
->mod_name
= "thunderx-l2c";
2071 edac_dev
->ctl_name
= "thunderx-l2c";
2073 ret
= edac_device_add_device(edac_dev
);
2075 dev_err(&pdev
->dev
, "Cannot add EDAC device: %d\n", ret
);
2079 if (IS_ENABLED(CONFIG_EDAC_DEBUG
)) {
2080 l2c
->debugfs
= edac_debugfs_create_dir(pdev
->dev
.kobj
.name
);
2082 ret
= thunderx_create_debugfs_nodes(l2c
->debugfs
, l2c_devattr
,
2085 if (ret
!= dfs_entries
) {
2086 dev_warn(&pdev
->dev
, "Error creating debugfs entries: %d%s\n",
2087 ret
, ret
>= 0 ? " created" : "");
2091 pci_set_drvdata(pdev
, edac_dev
);
2093 writeq(reg_en_mask
, l2c
->regs
+ reg_en_offs
);
2098 edac_device_free_ctl_info(edac_dev
);
2103 static void thunderx_l2c_remove(struct pci_dev
*pdev
)
2105 struct edac_device_ctl_info
*edac_dev
= pci_get_drvdata(pdev
);
2106 struct thunderx_l2c
*l2c
= edac_dev
->pvt_info
;
2108 switch (pdev
->device
) {
2109 case PCI_DEVICE_ID_THUNDER_L2C_TAD
:
2110 writeq(L2C_TAD_INT_ENA_ALL
, l2c
->regs
+ L2C_TAD_INT_ENA_W1C
);
2112 case PCI_DEVICE_ID_THUNDER_L2C_CBC
:
2113 writeq(L2C_CBC_INT_ENA_ALL
, l2c
->regs
+ L2C_CBC_INT_ENA_W1C
);
2115 case PCI_DEVICE_ID_THUNDER_L2C_MCI
:
2116 writeq(L2C_MCI_INT_ENA_ALL
, l2c
->regs
+ L2C_MCI_INT_ENA_W1C
);
2120 edac_debugfs_remove_recursive(l2c
->debugfs
);
2122 edac_device_del_device(&pdev
->dev
);
2123 edac_device_free_ctl_info(edac_dev
);
2126 MODULE_DEVICE_TABLE(pci
, thunderx_l2c_pci_tbl
);
2128 static struct pci_driver thunderx_l2c_driver
= {
2129 .name
= "thunderx_l2c_edac",
2130 .probe
= thunderx_l2c_probe
,
2131 .remove
= thunderx_l2c_remove
,
2132 .id_table
= thunderx_l2c_pci_tbl
,
2135 static int __init
thunderx_edac_init(void)
2139 rc
= pci_register_driver(&thunderx_lmc_driver
);
2143 rc
= pci_register_driver(&thunderx_ocx_driver
);
2147 rc
= pci_register_driver(&thunderx_l2c_driver
);
2153 pci_unregister_driver(&thunderx_ocx_driver
);
2155 pci_unregister_driver(&thunderx_lmc_driver
);
2160 static void __exit
thunderx_edac_exit(void)
2162 pci_unregister_driver(&thunderx_l2c_driver
);
2163 pci_unregister_driver(&thunderx_ocx_driver
);
2164 pci_unregister_driver(&thunderx_lmc_driver
);
2168 module_init(thunderx_edac_init
);
2169 module_exit(thunderx_edac_exit
);
2171 MODULE_LICENSE("GPL v2");
2172 MODULE_AUTHOR("Cavium, Inc.");
2173 MODULE_DESCRIPTION("EDAC Driver for Cavium ThunderX");