drivers/extcon/extcon-intel-cht-wc.c

   1 /*
   2  * Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC
   3  * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
   4  *
   5  * Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
   6  * Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  */
  17
  18 #include <linux/extcon-provider.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/kernel.h>
  21 #include <linux/mfd/intel_soc_pmic.h>
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/slab.h>
  26
  27 #define CHT_WC_PHYCTRL                  0x5e07
  28
  29 #define CHT_WC_CHGRCTRL0                0x5e16
  30 #define CHT_WC_CHGRCTRL0_CHGRRESET      BIT(0)
  31 #define CHT_WC_CHGRCTRL0_EMRGCHREN      BIT(1)
  32 #define CHT_WC_CHGRCTRL0_EXTCHRDIS      BIT(2)
  33 #define CHT_WC_CHGRCTRL0_SWCONTROL      BIT(3)
  34 #define CHT_WC_CHGRCTRL0_TTLCK_MASK     BIT(4)
  35 #define CHT_WC_CHGRCTRL0_CCSM_OFF_MASK  BIT(5)
  36 #define CHT_WC_CHGRCTRL0_DBPOFF_MASK    BIT(6)
  37 #define CHT_WC_CHGRCTRL0_WDT_NOKICK     BIT(7)
  38
  39 #define CHT_WC_CHGRCTRL1                0x5e17
  40
  41 #define CHT_WC_USBSRC                   0x5e29
  42 #define CHT_WC_USBSRC_STS_MASK          GENMASK(1, 0)
  43 #define CHT_WC_USBSRC_STS_SUCCESS       2
  44 #define CHT_WC_USBSRC_STS_FAIL          3
  45 #define CHT_WC_USBSRC_TYPE_SHIFT        2
  46 #define CHT_WC_USBSRC_TYPE_MASK         GENMASK(5, 2)
  47 #define CHT_WC_USBSRC_TYPE_NONE         0
  48 #define CHT_WC_USBSRC_TYPE_SDP          1
  49 #define CHT_WC_USBSRC_TYPE_DCP          2
  50 #define CHT_WC_USBSRC_TYPE_CDP          3
  51 #define CHT_WC_USBSRC_TYPE_ACA          4
  52 #define CHT_WC_USBSRC_TYPE_SE1          5
  53 #define CHT_WC_USBSRC_TYPE_MHL          6
  54 #define CHT_WC_USBSRC_TYPE_FLOAT_DP_DN  7
  55 #define CHT_WC_USBSRC_TYPE_OTHER        8
  56 #define CHT_WC_USBSRC_TYPE_DCP_EXTPHY   9
  57
  58 #define CHT_WC_PWRSRC_IRQ               0x6e03
  59 #define CHT_WC_PWRSRC_IRQ_MASK          0x6e0f
  60 #define CHT_WC_PWRSRC_STS               0x6e1e
  61 #define CHT_WC_PWRSRC_VBUS              BIT(0)
  62 #define CHT_WC_PWRSRC_DC                BIT(1)
  63 #define CHT_WC_PWRSRC_BAT               BIT(2)
  64 #define CHT_WC_PWRSRC_ID_GND            BIT(3)
  65 #define CHT_WC_PWRSRC_ID_FLOAT          BIT(4)
  66
  67 #define CHT_WC_VBUS_GPIO_CTLO           0x6e2d
  68 #define CHT_WC_VBUS_GPIO_CTLO_OUTPUT    BIT(0)
  69 #define CHT_WC_VBUS_GPIO_CTLO_DRV_OD    BIT(4)
  70 #define CHT_WC_VBUS_GPIO_CTLO_DIR_OUT   BIT(5)
  71
  72 enum cht_wc_usb_id {
  73         USB_ID_OTG,
  74         USB_ID_GND,
  75         USB_ID_FLOAT,
  76         USB_RID_A,
  77         USB_RID_B,
  78         USB_RID_C,
  79 };
  80
  81 enum cht_wc_mux_select {
  82         MUX_SEL_PMIC = 0,
  83         MUX_SEL_SOC,
  84 };
  85
  86 static const unsigned int cht_wc_extcon_cables[] = {
  87         EXTCON_USB,
  88         EXTCON_USB_HOST,
  89         EXTCON_CHG_USB_SDP,
  90         EXTCON_CHG_USB_CDP,
  91         EXTCON_CHG_USB_DCP,
  92         EXTCON_CHG_USB_ACA,
  93         EXTCON_NONE,
  94 };
  95
  96 struct cht_wc_extcon_data {
  97         struct device *dev;
  98         struct regmap *regmap;
  99         struct extcon_dev *edev;
 100         unsigned int previous_cable;
 101         bool usb_host;
 102 };
 103
 104 static int cht_wc_extcon_get_id(struct cht_wc_extcon_data *ext, int pwrsrc_sts)
 105 {
 106         if (pwrsrc_sts & CHT_WC_PWRSRC_ID_GND)
 107                 return USB_ID_GND;
 108         if (pwrsrc_sts & CHT_WC_PWRSRC_ID_FLOAT)
 109                 return USB_ID_FLOAT;
 110
 111         /*
 112          * Once we have iio support for the gpadc we should read the USBID
 113          * gpadc channel here and determine ACA role based on that.
 114          */
 115         return USB_ID_FLOAT;
 116 }
 117
 118 static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext,
 119                                      bool ignore_errors)
 120 {
 121         int ret, usbsrc, status;
 122         unsigned long timeout;
 123
 124         /* Charger detection can take upto 600ms, wait 800ms max. */
 125         timeout = jiffies + msecs_to_jiffies(800);
 126         do {
 127                 ret = regmap_read(ext->regmap, CHT_WC_USBSRC, &usbsrc);
 128                 if (ret) {
 129                         dev_err(ext->dev, "Error reading usbsrc: %d\n", ret);
 130                         return ret;
 131                 }
 132
 133                 status = usbsrc & CHT_WC_USBSRC_STS_MASK;
 134                 if (status == CHT_WC_USBSRC_STS_SUCCESS ||
 135                     status == CHT_WC_USBSRC_STS_FAIL)
 136                         break;
 137
 138                 msleep(50); /* Wait a bit before retrying */
 139         } while (time_before(jiffies, timeout));
 140
 141         if (status != CHT_WC_USBSRC_STS_SUCCESS) {
 142                 if (ignore_errors)
 143                         return EXTCON_CHG_USB_SDP; /* Save fallback */
 144
 145                 if (status == CHT_WC_USBSRC_STS_FAIL)
 146                         dev_warn(ext->dev, "Could not detect charger type\n");
 147                 else
 148                         dev_warn(ext->dev, "Timeout detecting charger type\n");
 149                 return EXTCON_CHG_USB_SDP; /* Save fallback */
 150         }
 151
 152         usbsrc = (usbsrc & CHT_WC_USBSRC_TYPE_MASK) >> CHT_WC_USBSRC_TYPE_SHIFT;
 153         switch (usbsrc) {
 154         default:
 155                 dev_warn(ext->dev,
 156                         "Unhandled charger type %d, defaulting to SDP\n",
 157                          ret);
 158                 /* Fall through, treat as SDP */
 159         case CHT_WC_USBSRC_TYPE_SDP:
 160         case CHT_WC_USBSRC_TYPE_FLOAT_DP_DN:
 161         case CHT_WC_USBSRC_TYPE_OTHER:
 162                 return EXTCON_CHG_USB_SDP;
 163         case CHT_WC_USBSRC_TYPE_CDP:
 164                 return EXTCON_CHG_USB_CDP;
 165         case CHT_WC_USBSRC_TYPE_DCP:
 166         case CHT_WC_USBSRC_TYPE_DCP_EXTPHY:
 167         case CHT_WC_USBSRC_TYPE_MHL: /* MHL2+ delivers upto 2A, treat as DCP */
 168                 return EXTCON_CHG_USB_DCP;
 169         case CHT_WC_USBSRC_TYPE_ACA:
 170                 return EXTCON_CHG_USB_ACA;
 171         }
 172 }
 173
 174 static void cht_wc_extcon_set_phymux(struct cht_wc_extcon_data *ext, u8 state)
 175 {
 176         int ret;
 177
 178         ret = regmap_write(ext->regmap, CHT_WC_PHYCTRL, state);
 179         if (ret)
 180                 dev_err(ext->dev, "Error writing phyctrl: %d\n", ret);
 181 }
 182
 183 static void cht_wc_extcon_set_5v_boost(struct cht_wc_extcon_data *ext,
 184                                        bool enable)
 185 {
 186         int ret, val;
 187
 188         /*
 189          * The 5V boost converter is enabled through a gpio on the PMIC, since
 190          * there currently is no gpio driver we access the gpio reg directly.
 191          */
 192         val = CHT_WC_VBUS_GPIO_CTLO_DRV_OD | CHT_WC_VBUS_GPIO_CTLO_DIR_OUT;
 193         if (enable)
 194                 val |= CHT_WC_VBUS_GPIO_CTLO_OUTPUT;
 195
 196         ret = regmap_write(ext->regmap, CHT_WC_VBUS_GPIO_CTLO, val);
 197         if (ret)
 198                 dev_err(ext->dev, "Error writing Vbus GPIO CTLO: %d\n", ret);
 199 }
 200
 201 /* Small helper to sync EXTCON_CHG_USB_SDP and EXTCON_USB state */
 202 static void cht_wc_extcon_set_state(struct cht_wc_extcon_data *ext,
 203                                     unsigned int cable, bool state)
 204 {
 205         extcon_set_state_sync(ext->edev, cable, state);
 206         if (cable == EXTCON_CHG_USB_SDP)
 207                 extcon_set_state_sync(ext->edev, EXTCON_USB, state);
 208 }
 209
 210 static void cht_wc_extcon_pwrsrc_event(struct cht_wc_extcon_data *ext)
 211 {
 212         int ret, pwrsrc_sts, id;
 213         unsigned int cable = EXTCON_NONE;
 214         /* Ignore errors in host mode, as the 5v boost converter is on then */
 215         bool ignore_get_charger_errors = ext->usb_host;
 216
 217         ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
 218         if (ret) {
 219                 dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
 220                 return;
 221         }
 222
 223         id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
 224         if (id == USB_ID_GND) {
 225                 /* The 5v boost causes a false VBUS / SDP detect, skip */
 226                 goto charger_det_done;
 227         }
 228
 229         /* Plugged into a host/charger or not connected? */
 230         if (!(pwrsrc_sts & CHT_WC_PWRSRC_VBUS)) {
 231                 /* Route D+ and D- to PMIC for future charger detection */
 232                 cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
 233                 goto set_state;
 234         }
 235
 236         ret = cht_wc_extcon_get_charger(ext, ignore_get_charger_errors);
 237         if (ret >= 0)
 238                 cable = ret;
 239
 240 charger_det_done:
 241         /* Route D+ and D- to SoC for the host or gadget controller */
 242         cht_wc_extcon_set_phymux(ext, MUX_SEL_SOC);
 243
 244 set_state:
 245         if (cable != ext->previous_cable) {
 246                 cht_wc_extcon_set_state(ext, cable, true);
 247                 cht_wc_extcon_set_state(ext, ext->previous_cable, false);
 248                 ext->previous_cable = cable;
 249         }
 250
 251         ext->usb_host = ((id == USB_ID_GND) || (id == USB_RID_A));
 252         extcon_set_state_sync(ext->edev, EXTCON_USB_HOST, ext->usb_host);
 253 }
 254
 255 static irqreturn_t cht_wc_extcon_isr(int irq, void *data)
 256 {
 257         struct cht_wc_extcon_data *ext = data;
 258         int ret, irqs;
 259
 260         ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_IRQ, &irqs);
 261         if (ret) {
 262                 dev_err(ext->dev, "Error reading irqs: %d\n", ret);
 263                 return IRQ_NONE;
 264         }
 265
 266         cht_wc_extcon_pwrsrc_event(ext);
 267
 268         ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ, irqs);
 269         if (ret) {
 270                 dev_err(ext->dev, "Error writing irqs: %d\n", ret);
 271                 return IRQ_NONE;
 272         }
 273
 274         return IRQ_HANDLED;
 275 }
 276
 277 static int cht_wc_extcon_sw_control(struct cht_wc_extcon_data *ext, bool enable)
 278 {
 279         int ret, mask, val;
 280
 281         mask = CHT_WC_CHGRCTRL0_SWCONTROL | CHT_WC_CHGRCTRL0_CCSM_OFF_MASK;
 282         val = enable ? mask : 0;
 283         ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val);
 284         if (ret)
 285                 dev_err(ext->dev, "Error setting sw control: %d\n", ret);
 286
 287         return ret;
 288 }
 289
 290 static int cht_wc_extcon_probe(struct platform_device *pdev)
 291 {
 292         struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
 293         struct cht_wc_extcon_data *ext;
 294         int irq, ret;
 295
 296         irq = platform_get_irq(pdev, 0);
 297         if (irq < 0)
 298                 return irq;
 299
 300         ext = devm_kzalloc(&pdev->dev, sizeof(*ext), GFP_KERNEL);
 301         if (!ext)
 302                 return -ENOMEM;
 303
 304         ext->dev = &pdev->dev;
 305         ext->regmap = pmic->regmap;
 306         ext->previous_cable = EXTCON_NONE;
 307
 308         /* Initialize extcon device */
 309         ext->edev = devm_extcon_dev_allocate(ext->dev, cht_wc_extcon_cables);
 310         if (IS_ERR(ext->edev))
 311                 return PTR_ERR(ext->edev);
 312
 313         /*
 314          * When a host-cable is detected the BIOS enables an external 5v boost
 315          * converter to power connected devices there are 2 problems with this:
 316          * 1) This gets seen by the external battery charger as a valid Vbus
 317          *    supply and it then tries to feed Vsys from this creating a
 318          *    feedback loop which causes aprox. 300 mA extra battery drain
 319          *    (and unless we drive the external-charger-disable pin high it
 320          *    also tries to charge the battery causing even more feedback).
 321          * 2) This gets seen by the pwrsrc block as a SDP USB Vbus supply
 322          * Since the external battery charger has its own 5v boost converter
 323          * which does not have these issues, we simply turn the separate
 324          * external 5v boost converter off and leave it off entirely.
 325          */
 326         cht_wc_extcon_set_5v_boost(ext, false);
 327
 328         /* Enable sw control */
 329         ret = cht_wc_extcon_sw_control(ext, true);
 330         if (ret)
 331                 return ret;
 332
 333         /* Register extcon device */
 334         ret = devm_extcon_dev_register(ext->dev, ext->edev);
 335         if (ret) {
 336                 dev_err(ext->dev, "Error registering extcon device: %d\n", ret);
 337                 goto disable_sw_control;
 338         }
 339
 340         /* Route D+ and D- to PMIC for initial charger detection */
 341         cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
 342
 343         /* Get initial state */
 344         cht_wc_extcon_pwrsrc_event(ext);
 345
 346         ret = devm_request_threaded_irq(ext->dev, irq, NULL, cht_wc_extcon_isr,
 347                                         IRQF_ONESHOT, pdev->name, ext);
 348         if (ret) {
 349                 dev_err(ext->dev, "Error requesting interrupt: %d\n", ret);
 350                 goto disable_sw_control;
 351         }
 352
 353         /* Unmask irqs */
 354         ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK,
 355                            (int)~(CHT_WC_PWRSRC_VBUS | CHT_WC_PWRSRC_ID_GND |
 356                                   CHT_WC_PWRSRC_ID_FLOAT));
 357         if (ret) {
 358                 dev_err(ext->dev, "Error writing irq-mask: %d\n", ret);
 359                 goto disable_sw_control;
 360         }
 361
 362         platform_set_drvdata(pdev, ext);
 363
 364         return 0;
 365
 366 disable_sw_control:
 367         cht_wc_extcon_sw_control(ext, false);
 368         return ret;
 369 }
 370
 371 static int cht_wc_extcon_remove(struct platform_device *pdev)
 372 {
 373         struct cht_wc_extcon_data *ext = platform_get_drvdata(pdev);
 374
 375         cht_wc_extcon_sw_control(ext, false);
 376
 377         return 0;
 378 }
 379
 380 static const struct platform_device_id cht_wc_extcon_table[] = {
 381         { .name = "cht_wcove_pwrsrc" },
 382         {},
 383 };
 384 MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table);
 385
 386 static struct platform_driver cht_wc_extcon_driver = {
 387         .probe = cht_wc_extcon_probe,
 388         .remove = cht_wc_extcon_remove,
 389         .id_table = cht_wc_extcon_table,
 390         .driver = {
 391                 .name = "cht_wcove_pwrsrc",
 392         },
 393 };
 394 module_platform_driver(cht_wc_extcon_driver);
 395
 396 MODULE_DESCRIPTION("Intel Cherrytrail Whiskey Cove PMIC extcon driver");
 397 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
 398 MODULE_LICENSE("GPL v2");