2 * Copyright 2015 IBM Corp.
4 * Joel Stanley <joel@jms.id.au>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <asm/div64.h>
13 #include <linux/clk.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/hashtable.h>
16 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
25 struct aspeed_bank_props
{
31 struct aspeed_gpio_config
{
32 unsigned int nr_gpios
;
33 const struct aspeed_bank_props
*props
;
37 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
38 * @timer_users: Tracks the number of users for each timer
40 * The @timer_users has four elements but the first element is unused. This is
41 * to simplify accounting and indexing, as a zero value in @offset_timer
42 * represents disabled debouncing for the GPIO. Any other value for an element
43 * of @offset_timer is used as an index into @timer_users. This behaviour of
44 * the zero value aligns with the behaviour of zero built from the timer
45 * configuration registers (i.e. debouncing is disabled).
48 struct gpio_chip chip
;
52 const struct aspeed_gpio_config
*config
;
55 unsigned int timer_users
[4];
59 struct aspeed_gpio_bank
{
62 uint16_t debounce_regs
;
63 const char names
[4][3];
66 static const int debounce_timers
[4] = { 0x00, 0x50, 0x54, 0x58 };
68 static const struct aspeed_gpio_bank aspeed_gpio_banks
[] = {
72 .debounce_regs
= 0x0040,
73 .names
= { "A", "B", "C", "D" },
78 .debounce_regs
= 0x0048,
79 .names
= { "E", "F", "G", "H" },
84 .debounce_regs
= 0x00b0,
85 .names
= { "I", "J", "K", "L" },
90 .debounce_regs
= 0x0100,
91 .names
= { "M", "N", "O", "P" },
96 .debounce_regs
= 0x0130,
97 .names
= { "Q", "R", "S", "T" },
102 .debounce_regs
= 0x0160,
103 .names
= { "U", "V", "W", "X" },
108 .debounce_regs
= 0x0190,
109 .names
= { "Y", "Z", "AA", "AB" },
114 .debounce_regs
= 0x01c0,
115 .names
= { "AC", "", "", "" },
119 #define GPIO_BANK(x) ((x) >> 5)
120 #define GPIO_OFFSET(x) ((x) & 0x1f)
121 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
123 #define GPIO_DATA 0x00
124 #define GPIO_DIR 0x04
126 #define GPIO_IRQ_ENABLE 0x00
127 #define GPIO_IRQ_TYPE0 0x04
128 #define GPIO_IRQ_TYPE1 0x08
129 #define GPIO_IRQ_TYPE2 0x0c
130 #define GPIO_IRQ_STATUS 0x10
132 #define GPIO_DEBOUNCE_SEL1 0x00
133 #define GPIO_DEBOUNCE_SEL2 0x04
135 #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
136 #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
137 #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
139 static const struct aspeed_gpio_bank
*to_bank(unsigned int offset
)
141 unsigned int bank
= GPIO_BANK(offset
);
143 WARN_ON(bank
> ARRAY_SIZE(aspeed_gpio_banks
));
144 return &aspeed_gpio_banks
[bank
];
147 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props
*props
)
149 return !(props
->input
|| props
->output
);
152 static inline const struct aspeed_bank_props
*find_bank_props(
153 struct aspeed_gpio
*gpio
, unsigned int offset
)
155 const struct aspeed_bank_props
*props
= gpio
->config
->props
;
157 while (!is_bank_props_sentinel(props
)) {
158 if (props
->bank
== GPIO_BANK(offset
))
166 static inline bool have_gpio(struct aspeed_gpio
*gpio
, unsigned int offset
)
168 const struct aspeed_bank_props
*props
= find_bank_props(gpio
, offset
);
169 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
170 unsigned int group
= GPIO_OFFSET(offset
) / 8;
172 return bank
->names
[group
][0] != '\0' &&
173 (!props
|| ((props
->input
| props
->output
) & GPIO_BIT(offset
)));
176 static inline bool have_input(struct aspeed_gpio
*gpio
, unsigned int offset
)
178 const struct aspeed_bank_props
*props
= find_bank_props(gpio
, offset
);
180 return !props
|| (props
->input
& GPIO_BIT(offset
));
183 #define have_irq(g, o) have_input((g), (o))
184 #define have_debounce(g, o) have_input((g), (o))
186 static inline bool have_output(struct aspeed_gpio
*gpio
, unsigned int offset
)
188 const struct aspeed_bank_props
*props
= find_bank_props(gpio
, offset
);
190 return !props
|| (props
->output
& GPIO_BIT(offset
));
193 static void __iomem
*bank_val_reg(struct aspeed_gpio
*gpio
,
194 const struct aspeed_gpio_bank
*bank
,
197 return gpio
->base
+ bank
->val_regs
+ reg
;
200 static void __iomem
*bank_irq_reg(struct aspeed_gpio
*gpio
,
201 const struct aspeed_gpio_bank
*bank
,
204 return gpio
->base
+ bank
->irq_regs
+ reg
;
207 static int aspeed_gpio_get(struct gpio_chip
*gc
, unsigned int offset
)
209 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
210 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
212 return !!(ioread32(bank_val_reg(gpio
, bank
, GPIO_DATA
))
216 static void __aspeed_gpio_set(struct gpio_chip
*gc
, unsigned int offset
,
219 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
220 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
224 addr
= bank_val_reg(gpio
, bank
, GPIO_DATA
);
225 reg
= ioread32(addr
);
228 reg
|= GPIO_BIT(offset
);
230 reg
&= ~GPIO_BIT(offset
);
232 iowrite32(reg
, addr
);
235 static void aspeed_gpio_set(struct gpio_chip
*gc
, unsigned int offset
,
238 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
241 spin_lock_irqsave(&gpio
->lock
, flags
);
243 __aspeed_gpio_set(gc
, offset
, val
);
245 spin_unlock_irqrestore(&gpio
->lock
, flags
);
248 static int aspeed_gpio_dir_in(struct gpio_chip
*gc
, unsigned int offset
)
250 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
251 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
255 if (!have_input(gpio
, offset
))
258 spin_lock_irqsave(&gpio
->lock
, flags
);
260 reg
= ioread32(bank_val_reg(gpio
, bank
, GPIO_DIR
));
261 iowrite32(reg
& ~GPIO_BIT(offset
), bank_val_reg(gpio
, bank
, GPIO_DIR
));
263 spin_unlock_irqrestore(&gpio
->lock
, flags
);
268 static int aspeed_gpio_dir_out(struct gpio_chip
*gc
,
269 unsigned int offset
, int val
)
271 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
272 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
276 if (!have_output(gpio
, offset
))
279 spin_lock_irqsave(&gpio
->lock
, flags
);
281 reg
= ioread32(bank_val_reg(gpio
, bank
, GPIO_DIR
));
282 iowrite32(reg
| GPIO_BIT(offset
), bank_val_reg(gpio
, bank
, GPIO_DIR
));
284 __aspeed_gpio_set(gc
, offset
, val
);
286 spin_unlock_irqrestore(&gpio
->lock
, flags
);
291 static int aspeed_gpio_get_direction(struct gpio_chip
*gc
, unsigned int offset
)
293 struct aspeed_gpio
*gpio
= gpiochip_get_data(gc
);
294 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
298 if (!have_input(gpio
, offset
))
301 if (!have_output(gpio
, offset
))
304 spin_lock_irqsave(&gpio
->lock
, flags
);
306 val
= ioread32(bank_val_reg(gpio
, bank
, GPIO_DIR
)) & GPIO_BIT(offset
);
308 spin_unlock_irqrestore(&gpio
->lock
, flags
);
314 static inline int irqd_to_aspeed_gpio_data(struct irq_data
*d
,
315 struct aspeed_gpio
**gpio
,
316 const struct aspeed_gpio_bank
**bank
,
320 struct aspeed_gpio
*internal
;
322 offset
= irqd_to_hwirq(d
);
324 internal
= irq_data_get_irq_chip_data(d
);
326 /* This might be a bit of a questionable place to check */
327 if (!have_irq(internal
, offset
))
331 *bank
= to_bank(offset
);
332 *bit
= GPIO_BIT(offset
);
337 static void aspeed_gpio_irq_ack(struct irq_data
*d
)
339 const struct aspeed_gpio_bank
*bank
;
340 struct aspeed_gpio
*gpio
;
342 void __iomem
*status_addr
;
346 rc
= irqd_to_aspeed_gpio_data(d
, &gpio
, &bank
, &bit
);
350 status_addr
= bank_irq_reg(gpio
, bank
, GPIO_IRQ_STATUS
);
352 spin_lock_irqsave(&gpio
->lock
, flags
);
353 iowrite32(bit
, status_addr
);
354 spin_unlock_irqrestore(&gpio
->lock
, flags
);
357 static void aspeed_gpio_irq_set_mask(struct irq_data
*d
, bool set
)
359 const struct aspeed_gpio_bank
*bank
;
360 struct aspeed_gpio
*gpio
;
366 rc
= irqd_to_aspeed_gpio_data(d
, &gpio
, &bank
, &bit
);
370 addr
= bank_irq_reg(gpio
, bank
, GPIO_IRQ_ENABLE
);
372 spin_lock_irqsave(&gpio
->lock
, flags
);
374 reg
= ioread32(addr
);
379 iowrite32(reg
, addr
);
381 spin_unlock_irqrestore(&gpio
->lock
, flags
);
384 static void aspeed_gpio_irq_mask(struct irq_data
*d
)
386 aspeed_gpio_irq_set_mask(d
, false);
389 static void aspeed_gpio_irq_unmask(struct irq_data
*d
)
391 aspeed_gpio_irq_set_mask(d
, true);
394 static int aspeed_gpio_set_type(struct irq_data
*d
, unsigned int type
)
400 const struct aspeed_gpio_bank
*bank
;
401 irq_flow_handler_t handler
;
402 struct aspeed_gpio
*gpio
;
407 rc
= irqd_to_aspeed_gpio_data(d
, &gpio
, &bank
, &bit
);
411 switch (type
& IRQ_TYPE_SENSE_MASK
) {
412 case IRQ_TYPE_EDGE_BOTH
:
415 case IRQ_TYPE_EDGE_RISING
:
418 case IRQ_TYPE_EDGE_FALLING
:
419 handler
= handle_edge_irq
;
421 case IRQ_TYPE_LEVEL_HIGH
:
424 case IRQ_TYPE_LEVEL_LOW
:
426 handler
= handle_level_irq
;
432 spin_lock_irqsave(&gpio
->lock
, flags
);
434 addr
= bank_irq_reg(gpio
, bank
, GPIO_IRQ_TYPE0
);
435 reg
= ioread32(addr
);
436 reg
= (reg
& ~bit
) | type0
;
437 iowrite32(reg
, addr
);
439 addr
= bank_irq_reg(gpio
, bank
, GPIO_IRQ_TYPE1
);
440 reg
= ioread32(addr
);
441 reg
= (reg
& ~bit
) | type1
;
442 iowrite32(reg
, addr
);
444 addr
= bank_irq_reg(gpio
, bank
, GPIO_IRQ_TYPE2
);
445 reg
= ioread32(addr
);
446 reg
= (reg
& ~bit
) | type2
;
447 iowrite32(reg
, addr
);
449 spin_unlock_irqrestore(&gpio
->lock
, flags
);
451 irq_set_handler_locked(d
, handler
);
456 static void aspeed_gpio_irq_handler(struct irq_desc
*desc
)
458 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
459 struct irq_chip
*ic
= irq_desc_get_chip(desc
);
460 struct aspeed_gpio
*data
= gpiochip_get_data(gc
);
461 unsigned int i
, p
, girq
;
464 chained_irq_enter(ic
, desc
);
466 for (i
= 0; i
< ARRAY_SIZE(aspeed_gpio_banks
); i
++) {
467 const struct aspeed_gpio_bank
*bank
= &aspeed_gpio_banks
[i
];
469 reg
= ioread32(bank_irq_reg(data
, bank
, GPIO_IRQ_STATUS
));
471 for_each_set_bit(p
, ®
, 32) {
472 girq
= irq_find_mapping(gc
->irq
.domain
, i
* 32 + p
);
473 generic_handle_irq(girq
);
478 chained_irq_exit(ic
, desc
);
481 static struct irq_chip aspeed_gpio_irqchip
= {
482 .name
= "aspeed-gpio",
483 .irq_ack
= aspeed_gpio_irq_ack
,
484 .irq_mask
= aspeed_gpio_irq_mask
,
485 .irq_unmask
= aspeed_gpio_irq_unmask
,
486 .irq_set_type
= aspeed_gpio_set_type
,
489 static void set_irq_valid_mask(struct aspeed_gpio
*gpio
)
491 const struct aspeed_bank_props
*props
= gpio
->config
->props
;
493 while (!is_bank_props_sentinel(props
)) {
495 const unsigned long int input
= props
->input
;
497 /* Pretty crummy approach, but similar to GPIO core */
498 for_each_clear_bit(offset
, &input
, 32) {
499 unsigned int i
= props
->bank
* 32 + offset
;
501 if (i
>= gpio
->config
->nr_gpios
)
504 clear_bit(i
, gpio
->chip
.irq
.valid_mask
);
511 static int aspeed_gpio_setup_irqs(struct aspeed_gpio
*gpio
,
512 struct platform_device
*pdev
)
516 rc
= platform_get_irq(pdev
, 0);
522 set_irq_valid_mask(gpio
);
524 rc
= gpiochip_irqchip_add(&gpio
->chip
, &aspeed_gpio_irqchip
,
525 0, handle_bad_irq
, IRQ_TYPE_NONE
);
527 dev_info(&pdev
->dev
, "Could not add irqchip\n");
531 gpiochip_set_chained_irqchip(&gpio
->chip
, &aspeed_gpio_irqchip
,
532 gpio
->irq
, aspeed_gpio_irq_handler
);
537 static int aspeed_gpio_request(struct gpio_chip
*chip
, unsigned int offset
)
539 if (!have_gpio(gpiochip_get_data(chip
), offset
))
542 return pinctrl_gpio_request(chip
->base
+ offset
);
545 static void aspeed_gpio_free(struct gpio_chip
*chip
, unsigned int offset
)
547 pinctrl_gpio_free(chip
->base
+ offset
);
550 static inline void __iomem
*bank_debounce_reg(struct aspeed_gpio
*gpio
,
551 const struct aspeed_gpio_bank
*bank
,
554 return gpio
->base
+ bank
->debounce_regs
+ reg
;
557 static int usecs_to_cycles(struct aspeed_gpio
*gpio
, unsigned long usecs
,
564 rate
= clk_get_rate(gpio
->clk
);
569 r
= do_div(n
, 1000000);
574 /* At least as long as the requested time */
580 /* Call under gpio->lock */
581 static int register_allocated_timer(struct aspeed_gpio
*gpio
,
582 unsigned int offset
, unsigned int timer
)
584 if (WARN(gpio
->offset_timer
[offset
] != 0,
585 "Offset %d already allocated timer %d\n",
586 offset
, gpio
->offset_timer
[offset
]))
589 if (WARN(gpio
->timer_users
[timer
] == UINT_MAX
,
590 "Timer user count would overflow\n"))
593 gpio
->offset_timer
[offset
] = timer
;
594 gpio
->timer_users
[timer
]++;
599 /* Call under gpio->lock */
600 static int unregister_allocated_timer(struct aspeed_gpio
*gpio
,
603 if (WARN(gpio
->offset_timer
[offset
] == 0,
604 "No timer allocated to offset %d\n", offset
))
607 if (WARN(gpio
->timer_users
[gpio
->offset_timer
[offset
]] == 0,
608 "No users recorded for timer %d\n",
609 gpio
->offset_timer
[offset
]))
612 gpio
->timer_users
[gpio
->offset_timer
[offset
]]--;
613 gpio
->offset_timer
[offset
] = 0;
618 /* Call under gpio->lock */
619 static inline bool timer_allocation_registered(struct aspeed_gpio
*gpio
,
622 return gpio
->offset_timer
[offset
] > 0;
625 /* Call under gpio->lock */
626 static void configure_timer(struct aspeed_gpio
*gpio
, unsigned int offset
,
629 const struct aspeed_gpio_bank
*bank
= to_bank(offset
);
630 const u32 mask
= GPIO_BIT(offset
);
634 addr
= bank_debounce_reg(gpio
, bank
, GPIO_DEBOUNCE_SEL1
);
635 val
= ioread32(addr
);
636 iowrite32((val
& ~mask
) | GPIO_SET_DEBOUNCE1(timer
, offset
), addr
);
638 addr
= bank_debounce_reg(gpio
, bank
, GPIO_DEBOUNCE_SEL2
);
639 val
= ioread32(addr
);
640 iowrite32((val
& ~mask
) | GPIO_SET_DEBOUNCE2(timer
, offset
), addr
);
643 static int enable_debounce(struct gpio_chip
*chip
, unsigned int offset
,
646 struct aspeed_gpio
*gpio
= gpiochip_get_data(chip
);
647 u32 requested_cycles
;
655 rc
= usecs_to_cycles(gpio
, usecs
, &requested_cycles
);
657 dev_warn(chip
->parent
, "Failed to convert %luus to cycles at %luHz: %d\n",
658 usecs
, clk_get_rate(gpio
->clk
), rc
);
662 spin_lock_irqsave(&gpio
->lock
, flags
);
664 if (timer_allocation_registered(gpio
, offset
)) {
665 rc
= unregister_allocated_timer(gpio
, offset
);
670 /* Try to find a timer already configured for the debounce period */
671 for (i
= 1; i
< ARRAY_SIZE(debounce_timers
); i
++) {
674 cycles
= ioread32(gpio
->base
+ debounce_timers
[i
]);
675 if (requested_cycles
== cycles
)
679 if (i
== ARRAY_SIZE(debounce_timers
)) {
683 * As there are no timers configured for the requested debounce
684 * period, find an unused timer instead
686 for (j
= 1; j
< ARRAY_SIZE(gpio
->timer_users
); j
++) {
687 if (gpio
->timer_users
[j
] == 0)
691 if (j
== ARRAY_SIZE(gpio
->timer_users
)) {
692 dev_warn(chip
->parent
,
693 "Debounce timers exhausted, cannot debounce for period %luus\n",
699 * We already adjusted the accounting to remove @offset
700 * as a user of its previous timer, so also configure
701 * the hardware so @offset has timers disabled for
704 configure_timer(gpio
, offset
, 0);
710 iowrite32(requested_cycles
, gpio
->base
+ debounce_timers
[i
]);
713 if (WARN(i
== 0, "Cannot register index of disabled timer\n")) {
718 register_allocated_timer(gpio
, offset
, i
);
719 configure_timer(gpio
, offset
, i
);
722 spin_unlock_irqrestore(&gpio
->lock
, flags
);
727 static int disable_debounce(struct gpio_chip
*chip
, unsigned int offset
)
729 struct aspeed_gpio
*gpio
= gpiochip_get_data(chip
);
733 spin_lock_irqsave(&gpio
->lock
, flags
);
735 rc
= unregister_allocated_timer(gpio
, offset
);
737 configure_timer(gpio
, offset
, 0);
739 spin_unlock_irqrestore(&gpio
->lock
, flags
);
744 static int set_debounce(struct gpio_chip
*chip
, unsigned int offset
,
747 struct aspeed_gpio
*gpio
= gpiochip_get_data(chip
);
749 if (!have_debounce(gpio
, offset
))
753 return enable_debounce(chip
, offset
, usecs
);
755 return disable_debounce(chip
, offset
);
758 static int aspeed_gpio_set_config(struct gpio_chip
*chip
, unsigned int offset
,
759 unsigned long config
)
761 unsigned long param
= pinconf_to_config_param(config
);
762 u32 arg
= pinconf_to_config_argument(config
);
764 if (param
== PIN_CONFIG_INPUT_DEBOUNCE
)
765 return set_debounce(chip
, offset
, arg
);
766 else if (param
== PIN_CONFIG_BIAS_DISABLE
||
767 param
== PIN_CONFIG_BIAS_PULL_DOWN
||
768 param
== PIN_CONFIG_DRIVE_STRENGTH
)
769 return pinctrl_gpio_set_config(offset
, config
);
770 else if (param
== PIN_CONFIG_DRIVE_OPEN_DRAIN
||
771 param
== PIN_CONFIG_DRIVE_OPEN_SOURCE
)
772 /* Return -ENOTSUPP to trigger emulation, as per datasheet */
779 * Any banks not specified in a struct aspeed_bank_props array are assumed to
780 * have the properties:
782 * { .input = 0xffffffff, .output = 0xffffffff }
785 static const struct aspeed_bank_props ast2400_bank_props
[] = {
787 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
788 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
792 static const struct aspeed_gpio_config ast2400_config
=
793 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
794 { .nr_gpios
= 220, .props
= ast2400_bank_props
, };
796 static const struct aspeed_bank_props ast2500_bank_props
[] = {
798 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
799 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
800 { 7, 0x000000ff, 0x000000ff }, /* AC */
804 static const struct aspeed_gpio_config ast2500_config
=
805 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
806 { .nr_gpios
= 232, .props
= ast2500_bank_props
, };
808 static const struct of_device_id aspeed_gpio_of_table
[] = {
809 { .compatible
= "aspeed,ast2400-gpio", .data
= &ast2400_config
, },
810 { .compatible
= "aspeed,ast2500-gpio", .data
= &ast2500_config
, },
813 MODULE_DEVICE_TABLE(of
, aspeed_gpio_of_table
);
815 static int __init
aspeed_gpio_probe(struct platform_device
*pdev
)
817 const struct of_device_id
*gpio_id
;
818 struct aspeed_gpio
*gpio
;
819 struct resource
*res
;
822 gpio
= devm_kzalloc(&pdev
->dev
, sizeof(*gpio
), GFP_KERNEL
);
826 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
827 gpio
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
828 if (IS_ERR(gpio
->base
))
829 return PTR_ERR(gpio
->base
);
831 spin_lock_init(&gpio
->lock
);
833 gpio_id
= of_match_node(aspeed_gpio_of_table
, pdev
->dev
.of_node
);
837 gpio
->clk
= of_clk_get(pdev
->dev
.of_node
, 0);
838 if (IS_ERR(gpio
->clk
)) {
840 "Failed to get clock from devicetree, debouncing disabled\n");
844 gpio
->config
= gpio_id
->data
;
846 gpio
->chip
.parent
= &pdev
->dev
;
847 gpio
->chip
.ngpio
= gpio
->config
->nr_gpios
;
848 gpio
->chip
.parent
= &pdev
->dev
;
849 gpio
->chip
.direction_input
= aspeed_gpio_dir_in
;
850 gpio
->chip
.direction_output
= aspeed_gpio_dir_out
;
851 gpio
->chip
.get_direction
= aspeed_gpio_get_direction
;
852 gpio
->chip
.request
= aspeed_gpio_request
;
853 gpio
->chip
.free
= aspeed_gpio_free
;
854 gpio
->chip
.get
= aspeed_gpio_get
;
855 gpio
->chip
.set
= aspeed_gpio_set
;
856 gpio
->chip
.set_config
= aspeed_gpio_set_config
;
857 gpio
->chip
.label
= dev_name(&pdev
->dev
);
858 gpio
->chip
.base
= -1;
859 gpio
->chip
.irq
.need_valid_mask
= true;
861 rc
= devm_gpiochip_add_data(&pdev
->dev
, &gpio
->chip
, gpio
);
866 devm_kzalloc(&pdev
->dev
, gpio
->chip
.ngpio
, GFP_KERNEL
);
868 return aspeed_gpio_setup_irqs(gpio
, pdev
);
871 static struct platform_driver aspeed_gpio_driver
= {
873 .name
= KBUILD_MODNAME
,
874 .of_match_table
= aspeed_gpio_of_table
,
878 module_platform_driver_probe(aspeed_gpio_driver
, aspeed_gpio_probe
);
880 MODULE_DESCRIPTION("Aspeed GPIO Driver");
881 MODULE_LICENSE("GPL");